w11 - vhd 0.794
W11 CPU core and support modules
Loading...
Searching...
No Matches
Constants | Instantiations | Signals
syn Architecture Reference
Architecture >> syn

Constants

rbaddr_eyemon  slv16 := x " ffd0 "
rbaddr_tim1  slv16 := x " fe11 "
rbaddr_tim0  slv16 := x " fe10 "
rbaddr_bram  slv16 := x " fe00 "

Signals

RB_SRES_TEST  rb_sres_type := rb_sres_init
RB_SRES_BRAM  rb_sres_type := rb_sres_init
RB_SRES_MON  rb_sres_type := rb_sres_init
RB_SRES_EMON  rb_sres_type := rb_sres_init
RB_SRES_TIM0  rb_sres_type := rb_sres_init
RB_SRES_TIM1  rb_sres_type := rb_sres_init
RB_SRES_SUM1  rb_sres_type := rb_sres_init
RB_LAM_TEST  slv16 := ( others = > ' 0 ' )
TIM0_DONE  slbit := ' 0 '
TIM0_BUSY  slbit := ' 0 '
TIM1_DONE  slbit := ' 0 '
TIM1_BUSY  slbit := ' 0 '

Instantiations

test  rbd_tester <Entity rbd_tester>
bram  rbd_bram <Entity rbd_bram>
mon  rbd_rbmon <Entity rbd_rbmon>
emon  rbd_eyemon <Entity rbd_eyemon>
tim0  rbd_timer <Entity rbd_timer>
tim1  rbd_timer <Entity rbd_timer>
rb_sres_or1  rb_sres_or_3 <Entity rb_sres_or_3>
rb_sres_or  rb_sres_or_4 <Entity rb_sres_or_4>

Detailed Description

Definition at line 60 of file rbd_tst_rlink.vhd.

Member Data Documentation

◆ RB_SRES_TEST

RB_SRES_TEST rb_sres_type := rb_sres_init
Signal

Definition at line 62 of file rbd_tst_rlink.vhd.

◆ RB_SRES_BRAM

RB_SRES_BRAM rb_sres_type := rb_sres_init
Signal

Definition at line 63 of file rbd_tst_rlink.vhd.

◆ RB_SRES_MON

RB_SRES_MON rb_sres_type := rb_sres_init
Signal

Definition at line 64 of file rbd_tst_rlink.vhd.

◆ RB_SRES_EMON

RB_SRES_EMON rb_sres_type := rb_sres_init
Signal

Definition at line 65 of file rbd_tst_rlink.vhd.

◆ RB_SRES_TIM0

RB_SRES_TIM0 rb_sres_type := rb_sres_init
Signal

Definition at line 66 of file rbd_tst_rlink.vhd.

◆ RB_SRES_TIM1

RB_SRES_TIM1 rb_sres_type := rb_sres_init
Signal

Definition at line 67 of file rbd_tst_rlink.vhd.

◆ RB_SRES_SUM1

RB_SRES_SUM1 rb_sres_type := rb_sres_init
Signal

Definition at line 68 of file rbd_tst_rlink.vhd.

◆ RB_LAM_TEST

RB_LAM_TEST slv16 := ( others = > ' 0 ' )
Signal

Definition at line 70 of file rbd_tst_rlink.vhd.

◆ TIM0_DONE

TIM0_DONE slbit := ' 0 '
Signal

Definition at line 72 of file rbd_tst_rlink.vhd.

◆ TIM0_BUSY

TIM0_BUSY slbit := ' 0 '
Signal

Definition at line 73 of file rbd_tst_rlink.vhd.

◆ TIM1_DONE

TIM1_DONE slbit := ' 0 '
Signal

Definition at line 74 of file rbd_tst_rlink.vhd.

◆ TIM1_BUSY

TIM1_BUSY slbit := ' 0 '
Signal

Definition at line 75 of file rbd_tst_rlink.vhd.

◆ rbaddr_eyemon

rbaddr_eyemon slv16 := x " ffd0 "
Constant

Definition at line 79 of file rbd_tst_rlink.vhd.

◆ rbaddr_tim1

rbaddr_tim1 slv16 := x " fe11 "
Constant

Definition at line 80 of file rbd_tst_rlink.vhd.

◆ rbaddr_tim0

rbaddr_tim0 slv16 := x " fe10 "
Constant

Definition at line 81 of file rbd_tst_rlink.vhd.

◆ rbaddr_bram

rbaddr_bram slv16 := x " fe00 "
Constant

Definition at line 82 of file rbd_tst_rlink.vhd.

◆ test

test rbd_tester
Instantiation

Definition at line 96 of file rbd_tst_rlink.vhd.

◆ bram

bram rbd_bram
Instantiation

Definition at line 106 of file rbd_tst_rlink.vhd.

◆ mon

mon rbd_rbmon
Instantiation

Definition at line 118 of file rbd_tst_rlink.vhd.

◆ emon

emon rbd_eyemon
Instantiation

Definition at line 131 of file rbd_tst_rlink.vhd.

◆ tim0

tim0 rbd_timer
Instantiation

Definition at line 144 of file rbd_tst_rlink.vhd.

◆ tim1

tim1 rbd_timer
Instantiation

Definition at line 157 of file rbd_tst_rlink.vhd.

◆ rb_sres_or1

rb_sres_or1 rb_sres_or_3
Instantiation

Definition at line 165 of file rbd_tst_rlink.vhd.

◆ rb_sres_or

rb_sres_or rb_sres_or_4
Instantiation

Definition at line 174 of file rbd_tst_rlink.vhd.

The documentation for this design unit was generated from the following file: