syn Architecture Reference

Architecture >> syn

Constants
ok_mod32	boolean := ( DWIDTHmod 32 ) = 0and ( ( DWIDTH + 35 ) / 36 ) = ( ( DWIDTH + 31 ) / 32 )
ok_mod16	boolean := ( DWIDTHmod 16 ) = 0and ( ( DWIDTH + 17 ) / 18 ) = ( ( DWIDTH + 16 ) / 16 )
ok_mod08	boolean := ( DWIDTHmod 32 ) = 0and ( ( DWIDTH + 8 ) / 9 ) = ( ( DWIDTH + 7 ) / 8 )
dw_mem	positive := ( ( DWIDTH + 35 ) / 36 ) * 36
dw_mem	positive := ( ( DWIDTH + 17 ) / 18 ) * 18
dw_mem	positive := ( ( DWIDTH + 8 ) / 9 ) * 9
dw_mem	positive := ( ( DWIDTH + 3 ) / 4 ) * 4
dw_mem	positive := ( ( DWIDTH + 1 ) / 2 ) * 2

Signals
L_DO	slv ( dw_mem - 1 downto 0 ) := ( others = > ' 0 ' )
L_DI	slv ( dw_mem - 1 downto 0 ) := ( others = > ' 0 ' )

Instantiations
mem	ramb16_s36
mem	ramb16_s36
mem	ramb16_s18
mem	ramb16_s18
mem	ramb16_s9
mem	ramb16_s9
mem	ramb16_s4
mem	ramb16_s2
mem	ramb16_s1

Detailed Description

Definition at line 45 of file ram_1swsr_xfirst_gen_unisim.vhd.

Member Data Documentation

ok_mod32

ok_mod32 boolean := ( DWIDTHmod 32 ) = 0and ( ( DWIDTH + 35 ) / 36 ) = ( ( DWIDTH + 31 ) / 32 )

Constant

Definition at line 47 of file ram_1swsr_xfirst_gen_unisim.vhd.

ok_mod16

ok_mod16 boolean := ( DWIDTHmod 16 ) = 0and ( ( DWIDTH + 17 ) / 18 ) = ( ( DWIDTH + 16 ) / 16 )

Constant

Definition at line 49 of file ram_1swsr_xfirst_gen_unisim.vhd.

ok_mod08

ok_mod08 boolean := ( DWIDTHmod 32 ) = 0and ( ( DWIDTH + 8 ) / 9 ) = ( ( DWIDTH + 7 ) / 8 )

Constant

Definition at line 51 of file ram_1swsr_xfirst_gen_unisim.vhd.

dw_mem [1/5]

dw_mem positive := ( ( DWIDTH + 35 ) / 36 ) * 36

Constant

Definition at line 61 of file ram_1swsr_xfirst_gen_unisim.vhd.

L_DO

L_DO slv ( dw_mem - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Definition at line 62 of file ram_1swsr_xfirst_gen_unisim.vhd.

L_DI

L_DI slv ( dw_mem - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Definition at line 63 of file ram_1swsr_xfirst_gen_unisim.vhd.

dw_mem [2/5]

positive :=(( DWIDTH+ 17)/ 18)* 18 dw_mem

Definition at line 116 of file ram_1swsr_xfirst_gen_unisim.vhd.

dw_mem [3/5]

positive :=(( DWIDTH+ 8)/ 9)* 9 dw_mem

Definition at line 171 of file ram_1swsr_xfirst_gen_unisim.vhd.

dw_mem [4/5]

positive :=(( DWIDTH+ 3)/ 4)* 4 dw_mem

Definition at line 226 of file ram_1swsr_xfirst_gen_unisim.vhd.

dw_mem [5/5]

positive :=(( DWIDTH+ 1)/ 2)* 2 dw_mem

Definition at line 258 of file ram_1swsr_xfirst_gen_unisim.vhd.

mem [1/9]

mem ramb16_s36

Instantiation

Definition at line 87 of file ram_1swsr_xfirst_gen_unisim.vhd.

mem [2/9]

mem ramb16_s36

Instantiation

Definition at line 111 of file ram_1swsr_xfirst_gen_unisim.vhd.

mem [3/9]

mem ramb16_s18

Instantiation

Definition at line 142 of file ram_1swsr_xfirst_gen_unisim.vhd.

mem [4/9]

mem ramb16_s18

Instantiation

Definition at line 166 of file ram_1swsr_xfirst_gen_unisim.vhd.

mem [5/9]

mem ramb16_s9

Instantiation

Definition at line 197 of file ram_1swsr_xfirst_gen_unisim.vhd.

mem [6/9]

mem ramb16_s9

Instantiation

Definition at line 221 of file ram_1swsr_xfirst_gen_unisim.vhd.

mem [7/9]

mem ramb16_s4

Instantiation

Definition at line 250 of file ram_1swsr_xfirst_gen_unisim.vhd.

mem [8/9]

mem ramb16_s2

Instantiation

Definition at line 282 of file ram_1swsr_xfirst_gen_unisim.vhd.

mem [9/9]

mem ramb16_s1

Instantiation

Definition at line 304 of file ram_1swsr_xfirst_gen_unisim.vhd.

---

The documentation for this design unit was generated from the following file:

• vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd