syn Architecture Reference

Architecture >> syn

Processes
proc_clk	( CLK )

Constants
memsize	positive := 2 ** AWIDTH
datzero	slv ( DWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Types
ram_type	( memsize - 1 downto 0 ) slv ( DWIDTH - 1 downto 0 )

Signals
RAM	ram_type := ( others = > datzero )

Attributes
ram_style	string
ram_style	signal is " distributed "

Instantiations
mem	ram16x1s
mem	ram32x1s
mem	ram64x1s

Detailed Description

Definition at line 51 of file ram_1swar_gen.vhd.

Member Function/Procedure/Process Documentation

proc_clk()

proc_clk (   CLK   )

Process

Definition at line 62 of file ram_1swar_gen.vhd.

Member Data Documentation

memsize

memsize positive := 2 ** AWIDTH

Constant

Definition at line 52 of file ram_1swar_gen.vhd.

datzero

datzero slv ( DWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Constant

Definition at line 53 of file ram_1swar_gen.vhd.

ram_type

ram_type ( memsize - 1 downto 0 ) slv ( DWIDTH - 1 downto 0 )

Type

Definition at line 54 of file ram_1swar_gen.vhd.

RAM

RAM ram_type := ( others = > datzero )

Signal

Definition at line 55 of file ram_1swar_gen.vhd.

ram_style [1/2]

ram_style string

Attribute

Definition at line 57 of file ram_1swar_gen.vhd.

ram_style [2/2]

ram_style signal is " distributed "

Attribute

Definition at line 58 of file ram_1swar_gen.vhd.

mem [1/3]

mem ram16x1s

Instantiation

Definition at line 66 of file ram_1swar_gen_unisim.vhd.

mem [2/3]

mem ram32x1s

Instantiation

Definition at line 85 of file ram_1swar_gen_unisim.vhd.

mem [3/3]

mem ram64x1s

Instantiation

Definition at line 105 of file ram_1swar_gen_unisim.vhd.

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The documentation for this design unit was generated from the following file:

• vlib/memlib/ram_1swar_gen.vhd