Inheritance diagram for migui_arty_mig:

[legend]

Entities
arch_migui_arty_mig	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Generics
BANK_WIDTH	integer := 3
CK_WIDTH	integer := 1
COL_WIDTH	integer := 10
CS_WIDTH	integer := 1
nCS_PER_RANK	integer := 1
CKE_WIDTH	integer := 1
DATA_BUF_ADDR_WIDTH	integer := 5
DQ_CNT_WIDTH	integer := 4
DQ_PER_DM	integer := 8
DM_WIDTH	integer := 2
DQ_WIDTH	integer := 16
DQS_WIDTH	integer := 2
DQS_CNT_WIDTH	integer := 1
DRAM_WIDTH	integer := 8
ECC	string := " OFF "
ECC_TEST	string := " OFF "
DATA_WIDTH	integer := 16
PAYLOAD_WIDTH	integer := 16
MEM_ADDR_ORDER	string := " ROW_BANK_COLUMN "
nBANK_MACHS	integer := 2
RANKS	integer := 1
ODT_WIDTH	integer := 1
ROW_WIDTH	integer := 14
ADDR_WIDTH	integer := 28
USE_CS_PORT	integer := 1
USE_DM_PORT	integer := 1
USE_ODT_PORT	integer := 1
PHY_CONTROL_MASTER_BANK	integer := 0
MEM_DENSITY	string := " 2Gb "
MEM_SPEEDGRADE	string := " 15E "
MEM_DEVICE_WIDTH	integer := 16
AL	string := " 0 "
nAL	integer := 0
BURST_MODE	string := " 8 "
BURST_TYPE	string := " SEQ "
CL	integer := 5
CWL	integer := 5
OUTPUT_DRV	string := " LOW "
RTT_NOM	string := " 40 "
RTT_WR	string := " OFF "
ADDR_CMD_MODE	string := " 1T "
REG_CTRL	string := " OFF "
CA_MIRROR	string := " OFF "
VDD_OP_VOLT	string := " 135 "
CLKIN_PERIOD	integer := 6000
CLKFBOUT_MULT	integer := 8
DIVCLK_DIVIDE	integer := 1
CLKOUT0_PHASE	real := 0 . 0
CLKOUT0_DIVIDE	integer := 2
CLKOUT1_DIVIDE	integer := 4
CLKOUT2_DIVIDE	integer := 64
CLKOUT3_DIVIDE	integer := 16
MMCM_VCO	integer := 666
MMCM_MULT_F	integer := 8
MMCM_DIVCLK_DIVIDE	integer := 1
tCKE	integer := 5625
tFAW	integer := 45000
tPRDI	integer := 1000000
tRAS	integer := 36000
tRCD	integer := 13500
tREFI	integer := 7800000
tRFC	integer := 160000
tRP	integer := 13500
tRRD	integer := 7500
tRTP	integer := 7500
tWTR	integer := 7500
tZQI	integer := 128000000
tZQCS	integer := 64
SIM_BYPASS_INIT_CAL	string := " OFF "
SIMULATION	string := " FALSE "
BYTE_LANES_B0	std_logic_vector ( 3 downto 0 ) := " 1111 "
BYTE_LANES_B1	std_logic_vector ( 3 downto 0 ) := " 0000 "
BYTE_LANES_B2	std_logic_vector ( 3 downto 0 ) := " 0000 "
BYTE_LANES_B3	std_logic_vector ( 3 downto 0 ) := " 0000 "
BYTE_LANES_B4	std_logic_vector ( 3 downto 0 ) := " 0000 "
DATA_CTL_B0	std_logic_vector ( 3 downto 0 ) := " 1100 "
DATA_CTL_B1	std_logic_vector ( 3 downto 0 ) := " 0000 "
DATA_CTL_B2	std_logic_vector ( 3 downto 0 ) := " 0000 "
DATA_CTL_B3	std_logic_vector ( 3 downto 0 ) := " 0000 "
DATA_CTL_B4	std_logic_vector ( 3 downto 0 ) := " 0000 "
PHY_0_BITLANES	std_logic_vector ( 47 downto 0 ) := X " 3FE3FEFFFBFF "
PHY_1_BITLANES	std_logic_vector ( 47 downto 0 ) := X " 000000000000 "
PHY_2_BITLANES	std_logic_vector ( 47 downto 0 ) := X " 000000000000 "
CK_BYTE_MAP	std_logic_vector ( 143 downto 0 ) := X " 000000000000000000000000000000000000 "
ADDR_MAP	std_logic_vector ( 191 downto 0 ) := X " 00000000000200400900700100500600301001201401101A "
BANK_MAP	std_logic_vector ( 35 downto 0 ) := X " 01B017013 "
CAS_MAP	std_logic_vector ( 11 downto 0 ) := X " 015 "
CKE_ODT_BYTE_MAP	std_logic_vector ( 7 downto 0 ) := X " 00 "
CKE_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000019 "
ODT_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000008 "
CS_MAP	std_logic_vector ( 119 downto 0 ) := X " 00000000000000000000000000000B "
PARITY_MAP	std_logic_vector ( 11 downto 0 ) := X " 000 "
RAS_MAP	std_logic_vector ( 11 downto 0 ) := X " 016 "
WE_MAP	std_logic_vector ( 11 downto 0 ) := X " 018 "
DQS_BYTE_MAP	std_logic_vector ( 143 downto 0 ) := X " 000000000000000000000000000000000203 "
DATA0_MAP	std_logic_vector ( 95 downto 0 ) := X " 034032038035031037036033 "
DATA1_MAP	std_logic_vector ( 95 downto 0 ) := X " 023026022028025027021024 "
DATA2_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA3_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA4_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA5_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA6_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA7_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA8_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA9_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA10_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA11_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA12_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA13_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA14_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA15_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA16_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
DATA17_MAP	std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "
MASK0_MAP	std_logic_vector ( 107 downto 0 ) := X " 000000000000000000000029039 "
MASK1_MAP	std_logic_vector ( 107 downto 0 ) := X " 000000000000000000000000000 "
SLOT_0_CONFIG	std_logic_vector ( 7 downto 0 ) := " 00000001 "
SLOT_1_CONFIG	std_logic_vector ( 7 downto 0 ) := " 00000000 "
IBUF_LPWR_MODE	string := " OFF "
DATA_IO_IDLE_PWRDWN	string := " OFF "
BANK_TYPE	string := " HR_IO "
DATA_IO_PRIM_TYPE	string := " DEFAULT "
CKE_ODT_AUX	string := " FALSE "
USER_REFRESH	string := " OFF "
WRLVL	string := " ON "
ORDERING	string := " STRICT "
CALIB_ROW_ADD	std_logic_vector ( 15 downto 0 ) := X " 0000 "
CALIB_COL_ADD	std_logic_vector ( 11 downto 0 ) := X " 000 "
CALIB_BA_ADD	std_logic_vector ( 2 downto 0 ) := " 000 "
TCQ	integer := 100
IDELAY_ADJ	string := " OFF "
FINE_PER_BIT	string := " OFF "
CENTER_COMP_MODE	string := " OFF "
PI_VAL_ADJ	string := " OFF "
IODELAY_GRP0	string := " MIGUI_ARTY_IODELAY_MIG0 "
IODELAY_GRP1	string := " MIGUI_ARTY_IODELAY_MIG1 "
SYSCLK_TYPE	string := " NO_BUFFER "
REFCLK_TYPE	string := " NO_BUFFER "
SYS_RST_PORT	string := " FALSE "
FPGA_SPEED_GRADE	integer := 1
CMD_PIPE_PLUS1	string := " ON "
DRAM_TYPE	string := " DDR3 "
CAL_WIDTH	string := " HALF "
STARVE_LIMIT	integer := 2
REF_CLK_MMCM_IODELAY_CTRL	string := " FALSE "
REFCLK_FREQ	real := 200 . 0
DIFF_TERM_REFCLK	string := " TRUE "
tCK	integer := 3000
nCK_PER_CLK	integer := 4
DIFF_TERM_SYSCLK	string := " TRUE "
DEBUG_PORT	string := " OFF "
TEMP_MON_CONTROL	string := " EXTERNAL "
FPGA_VOLT_TYPE	string := " N "
RST_ACT_LOW	integer := 0

Ports
ddr3_dq	inout	std_logic_vector ( DQ_WIDTH - 1 downto 0 )
ddr3_dqs_p	inout	std_logic_vector ( DQS_WIDTH - 1 downto 0 )
ddr3_dqs_n	inout	std_logic_vector ( DQS_WIDTH - 1 downto 0 )
ddr3_addr	out	std_logic_vector ( ROW_WIDTH - 1 downto 0 )
ddr3_ba	out	std_logic_vector ( BANK_WIDTH - 1 downto 0 )
ddr3_ras_n	out	std_logic
ddr3_cas_n	out	std_logic
ddr3_we_n	out	std_logic
ddr3_reset_n	out	std_logic
ddr3_ck_p	out	std_logic_vector ( CK_WIDTH - 1 downto 0 )
ddr3_ck_n	out	std_logic_vector ( CK_WIDTH - 1 downto 0 )
ddr3_cke	out	std_logic_vector ( CKE_WIDTH - 1 downto 0 )
ddr3_cs_n	out	std_logic_vector ( ( CS_WIDTH** * nCS_PER_RANK ) - 1 downto 0 )**
ddr3_dm	out	std_logic_vector ( DM_WIDTH - 1 downto 0 )
ddr3_odt	out	std_logic_vector ( ODT_WIDTH - 1 downto 0 )
sys_clk_i	in	std_logic
clk_ref_i	in	std_logic
app_addr	in	std_logic_vector ( ADDR_WIDTH - 1 downto 0 )
app_cmd	in	std_logic_vector ( 2 downto 0 )
app_en	in	std_logic
app_wdf_data	in	std_logic_vector ( ( nCK_PER_CLK** * 2 * PAYLOAD_WIDTH ) - 1 downto 0 )**
app_wdf_end	in	std_logic
app_wdf_mask	in	std_logic_vector ( ( ( nCK_PER_CLK** * 2 * PAYLOAD_WIDTH ) / 8 ) - 1 downto 0 )**
app_wdf_wren	in	std_logic
app_rd_data	out	std_logic_vector ( ( nCK_PER_CLK** * 2 * PAYLOAD_WIDTH ) - 1 downto 0 )**
app_rd_data_end	out	std_logic
app_rd_data_valid	out	std_logic
app_rdy	out	std_logic
app_wdf_rdy	out	std_logic
app_sr_req	in	std_logic
app_ref_req	in	std_logic
app_zq_req	in	std_logic
app_sr_active	out	std_logic
app_ref_ack	out	std_logic
app_zq_ack	out	std_logic
ui_clk	out	std_logic
ui_clk_sync_rst	out	std_logic
init_calib_complete	out	std_logic
device_temp_i	in	std_logic_vector ( 11 downto 0 )
device_temp	out	std_logic_vector ( 11 downto 0 )
sys_rst	in	std_logic

Detailed Description

Definition at line 77 of file migui_arty_mig.vhd.

Member Data Documentation

◆ BANK_WIDTH

BANK_WIDTH integer := 3

Generic

Definition at line 82 of file migui_arty_mig.vhd.

◆ CK_WIDTH

CK_WIDTH integer := 1

Generic

Definition at line 84 of file migui_arty_mig.vhd.

◆ COL_WIDTH

COL_WIDTH integer := 10

Generic

Definition at line 86 of file migui_arty_mig.vhd.

◆ CS_WIDTH

CS_WIDTH integer := 1

Generic

Definition at line 88 of file migui_arty_mig.vhd.

◆ nCS_PER_RANK

nCS_PER_RANK integer := 1

Generic

Definition at line 90 of file migui_arty_mig.vhd.

◆ CKE_WIDTH

CKE_WIDTH integer := 1

Generic

Definition at line 92 of file migui_arty_mig.vhd.

◆ DATA_BUF_ADDR_WIDTH

DATA_BUF_ADDR_WIDTH integer := 5

Generic

Definition at line 94 of file migui_arty_mig.vhd.

◆ DQ_CNT_WIDTH

DQ_CNT_WIDTH integer := 4

Generic

Definition at line 95 of file migui_arty_mig.vhd.

◆ DQ_PER_DM

DQ_PER_DM integer := 8

Generic

Definition at line 97 of file migui_arty_mig.vhd.

◆ DM_WIDTH

DM_WIDTH integer := 2

Generic

Definition at line 98 of file migui_arty_mig.vhd.

◆ DQ_WIDTH

DQ_WIDTH integer := 16

Generic

Definition at line 100 of file migui_arty_mig.vhd.

◆ DQS_WIDTH

DQS_WIDTH integer := 2

Generic

Definition at line 102 of file migui_arty_mig.vhd.

◆ DQS_CNT_WIDTH

DQS_CNT_WIDTH integer := 1

Generic

Definition at line 103 of file migui_arty_mig.vhd.

◆ DRAM_WIDTH

DRAM_WIDTH integer := 8

Generic

Definition at line 105 of file migui_arty_mig.vhd.

◆ ECC

ECC string := " OFF "

Generic

Definition at line 107 of file migui_arty_mig.vhd.

◆ ECC_TEST

ECC_TEST string := " OFF "

Generic

Definition at line 108 of file migui_arty_mig.vhd.

◆ DATA_WIDTH

DATA_WIDTH integer := 16

Generic

Definition at line 109 of file migui_arty_mig.vhd.

◆ PAYLOAD_WIDTH

PAYLOAD_WIDTH integer := 16

Generic

Definition at line 110 of file migui_arty_mig.vhd.

◆ MEM_ADDR_ORDER

MEM_ADDR_ORDER string := " ROW_BANK_COLUMN "

Generic

Definition at line 111 of file migui_arty_mig.vhd.

◆ nBANK_MACHS

nBANK_MACHS integer := 2

Generic

Definition at line 120 of file migui_arty_mig.vhd.

◆ RANKS

RANKS integer := 1

Generic

Definition at line 121 of file migui_arty_mig.vhd.

◆ ODT_WIDTH

ODT_WIDTH integer := 1

Generic

Definition at line 123 of file migui_arty_mig.vhd.

◆ ROW_WIDTH

ROW_WIDTH integer := 14

Generic

Definition at line 125 of file migui_arty_mig.vhd.

◆ ADDR_WIDTH

ADDR_WIDTH integer := 28

Generic

Definition at line 127 of file migui_arty_mig.vhd.

◆ USE_CS_PORT

USE_CS_PORT integer := 1

Generic

Definition at line 132 of file migui_arty_mig.vhd.

◆ USE_DM_PORT

USE_DM_PORT integer := 1

Generic

Definition at line 137 of file migui_arty_mig.vhd.

◆ USE_ODT_PORT

USE_ODT_PORT integer := 1

Generic

Definition at line 144 of file migui_arty_mig.vhd.

◆ PHY_CONTROL_MASTER_BANK

PHY_CONTROL_MASTER_BANK integer := 0

Generic

Definition at line 151 of file migui_arty_mig.vhd.

◆ MEM_DENSITY

MEM_DENSITY string := " 2Gb "

Generic

Definition at line 154 of file migui_arty_mig.vhd.

◆ MEM_SPEEDGRADE

MEM_SPEEDGRADE string := " 15E "

Generic

Definition at line 157 of file migui_arty_mig.vhd.

◆ MEM_DEVICE_WIDTH

MEM_DEVICE_WIDTH integer := 16

Generic

Definition at line 160 of file migui_arty_mig.vhd.

◆ AL

AL string := " 0 "

Generic

Definition at line 167 of file migui_arty_mig.vhd.

◆ nAL

nAL integer := 0

Generic

Definition at line 173 of file migui_arty_mig.vhd.

◆ BURST_MODE

BURST_MODE string := " 8 "

Generic

Definition at line 176 of file migui_arty_mig.vhd.

◆ BURST_TYPE

BURST_TYPE string := " SEQ "

Generic

Definition at line 183 of file migui_arty_mig.vhd.

◆ CL

CL integer := 5

Generic

Definition at line 188 of file migui_arty_mig.vhd.

◆ CWL

CWL integer := 5

Generic

Definition at line 192 of file migui_arty_mig.vhd.

◆ OUTPUT_DRV

OUTPUT_DRV string := " LOW "

Generic

Definition at line 196 of file migui_arty_mig.vhd.

◆ RTT_NOM

RTT_NOM string := " 40 "

Generic

Definition at line 200 of file migui_arty_mig.vhd.

◆ RTT_WR

RTT_WR string := " OFF "

Generic

Definition at line 205 of file migui_arty_mig.vhd.

◆ ADDR_CMD_MODE

ADDR_CMD_MODE string := " 1T "

Generic

Definition at line 210 of file migui_arty_mig.vhd.

◆ REG_CTRL

REG_CTRL string := " OFF "

Generic

Definition at line 212 of file migui_arty_mig.vhd.

◆ CA_MIRROR

CA_MIRROR string := " OFF "

Generic

Definition at line 215 of file migui_arty_mig.vhd.

◆ VDD_OP_VOLT

VDD_OP_VOLT string := " 135 "

Generic

Definition at line 217 of file migui_arty_mig.vhd.

◆ CLKIN_PERIOD

CLKIN_PERIOD integer := 6000

Generic

Definition at line 225 of file migui_arty_mig.vhd.

◆ CLKFBOUT_MULT

CLKFBOUT_MULT integer := 8

Generic

Definition at line 227 of file migui_arty_mig.vhd.

◆ DIVCLK_DIVIDE

DIVCLK_DIVIDE integer := 1

Generic

Definition at line 229 of file migui_arty_mig.vhd.

◆ CLKOUT0_PHASE

CLKOUT0_PHASE real := 0 . 0

Generic

Definition at line 231 of file migui_arty_mig.vhd.

◆ CLKOUT0_DIVIDE

CLKOUT0_DIVIDE integer := 2

Generic

Definition at line 233 of file migui_arty_mig.vhd.

◆ CLKOUT1_DIVIDE

CLKOUT1_DIVIDE integer := 4

Generic

Definition at line 235 of file migui_arty_mig.vhd.

◆ CLKOUT2_DIVIDE

CLKOUT2_DIVIDE integer := 64

Generic

Definition at line 237 of file migui_arty_mig.vhd.

◆ CLKOUT3_DIVIDE

CLKOUT3_DIVIDE integer := 16

Generic

Definition at line 239 of file migui_arty_mig.vhd.

◆ MMCM_VCO

MMCM_VCO integer := 666

Generic

Definition at line 241 of file migui_arty_mig.vhd.

◆ MMCM_MULT_F

MMCM_MULT_F integer := 8

Generic

Definition at line 243 of file migui_arty_mig.vhd.

◆ MMCM_DIVCLK_DIVIDE

MMCM_DIVCLK_DIVIDE integer := 1

Generic

Definition at line 245 of file migui_arty_mig.vhd.

◆ tCKE

tCKE integer := 5625

Generic

Definition at line 252 of file migui_arty_mig.vhd.

◆ tFAW

tFAW integer := 45000

Generic

Definition at line 254 of file migui_arty_mig.vhd.

◆ tPRDI

tPRDI integer := 1000000

Generic

Definition at line 256 of file migui_arty_mig.vhd.

◆ tRAS

tRAS integer := 36000

Generic

Definition at line 258 of file migui_arty_mig.vhd.

◆ tRCD

tRCD integer := 13500

Generic

Definition at line 260 of file migui_arty_mig.vhd.

◆ tREFI

tREFI integer := 7800000

Generic

Definition at line 262 of file migui_arty_mig.vhd.

◆ tRFC

tRFC integer := 160000

Generic

Definition at line 264 of file migui_arty_mig.vhd.

◆ tRP

tRP integer := 13500

Generic

Definition at line 266 of file migui_arty_mig.vhd.

◆ tRRD

tRRD integer := 7500

Generic

Definition at line 268 of file migui_arty_mig.vhd.

◆ tRTP

tRTP integer := 7500

Generic

Definition at line 270 of file migui_arty_mig.vhd.

◆ tWTR

tWTR integer := 7500

Generic

Definition at line 272 of file migui_arty_mig.vhd.

◆ tZQI

tZQI integer := 128000000

Generic

Definition at line 274 of file migui_arty_mig.vhd.

◆ tZQCS

tZQCS integer := 64

Generic

Definition at line 276 of file migui_arty_mig.vhd.

◆ SIM_BYPASS_INIT_CAL

SIM_BYPASS_INIT_CAL string := " OFF "

Generic

Definition at line 282 of file migui_arty_mig.vhd.

◆ SIMULATION

SIMULATION string := " FALSE "

Generic

Definition at line 289 of file migui_arty_mig.vhd.

◆ BYTE_LANES_B0

BYTE_LANES_B0 std_logic_vector ( 3 downto 0 ) := " 1111 "

Generic

Definition at line 298 of file migui_arty_mig.vhd.

◆ BYTE_LANES_B1

BYTE_LANES_B1 std_logic_vector ( 3 downto 0 ) := " 0000 "

Generic

Definition at line 300 of file migui_arty_mig.vhd.

◆ BYTE_LANES_B2

BYTE_LANES_B2 std_logic_vector ( 3 downto 0 ) := " 0000 "

Generic

Definition at line 302 of file migui_arty_mig.vhd.

◆ BYTE_LANES_B3

BYTE_LANES_B3 std_logic_vector ( 3 downto 0 ) := " 0000 "

Generic

Definition at line 304 of file migui_arty_mig.vhd.

◆ BYTE_LANES_B4

BYTE_LANES_B4 std_logic_vector ( 3 downto 0 ) := " 0000 "

Generic

Definition at line 306 of file migui_arty_mig.vhd.

◆ DATA_CTL_B0

DATA_CTL_B0 std_logic_vector ( 3 downto 0 ) := " 1100 "

Generic

Definition at line 308 of file migui_arty_mig.vhd.

◆ DATA_CTL_B1

DATA_CTL_B1 std_logic_vector ( 3 downto 0 ) := " 0000 "

Generic

Definition at line 313 of file migui_arty_mig.vhd.

◆ DATA_CTL_B2

DATA_CTL_B2 std_logic_vector ( 3 downto 0 ) := " 0000 "

Generic

Definition at line 318 of file migui_arty_mig.vhd.

◆ DATA_CTL_B3

DATA_CTL_B3 std_logic_vector ( 3 downto 0 ) := " 0000 "

Generic

Definition at line 323 of file migui_arty_mig.vhd.

◆ DATA_CTL_B4

DATA_CTL_B4 std_logic_vector ( 3 downto 0 ) := " 0000 "

Generic

Definition at line 328 of file migui_arty_mig.vhd.

◆ PHY_0_BITLANES

PHY_0_BITLANES std_logic_vector ( 47 downto 0 ) := X " 3FE3FEFFFBFF "

Generic

Definition at line 333 of file migui_arty_mig.vhd.

◆ PHY_1_BITLANES

PHY_1_BITLANES std_logic_vector ( 47 downto 0 ) := X " 000000000000 "

Generic

Definition at line 334 of file migui_arty_mig.vhd.

◆ PHY_2_BITLANES

PHY_2_BITLANES std_logic_vector ( 47 downto 0 ) := X " 000000000000 "

Generic

Definition at line 335 of file migui_arty_mig.vhd.

◆ CK_BYTE_MAP

CK_BYTE_MAP std_logic_vector ( 143 downto 0 ) := X " 000000000000000000000000000000000000 "

Generic

Definition at line 339 of file migui_arty_mig.vhd.

◆ ADDR_MAP

ADDR_MAP std_logic_vector ( 191 downto 0 ) := X " 00000000000200400900700100500600301001201401101A "

Generic

Definition at line 341 of file migui_arty_mig.vhd.

◆ BANK_MAP

BANK_MAP std_logic_vector ( 35 downto 0 ) := X " 01B017013 "

Generic

Definition at line 342 of file migui_arty_mig.vhd.

◆ CAS_MAP

CAS_MAP std_logic_vector ( 11 downto 0 ) := X " 015 "

Generic

Definition at line 343 of file migui_arty_mig.vhd.

◆ CKE_ODT_BYTE_MAP

CKE_ODT_BYTE_MAP std_logic_vector ( 7 downto 0 ) := X " 00 "

Generic

Definition at line 344 of file migui_arty_mig.vhd.

◆ CKE_MAP

CKE_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000019 "

Generic

Definition at line 345 of file migui_arty_mig.vhd.

◆ ODT_MAP

ODT_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000008 "

Generic

Definition at line 346 of file migui_arty_mig.vhd.

◆ CS_MAP

CS_MAP std_logic_vector ( 119 downto 0 ) := X " 00000000000000000000000000000B "

Generic

Definition at line 347 of file migui_arty_mig.vhd.

◆ PARITY_MAP

PARITY_MAP std_logic_vector ( 11 downto 0 ) := X " 000 "

Generic

Definition at line 348 of file migui_arty_mig.vhd.

◆ RAS_MAP

RAS_MAP std_logic_vector ( 11 downto 0 ) := X " 016 "

Generic

Definition at line 349 of file migui_arty_mig.vhd.

◆ WE_MAP

WE_MAP std_logic_vector ( 11 downto 0 ) := X " 018 "

Generic

Definition at line 350 of file migui_arty_mig.vhd.

◆ DQS_BYTE_MAP

DQS_BYTE_MAP std_logic_vector ( 143 downto 0 ) := X " 000000000000000000000000000000000203 "

Generic

Definition at line 352 of file migui_arty_mig.vhd.

◆ DATA0_MAP

DATA0_MAP std_logic_vector ( 95 downto 0 ) := X " 034032038035031037036033 "

Generic

Definition at line 353 of file migui_arty_mig.vhd.

◆ DATA1_MAP

DATA1_MAP std_logic_vector ( 95 downto 0 ) := X " 023026022028025027021024 "

Generic

Definition at line 354 of file migui_arty_mig.vhd.

◆ DATA2_MAP

DATA2_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "

Generic

Definition at line 355 of file migui_arty_mig.vhd.

◆ DATA3_MAP

DATA3_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "

Generic

Definition at line 356 of file migui_arty_mig.vhd.

◆ DATA4_MAP

DATA4_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "

Generic

Definition at line 357 of file migui_arty_mig.vhd.

◆ DATA5_MAP

DATA5_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "

Generic

Definition at line 358 of file migui_arty_mig.vhd.

◆ DATA6_MAP

DATA6_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "

Generic

Definition at line 359 of file migui_arty_mig.vhd.

◆ DATA7_MAP

DATA7_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "

Generic

Definition at line 360 of file migui_arty_mig.vhd.

◆ DATA8_MAP

DATA8_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "

Generic

Definition at line 361 of file migui_arty_mig.vhd.

◆ DATA9_MAP

DATA9_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "

Generic

Definition at line 362 of file migui_arty_mig.vhd.

◆ DATA10_MAP

DATA10_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "

Generic

Definition at line 363 of file migui_arty_mig.vhd.

◆ DATA11_MAP

DATA11_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "

Generic

Definition at line 364 of file migui_arty_mig.vhd.

◆ DATA12_MAP

DATA12_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "

Generic

Definition at line 365 of file migui_arty_mig.vhd.

◆ DATA13_MAP

DATA13_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "

Generic

Definition at line 366 of file migui_arty_mig.vhd.

◆ DATA14_MAP

DATA14_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "

Generic

Definition at line 367 of file migui_arty_mig.vhd.

◆ DATA15_MAP

DATA15_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "

Generic

Definition at line 368 of file migui_arty_mig.vhd.

◆ DATA16_MAP

DATA16_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "

Generic

Definition at line 369 of file migui_arty_mig.vhd.

◆ DATA17_MAP

DATA17_MAP std_logic_vector ( 95 downto 0 ) := X " 000000000000000000000000 "

Generic

Definition at line 370 of file migui_arty_mig.vhd.

◆ MASK0_MAP

MASK0_MAP std_logic_vector ( 107 downto 0 ) := X " 000000000000000000000029039 "

Generic

Definition at line 371 of file migui_arty_mig.vhd.

◆ MASK1_MAP

MASK1_MAP std_logic_vector ( 107 downto 0 ) := X " 000000000000000000000000000 "

Generic

Definition at line 372 of file migui_arty_mig.vhd.

◆ SLOT_0_CONFIG

SLOT_0_CONFIG std_logic_vector ( 7 downto 0 ) := " 00000001 "

Generic

Definition at line 374 of file migui_arty_mig.vhd.

◆ SLOT_1_CONFIG

SLOT_1_CONFIG std_logic_vector ( 7 downto 0 ) := " 00000000 "

Generic

Definition at line 376 of file migui_arty_mig.vhd.

◆ IBUF_LPWR_MODE

IBUF_LPWR_MODE string := " OFF "

Generic

Definition at line 382 of file migui_arty_mig.vhd.

◆ DATA_IO_IDLE_PWRDWN

DATA_IO_IDLE_PWRDWN string := " OFF "

Generic

Definition at line 384 of file migui_arty_mig.vhd.

◆ BANK_TYPE

BANK_TYPE string := " HR_IO "

Generic

Definition at line 386 of file migui_arty_mig.vhd.

◆ DATA_IO_PRIM_TYPE

DATA_IO_PRIM_TYPE string := " DEFAULT "

Generic

Definition at line 388 of file migui_arty_mig.vhd.

◆ CKE_ODT_AUX

CKE_ODT_AUX string := " FALSE "

Generic

Definition at line 390 of file migui_arty_mig.vhd.

◆ USER_REFRESH

USER_REFRESH string := " OFF "

Generic

Definition at line 391 of file migui_arty_mig.vhd.

◆ WRLVL

WRLVL string := " ON "

Generic

Definition at line 392 of file migui_arty_mig.vhd.

◆ ORDERING

ORDERING string := " STRICT "

Generic

Definition at line 395 of file migui_arty_mig.vhd.

◆ CALIB_ROW_ADD

CALIB_ROW_ADD std_logic_vector ( 15 downto 0 ) := X " 0000 "

Generic

Definition at line 397 of file migui_arty_mig.vhd.

◆ CALIB_COL_ADD

CALIB_COL_ADD std_logic_vector ( 11 downto 0 ) := X " 000 "

Generic

Definition at line 400 of file migui_arty_mig.vhd.

◆ CALIB_BA_ADD

CALIB_BA_ADD std_logic_vector ( 2 downto 0 ) := " 000 "

Generic

Definition at line 403 of file migui_arty_mig.vhd.

◆ TCQ

TCQ integer := 100

Generic

Definition at line 406 of file migui_arty_mig.vhd.

◆ IDELAY_ADJ

IDELAY_ADJ string := " OFF "

Generic

Definition at line 407 of file migui_arty_mig.vhd.

◆ FINE_PER_BIT

FINE_PER_BIT string := " OFF "

Generic

Definition at line 408 of file migui_arty_mig.vhd.

◆ CENTER_COMP_MODE

CENTER_COMP_MODE string := " OFF "

Generic

Definition at line 409 of file migui_arty_mig.vhd.

◆ PI_VAL_ADJ

PI_VAL_ADJ string := " OFF "

Generic

Definition at line 410 of file migui_arty_mig.vhd.

◆ IODELAY_GRP0

IODELAY_GRP0 string := " MIGUI_ARTY_IODELAY_MIG0 "

Generic

Definition at line 411 of file migui_arty_mig.vhd.

◆ IODELAY_GRP1

IODELAY_GRP1 string := " MIGUI_ARTY_IODELAY_MIG1 "

Generic

Definition at line 415 of file migui_arty_mig.vhd.

◆ SYSCLK_TYPE

SYSCLK_TYPE string := " NO_BUFFER "

Generic

Definition at line 419 of file migui_arty_mig.vhd.

◆ REFCLK_TYPE

REFCLK_TYPE string := " NO_BUFFER "

Generic

Definition at line 422 of file migui_arty_mig.vhd.

◆ SYS_RST_PORT

SYS_RST_PORT string := " FALSE "

Generic

Definition at line 425 of file migui_arty_mig.vhd.

◆ FPGA_SPEED_GRADE

FPGA_SPEED_GRADE integer := 1

Generic

Definition at line 430 of file migui_arty_mig.vhd.

◆ CMD_PIPE_PLUS1

CMD_PIPE_PLUS1 string := " ON "

Generic

Definition at line 433 of file migui_arty_mig.vhd.

◆ DRAM_TYPE

DRAM_TYPE string := " DDR3 "

Generic

Definition at line 436 of file migui_arty_mig.vhd.

◆ CAL_WIDTH

CAL_WIDTH string := " HALF "

Generic

Definition at line 437 of file migui_arty_mig.vhd.

◆ STARVE_LIMIT

STARVE_LIMIT integer := 2

Generic

Definition at line 438 of file migui_arty_mig.vhd.

◆ REF_CLK_MMCM_IODELAY_CTRL

REF_CLK_MMCM_IODELAY_CTRL string := " FALSE "

Generic

Definition at line 440 of file migui_arty_mig.vhd.

◆ REFCLK_FREQ

REFCLK_FREQ real := 200 . 0

Generic

Definition at line 445 of file migui_arty_mig.vhd.

◆ DIFF_TERM_REFCLK

DIFF_TERM_REFCLK string := " TRUE "

Generic

Definition at line 447 of file migui_arty_mig.vhd.

◆ tCK

tCK integer := 3000

Generic

Definition at line 453 of file migui_arty_mig.vhd.

◆ nCK_PER_CLK

nCK_PER_CLK integer := 4

Generic

Definition at line 456 of file migui_arty_mig.vhd.

◆ DIFF_TERM_SYSCLK

DIFF_TERM_SYSCLK string := " TRUE "

Generic

Definition at line 458 of file migui_arty_mig.vhd.

◆ DEBUG_PORT

DEBUG_PORT string := " OFF "

Generic

Definition at line 465 of file migui_arty_mig.vhd.

◆ TEMP_MON_CONTROL

TEMP_MON_CONTROL string := " EXTERNAL "

Generic

Definition at line 472 of file migui_arty_mig.vhd.

◆ FPGA_VOLT_TYPE

FPGA_VOLT_TYPE string := " N "

Generic

Definition at line 477 of file migui_arty_mig.vhd.

◆ RST_ACT_LOW

RST_ACT_LOW integer := 0

Generic

Definition at line 484 of file migui_arty_mig.vhd.

◆ ddr3_dq

ddr3_dq inout std_logic_vector ( DQ_WIDTH - 1 downto 0 )

Port

Definition at line 488 of file migui_arty_mig.vhd.

◆ ddr3_dqs_p

ddr3_dqs_p inout std_logic_vector ( DQS_WIDTH - 1 downto 0 )

Port

Definition at line 489 of file migui_arty_mig.vhd.

◆ ddr3_dqs_n

ddr3_dqs_n inout std_logic_vector ( DQS_WIDTH - 1 downto 0 )

Port

Definition at line 490 of file migui_arty_mig.vhd.

◆ ddr3_addr

ddr3_addr out std_logic_vector ( ROW_WIDTH - 1 downto 0 )

Port

Definition at line 493 of file migui_arty_mig.vhd.

◆ ddr3_ba

ddr3_ba out std_logic_vector ( BANK_WIDTH - 1 downto 0 )

Port

Definition at line 494 of file migui_arty_mig.vhd.

◆ ddr3_ras_n

ddr3_ras_n out std_logic

Port

Definition at line 495 of file migui_arty_mig.vhd.

◆ ddr3_cas_n

ddr3_cas_n out std_logic

Port

Definition at line 496 of file migui_arty_mig.vhd.

◆ ddr3_we_n

ddr3_we_n out std_logic

Port

Definition at line 497 of file migui_arty_mig.vhd.

◆ ddr3_reset_n

ddr3_reset_n out std_logic

Port

Definition at line 498 of file migui_arty_mig.vhd.

◆ ddr3_ck_p

ddr3_ck_p out std_logic_vector ( CK_WIDTH - 1 downto 0 )

Port

Definition at line 499 of file migui_arty_mig.vhd.

◆ ddr3_ck_n

ddr3_ck_n out std_logic_vector ( CK_WIDTH - 1 downto 0 )

Port

Definition at line 500 of file migui_arty_mig.vhd.

◆ ddr3_cke

ddr3_cke out std_logic_vector ( CKE_WIDTH - 1 downto 0 )

Port

Definition at line 501 of file migui_arty_mig.vhd.

◆ ddr3_cs_n

ddr3_cs_n out std_logic_vector ( ( CS_WIDTH * nCS_PER_RANK ) - 1 downto 0 )

Port

Definition at line 502 of file migui_arty_mig.vhd.

◆ ddr3_dm

ddr3_dm out std_logic_vector ( DM_WIDTH - 1 downto 0 )

Port

Definition at line 503 of file migui_arty_mig.vhd.

◆ ddr3_odt

ddr3_odt out std_logic_vector ( ODT_WIDTH - 1 downto 0 )

Port

Definition at line 504 of file migui_arty_mig.vhd.

◆ sys_clk_i

sys_clk_i in std_logic

Port

Definition at line 508 of file migui_arty_mig.vhd.

◆ clk_ref_i

clk_ref_i in std_logic

Port

Definition at line 510 of file migui_arty_mig.vhd.

◆ app_addr

app_addr in std_logic_vector ( ADDR_WIDTH - 1 downto 0 )

Port

Definition at line 512 of file migui_arty_mig.vhd.

◆ app_cmd

app_cmd in std_logic_vector ( 2 downto 0 )

Port

Definition at line 513 of file migui_arty_mig.vhd.

◆ app_en

app_en in std_logic

Port

Definition at line 514 of file migui_arty_mig.vhd.

◆ app_wdf_data

app_wdf_data in std_logic_vector ( ( nCK_PER_CLK * 2 * PAYLOAD_WIDTH ) - 1 downto 0 )

Port

Definition at line 515 of file migui_arty_mig.vhd.

◆ app_wdf_end

app_wdf_end in std_logic

Port

Definition at line 516 of file migui_arty_mig.vhd.

◆ app_wdf_mask

app_wdf_mask in std_logic_vector ( ( ( nCK_PER_CLK * 2 * PAYLOAD_WIDTH ) / 8 ) - 1 downto 0 )

Port

Definition at line 517 of file migui_arty_mig.vhd.

◆ app_wdf_wren

app_wdf_wren in std_logic

Port

Definition at line 518 of file migui_arty_mig.vhd.

◆ app_rd_data

app_rd_data out std_logic_vector ( ( nCK_PER_CLK * 2 * PAYLOAD_WIDTH ) - 1 downto 0 )

Port

Definition at line 519 of file migui_arty_mig.vhd.

◆ app_rd_data_end

app_rd_data_end out std_logic

Port

Definition at line 520 of file migui_arty_mig.vhd.

◆ app_rd_data_valid

app_rd_data_valid out std_logic

Port

Definition at line 521 of file migui_arty_mig.vhd.

◆ app_rdy

app_rdy out std_logic

Port

Definition at line 522 of file migui_arty_mig.vhd.

◆ app_wdf_rdy

app_wdf_rdy out std_logic

Port

Definition at line 523 of file migui_arty_mig.vhd.

◆ app_sr_req

app_sr_req in std_logic

Port

Definition at line 524 of file migui_arty_mig.vhd.

◆ app_ref_req

app_ref_req in std_logic

Port

Definition at line 525 of file migui_arty_mig.vhd.

◆ app_zq_req

app_zq_req in std_logic

Port

Definition at line 526 of file migui_arty_mig.vhd.

◆ app_sr_active

app_sr_active out std_logic

Port

Definition at line 527 of file migui_arty_mig.vhd.

◆ app_ref_ack

app_ref_ack out std_logic

Port

Definition at line 528 of file migui_arty_mig.vhd.

◆ app_zq_ack

app_zq_ack out std_logic

Port

Definition at line 529 of file migui_arty_mig.vhd.

◆ ui_clk

ui_clk out std_logic

Port

Definition at line 530 of file migui_arty_mig.vhd.

◆ ui_clk_sync_rst

ui_clk_sync_rst out std_logic

Port

Definition at line 531 of file migui_arty_mig.vhd.

◆ init_calib_complete

init_calib_complete out std_logic

Port

Definition at line 534 of file migui_arty_mig.vhd.

◆ device_temp_i

device_temp_i in std_logic_vector ( 11 downto 0 )

Port

Definition at line 535 of file migui_arty_mig.vhd.

◆ device_temp

device_temp out std_logic_vector ( 11 downto 0 )

Port

Definition at line 539 of file migui_arty_mig.vhd.

◆ sys_rst

sys_rst in std_logic

Port

Definition at line 546 of file migui_arty_mig.vhd.

◆ ieee

ieee

Library

Definition at line 72 of file migui_arty_mig.vhd.

◆ std_logic_1164

std_logic_1164

use clause

Definition at line 73 of file migui_arty_mig.vhd.

◆ numeric_std

numeric_std

use clause

Definition at line 74 of file migui_arty_mig.vhd.

The documentation for this design unit was generated from the following files:

sys_gen/tst_mig/arty/project_mflow/project_mflow.gen/sources_1/ip/migui_arty/migui_arty/user_design/rtl/migui_arty_mig.vhd
sys_gen/tst_mig/arty/project_mflow/project_mflow.gen/sources_1/ip/migui_arty/migui_arty/user_design/rtl/migui_arty_mig_sim.vhd
sys_gen/tst_sram/arty/project_mflow/project_mflow.gen/sources_1/ip/migui_arty/migui_arty/user_design/rtl/migui_arty_mig.vhd
sys_gen/tst_sram/arty/project_mflow/project_mflow.gen/sources_1/ip/migui_arty/migui_arty/user_design/rtl/migui_arty_mig_sim.vhd
sys_gen/w11a/arty/project_mflow/project_mflow.gen/sources_1/ip/migui_arty/migui_arty/user_design/rtl/migui_arty_mig.vhd
sys_gen/w11a/arty/project_mflow/project_mflow.gen/sources_1/ip/migui_arty/migui_arty/user_design/rtl/migui_arty_mig_sim.vhd

Entities

Libraries

Use Clauses

Generics

Ports

Detailed Description

Member Data Documentation

◆ BANK_WIDTH

◆ CK_WIDTH

◆ COL_WIDTH

◆ CS_WIDTH

◆ nCS_PER_RANK

◆ CKE_WIDTH

◆ DATA_BUF_ADDR_WIDTH

◆ DQ_CNT_WIDTH

◆ DQ_PER_DM

◆ DM_WIDTH

◆ DQ_WIDTH

◆ DQS_WIDTH

◆ DQS_CNT_WIDTH

◆ DRAM_WIDTH

◆ ECC

◆ ECC_TEST

◆ DATA_WIDTH

◆ PAYLOAD_WIDTH

◆ MEM_ADDR_ORDER

◆ nBANK_MACHS

◆ RANKS

◆ ODT_WIDTH

◆ ROW_WIDTH

◆ ADDR_WIDTH

◆ USE_CS_PORT

◆ USE_DM_PORT

◆ USE_ODT_PORT

◆ PHY_CONTROL_MASTER_BANK

◆ MEM_DENSITY

◆ MEM_SPEEDGRADE

◆ MEM_DEVICE_WIDTH

◆ AL

◆ nAL

◆ BURST_MODE

◆ BURST_TYPE

◆ CL

◆ CWL

◆ OUTPUT_DRV

◆ RTT_NOM

◆ RTT_WR

◆ ADDR_CMD_MODE

◆ REG_CTRL

◆ CA_MIRROR

◆ VDD_OP_VOLT

◆ CLKIN_PERIOD

◆ CLKFBOUT_MULT

◆ DIVCLK_DIVIDE

◆ CLKOUT0_PHASE

◆ CLKOUT0_DIVIDE

◆ CLKOUT1_DIVIDE

◆ CLKOUT2_DIVIDE

◆ CLKOUT3_DIVIDE

◆ MMCM_VCO

◆ MMCM_MULT_F

◆ MMCM_DIVCLK_DIVIDE

◆ tCKE

◆ tFAW

◆ tPRDI

◆ tRAS

◆ tRCD

◆ tREFI

◆ tRFC

◆ tRP

◆ tRRD

◆ tRTP

◆ tWTR

◆ tZQI

◆ tZQCS

◆ SIM_BYPASS_INIT_CAL

◆ SIMULATION

◆ BYTE_LANES_B0

◆ BYTE_LANES_B1

◆ BYTE_LANES_B2