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W11 CPU core and support modules
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migui_arty_mig_sim.vhd
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48--*****************************************************************************
49-- ____ ____
50-- / /\/ /
51-- /___/ \ / Vendor : Xilinx
52-- \ \ \/ Version : 4.2
53-- \ \ Application : MIG
54-- / / Filename : migui_arty_mig.vhd
55-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
56-- \ \ / \ Date Created : Wed Feb 01 2012
57-- \___\/\___\
58--
59-- Device : 7 Series
60-- Design Name : DDR3 SDRAM
61-- Purpose :
62-- Top-level module. This module can be instantiated in the
63-- system and interconnect as shown in user design wrapper file (user top module).
64-- In addition to the memory controller, the module instantiates:
65-- 1. Clock generation/distribution, reset logic
66-- 2. IDELAY control block
67-- 3. Debug logic
68-- Reference :
69-- Revision History :
70--*****************************************************************************
71
72library ieee;
73use ieee.std_logic_1164.all;
74use ieee.numeric_std.all;
75
76
77entity migui_arty_mig is
78 generic (
79 --***************************************************************************
80 -- The following parameters refer to width of various ports
81 --***************************************************************************
82 BANK_WIDTH : integer := 3;
83 -- # of memory Bank Address bits.
84 CK_WIDTH : integer := 1;
85 -- # of CK/CK# outputs to memory.
86 COL_WIDTH : integer := 10;
87 -- # of memory Column Address bits.
88 CS_WIDTH : integer := 1;
89 -- # of unique CS outputs to memory.
90 nCS_PER_RANK : integer := 1;
91 -- # of unique CS outputs per rank for phy
92 CKE_WIDTH : integer := 1;
93 -- # of CKE outputs to memory.
94 DATA_BUF_ADDR_WIDTH : integer := 5;
95 DQ_CNT_WIDTH : integer := 4;
96 -- = ceil(log2(DQ_WIDTH))
97 DQ_PER_DM : integer := 8;
98 DM_WIDTH : integer := 2;
99 -- # of DM (data mask)
100 DQ_WIDTH : integer := 16;
101 -- # of DQ (data)
102 DQS_WIDTH : integer := 2;
103 DQS_CNT_WIDTH : integer := 1;
104 -- = ceil(log2(DQS_WIDTH))
105 DRAM_WIDTH : integer := 8;
106 -- # of DQ per DQS
107 ECC : string := "OFF";
108 ECC_TEST : string := "OFF";
109 DATA_WIDTH : integer := 16;
110 PAYLOAD_WIDTH : integer := 16;
111 MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
112 --Possible Parameters
113 --1.BANK_ROW_COLUMN : Address mapping is
114 -- in form of Bank Row Column.
115 --2.ROW_BANK_COLUMN : Address mapping is
116 -- in the form of Row Bank Column.
117 --3.TG_TEST : Scrambles Address bits
118 -- for distributed Addressing.
119 --nBANK_MACHS : integer := 4;
120 nBANK_MACHS : integer := 2;
121 RANKS : integer := 1;
122 -- # of Ranks.
123 ODT_WIDTH : integer := 1;
124 -- # of ODT outputs to memory.
125 ROW_WIDTH : integer := 14;
126 -- # of memory Row Address bits.
127 ADDR_WIDTH : integer := 28;
128 -- # = RANK_WIDTH + BANK_WIDTH
129 -- + ROW_WIDTH + COL_WIDTH;
130 -- Chip Select is always tied to low for
131 -- single rank devices
132 USE_CS_PORT : integer := 1;
133 -- # = 1, When Chip Select (CS#) output is enabled
134 -- = 0, When Chip Select (CS#) output is disabled
135 -- If CS_N disabled, user must connect
136 -- DRAM CS_N input(s) to ground
137 USE_DM_PORT : integer := 1;
138 -- # = 1, When Data Mask option is enabled
139 -- = 0, When Data Mask option is disbaled
140 -- When Data Mask option is disabled in
141 -- MIG Controller Options page, the logic
142 -- related to Data Mask should not get
143 -- synthesized
144 USE_ODT_PORT : integer := 1;
145 -- # = 1, When ODT output is enabled
146 -- = 0, When ODT output is disabled
147 -- Parameter configuration for Dynamic ODT support:
148 -- USE_ODT_PORT = 0, RTT_NOM = "DISABLED", RTT_WR = "60/120".
149 -- This configuration allows to save ODT pin mapping from FPGA.
150 -- The user can tie the ODT input of DRAM to HIGH.
151 PHY_CONTROL_MASTER_BANK : integer := 0;
152 -- The bank index where master PHY_CONTROL resides,
153 -- equal to the PLL residing bank
154 MEM_DENSITY : string := "2Gb";
155 -- Indicates the density of the Memory part
156 -- Added for the sake of Vivado simulations
157 MEM_SPEEDGRADE : string := "15E";
158 -- Indicates the Speed grade of Memory Part
159 -- Added for the sake of Vivado simulations
160 MEM_DEVICE_WIDTH : integer := 16;
161 -- Indicates the device width of the Memory Part
162 -- Added for the sake of Vivado simulations
163
164 --***************************************************************************
165 -- The following parameters are mode register settings
166 --***************************************************************************
167 AL : string := "0";
168 -- DDR3 SDRAM:
169 -- Additive Latency (Mode Register 1).
170 -- # = "0", "CL-1", "CL-2".
171 -- DDR2 SDRAM:
172 -- Additive Latency (Extended Mode Register).
173 nAL : integer := 0;
174 -- # Additive Latency in number of clock
175 -- cycles.
176 BURST_MODE : string := "8";
177 -- DDR3 SDRAM:
178 -- Burst Length (Mode Register 0).
179 -- # = "8", "4", "OTF".
180 -- DDR2 SDRAM:
181 -- Burst Length (Mode Register).
182 -- # = "8", "4".
183 BURST_TYPE : string := "SEQ";
184 -- DDR3 SDRAM: Burst Type (Mode Register 0).
185 -- DDR2 SDRAM: Burst Type (Mode Register).
186 -- # = "SEQ" - (Sequential),
187 -- = "INT" - (Interleaved).
188 CL : integer := 5;
189 -- in number of clock cycles
190 -- DDR3 SDRAM: CAS Latency (Mode Register 0).
191 -- DDR2 SDRAM: CAS Latency (Mode Register).
192 CWL : integer := 5;
193 -- in number of clock cycles
194 -- DDR3 SDRAM: CAS Write Latency (Mode Register 2).
195 -- DDR2 SDRAM: Can be ignored
196 OUTPUT_DRV : string := "LOW";
197 -- Output Driver Impedance Control (Mode Register 1).
198 -- # = "HIGH" - RZQ/7,
199 -- = "LOW" - RZQ/6.
200 RTT_NOM : string := "40";
201 -- RTT_NOM (ODT) (Mode Register 1).
202 -- = "120" - RZQ/2,
203 -- = "60" - RZQ/4,
204 -- = "40" - RZQ/6.
205 RTT_WR : string := "OFF";
206 -- RTT_WR (ODT) (Mode Register 2).
207 -- # = "OFF" - Dynamic ODT off,
208 -- = "120" - RZQ/2,
209 -- = "60" - RZQ/4,
210 ADDR_CMD_MODE : string := "1T" ;
211 -- # = "1T", "2T".
212 REG_CTRL : string := "OFF";
213 -- # = "ON" - RDIMMs,
214 -- = "OFF" - Components, SODIMMs, UDIMMs.
215 CA_MIRROR : string := "OFF";
216 -- C/A mirror opt for DDR3 dual rank
217 VDD_OP_VOLT : string := "135";
218 -- # = "150" - 1.5V Vdd Memory part
219 -- = "135" - 1.35V Vdd Memory part
220
221 --***************************************************************************
222 -- The following parameters are multiplier and divisor factors for PLLE2.
223 -- Based on the selected design frequency these parameters vary.
224 --***************************************************************************
225 CLKIN_PERIOD : integer := 6000;
226 -- Input Clock Period
227 CLKFBOUT_MULT : integer := 8;
228 -- write PLL VCO multiplier
229 DIVCLK_DIVIDE : integer := 1;
230 -- write PLL VCO divisor
231 CLKOUT0_PHASE : real := 0.0;
232 -- Phase for PLL output clock (CLKOUT0)
233 CLKOUT0_DIVIDE : integer := 2;
234 -- VCO output divisor for PLL output clock (CLKOUT0)
235 CLKOUT1_DIVIDE : integer := 4;
236 -- VCO output divisor for PLL output clock (CLKOUT1)
237 CLKOUT2_DIVIDE : integer := 64;
238 -- VCO output divisor for PLL output clock (CLKOUT2)
239 CLKOUT3_DIVIDE : integer := 16;
240 -- VCO output divisor for PLL output clock (CLKOUT3)
241 MMCM_VCO : integer := 666;
242 -- Max Freq (MHz) of MMCM VCO
243 MMCM_MULT_F : integer := 8;
244 -- write MMCM VCO multiplier
245 MMCM_DIVCLK_DIVIDE : integer := 1;
246 -- write MMCM VCO divisor
247
248 --***************************************************************************
249 -- Memory Timing Parameters. These parameters varies based on the selected
250 -- memory part.
251 --***************************************************************************
252 tCKE : integer := 5625;
253 -- memory tCKE paramter in pS
254 tFAW : integer := 45000;
255 -- memory tRAW paramter in pS.
256 tPRDI : integer := 1000000;
257 -- memory tPRDI paramter in pS.
258 tRAS : integer := 36000;
259 -- memory tRAS paramter in pS.
260 tRCD : integer := 13500;
261 -- memory tRCD paramter in pS.
262 tREFI : integer := 7800000;
263 -- memory tREFI paramter in pS.
264 tRFC : integer := 160000;
265 -- memory tRFC paramter in pS.
266 tRP : integer := 13500;
267 -- memory tRP paramter in pS.
268 tRRD : integer := 7500;
269 -- memory tRRD paramter in pS.
270 tRTP : integer := 7500;
271 -- memory tRTP paramter in pS.
272 tWTR : integer := 7500;
273 -- memory tWTR paramter in pS.
274 tZQI : integer := 128000000;
275 -- memory tZQI paramter in nS.
276 tZQCS : integer := 64;--64;
277 -- memory tZQCS paramter in clock cycles.
278
279 --***************************************************************************
280 -- Simulation parameters
281 --***************************************************************************
282 SIM_BYPASS_INIT_CAL : string := "FAST";
283 -- # = "OFF" - Complete memory init &
284 -- calibration sequence
285 -- # = "SKIP" - Not supported
286 -- # = "FAST" - Complete memory init & use
287 -- abbreviated calib sequence
288
289 SIMULATION : string := "TRUE";
290 -- Should be TRUE during design simulations and
291 -- FALSE during implementations
292
293 --***************************************************************************
294 -- The following parameters varies based on the pin out entered in MIG GUI.
295 -- Do not change any of these parameters directly by editing the RTL.
296 -- Any changes required should be done through GUI and the design regenerated.
297 --***************************************************************************
298 BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "1111";
299 -- Byte lanes used in an IO column.
300 BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "0000";
301 -- Byte lanes used in an IO column.
302 BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "0000";
303 -- Byte lanes used in an IO column.
304 BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
305 -- Byte lanes used in an IO column.
306 BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
307 -- Byte lanes used in an IO column.
308 DATA_CTL_B0 : std_logic_vector(3 downto 0) := "1100";
309 -- Indicates Byte lane is data byte lane
310 -- or control Byte lane. '1' in a bit
311 -- position indicates a data byte lane and
312 -- a '0' indicates a control byte lane
313 DATA_CTL_B1 : std_logic_vector(3 downto 0) := "0000";
314 -- Indicates Byte lane is data byte lane
315 -- or control Byte lane. '1' in a bit
316 -- position indicates a data byte lane and
317 -- a '0' indicates a control byte lane
318 DATA_CTL_B2 : std_logic_vector(3 downto 0) := "0000";
319 -- Indicates Byte lane is data byte lane
320 -- or control Byte lane. '1' in a bit
321 -- position indicates a data byte lane and
322 -- a '0' indicates a control byte lane
323 DATA_CTL_B3 : std_logic_vector(3 downto 0) := "0000";
324 -- Indicates Byte lane is data byte lane
325 -- or control Byte lane. '1' in a bit
326 -- position indicates a data byte lane and
327 -- a '0' indicates a control byte lane
328 DATA_CTL_B4 : std_logic_vector(3 downto 0) := "0000";
329 -- Indicates Byte lane is data byte lane
330 -- or control Byte lane. '1' in a bit
331 -- position indicates a data byte lane and
332 -- a '0' indicates a control byte lane
333 PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"3FE3FEFFFBFF";
334 PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
335 PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
336
337 -- control/address/data pin mapping parameters
338 CK_BYTE_MAP
339 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
340 ADDR_MAP
341 : std_logic_vector(191 downto 0) := X"00000000000200400900700100500600301001201401101A";
342 BANK_MAP : std_logic_vector(35 downto 0) := X"01B017013";
343 CAS_MAP : std_logic_vector(11 downto 0) := X"015";
344 CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
345 CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000019";
346 ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000008";
347 CS_MAP : std_logic_vector(119 downto 0) := X"00000000000000000000000000000B";
348 PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
349 RAS_MAP : std_logic_vector(11 downto 0) := X"016";
350 WE_MAP : std_logic_vector(11 downto 0) := X"018";
351 DQS_BYTE_MAP
352 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000203";
353 DATA0_MAP : std_logic_vector(95 downto 0) := X"034032038035031037036033";
354 DATA1_MAP : std_logic_vector(95 downto 0) := X"023026022028025027021024";
355 DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
356 DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
357 DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
358 DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
359 DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
360 DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
361 DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
362 DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
363 DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
364 DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
365 DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
366 DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
367 DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
368 DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
369 DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
370 DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
371 MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000029039";
372 MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
373
374 SLOT_0_CONFIG : std_logic_vector(7 downto 0) := "00000001";
375 -- Mapping of Ranks.
376 SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
377 -- Mapping of Ranks.
378
379 --***************************************************************************
380 -- IODELAY and PHY related parameters
381 --***************************************************************************
382 IBUF_LPWR_MODE : string := "OFF";
383 -- to phy_top
384 DATA_IO_IDLE_PWRDWN : string := "OFF";
385 -- # = "ON", "OFF"
386 BANK_TYPE : string := "HR_IO";
387 -- # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
388 DATA_IO_PRIM_TYPE : string := "DEFAULT";
389 -- # = "HP_LP", "HR_LP", "DEFAULT"
390 CKE_ODT_AUX : string := "FALSE";
391 USER_REFRESH : string := "OFF";
392 WRLVL : string := "ON";
393 -- # = "ON" - DDR3 SDRAM
394 -- = "OFF" - DDR2 SDRAM.
395 ORDERING : string := "STRICT";
396 -- # = "NORM", "STRICT", "RELAXED".
397 CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000";
398 -- Calibration row address will be used for
399 -- calibration read and write operations
400 CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000";
401 -- Calibration column address will be used for
402 -- calibration read and write operations
403 CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000";
404 -- Calibration bank address will be used for
405 -- calibration read and write operations
406 TCQ : integer := 100;
407 IDELAY_ADJ : string := "OFF";
408 FINE_PER_BIT : string := "OFF";
409 CENTER_COMP_MODE : string := "OFF";
410 PI_VAL_ADJ : string := "OFF";
411 IODELAY_GRP0 : string := "MIGUI_ARTY_IODELAY_MIG0";
412 -- It is associated to a set of IODELAYs with
413 -- an IDELAYCTRL that have same IODELAY CONTROLLER
414 -- clock frequency (200MHz).
415 IODELAY_GRP1 : string := "MIGUI_ARTY_IODELAY_MIG1";
416 -- It is associated to a set of IODELAYs with
417 -- an IDELAYCTRL that have same IODELAY CONTROLLER
418 -- clock frequency (300MHz/400MHz).
419 SYSCLK_TYPE : string := "NO_BUFFER";
420 -- System clock type DIFFERENTIAL, SINGLE_ENDED,
421 -- NO_BUFFER
422 REFCLK_TYPE : string := "NO_BUFFER";
423 -- Reference clock type DIFFERENTIAL, SINGLE_ENDED
424 -- NO_BUFFER, USE_SYSTEM_CLOCK
425 SYS_RST_PORT : string := "FALSE";
426 -- "TRUE" - if pin is selected for sys_rst
427 -- and IBUF will be instantiated.
428 -- "FALSE" - if pin is not selected for sys_rst
429
430 FPGA_SPEED_GRADE : integer := 1;
431 -- FPGA speed grade
432
433 CMD_PIPE_PLUS1 : string := "ON";
434 -- add pipeline stage between MC and PHY
435
436 DRAM_TYPE : string := "DDR3";
437 CAL_WIDTH : string := "HALF";
438 STARVE_LIMIT : integer := 2;
439 -- # = 2,3,4.
440 REF_CLK_MMCM_IODELAY_CTRL : string := "FALSE";
441
442 --***************************************************************************
443 -- Referece clock frequency parameters
444 --***************************************************************************
445 REFCLK_FREQ : real := 200.0;
446 -- IODELAYCTRL reference clock frequency
447 DIFF_TERM_REFCLK : string := "TRUE";
448 -- Differential Termination for idelay
449 -- reference clock input pins
450 --***************************************************************************
451 -- System clock frequency parameters
452 --***************************************************************************
453 tCK : integer := 3000;
454 -- memory tCK paramter.
455 -- # = Clock Period in pS.
456 nCK_PER_CLK : integer := 4;
457 -- # of memory CKs per fabric CLK
458 DIFF_TERM_SYSCLK : string := "TRUE";
459 -- Differential Termination for System
460 -- clock input pins
461
462 --***************************************************************************
463 -- Debug parameters
464 --***************************************************************************
465 DEBUG_PORT : string := "OFF";
466 -- # = "ON" Enable debug signals/controls.
467 -- = "OFF" Disable debug signals/controls.
468
469 --***************************************************************************
470 -- Temparature monitor parameter
471 --***************************************************************************
472 TEMP_MON_CONTROL : string := "EXTERNAL";
473 -- # = "INTERNAL", "EXTERNAL"
474 --***************************************************************************
475 -- FPGA Voltage Type parameter
476 --***************************************************************************
477 FPGA_VOLT_TYPE : string := "N";
478 -- # = "L", "N". When FPGA VccINT is 0.9v,
479 -- the value is "L", else it is "N"
480
481 RST_ACT_LOW : integer := 0
482 -- =1 for active low reset,
483 -- =0 for active high.
484 );
485 port (
486
487 -- Inouts
488 ddr3_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
489 ddr3_dqs_p : inout std_logic_vector(DQS_WIDTH-1 downto 0);
490 ddr3_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
491
492 -- Outputs
493 ddr3_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
494 ddr3_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
495 ddr3_ras_n : out std_logic;
496 ddr3_cas_n : out std_logic;
497 ddr3_we_n : out std_logic;
498 ddr3_reset_n : out std_logic;
499 ddr3_ck_p : out std_logic_vector(CK_WIDTH-1 downto 0);
500 ddr3_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
501 ddr3_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
502 ddr3_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
503 ddr3_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
504 ddr3_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
505
506 -- Inputs
507 -- Single-ended system clock
508 sys_clk_i : in std_logic;
509 -- Single-ended iodelayctrl clk (reference clock)
510 clk_ref_i : in std_logic;
511 -- user interface signals
512 app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
513 app_cmd : in std_logic_vector(2 downto 0);
514 app_en : in std_logic;
515 app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
516 app_wdf_end : in std_logic;
517 app_wdf_mask : in std_logic_vector(((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8)-1 downto 0) ;
518 app_wdf_wren : in std_logic;
519 app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
520 app_rd_data_end : out std_logic;
521 app_rd_data_valid : out std_logic;
522 app_rdy : out std_logic;
523 app_wdf_rdy : out std_logic;
524 app_sr_req : in std_logic;
525 app_ref_req : in std_logic;
526 app_zq_req : in std_logic;
527 app_sr_active : out std_logic;
528 app_ref_ack : out std_logic;
529 app_zq_ack : out std_logic;
530 ui_clk : out std_logic;
531 ui_clk_sync_rst : out std_logic;
532
533
534 init_calib_complete : out std_logic;
535 device_temp_i : in std_logic_vector(11 downto 0);
536 -- The 12 MSB bits of the temperature sensor transfer
537 -- function need to be connected to this port. This port
538 -- will be synchronized w.r.t. to fabric clock internally.
539 device_temp : out std_logic_vector(11 downto 0);
540
541
542 -- System reset - Default polarity of sys_rst pin is Active Low.
543 -- System reset polarity will change based on the option
544 -- selected in GUI.
545 sys_rst : in std_logic
546 );
547
548end entity migui_arty_mig;
549
550architecture arch_migui_arty_mig of migui_arty_mig is
551
552
553 -- clogb2 function - ceiling of log base 2
554 function clogb2 (size : integer) return integer is
555 variable base : integer := 1;
556 variable inp : integer := 0;
557 begin
558 inp := size - 1;
559 while (inp > 1) loop
560 inp := inp/2 ;
561 base := base + 1;
562 end loop;
563 return base;
564 end function;
565 function ECCWIDTH return integer is
566 begin
567 if(ECC = "OFF") then
568 return 0;
569 else
570 if(DATA_WIDTH <= 4) then
571 return 4;
572 elsif(DATA_WIDTH <= 10) then
573 return 5;
574 elsif(DATA_WIDTH <= 26) then
575 return 6;
576 elsif(DATA_WIDTH <= 57) then
577 return 7;
578 elsif(DATA_WIDTH <= 120) then
579 return 8;
580 elsif(DATA_WIDTH <= 247) then
581 return 9;
582 else
583 return 10;
584 end if;
585 end if;
586 end function;
587
588 constant RANK_WIDTH : integer := clogb2(RANKS);
589
590 function XWIDTH return integer is
591 begin
592 if(CS_WIDTH = 1) then
593 return 0;
594 else
595 return RANK_WIDTH;
596 end if;
597 end function;
598
599 constant TAPSPERKCLK : integer := (56*MMCM_MULT_F)/nCK_PER_CLK;
600
601 function TEMP_MON return string is
602 begin
603 if(SIMULATION = "TRUE") then
604 return "ON";
605 else
606 return "OFF";
607 end if;
608 end function;
609
610
611
612
613 constant BM_CNT_WIDTH : integer := clogb2(nBANK_MACHS);
614 constant ECC_WIDTH : integer := ECCWIDTH;
615 constant DATA_BUF_OFFSET_WIDTH : integer := 1;
616 constant MC_ERR_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH
617 + COL_WIDTH + DATA_BUF_OFFSET_WIDTH;
618 constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
619 constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
620 constant TEMP_MON_EN : string := TEMP_MON;
621 -- Enable or disable the temp monitor module
622 constant tTEMPSAMPLE : integer := 10000000; -- sample every 10 us
623 constant XADC_CLK_PERIOD : integer := 5000; -- Use 200 MHz IODELAYCTRL clock
624
625
626
627-- Start of User Design wrapper top component
628
629 component migui_arty
630 port(
631 sys_rst : in std_logic
632 );
633 end component migui_arty;
634
635-- End of User Design wrapper top component
636
637
638
639 component mig_7series_v4_2_iodelay_ctrl is
640 generic(
641 TCQ : integer;
642 IODELAY_GRP0 : string;
643 IODELAY_GRP1 : string;
644 REFCLK_TYPE : string;
645 SYSCLK_TYPE : string;
646 SYS_RST_PORT : string;
647 RST_ACT_LOW : integer;
648 DIFF_TERM_REFCLK : string;
649 FPGA_SPEED_GRADE : integer;
650 REF_CLK_MMCM_IODELAY_CTRL : string
651 );
652 port (
653 clk_ref_p : in std_logic;
654 clk_ref_n : in std_logic;
655 clk_ref_i : in std_logic;
656 sys_rst : in std_logic;
657 clk_ref : out std_logic_vector(1 downto 0);
658 sys_rst_o : out std_logic;
659 iodelay_ctrl_rdy : out std_logic_vector(1 downto 0)
660 );
661 end component mig_7series_v4_2_iodelay_ctrl;
662
663 component mig_7series_v4_2_clk_ibuf is
664 generic (
665 SYSCLK_TYPE : string;
666 DIFF_TERM_SYSCLK : string
667 );
668 port (
669 sys_clk_p : in std_logic;
670 sys_clk_n : in std_logic;
671 sys_clk_i : in std_logic;
672 mmcm_clk : out std_logic
673 );
674 end component mig_7series_v4_2_clk_ibuf;
675
676 component mig_7series_v4_2_infrastructure is
677 generic (
678 SIMULATION : string := "TRUE";
679 TCQ : integer;
680 CLKIN_PERIOD : integer;
681 nCK_PER_CLK : integer;
682 SYSCLK_TYPE : string;
683 UI_EXTRA_CLOCKS : string := "FALSE";
684 CLKFBOUT_MULT : integer;
685 DIVCLK_DIVIDE : integer;
686 CLKOUT0_PHASE : real;
687 CLKOUT0_DIVIDE : integer;
688 CLKOUT1_DIVIDE : integer;
689 CLKOUT2_DIVIDE : integer;
690 CLKOUT3_DIVIDE : integer;
691 MMCM_VCO : integer;
692 MMCM_MULT_F : integer;
693 MMCM_DIVCLK_DIVIDE : integer;
694 MMCM_CLKOUT0_EN : string := "FALSE";
695 MMCM_CLKOUT1_EN : string := "FALSE";
696 MMCM_CLKOUT2_EN : string := "FALSE";
697 MMCM_CLKOUT3_EN : string := "FALSE";
698 MMCM_CLKOUT4_EN : string := "FALSE";
699 MMCM_CLKOUT0_DIVIDE : integer := 1;
700 MMCM_CLKOUT1_DIVIDE : integer := 1;
701 MMCM_CLKOUT2_DIVIDE : integer := 1;
702 MMCM_CLKOUT3_DIVIDE : integer := 1;
703 MMCM_CLKOUT4_DIVIDE : integer := 1;
704 RST_ACT_LOW : integer;
705 tCK : integer;
706 MEM_TYPE : string
707 );
708 port (
709 mmcm_clk : in std_logic;
710 sys_rst : in std_logic;
711 iodelay_ctrl_rdy : in std_logic_vector(1 downto 0);
712 psen : in std_logic;
713 psincdec : in std_logic;
714 clk : out std_logic;
715 clk_div2 : out std_logic;
716 rst_div2 : out std_logic;
717 mem_refclk : out std_logic;
718 freq_refclk : out std_logic;
719 sync_pulse : out std_logic;
720 mmcm_ps_clk : out std_logic;
721 poc_sample_pd : out std_logic;
722 iddr_rst : out std_logic;
723 psdone : out std_logic;
724-- auxout_clk : out std_logic;
725 ui_addn_clk_0 : out std_logic;
726 ui_addn_clk_1 : out std_logic;
727 ui_addn_clk_2 : out std_logic;
728 ui_addn_clk_3 : out std_logic;
729 ui_addn_clk_4 : out std_logic;
730 pll_locked : out std_logic;
731 mmcm_locked : out std_logic;
732 rstdiv0 : out std_logic;
733 rst_phaser_ref : out std_logic;
734 ref_dll_lock : in std_logic
735 );
736 end component mig_7series_v4_2_infrastructure;
737
738 component mig_7series_v4_2_tempmon is
739 generic (
740 TCQ : integer;
741 TEMP_MON_CONTROL : string;
742 XADC_CLK_PERIOD : integer;
743 tTEMPSAMPLE : integer
744 );
745 port (
746 clk : in std_logic;
747 xadc_clk : in std_logic;
748 rst : in std_logic;
749 device_temp_i : in std_logic_vector(11 downto 0);
750 device_temp : out std_logic_vector(11 downto 0)
751 );
752 end component mig_7series_v4_2_tempmon;
753
754 component mig_7series_v4_2_memc_ui_top_std is
755 generic (
756 TCQ : integer;
757 DDR3_VDD_OP_VOLT : string := "135";
758 PAYLOAD_WIDTH : integer;
759 ADDR_CMD_MODE : string;
760 AL : string;
761 BANK_WIDTH : integer;
762 BM_CNT_WIDTH : integer;
763 BURST_MODE : string;
764 BURST_TYPE : string;
765 CA_MIRROR : string;
766 CK_WIDTH : integer;
767 CL : integer;
768 COL_WIDTH : integer;
769 CMD_PIPE_PLUS1 : string;
770 CS_WIDTH : integer;
771 CKE_WIDTH : integer;
772 CWL : integer;
773 DATA_WIDTH : integer;
774 DATA_BUF_ADDR_WIDTH : integer;
775 DATA_BUF_OFFSET_WIDTH : integer := 1;
776 DDR2_DQSN_ENABLE : string := "YES";
777 DM_WIDTH : integer;
778 DQ_CNT_WIDTH : integer;
779 DQ_WIDTH : integer;
780 DQS_CNT_WIDTH : integer;
781 DQS_WIDTH : integer;
782 DRAM_TYPE : string;
783 DRAM_WIDTH : integer;
784 ECC : string;
785 ECC_WIDTH : integer;
786 ECC_TEST : string;
787 MC_ERR_ADDR_WIDTH : integer;
788 MASTER_PHY_CTL : integer;
789 nAL : integer;
790 nBANK_MACHS : integer;
791 nCK_PER_CLK : integer;
792 nCS_PER_RANK : integer;
793 ORDERING : string;
794 IBUF_LPWR_MODE : string;
795 BANK_TYPE : string;
796 DATA_IO_PRIM_TYPE : string;
797 DATA_IO_IDLE_PWRDWN : string;
798 IODELAY_GRP0 : string;
799 IODELAY_GRP1 : string;
800 FPGA_SPEED_GRADE : integer;
801 OUTPUT_DRV : string;
802 REG_CTRL : string;
803 RTT_NOM : string;
804 RTT_WR : string;
805 STARVE_LIMIT : integer;
806 tCK : integer;
807 tCKE : integer;
808 tFAW : integer;
809 tPRDI : integer;
810 tRAS : integer;
811 tRCD : integer;
812 tREFI : integer;
813 tRFC : integer;
814 tRP : integer;
815 tRRD : integer;
816 tRTP : integer;
817 tWTR : integer;
818 tZQI : integer;
819 tZQCS : integer;
820 USER_REFRESH : string;
821 TEMP_MON_EN : string;
822 WRLVL : string;
823 DEBUG_PORT : string;
824 CAL_WIDTH : string;
825 RANK_WIDTH : integer;
826 RANKS : integer;
827 ODT_WIDTH : integer;
828 ROW_WIDTH : integer;
829 ADDR_WIDTH : integer;
830 APP_MASK_WIDTH : integer;
831 APP_DATA_WIDTH : integer;
832 BYTE_LANES_B0 : std_logic_vector(3 downto 0);
833 BYTE_LANES_B1 : std_logic_vector(3 downto 0);
834 BYTE_LANES_B2 : std_logic_vector(3 downto 0);
835 BYTE_LANES_B3 : std_logic_vector(3 downto 0);
836 BYTE_LANES_B4 : std_logic_vector(3 downto 0);
837 DATA_CTL_B0 : std_logic_vector(3 downto 0);
838 DATA_CTL_B1 : std_logic_vector(3 downto 0);
839 DATA_CTL_B2 : std_logic_vector(3 downto 0);
840 DATA_CTL_B3 : std_logic_vector(3 downto 0);
841 DATA_CTL_B4 : std_logic_vector(3 downto 0);
842 PHY_0_BITLANES : std_logic_vector(47 downto 0);
843 PHY_1_BITLANES : std_logic_vector(47 downto 0);
844 PHY_2_BITLANES : std_logic_vector(47 downto 0);
845 CK_BYTE_MAP : std_logic_vector(143 downto 0);
846 ADDR_MAP : std_logic_vector(191 downto 0);
847 BANK_MAP : std_logic_vector(35 downto 0);
848 CAS_MAP : std_logic_vector(11 downto 0);
849 CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0);
850 CKE_MAP : std_logic_vector(95 downto 0);
851 ODT_MAP : std_logic_vector(95 downto 0);
852 CKE_ODT_AUX : string;
853 CS_MAP : std_logic_vector(119 downto 0);
854 PARITY_MAP : std_logic_vector(11 downto 0);
855 RAS_MAP : std_logic_vector(11 downto 0);
856 WE_MAP : std_logic_vector(11 downto 0);
857 DQS_BYTE_MAP : std_logic_vector(143 downto 0);
858 DATA0_MAP : std_logic_vector(95 downto 0);
859 DATA1_MAP : std_logic_vector(95 downto 0);
860 DATA2_MAP : std_logic_vector(95 downto 0);
861 DATA3_MAP : std_logic_vector(95 downto 0);
862 DATA4_MAP : std_logic_vector(95 downto 0);
863 DATA5_MAP : std_logic_vector(95 downto 0);
864 DATA6_MAP : std_logic_vector(95 downto 0);
865 DATA7_MAP : std_logic_vector(95 downto 0);
866 DATA8_MAP : std_logic_vector(95 downto 0);
867 DATA9_MAP : std_logic_vector(95 downto 0);
868 DATA10_MAP : std_logic_vector(95 downto 0);
869 DATA11_MAP : std_logic_vector(95 downto 0);
870 DATA12_MAP : std_logic_vector(95 downto 0);
871 DATA13_MAP : std_logic_vector(95 downto 0);
872 DATA14_MAP : std_logic_vector(95 downto 0);
873 DATA15_MAP : std_logic_vector(95 downto 0);
874 DATA16_MAP : std_logic_vector(95 downto 0);
875 DATA17_MAP : std_logic_vector(95 downto 0);
876 MASK0_MAP : std_logic_vector(107 downto 0);
877 MASK1_MAP : std_logic_vector(107 downto 0);
878 SLOT_0_CONFIG : std_logic_vector(7 downto 0);
879 SLOT_1_CONFIG : std_logic_vector(7 downto 0);
880 MEM_ADDR_ORDER : string;
881 CALIB_ROW_ADD : std_logic_vector(15 downto 0);
882 CALIB_COL_ADD : std_logic_vector(11 downto 0);
883 CALIB_BA_ADD : std_logic_vector(2 downto 0);
884 SIM_BYPASS_INIT_CAL : string;
885 REFCLK_FREQ : real;
886 USE_CS_PORT : integer;
887 USE_DM_PORT : integer;
888 USE_ODT_PORT : integer;
889 IDELAY_ADJ : string;
890 FINE_PER_BIT : string;
891 CENTER_COMP_MODE : string;
892 PI_VAL_ADJ : string;
893 TAPSPERKCLK : integer;
894 SKIP_CALIB : string;
895 FPGA_VOLT_TYPE : string
896 );
897 port (
898 clk : in std_logic;
899 clk_div2 : in std_logic;
900 rst_div2 : in std_logic;
901 clk_ref : in std_logic_vector(1 downto 0);
902 mem_refclk : in std_logic;
903 freq_refclk : in std_logic;
904 pll_lock : in std_logic;
905 sync_pulse : in std_logic;
906 mmcm_ps_clk : in std_logic;
907 poc_sample_pd : in std_logic;
908 rst : in std_logic;
909
910 ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
911 ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
912 ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
913 ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
914 ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
915 ddr_cas_n : out std_logic;
916 ddr_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
917 ddr_ck : out std_logic_vector(CK_WIDTH-1 downto 0);
918 ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
919 ddr_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
920 ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
921 ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
922 ddr_ras_n : out std_logic;
923 ddr_reset_n : out std_logic;
924 ddr_parity : out std_logic;
925 ddr_we_n : out std_logic;
926
927 bank_mach_next : out std_logic_vector(BM_CNT_WIDTH-1 downto 0);
928
929 app_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
930 app_cmd : in std_logic_vector(2 downto 0);
931 app_en : in std_logic;
932 app_hi_pri : in std_logic;
933 app_wdf_data : in std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
934 app_wdf_end : in std_logic;
935 app_wdf_mask : in std_logic_vector(((nCK_PER_CLK*2*PAYLOAD_WIDTH)/8)-1 downto 0);
936 app_wdf_wren : in std_logic;
937 app_correct_en_i : in std_logic;
938 app_raw_not_ecc : in std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
939 app_ecc_multiple_err : out std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
940 app_ecc_single_err : out std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
941 app_rd_data : out std_logic_vector((nCK_PER_CLK*2*PAYLOAD_WIDTH)-1 downto 0);
942 app_rd_data_end : out std_logic;
943 app_rd_data_valid : out std_logic;
944 app_rdy : out std_logic;
945 app_wdf_rdy : out std_logic;
946 app_sr_req : in std_logic;
947 app_sr_active : out std_logic;
948 app_ref_req : in std_logic;
949 app_ref_ack : out std_logic;
950 app_zq_req : in std_logic;
951 app_zq_ack : out std_logic;
952
953 calib_tap_req : out std_logic;
954 calib_tap_addr : in std_logic_vector(6 downto 0);
955 calib_tap_load : in std_logic;
956 calib_tap_val : in std_logic_vector(7 downto 0);
957 calib_tap_load_done : in std_logic;
958
959 device_temp : in std_logic_vector(11 downto 0);
960
961 psen : out std_logic;
962 psincdec : out std_logic;
963 psdone : in std_logic;
964
965 dbg_idel_down_all : in std_logic;
966 dbg_idel_down_cpt : in std_logic;
967 dbg_idel_up_all : in std_logic;
968 dbg_idel_up_cpt : in std_logic;
969 dbg_sel_all_idel_cpt : in std_logic;
970 dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
971 dbg_cpt_first_edge_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
972 dbg_cpt_second_edge_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
973 dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
974 dbg_rddata : out std_logic_vector((2*nCK_PER_CLK*DQ_WIDTH)-1 downto 0);
975 dbg_rdlvl_done : out std_logic_vector(1 downto 0);
976 dbg_rdlvl_err : out std_logic_vector(1 downto 0);
977 dbg_rdlvl_start : out std_logic_vector(1 downto 0);
978 dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
979 dbg_wl_edge_detect_valid : out std_logic;
980 dbg_wrlvl_done : out std_logic;
981 dbg_wrlvl_err : out std_logic;
982 dbg_wrlvl_start : out std_logic;
983 dbg_final_po_fine_tap_cnt : out std_logic_vector((6*DQS_WIDTH)-1 downto 0);
984 dbg_final_po_coarse_tap_cnt : out std_logic_vector((3*DQS_WIDTH)-1 downto 0);
985 init_calib_complete : out std_logic;
986 dbg_sel_pi_incdec : in std_logic;
987 dbg_sel_po_incdec : in std_logic;
988 dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
989 dbg_pi_f_inc : in std_logic;
990 dbg_pi_f_dec : in std_logic;
991 dbg_po_f_inc : in std_logic;
992 dbg_po_f_stg23_sel : in std_logic;
993 dbg_po_f_dec : in std_logic;
994 dbg_cpt_tap_cnt : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
995 dbg_dq_idelay_tap_cnt : out std_logic_vector((5*DQS_WIDTH*RANKS)-1 downto 0);
996 dbg_rddata_valid : out std_logic;
997 dbg_wrlvl_fine_tap_cnt : out std_logic_vector((6*DQS_WIDTH)-1 downto 0);
998 dbg_wrlvl_coarse_tap_cnt : out std_logic_vector((3*DQS_WIDTH)-1 downto 0);
999 rst_phaser_ref : in std_logic;
1000 ref_dll_lock : out std_logic;
1001 iddr_rst : in std_logic;
1002 dbg_rd_data_offset : out std_logic_vector((6*RANKS)-1 downto 0);
1003 dbg_calib_top : out std_logic_vector(255 downto 0);
1004 dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
1005 dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
1006 dbg_phy_wrcal : out std_logic_vector(99 downto 0);
1007 dbg_phy_init : out std_logic_vector(255 downto 0);
1008 dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
1009 dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
1010 dbg_pi_counter_read_val : out std_logic_vector(5 downto 0);
1011 dbg_po_counter_read_val : out std_logic_vector(8 downto 0);
1012 dbg_pi_phaselock_start : out std_logic;
1013 dbg_pi_phaselocked_done : out std_logic;
1014 dbg_pi_phaselock_err : out std_logic;
1015 dbg_pi_dqsfound_start : out std_logic;
1016 dbg_pi_dqsfound_done : out std_logic;
1017 dbg_pi_dqsfound_err : out std_logic;
1018 dbg_wrcal_start : out std_logic;
1019 dbg_wrcal_done : out std_logic;
1020 dbg_wrcal_err : out std_logic;
1021 dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
1022 dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
1023 dbg_calib_rd_data_offset_1 : out std_logic_vector((6*RANKS)-1 downto 0);
1024 dbg_calib_rd_data_offset_2 : out std_logic_vector((6*RANKS)-1 downto 0);
1025 dbg_data_offset : out std_logic_vector(5 downto 0);
1026 dbg_data_offset_1 : out std_logic_vector(5 downto 0);
1027 dbg_data_offset_2 : out std_logic_vector(5 downto 0);
1028 dbg_oclkdelay_calib_start : out std_logic;
1029 dbg_oclkdelay_calib_done : out std_logic;
1030 dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
1031 dbg_oclkdelay_rd_data : out std_logic_vector((DRAM_WIDTH*16)-1 downto 0);
1032 dbg_prbs_final_dqs_tap_cnt_r : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
1033 dbg_prbs_first_edge_taps : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
1034 dbg_prbs_second_edge_taps : out std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
1035 dbg_poc : out std_logic_vector (1023 downto 0)
1036 );
1037 end component mig_7series_v4_2_memc_ui_top_std;
1038
1039
1040 -- Signal declarations
1041
1042 signal bank_mach_next : std_logic_vector(BM_CNT_WIDTH-1 downto 0);
1043 signal clk : std_logic;
1044 signal clk_ref : std_logic_vector(1 downto 0);
1045 signal iodelay_ctrl_rdy : std_logic_vector(1 downto 0);
1046 signal clk_ref_in : std_logic;
1047 signal sys_rst_o : std_logic;
1048 signal clk_div2 : std_logic;
1049 signal rst_div2 : std_logic;
1050 signal freq_refclk : std_logic;
1051 signal mem_refclk : std_logic;
1052 signal pll_locked : std_logic;
1053 signal sync_pulse : std_logic;
1054 signal mmcm_ps_clk : std_logic;
1055 signal poc_sample_pd : std_logic;
1056 signal psen : std_logic;
1057 signal psincdec : std_logic;
1058 signal psdone : std_logic;
1059 signal iddr_rst : std_logic;
1060 signal ref_dll_lock : std_logic;
1061 signal rst_phaser_ref : std_logic;
1062
1063 signal rst : std_logic;
1064
1065 signal app_ecc_multiple_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
1066 signal app_ecc_single_err : std_logic_vector((2*nCK_PER_CLK)-1 downto 0);
1067 signal ddr3_parity : std_logic;
1068
1069 signal init_calib_complete_i : std_logic;
1070
1071 signal sys_clk_p : std_logic;
1072 signal sys_clk_n : std_logic;
1073 signal mmcm_clk : std_logic;
1074 signal clk_ref_p : std_logic;
1075 signal clk_ref_n : std_logic;
1076 signal device_temp_s : std_logic_vector(11 downto 0);
1077
1078 -- Debug port signals
1079 signal dbg_idel_down_all : std_logic;
1080 signal dbg_idel_down_cpt : std_logic;
1081 signal dbg_idel_up_all : std_logic;
1082 signal dbg_idel_up_cpt : std_logic;
1083 signal dbg_sel_all_idel_cpt : std_logic;
1084 signal dbg_sel_idel_cpt : std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
1085 signal dbg_po_f_stg23_sel : std_logic;
1086 signal dbg_sel_pi_incdec : std_logic;
1087 signal dbg_sel_po_incdec : std_logic;
1088 signal dbg_byte_sel : std_logic_vector(DQS_CNT_WIDTH downto 0);
1089 signal dbg_pi_f_inc : std_logic;
1090 signal dbg_po_f_inc : std_logic;
1091 signal dbg_pi_f_dec : std_logic;
1092 signal dbg_po_f_dec : std_logic;
1093 signal dbg_pi_counter_read_val : std_logic_vector(5 downto 0);
1094 signal dbg_po_counter_read_val : std_logic_vector(8 downto 0);
1095 signal dbg_prbs_final_dqs_tap_cnt_r : std_logic_vector(11 downto 0);
1096 signal dbg_prbs_first_edge_taps : std_logic_vector(11 downto 0);
1097 signal dbg_prbs_second_edge_taps : std_logic_vector(11 downto 0);
1098 signal dbg_cpt_tap_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
1099 signal dbg_dq_idelay_tap_cnt : std_logic_vector((5*DQS_WIDTH*RANKS)-1 downto 0);
1100 signal dbg_calib_top : std_logic_vector(255 downto 0);
1101 signal dbg_cpt_first_edge_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
1102 signal dbg_cpt_second_edge_cnt : std_logic_vector((6*DQS_WIDTH*RANKS)-1 downto 0);
1103 signal dbg_rd_data_offset : std_logic_vector((6*RANKS)-1 downto 0);
1104 signal dbg_phy_rdlvl : std_logic_vector(255 downto 0);
1105 signal dbg_phy_wrcal : std_logic_vector(99 downto 0);
1106 signal dbg_final_po_fine_tap_cnt : std_logic_vector((6*DQS_WIDTH)-1 downto 0);
1107 signal dbg_final_po_coarse_tap_cnt : std_logic_vector((3*DQS_WIDTH)-1 downto 0);
1108 signal dbg_phy_wrlvl : std_logic_vector(255 downto 0);
1109 signal dbg_phy_init : std_logic_vector(255 downto 0);
1110 signal dbg_prbs_rdlvl : std_logic_vector(255 downto 0);
1111 signal dbg_dqs_found_cal : std_logic_vector(255 downto 0);
1112 signal dbg_pi_phaselock_start : std_logic;
1113 signal dbg_pi_phaselocked_done : std_logic;
1114 signal dbg_pi_phaselock_err : std_logic;
1115 signal dbg_pi_dqsfound_start : std_logic;
1116 signal dbg_pi_dqsfound_done : std_logic;
1117 signal dbg_pi_dqsfound_err : std_logic;
1118 signal dbg_wrcal_start : std_logic;
1119 signal dbg_wrcal_done : std_logic;
1120 signal dbg_wrcal_err : std_logic;
1121 signal dbg_pi_dqs_found_lanes_phy4lanes : std_logic_vector(11 downto 0);
1122 signal dbg_pi_phase_locked_phy4lanes : std_logic_vector(11 downto 0);
1123 signal dbg_oclkdelay_calib_start : std_logic;
1124 signal dbg_oclkdelay_calib_done : std_logic;
1125 signal dbg_phy_oclkdelay_cal : std_logic_vector(255 downto 0);
1126 signal dbg_oclkdelay_rd_data : std_logic_vector((DRAM_WIDTH*16)-1 downto 0);
1127 signal dbg_rd_data_edge_detect : std_logic_vector(DQS_WIDTH-1 downto 0);
1128 signal dbg_rddata : std_logic_vector((2*nCK_PER_CLK*DQ_WIDTH)-1 downto 0);
1129 signal dbg_rddata_valid : std_logic;
1130 signal dbg_rdlvl_done : std_logic_vector(1 downto 0);
1131 signal dbg_rdlvl_err : std_logic_vector(1 downto 0);
1132 signal dbg_rdlvl_start : std_logic_vector(1 downto 0);
1133 signal dbg_wrlvl_fine_tap_cnt : std_logic_vector((6*DQS_WIDTH)-1 downto 0);
1134 signal dbg_wrlvl_coarse_tap_cnt : std_logic_vector((3*DQS_WIDTH)-1 downto 0);
1135 signal dbg_tap_cnt_during_wrlvl : std_logic_vector(5 downto 0);
1136 signal dbg_wl_edge_detect_valid : std_logic;
1137 signal dbg_wrlvl_done : std_logic;
1138 signal dbg_wrlvl_err : std_logic;
1139 signal dbg_wrlvl_start : std_logic;
1140 signal dbg_rddata_r : std_logic_vector(63 downto 0);
1141 signal dbg_rddata_valid_r : std_logic;
1142 signal ocal_tap_cnt : std_logic_vector(53 downto 0);
1143 signal dbg_dqs : std_logic_vector(4 downto 0);
1144 signal dbg_bit : std_logic_vector(8 downto 0);
1145 signal rd_data_edge_detect_r : std_logic_vector(8 downto 0);
1146 signal wl_po_fine_cnt : std_logic_vector(53 downto 0);
1147 signal wl_po_coarse_cnt : std_logic_vector(26 downto 0);
1148 signal dbg_calib_rd_data_offset_1 : std_logic_vector((6*RANKS)-1 downto 0);
1149 signal dbg_calib_rd_data_offset_2 : std_logic_vector((6*RANKS)-1 downto 0);
1150 signal dbg_data_offset : std_logic_vector(5 downto 0);
1151 signal dbg_data_offset_1 : std_logic_vector(5 downto 0);
1152 signal dbg_data_offset_2 : std_logic_vector(5 downto 0);
1153 signal all_zeros : std_logic_vector((2*nCK_PER_CLK)-1 downto 0) := (others => '0');
1154
1155 signal ddr3_ila_basic_int : std_logic_vector(119 downto 0);
1156 signal ddr3_ila_wrpath_int : std_logic_vector(390 downto 0);
1157 signal ddr3_ila_rdpath_int : std_logic_vector(1023 downto 0);
1158 signal dbg_prbs_final_dqs_tap_cnt_r_int : std_logic_vector(11 downto 0);
1159 signal dbg_prbs_first_edge_taps_int : std_logic_vector(11 downto 0);
1160 signal dbg_prbs_second_edge_taps_int : std_logic_vector(11 downto 0);
1161
1162
1163begin
1164
1165--***************************************************************************
1166
1167
1168
1169
1170
1171 ui_clk <= clk;
1172 ui_clk_sync_rst <= rst;
1173
1174 sys_clk_p <= '0';
1175 sys_clk_n <= '0';
1176 clk_ref_p <= '0';
1177 clk_ref_n <= '0';
1178 init_calib_complete <= init_calib_complete_i;
1179 device_temp <= device_temp_s;
1180
1181
1182
1183 clk_ref_in_use_sys_clk : if (REFCLK_TYPE = "USE_SYSTEM_CLOCK") generate
1184 clk_ref_in <= mmcm_clk;
1185 end generate;
1186
1187 clk_ref_in_others : if (REFCLK_TYPE /= "USE_SYSTEM_CLOCK") generate
1188 clk_ref_in <= clk_ref_i;
1189 end generate;
1190
1191 u_iodelay_ctrl : mig_7series_v4_2_iodelay_ctrl
1192 generic map
1193 (
1194 TCQ => TCQ,
1195 IODELAY_GRP0 => IODELAY_GRP0,
1196 IODELAY_GRP1 => IODELAY_GRP1,
1197 REFCLK_TYPE => REFCLK_TYPE,
1198 SYSCLK_TYPE => SYSCLK_TYPE,
1199 SYS_RST_PORT => SYS_RST_PORT,
1200 RST_ACT_LOW => RST_ACT_LOW,
1201 DIFF_TERM_REFCLK => DIFF_TERM_REFCLK,
1202 FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
1203 REF_CLK_MMCM_IODELAY_CTRL => REF_CLK_MMCM_IODELAY_CTRL
1204 )
1205 port map
1206 (
1207 -- Outputs
1208 iodelay_ctrl_rdy => iodelay_ctrl_rdy,
1209 sys_rst_o => sys_rst_o,
1210 clk_ref => clk_ref,
1211 -- Inputs
1212 clk_ref_p => clk_ref_p,
1213 clk_ref_n => clk_ref_n,
1214 clk_ref_i => clk_ref_in,
1215 sys_rst => sys_rst
1216 );
1217 u_ddr3_clk_ibuf : mig_7series_v4_2_clk_ibuf
1218 generic map
1219 (
1220 SYSCLK_TYPE => SYSCLK_TYPE,
1221 DIFF_TERM_SYSCLK => DIFF_TERM_SYSCLK
1222 )
1223 port map
1224 (
1225 sys_clk_p => sys_clk_p,
1226 sys_clk_n => sys_clk_n,
1227 sys_clk_i => sys_clk_i,
1228 mmcm_clk => mmcm_clk
1229 );
1230 -- Temperature monitoring logic
1231
1232 temp_mon_enabled : if (TEMP_MON_EN = "ON") generate
1233 u_tempmon : mig_7series_v4_2_tempmon
1234 generic map
1235 (
1236 TCQ => TCQ,
1237 TEMP_MON_CONTROL => TEMP_MON_CONTROL,
1238 XADC_CLK_PERIOD => XADC_CLK_PERIOD,
1239 tTEMPSAMPLE => tTEMPSAMPLE
1240 )
1241 port map
1242 (
1243 clk => clk,
1244 xadc_clk => clk_ref(0),
1245 rst => rst,
1246 device_temp_i => device_temp_i,
1247 device_temp => device_temp_s
1248 );
1249 end generate;
1250
1251 temp_mon_disabled : if (TEMP_MON_EN /= "ON") generate
1252 device_temp_s <= (others => '0');
1253 end generate;
1254
1255
1256 u_ddr3_infrastructure : mig_7series_v4_2_infrastructure
1257 generic map
1258 (
1259 TCQ => TCQ,
1260 nCK_PER_CLK => nCK_PER_CLK,
1261 CLKIN_PERIOD => CLKIN_PERIOD,
1262 SYSCLK_TYPE => SYSCLK_TYPE,
1263 CLKFBOUT_MULT => CLKFBOUT_MULT,
1264 DIVCLK_DIVIDE => DIVCLK_DIVIDE,
1265 CLKOUT0_PHASE => CLKOUT0_PHASE,
1266 CLKOUT0_DIVIDE => CLKOUT0_DIVIDE,
1267 CLKOUT1_DIVIDE => CLKOUT1_DIVIDE,
1268 CLKOUT2_DIVIDE => CLKOUT2_DIVIDE,
1269 CLKOUT3_DIVIDE => CLKOUT3_DIVIDE,
1270 MMCM_VCO => MMCM_VCO,
1271 MMCM_MULT_F => MMCM_MULT_F,
1272 MMCM_DIVCLK_DIVIDE => MMCM_DIVCLK_DIVIDE,
1273 RST_ACT_LOW => RST_ACT_LOW,
1274 tCK => tCK,
1275 MEM_TYPE => DRAM_TYPE
1276 )
1277 port map
1278 (
1279 -- Outputs
1280 rstdiv0 => rst,
1281 clk => clk,
1282 clk_div2 => clk_div2,
1283 rst_div2 => rst_div2,
1284 mem_refclk => mem_refclk,
1285 freq_refclk => freq_refclk,
1286 sync_pulse => sync_pulse,
1287 psen => psen,
1288 psincdec => psincdec,
1289 mmcm_ps_clk => mmcm_ps_clk,
1290 poc_sample_pd => poc_sample_pd,
1291 iddr_rst => iddr_rst,
1292 psdone => psdone,
1293-- auxout_clk => open,
1294 ui_addn_clk_0 => open,
1295 ui_addn_clk_1 => open,
1296 ui_addn_clk_2 => open,
1297 ui_addn_clk_3 => open,
1298 ui_addn_clk_4 => open,
1299 pll_locked => pll_locked,
1300 mmcm_locked => open,
1301 rst_phaser_ref => rst_phaser_ref,
1302 -- Inputs
1303 mmcm_clk => mmcm_clk,
1304 sys_rst => sys_rst_o,
1305 iodelay_ctrl_rdy => iodelay_ctrl_rdy,
1306 ref_dll_lock => ref_dll_lock
1307 );
1308
1309
1310 u_memc_ui_top_std : mig_7series_v4_2_memc_ui_top_std
1311 generic map (
1312 TCQ => TCQ,
1313 ADDR_CMD_MODE => ADDR_CMD_MODE,
1314 AL => AL,
1315 PAYLOAD_WIDTH => PAYLOAD_WIDTH,
1316 BANK_WIDTH => BANK_WIDTH,
1317 BM_CNT_WIDTH => BM_CNT_WIDTH,
1318 BURST_MODE => BURST_MODE,
1319 BURST_TYPE => BURST_TYPE,
1320 CA_MIRROR => CA_MIRROR,
1321 DDR3_VDD_OP_VOLT => VDD_OP_VOLT,
1322 CK_WIDTH => CK_WIDTH,
1323 COL_WIDTH => COL_WIDTH,
1324 CMD_PIPE_PLUS1 => CMD_PIPE_PLUS1,
1325 CS_WIDTH => CS_WIDTH,
1326 nCS_PER_RANK => nCS_PER_RANK,
1327 CKE_WIDTH => CKE_WIDTH,
1328 DATA_WIDTH => DATA_WIDTH,
1329 DATA_BUF_ADDR_WIDTH => DATA_BUF_ADDR_WIDTH,
1330 DM_WIDTH => DM_WIDTH,
1331 DQ_CNT_WIDTH => DQ_CNT_WIDTH,
1332 DQ_WIDTH => DQ_WIDTH,
1333 DQS_CNT_WIDTH => DQS_CNT_WIDTH,
1334 DQS_WIDTH => DQS_WIDTH,
1335 DRAM_TYPE => DRAM_TYPE,
1336 DRAM_WIDTH => DRAM_WIDTH,
1337 ECC => ECC,
1338 ECC_WIDTH => ECC_WIDTH,
1339 ECC_TEST => ECC_TEST,
1340 MC_ERR_ADDR_WIDTH => MC_ERR_ADDR_WIDTH,
1341 REFCLK_FREQ => REFCLK_FREQ,
1342 nAL => nAL,
1343 nBANK_MACHS => nBANK_MACHS,
1344 CKE_ODT_AUX => CKE_ODT_AUX,
1345 nCK_PER_CLK => nCK_PER_CLK,
1346 ORDERING => ORDERING,
1347 OUTPUT_DRV => OUTPUT_DRV,
1348 IBUF_LPWR_MODE => IBUF_LPWR_MODE,
1349 DATA_IO_IDLE_PWRDWN => DATA_IO_IDLE_PWRDWN,
1350 BANK_TYPE => BANK_TYPE,
1351 DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE,
1352 IODELAY_GRP0 => IODELAY_GRP0,
1353 IODELAY_GRP1 => IODELAY_GRP1,
1354 FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
1355 REG_CTRL => REG_CTRL,
1356 RTT_NOM => RTT_NOM,
1357 RTT_WR => RTT_WR,
1358 CL => CL,
1359 CWL => CWL,
1360 tCK => tCK,
1361 tCKE => tCKE,
1362 tFAW => tFAW,
1363 tPRDI => tPRDI,
1364 tRAS => tRAS,
1365 tRCD => tRCD,
1366 tREFI => tREFI,
1367 tRFC => tRFC,
1368 tRP => tRP,
1369 tRRD => tRRD,
1370 tRTP => tRTP,
1371 tWTR => tWTR,
1372 tZQI => tZQI,
1373 tZQCS => tZQCS,
1374 USER_REFRESH => USER_REFRESH,
1375 TEMP_MON_EN => TEMP_MON_EN,
1376 WRLVL => WRLVL,
1377 DEBUG_PORT => DEBUG_PORT,
1378 CAL_WIDTH => CAL_WIDTH,
1379 RANK_WIDTH => RANK_WIDTH,
1380 RANKS => RANKS,
1381 ODT_WIDTH => ODT_WIDTH,
1382 ROW_WIDTH => ROW_WIDTH,
1383 ADDR_WIDTH => ADDR_WIDTH,
1384 APP_DATA_WIDTH => APP_DATA_WIDTH,
1385 APP_MASK_WIDTH => APP_MASK_WIDTH,
1386 SIM_BYPASS_INIT_CAL => SIM_BYPASS_INIT_CAL,
1387 BYTE_LANES_B0 => BYTE_LANES_B0,
1388 BYTE_LANES_B1 => BYTE_LANES_B1,
1389 BYTE_LANES_B2 => BYTE_LANES_B2,
1390 BYTE_LANES_B3 => BYTE_LANES_B3,
1391 BYTE_LANES_B4 => BYTE_LANES_B4,
1392 DATA_CTL_B0 => DATA_CTL_B0,
1393 DATA_CTL_B1 => DATA_CTL_B1,
1394 DATA_CTL_B2 => DATA_CTL_B2,
1395 DATA_CTL_B3 => DATA_CTL_B3,
1396 DATA_CTL_B4 => DATA_CTL_B4,
1397 PHY_0_BITLANES => PHY_0_BITLANES,
1398 PHY_1_BITLANES => PHY_1_BITLANES,
1399 PHY_2_BITLANES => PHY_2_BITLANES,
1400 CK_BYTE_MAP => CK_BYTE_MAP,
1401 ADDR_MAP => ADDR_MAP,
1402 BANK_MAP => BANK_MAP,
1403 CAS_MAP => CAS_MAP,
1404 CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP,
1405 CKE_MAP => CKE_MAP,
1406 ODT_MAP => ODT_MAP,
1407 CS_MAP => CS_MAP,
1408 PARITY_MAP => PARITY_MAP,
1409 RAS_MAP => RAS_MAP,
1410 WE_MAP => WE_MAP,
1411 DQS_BYTE_MAP => DQS_BYTE_MAP,
1412 DATA0_MAP => DATA0_MAP,
1413 DATA1_MAP => DATA1_MAP,
1414 DATA2_MAP => DATA2_MAP,
1415 DATA3_MAP => DATA3_MAP,
1416 DATA4_MAP => DATA4_MAP,
1417 DATA5_MAP => DATA5_MAP,
1418 DATA6_MAP => DATA6_MAP,
1419 DATA7_MAP => DATA7_MAP,
1420 DATA8_MAP => DATA8_MAP,
1421 DATA9_MAP => DATA9_MAP,
1422 DATA10_MAP => DATA10_MAP,
1423 DATA11_MAP => DATA11_MAP,
1424 DATA12_MAP => DATA12_MAP,
1425 DATA13_MAP => DATA13_MAP,
1426 DATA14_MAP => DATA14_MAP,
1427 DATA15_MAP => DATA15_MAP,
1428 DATA16_MAP => DATA16_MAP,
1429 DATA17_MAP => DATA17_MAP,
1430 MASK0_MAP => MASK0_MAP,
1431 MASK1_MAP => MASK1_MAP,
1432 CALIB_ROW_ADD => CALIB_ROW_ADD,
1433 CALIB_COL_ADD => CALIB_COL_ADD,
1434 CALIB_BA_ADD => CALIB_BA_ADD,
1435 SLOT_0_CONFIG => SLOT_0_CONFIG,
1436 SLOT_1_CONFIG => SLOT_1_CONFIG,
1437 MEM_ADDR_ORDER => MEM_ADDR_ORDER,
1438 STARVE_LIMIT => STARVE_LIMIT,
1439 USE_CS_PORT => USE_CS_PORT,
1440 USE_DM_PORT => USE_DM_PORT,
1441 USE_ODT_PORT => USE_ODT_PORT,
1442 MASTER_PHY_CTL => PHY_CONTROL_MASTER_BANK,
1443 IDELAY_ADJ => IDELAY_ADJ,
1444 FINE_PER_BIT => FINE_PER_BIT,
1445 CENTER_COMP_MODE => CENTER_COMP_MODE,
1446 PI_VAL_ADJ => PI_VAL_ADJ,
1447 TAPSPERKCLK => TAPSPERKCLK,
1448 SKIP_CALIB => "FALSE",
1449 FPGA_VOLT_TYPE => FPGA_VOLT_TYPE
1450 )
1451 port map (
1452 clk => clk,
1453 clk_div2 => clk_div2,
1454 rst_div2 => rst_div2,
1455 clk_ref => clk_ref,
1456 mem_refclk => mem_refclk, --memory clock
1457 freq_refclk => freq_refclk,
1458 pll_lock => pll_locked,
1459 sync_pulse => sync_pulse,
1460 rst => rst,
1461 rst_phaser_ref => rst_phaser_ref,
1462 ref_dll_lock => ref_dll_lock,
1463 iddr_rst => iddr_rst,
1464 mmcm_ps_clk => mmcm_ps_clk,
1465 poc_sample_pd => poc_sample_pd,
1466
1467-- Memory interface ports
1468 ddr_dq => ddr3_dq,
1469 ddr_dqs_n => ddr3_dqs_n,
1470 ddr_dqs => ddr3_dqs_p,
1471 ddr_addr => ddr3_addr,
1472 ddr_ba => ddr3_ba,
1473 ddr_cas_n => ddr3_cas_n,
1474 ddr_ck_n => ddr3_ck_n,
1475 ddr_ck => ddr3_ck_p,
1476 ddr_cke => ddr3_cke,
1477 ddr_cs_n => ddr3_cs_n,
1478 ddr_dm => ddr3_dm,
1479 ddr_odt => ddr3_odt,
1480 ddr_ras_n => ddr3_ras_n,
1481 ddr_reset_n => ddr3_reset_n,
1482 ddr_parity => ddr3_parity,
1483 ddr_we_n => ddr3_we_n,
1484 bank_mach_next => bank_mach_next,
1485
1486-- Application interface ports
1487 app_addr => app_addr,
1488 app_cmd => app_cmd,
1489 app_en => app_en,
1490 app_hi_pri => '0',
1491 app_wdf_data => app_wdf_data,
1492 app_wdf_end => app_wdf_end,
1493 app_wdf_mask => app_wdf_mask,
1494 app_wdf_wren => app_wdf_wren,
1495 app_ecc_multiple_err => app_ecc_multiple_err,
1496 app_ecc_single_err => app_ecc_single_err,
1497 app_rd_data => app_rd_data,
1498 app_rd_data_end => app_rd_data_end,
1499 app_rd_data_valid => app_rd_data_valid,
1500 app_rdy => app_rdy,
1501 app_wdf_rdy => app_wdf_rdy,
1502 app_sr_req => app_sr_req,
1503 app_sr_active => app_sr_active,
1504 app_ref_req => app_ref_req,
1505 app_ref_ack => app_ref_ack,
1506 app_zq_req => app_zq_req,
1507 app_zq_ack => app_zq_ack,
1508 app_raw_not_ecc => all_zeros,
1509 app_correct_en_i => '1',
1510
1511 psen => psen,
1512 psincdec => psincdec,
1513 psdone => psdone,
1514 device_temp => device_temp_s,
1515
1516 -- Ports to be used when SKIP_CALIB="TRUE"
1517 calib_tap_req => open,
1518 calib_tap_addr => (others => '0'),
1519 calib_tap_load => '0',
1520 calib_tap_val => (others => '0'),
1521 calib_tap_load_done => '0',
1522
1523-- Debug logic ports
1524 dbg_idel_up_all => dbg_idel_up_all,
1525 dbg_idel_down_all => dbg_idel_down_all,
1526 dbg_idel_up_cpt => dbg_idel_up_cpt,
1527 dbg_idel_down_cpt => dbg_idel_down_cpt,
1528 dbg_sel_idel_cpt => dbg_sel_idel_cpt,
1529 dbg_sel_all_idel_cpt => dbg_sel_all_idel_cpt,
1530 dbg_sel_pi_incdec => dbg_sel_pi_incdec,
1531 dbg_sel_po_incdec => dbg_sel_po_incdec,
1532 dbg_byte_sel => dbg_byte_sel,
1533 dbg_pi_f_inc => dbg_pi_f_inc,
1534 dbg_pi_f_dec => dbg_pi_f_dec,
1535 dbg_po_f_inc => dbg_po_f_inc,
1536 dbg_po_f_stg23_sel => dbg_po_f_stg23_sel,
1537 dbg_po_f_dec => dbg_po_f_dec,
1538 dbg_cpt_tap_cnt => dbg_cpt_tap_cnt,
1539 dbg_dq_idelay_tap_cnt => dbg_dq_idelay_tap_cnt,
1540 dbg_calib_top => dbg_calib_top,
1541 dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt,
1542 dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt,
1543 dbg_rd_data_offset => dbg_rd_data_offset,
1544 dbg_phy_rdlvl => dbg_phy_rdlvl,
1545 dbg_phy_wrcal => dbg_phy_wrcal,
1546 dbg_final_po_fine_tap_cnt => dbg_final_po_fine_tap_cnt,
1547 dbg_final_po_coarse_tap_cnt => dbg_final_po_coarse_tap_cnt,
1548 dbg_rd_data_edge_detect => dbg_rd_data_edge_detect,
1549 dbg_rddata => dbg_rddata,
1550 dbg_rddata_valid => dbg_rddata_valid,
1551 dbg_rdlvl_done => dbg_rdlvl_done,
1552 dbg_rdlvl_err => dbg_rdlvl_err,
1553 dbg_rdlvl_start => dbg_rdlvl_start,
1554 dbg_wrlvl_fine_tap_cnt => dbg_wrlvl_fine_tap_cnt,
1555 dbg_wrlvl_coarse_tap_cnt => dbg_wrlvl_coarse_tap_cnt,
1556 dbg_tap_cnt_during_wrlvl => dbg_tap_cnt_during_wrlvl,
1557 dbg_wl_edge_detect_valid => dbg_wl_edge_detect_valid,
1558 dbg_wrlvl_done => dbg_wrlvl_done,
1559 dbg_wrlvl_err => dbg_wrlvl_err,
1560 dbg_wrlvl_start => dbg_wrlvl_start,
1561 dbg_phy_wrlvl => dbg_phy_wrlvl,
1562 dbg_phy_init => dbg_phy_init,
1563 dbg_prbs_rdlvl => dbg_prbs_rdlvl,
1564 dbg_dqs_found_cal => dbg_dqs_found_cal,
1565 dbg_pi_counter_read_val => dbg_pi_counter_read_val,
1566 dbg_po_counter_read_val => dbg_po_counter_read_val,
1567 dbg_pi_phaselock_start => dbg_pi_phaselock_start,
1568 dbg_pi_phaselocked_done => dbg_pi_phaselocked_done,
1569 dbg_pi_phaselock_err => dbg_pi_phaselock_err,
1570 dbg_pi_phase_locked_phy4lanes => dbg_pi_phase_locked_phy4lanes,
1571 dbg_pi_dqsfound_start => dbg_pi_dqsfound_start,
1572 dbg_pi_dqsfound_done => dbg_pi_dqsfound_done,
1573 dbg_pi_dqsfound_err => dbg_pi_dqsfound_err,
1574 dbg_pi_dqs_found_lanes_phy4lanes => dbg_pi_dqs_found_lanes_phy4lanes,
1575 dbg_calib_rd_data_offset_1 => dbg_calib_rd_data_offset_1,
1576 dbg_calib_rd_data_offset_2 => dbg_calib_rd_data_offset_2,
1577 dbg_data_offset => dbg_data_offset,
1578 dbg_data_offset_1 => dbg_data_offset_1,
1579 dbg_data_offset_2 => dbg_data_offset_2,
1580 dbg_wrcal_start => dbg_wrcal_start,
1581 dbg_wrcal_done => dbg_wrcal_done,
1582 dbg_wrcal_err => dbg_wrcal_err,
1583 dbg_phy_oclkdelay_cal => dbg_phy_oclkdelay_cal,
1584 dbg_oclkdelay_rd_data => dbg_oclkdelay_rd_data,
1585 dbg_oclkdelay_calib_start => dbg_oclkdelay_calib_start,
1586 dbg_oclkdelay_calib_done => dbg_oclkdelay_calib_done,
1587 dbg_prbs_final_dqs_tap_cnt_r => dbg_prbs_final_dqs_tap_cnt_r_int,
1588 dbg_prbs_first_edge_taps => dbg_prbs_first_edge_taps_int,
1589 dbg_prbs_second_edge_taps => dbg_prbs_second_edge_taps_int,
1590 init_calib_complete => init_calib_complete_i,
1591 dbg_poc => open
1592 );
1593
1594
1595
1596
1597
1598
1599
1600 --*********************************************************************
1601 -- Resetting all RTL debug inputs as the debug ports are not enabled
1602 --*********************************************************************
1603 dbg_idel_down_all <= '0';
1604 dbg_idel_down_cpt <= '0';
1605 dbg_idel_up_all <= '0';
1606 dbg_idel_up_cpt <= '0';
1607 dbg_sel_all_idel_cpt <= '0';
1608 dbg_sel_idel_cpt <= (others => '0');
1609 dbg_byte_sel <= (others => '0');
1610 dbg_sel_pi_incdec <= '0';
1611 dbg_pi_f_inc <= '0';
1612 dbg_pi_f_dec <= '0';
1613 dbg_po_f_inc <= '0';
1614 dbg_po_f_dec <= '0';
1615 dbg_po_f_stg23_sel <= '0';
1616 dbg_sel_po_incdec <= '0';
1617
1618
1619
1620end architecture arch_migui_arty_mig;
1621
1622
1623
migui_arty_mig.arch_migui_arty_mig
Definition: migui_arty_mig.vhd:550
u_memc_ui_top_std
mig_7series_v4_2_memc_ui_top_std u_memc_ui_top_stdu_memc_ui_top_std
Definition: migui_arty_mig_sim.vhd:1592
migui_arty_mig.arch_migui_arty_mig.mmcm_ps_clk
std_logic mmcm_ps_clk
Definition: migui_arty_mig.vhd:1054
migui_arty_mig.arch_migui_arty_mig.BM_CNT_WIDTH
integer := clogb2( nBANK_MACHS ) BM_CNT_WIDTH
Definition: migui_arty_mig.vhd:613
migui_arty_mig.arch_migui_arty_mig.sync_pulse
std_logic sync_pulse
Definition: migui_arty_mig.vhd:1053
migui_arty_mig.arch_migui_arty_mig.dbg_oclkdelay_calib_start
std_logic dbg_oclkdelay_calib_start
Definition: migui_arty_mig.vhd:1123
migui_arty_mig.arch_migui_arty_mig.dbg_pi_phase_locked_phy4lanes
std_logic_vector( 11 downto 0) dbg_pi_phase_locked_phy4lanes
Definition: migui_arty_mig.vhd:1122
migui_arty_mig.arch_migui_arty_mig.dbg_wl_edge_detect_valid
std_logic dbg_wl_edge_detect_valid
Definition: migui_arty_mig.vhd:1136
migui_arty_mig.arch_migui_arty_mig.sys_rst_o
std_logic sys_rst_o
Definition: migui_arty_mig.vhd:1047
migui_arty_mig.arch_migui_arty_mig.rd_data_edge_detect_r
std_logic_vector( 8 downto 0) rd_data_edge_detect_r
Definition: migui_arty_mig.vhd:1145
migui_arty_mig.arch_migui_arty_mig.clk_ref_n
std_logic clk_ref_n
Definition: migui_arty_mig.vhd:1075
migui_arty_mig.arch_migui_arty_mig.dbg_final_po_fine_tap_cnt
std_logic_vector(( 6* DQS_WIDTH)- 1 downto 0) dbg_final_po_fine_tap_cnt
Definition: migui_arty_mig.vhd:1106
migui_arty_mig.arch_migui_arty_mig.dbg_prbs_final_dqs_tap_cnt_r
std_logic_vector( 11 downto 0) dbg_prbs_final_dqs_tap_cnt_r
Definition: migui_arty_mig.vhd:1095
migui_arty_mig.arch_migui_arty_mig.dbg_prbs_rdlvl
std_logic_vector( 255 downto 0) dbg_prbs_rdlvl
Definition: migui_arty_mig.vhd:1110
migui_arty_mig.arch_migui_arty_mig.clk
std_logic clk
Definition: migui_arty_mig.vhd:1043
migui_arty_mig.arch_migui_arty_mig.dbg_rdlvl_err
std_logic_vector( 1 downto 0) dbg_rdlvl_err
Definition: migui_arty_mig.vhd:1131
migui_arty_mig.arch_migui_arty_mig.ref_dll_lock
std_logic ref_dll_lock
Definition: migui_arty_mig.vhd:1060
migui_arty_mig.arch_migui_arty_mig.dbg_pi_dqs_found_lanes_phy4lanes
std_logic_vector( 11 downto 0) dbg_pi_dqs_found_lanes_phy4lanes
Definition: migui_arty_mig.vhd:1121
migui_arty_mig.arch_migui_arty_mig.dbg_prbs_first_edge_taps
std_logic_vector( 11 downto 0) dbg_prbs_first_edge_taps
Definition: migui_arty_mig.vhd:1096
migui_arty_mig.arch_migui_arty_mig.dbg_wrlvl_err
std_logic dbg_wrlvl_err
Definition: migui_arty_mig.vhd:1138
migui_arty_mig.arch_migui_arty_mig.dbg_sel_all_idel_cpt
std_logic dbg_sel_all_idel_cpt
Definition: migui_arty_mig.vhd:1083
migui_arty_mig.arch_migui_arty_mig.dbg_dqs
std_logic_vector( 4 downto 0) dbg_dqs
Definition: migui_arty_mig.vhd:1143
migui_arty_mig.arch_migui_arty_mig.RANK_WIDTH
integer := clogb2( RANKS ) RANK_WIDTH
Definition: migui_arty_mig.vhd:588
migui_arty_mig.arch_migui_arty_mig.iodelay_ctrl_rdy
std_logic_vector( 1 downto 0) iodelay_ctrl_rdy
Definition: migui_arty_mig.vhd:1045
migui_arty_mig.arch_migui_arty_mig.dbg_rdlvl_done
std_logic_vector( 1 downto 0) dbg_rdlvl_done
Definition: migui_arty_mig.vhd:1130
migui_arty_mig.arch_migui_arty_mig.clk_ref
std_logic_vector( 1 downto 0) clk_ref
Definition: migui_arty_mig.vhd:1044
migui_arty_mig.arch_migui_arty_mig.dbg_sel_pi_incdec
std_logic dbg_sel_pi_incdec
Definition: migui_arty_mig.vhd:1086
migui_arty_mig.arch_migui_arty_mig.dbg_wrcal_err
std_logic dbg_wrcal_err
Definition: migui_arty_mig.vhd:1120
u_iodelay_ctrl
mig_7series_v4_2_iodelay_ctrl u_iodelay_ctrlu_iodelay_ctrl
Definition: migui_arty_mig_sim.vhd:1216
migui_arty_mig.arch_migui_arty_mig.dbg_po_f_dec
std_logic dbg_po_f_dec
Definition: migui_arty_mig.vhd:1092
migui_arty_mig.arch_migui_arty_mig.MC_ERR_ADDR_WIDTH
integer := XWIDTH+ BANK_WIDTH+ ROW_WIDTH+ COL_WIDTH+ DATA_BUF_OFFSET_WIDTH MC_ERR_ADDR_WIDTH
Definition: migui_arty_mig.vhd:616
migui_arty_mig.arch_migui_arty_mig.ddr3_ila_basic_int
std_logic_vector( 119 downto 0) ddr3_ila_basic_int
Definition: migui_arty_mig.vhd:1155
migui_arty_mig.arch_migui_arty_mig.device_temp_s
std_logic_vector( 11 downto 0) device_temp_s
Definition: migui_arty_mig.vhd:1076
migui_arty_mig.arch_migui_arty_mig.dbg_rdlvl_start
std_logic_vector( 1 downto 0) dbg_rdlvl_start
Definition: migui_arty_mig.vhd:1132
migui_arty_mig.arch_migui_arty_mig.sys_clk_n
std_logic sys_clk_n
Definition: migui_arty_mig.vhd:1072
migui_arty_mig.arch_migui_arty_mig.iddr_rst
std_logic iddr_rst
Definition: migui_arty_mig.vhd:1059
migui_arty_mig.arch_migui_arty_mig.dbg_dqs_found_cal
std_logic_vector( 255 downto 0) dbg_dqs_found_cal
Definition: migui_arty_mig.vhd:1111
migui_arty_mig.arch_migui_arty_mig.dbg_byte_sel
std_logic_vector( DQS_CNT_WIDTH downto 0) dbg_byte_sel
Definition: migui_arty_mig.vhd:1088
migui_arty_mig.arch_migui_arty_mig.dbg_idel_up_cpt
std_logic dbg_idel_up_cpt
Definition: migui_arty_mig.vhd:1082
migui_arty_mig.arch_migui_arty_mig.app_ecc_single_err
std_logic_vector(( 2* nCK_PER_CLK)- 1 downto 0) app_ecc_single_err
Definition: migui_arty_mig.vhd:1066
migui_arty_mig.arch_migui_arty_mig.dbg_pi_dqsfound_err
std_logic dbg_pi_dqsfound_err
Definition: migui_arty_mig.vhd:1117
migui_arty_mig.arch_migui_arty_mig.dbg_sel_po_incdec
std_logic dbg_sel_po_incdec
Definition: migui_arty_mig.vhd:1087
migui_arty_mig.arch_migui_arty_mig.dbg_oclkdelay_rd_data
std_logic_vector(( DRAM_WIDTH* 16)- 1 downto 0) dbg_oclkdelay_rd_data
Definition: migui_arty_mig.vhd:1126
migui_arty_mig.arch_migui_arty_mig.ocal_tap_cnt
std_logic_vector( 53 downto 0) ocal_tap_cnt
Definition: migui_arty_mig.vhd:1142
migui_arty_mig.arch_migui_arty_mig.dbg_rddata_r
std_logic_vector( 63 downto 0) dbg_rddata_r
Definition: migui_arty_mig.vhd:1140
migui_arty_mig.arch_migui_arty_mig.dbg_dq_idelay_tap_cnt
std_logic_vector(( 5* DQS_WIDTH* RANKS)- 1 downto 0) dbg_dq_idelay_tap_cnt
Definition: migui_arty_mig.vhd:1099
migui_arty_mig.arch_migui_arty_mig.freq_refclk
std_logic freq_refclk
Definition: migui_arty_mig.vhd:1050
migui_arty_mig.arch_migui_arty_mig.dbg_pi_phaselocked_done
std_logic dbg_pi_phaselocked_done
Definition: migui_arty_mig.vhd:1113
migui_arty_mig.arch_migui_arty_mig.dbg_phy_rdlvl
std_logic_vector( 255 downto 0) dbg_phy_rdlvl
Definition: migui_arty_mig.vhd:1104
migui_arty_mig.arch_migui_arty_mig.dbg_data_offset
std_logic_vector( 5 downto 0) dbg_data_offset
Definition: migui_arty_mig.vhd:1150
migui_arty_mig.arch_migui_arty_mig.dbg_rddata_valid_r
std_logic dbg_rddata_valid_r
Definition: migui_arty_mig.vhd:1141
migui_arty_mig.arch_migui_arty_mig.TEMP_MON_EN
string := TEMP_MON TEMP_MON_EN
Definition: migui_arty_mig.vhd:620
migui_arty_mig.arch_migui_arty_mig.dbg_pi_counter_read_val
std_logic_vector( 5 downto 0) dbg_pi_counter_read_val
Definition: migui_arty_mig.vhd:1093
migui_arty_mig.arch_migui_arty_mig.dbg_rddata
std_logic_vector(( 2* nCK_PER_CLK* DQ_WIDTH)- 1 downto 0) dbg_rddata
Definition: migui_arty_mig.vhd:1128
migui_arty_mig.arch_migui_arty_mig.dbg_oclkdelay_calib_done
std_logic dbg_oclkdelay_calib_done
Definition: migui_arty_mig.vhd:1124
migui_arty_mig.arch_migui_arty_mig.clk_ref_in
std_logic clk_ref_in
Definition: migui_arty_mig.vhd:1046
migui_arty_mig.arch_migui_arty_mig.dbg_po_f_inc
std_logic dbg_po_f_inc
Definition: migui_arty_mig.vhd:1090
migui_arty_mig.arch_migui_arty_mig.dbg_pi_phaselock_start
std_logic dbg_pi_phaselock_start
Definition: migui_arty_mig.vhd:1112
migui_arty_mig.arch_migui_arty_mig.dbg_cpt_tap_cnt
std_logic_vector(( 6* DQS_WIDTH* RANKS)- 1 downto 0) dbg_cpt_tap_cnt
Definition: migui_arty_mig.vhd:1098
u_tempmon
mig_7series_v4_2_tempmon u_tempmonu_tempmon
Definition: migui_arty_mig_sim.vhd:1248
migui_arty_mig.arch_migui_arty_mig.TAPSPERKCLK
integer :=( 56* MMCM_MULT_F)/ nCK_PER_CLK TAPSPERKCLK
Definition: migui_arty_mig.vhd:599
migui_arty_mig.arch_migui_arty_mig.mmcm_clk
std_logic mmcm_clk
Definition: migui_arty_mig.vhd:1073
migui_arty_mig.arch_migui_arty_mig.ddr3_ila_rdpath_int
std_logic_vector( 1023 downto 0) ddr3_ila_rdpath_int
Definition: migui_arty_mig.vhd:1157
migui_arty_mig.arch_migui_arty_mig.psen
std_logic psen
Definition: migui_arty_mig.vhd:1056
migui_arty_mig.arch_migui_arty_mig.psincdec
std_logic psincdec
Definition: migui_arty_mig.vhd:1057
migui_arty_mig.arch_migui_arty_mig.ECC_WIDTH
integer := ECCWIDTH ECC_WIDTH
Definition: migui_arty_mig.vhd:614
migui_arty_mig.arch_migui_arty_mig.dbg_wrlvl_start
std_logic dbg_wrlvl_start
Definition: migui_arty_mig.vhd:1139
migui_arty_mig.arch_migui_arty_mig.dbg_rd_data_edge_detect
std_logic_vector( DQS_WIDTH- 1 downto 0) dbg_rd_data_edge_detect
Definition: migui_arty_mig.vhd:1127
migui_arty_mig.arch_migui_arty_mig.clk_ref_p
std_logic clk_ref_p
Definition: migui_arty_mig.vhd:1074
migui_arty_mig.arch_migui_arty_mig.dbg_calib_top
std_logic_vector( 255 downto 0) dbg_calib_top
Definition: migui_arty_mig.vhd:1100
migui_arty_mig.arch_migui_arty_mig.dbg_phy_oclkdelay_cal
std_logic_vector( 255 downto 0) dbg_phy_oclkdelay_cal
Definition: migui_arty_mig.vhd:1125
migui_arty_mig.arch_migui_arty_mig.dbg_idel_up_all
std_logic dbg_idel_up_all
Definition: migui_arty_mig.vhd:1081
migui_arty_mig.arch_migui_arty_mig.app_ecc_multiple_err
std_logic_vector(( 2* nCK_PER_CLK)- 1 downto 0) app_ecc_multiple_err
Definition: migui_arty_mig.vhd:1065
migui_arty_mig.arch_migui_arty_mig.dbg_wrcal_start
std_logic dbg_wrcal_start
Definition: migui_arty_mig.vhd:1118
migui_arty_mig.arch_migui_arty_mig.dbg_wrcal_done
std_logic dbg_wrcal_done
Definition: migui_arty_mig.vhd:1119
migui_arty_mig.arch_migui_arty_mig.poc_sample_pd
std_logic poc_sample_pd
Definition: migui_arty_mig.vhd:1055
migui_arty_mig.arch_migui_arty_mig.dbg_prbs_second_edge_taps_int
std_logic_vector( 11 downto 0) dbg_prbs_second_edge_taps_int
Definition: migui_arty_mig.vhd:1160
migui_arty_mig.arch_migui_arty_mig.XADC_CLK_PERIOD
integer := 5000 XADC_CLK_PERIOD
Definition: migui_arty_mig.vhd:623
migui_arty_mig.arch_migui_arty_mig.dbg_wrlvl_done
std_logic dbg_wrlvl_done
Definition: migui_arty_mig.vhd:1137
migui_arty_mig.arch_migui_arty_mig.psdone
std_logic psdone
Definition: migui_arty_mig.vhd:1058
migui_arty_mig.arch_migui_arty_mig.dbg_calib_rd_data_offset_1
std_logic_vector(( 6* RANKS)- 1 downto 0) dbg_calib_rd_data_offset_1
Definition: migui_arty_mig.vhd:1148
migui_arty_mig.arch_migui_arty_mig.dbg_pi_phaselock_err
std_logic dbg_pi_phaselock_err
Definition: migui_arty_mig.vhd:1114
migui_arty_mig.arch_migui_arty_mig.mem_refclk
std_logic mem_refclk
Definition: migui_arty_mig.vhd:1051
migui_arty_mig.arch_migui_arty_mig.dbg_data_offset_2
std_logic_vector( 5 downto 0) dbg_data_offset_2
Definition: migui_arty_mig.vhd:1152
migui_arty_mig.arch_migui_arty_mig.dbg_tap_cnt_during_wrlvl
std_logic_vector( 5 downto 0) dbg_tap_cnt_during_wrlvl
Definition: migui_arty_mig.vhd:1135
migui_arty_mig.arch_migui_arty_mig.dbg_phy_wrlvl
std_logic_vector( 255 downto 0) dbg_phy_wrlvl
Definition: migui_arty_mig.vhd:1108
migui_arty_mig.arch_migui_arty_mig.dbg_prbs_second_edge_taps
std_logic_vector( 11 downto 0) dbg_prbs_second_edge_taps
Definition: migui_arty_mig.vhd:1097
migui_arty_mig.arch_migui_arty_mig.ddr3_ila_wrpath_int
std_logic_vector( 390 downto 0) ddr3_ila_wrpath_int
Definition: migui_arty_mig.vhd:1156
migui_arty_mig.arch_migui_arty_mig.rst
std_logic rst
Definition: migui_arty_mig.vhd:1063
migui_arty_mig.arch_migui_arty_mig.dbg_cpt_second_edge_cnt
std_logic_vector(( 6* DQS_WIDTH* RANKS)- 1 downto 0) dbg_cpt_second_edge_cnt
Definition: migui_arty_mig.vhd:1102
migui_arty_mig.arch_migui_arty_mig.dbg_wrlvl_fine_tap_cnt
std_logic_vector(( 6* DQS_WIDTH)- 1 downto 0) dbg_wrlvl_fine_tap_cnt
Definition: migui_arty_mig.vhd:1133
migui_arty_mig.arch_migui_arty_mig.wl_po_fine_cnt
std_logic_vector( 53 downto 0) wl_po_fine_cnt
Definition: migui_arty_mig.vhd:1146
migui_arty_mig.arch_migui_arty_mig.dbg_final_po_coarse_tap_cnt
std_logic_vector(( 3* DQS_WIDTH)- 1 downto 0) dbg_final_po_coarse_tap_cnt
Definition: migui_arty_mig.vhd:1107
migui_arty_mig.arch_migui_arty_mig.rst_phaser_ref
std_logic rst_phaser_ref
Definition: migui_arty_mig.vhd:1061
migui_arty_mig.arch_migui_arty_mig.bank_mach_next
std_logic_vector( BM_CNT_WIDTH- 1 downto 0) bank_mach_next
Definition: migui_arty_mig.vhd:1042
migui_arty_mig.arch_migui_arty_mig.dbg_rd_data_offset
std_logic_vector(( 6* RANKS)- 1 downto 0) dbg_rd_data_offset
Definition: migui_arty_mig.vhd:1103
migui_arty_mig.arch_migui_arty_mig.clk_div2
std_logic clk_div2
Definition: migui_arty_mig.vhd:1048
migui_arty_mig.arch_migui_arty_mig.APP_MASK_WIDTH
integer := APP_DATA_WIDTH/ 8 APP_MASK_WIDTH
Definition: migui_arty_mig.vhd:619
migui_arty_mig.arch_migui_arty_mig.all_zeros
std_logic_vector(( 2* nCK_PER_CLK)- 1 downto 0) :=( others => '0') all_zeros
Definition: migui_arty_mig.vhd:1153
migui_arty_mig.arch_migui_arty_mig.dbg_idel_down_all
std_logic dbg_idel_down_all
Definition: migui_arty_mig.vhd:1079
migui_arty_mig.arch_migui_arty_mig.dbg_pi_f_dec
std_logic dbg_pi_f_dec
Definition: migui_arty_mig.vhd:1091
migui_arty_mig.arch_migui_arty_mig.dbg_wrlvl_coarse_tap_cnt
std_logic_vector(( 3* DQS_WIDTH)- 1 downto 0) dbg_wrlvl_coarse_tap_cnt
Definition: migui_arty_mig.vhd:1134
migui_arty_mig.arch_migui_arty_mig.dbg_pi_f_inc
std_logic dbg_pi_f_inc
Definition: migui_arty_mig.vhd:1089
u_ddr3_clk_ibuf
mig_7series_v4_2_clk_ibuf u_ddr3_clk_ibufu_ddr3_clk_ibuf
Definition: migui_arty_mig_sim.vhd:1229
migui_arty_mig.arch_migui_arty_mig.dbg_idel_down_cpt
std_logic dbg_idel_down_cpt
Definition: migui_arty_mig.vhd:1080
migui_arty_mig.arch_migui_arty_mig.init_calib_complete_i
std_logic init_calib_complete_i
Definition: migui_arty_mig.vhd:1069
migui_arty_mig.arch_migui_arty_mig.wl_po_coarse_cnt
std_logic_vector( 26 downto 0) wl_po_coarse_cnt
Definition: migui_arty_mig.vhd:1147
migui_arty_mig.arch_migui_arty_mig.APP_DATA_WIDTH
integer := 2* nCK_PER_CLK* PAYLOAD_WIDTH APP_DATA_WIDTH
Definition: migui_arty_mig.vhd:618
migui_arty_mig.arch_migui_arty_mig.dbg_calib_rd_data_offset_2
std_logic_vector(( 6* RANKS)- 1 downto 0) dbg_calib_rd_data_offset_2
Definition: migui_arty_mig.vhd:1149
migui_arty_mig.arch_migui_arty_mig.dbg_prbs_first_edge_taps_int
std_logic_vector( 11 downto 0) dbg_prbs_first_edge_taps_int
Definition: migui_arty_mig.vhd:1159
migui_arty_mig.arch_migui_arty_mig.dbg_phy_init
std_logic_vector( 255 downto 0) dbg_phy_init
Definition: migui_arty_mig.vhd:1109
migui_arty_mig.arch_migui_arty_mig.rst_div2
std_logic rst_div2
Definition: migui_arty_mig.vhd:1049
migui_arty_mig.arch_migui_arty_mig.dbg_pi_dqsfound_start
std_logic dbg_pi_dqsfound_start
Definition: migui_arty_mig.vhd:1115
migui_arty_mig.arch_migui_arty_mig.dbg_phy_wrcal
std_logic_vector( 99 downto 0) dbg_phy_wrcal
Definition: migui_arty_mig.vhd:1105
migui_arty_mig.arch_migui_arty_mig.ddr3_parity
std_logic ddr3_parity
Definition: migui_arty_mig.vhd:1067
migui_arty_mig.arch_migui_arty_mig.pll_locked
std_logic pll_locked
Definition: migui_arty_mig.vhd:1052
migui_arty_mig.arch_migui_arty_mig.clogb2
integer clogb2size,
Definition: migui_arty_mig.vhd:554
migui_arty_mig.arch_migui_arty_mig.dbg_data_offset_1
std_logic_vector( 5 downto 0) dbg_data_offset_1
Definition: migui_arty_mig.vhd:1151
migui_arty_mig.arch_migui_arty_mig.dbg_prbs_final_dqs_tap_cnt_r_int
std_logic_vector( 11 downto 0) dbg_prbs_final_dqs_tap_cnt_r_int
Definition: migui_arty_mig.vhd:1158
migui_arty_mig.arch_migui_arty_mig.dbg_rddata_valid
std_logic dbg_rddata_valid
Definition: migui_arty_mig.vhd:1129
migui_arty_mig.arch_migui_arty_mig.tTEMPSAMPLE
integer := 10000000 tTEMPSAMPLE
Definition: migui_arty_mig.vhd:622
migui_arty_mig.arch_migui_arty_mig.DATA_BUF_OFFSET_WIDTH
integer := 1 DATA_BUF_OFFSET_WIDTH
Definition: migui_arty_mig.vhd:615
migui_arty_mig.arch_migui_arty_mig.sys_clk_p
std_logic sys_clk_p
Definition: migui_arty_mig.vhd:1071
migui_arty_mig.arch_migui_arty_mig.dbg_sel_idel_cpt
std_logic_vector( DQS_CNT_WIDTH- 1 downto 0) dbg_sel_idel_cpt
Definition: migui_arty_mig.vhd:1084
migui_arty_mig.arch_migui_arty_mig.dbg_cpt_first_edge_cnt
std_logic_vector(( 6* DQS_WIDTH* RANKS)- 1 downto 0) dbg_cpt_first_edge_cnt
Definition: migui_arty_mig.vhd:1101
migui_arty_mig.arch_migui_arty_mig.dbg_pi_dqsfound_done
std_logic dbg_pi_dqsfound_done
Definition: migui_arty_mig.vhd:1116
migui_arty_mig.arch_migui_arty_mig.dbg_po_f_stg23_sel
std_logic dbg_po_f_stg23_sel
Definition: migui_arty_mig.vhd:1085
migui_arty_mig.arch_migui_arty_mig.dbg_bit
std_logic_vector( 8 downto 0) dbg_bit
Definition: migui_arty_mig.vhd:1144
migui_arty_mig.arch_migui_arty_mig.dbg_po_counter_read_val
std_logic_vector( 8 downto 0) dbg_po_counter_read_val
Definition: migui_arty_mig.vhd:1094
u_ddr3_infrastructure
mig_7series_v4_2_infrastructure u_ddr3_infrastructureu_ddr3_infrastructure
Definition: migui_arty_mig_sim.vhd:1307
migui_arty_mig
Definition: migui_arty_mig.vhd:77
migui_arty_mig.BYTE_LANES_B4
BYTE_LANES_B4 std_logic_vector( 3 downto 0) := "0000"
Definition: migui_arty_mig.vhd:306
migui_arty_mig.app_sr_req
in app_sr_req std_logic
Definition: migui_arty_mig.vhd:524
migui_arty_mig.FPGA_SPEED_GRADE
FPGA_SPEED_GRADE integer := 1
Definition: migui_arty_mig.vhd:430
migui_arty_mig.DATA_CTL_B3
DATA_CTL_B3 std_logic_vector( 3 downto 0) := "0000"
Definition: migui_arty_mig.vhd:323
migui_arty_mig.VDD_OP_VOLT
VDD_OP_VOLT string := "135"
Definition: migui_arty_mig.vhd:217
migui_arty_mig.DQS_WIDTH
DQS_WIDTH integer := 2
Definition: migui_arty_mig.vhd:102
migui_arty_mig.device_temp_i
in device_temp_i std_logic_vector( 11 downto 0)
Definition: migui_arty_mig.vhd:535
migui_arty_mig.SIMULATION
SIMULATION string := "FALSE"
Definition: migui_arty_mig.vhd:289
migui_arty_mig.USE_ODT_PORT
USE_ODT_PORT integer := 1
Definition: migui_arty_mig.vhd:144
migui_arty_mig.ddr3_cke
out ddr3_cke std_logic_vector( CKE_WIDTH- 1 downto 0)
Definition: migui_arty_mig.vhd:501
migui_arty_mig.PHY_1_BITLANES
PHY_1_BITLANES std_logic_vector( 47 downto 0) := X"000000000000"
Definition: migui_arty_mig.vhd:334
migui_arty_mig.tREFI
tREFI integer := 7800000
Definition: migui_arty_mig.vhd:262
migui_arty_mig.app_rd_data
out app_rd_data std_logic_vector(( nCK_PER_CLK* 2* PAYLOAD_WIDTH)- 1 downto 0)
Definition: migui_arty_mig.vhd:519
migui_arty_mig.ddr3_cas_n
out ddr3_cas_n std_logic
Definition: migui_arty_mig.vhd:496
migui_arty_mig.TCQ
TCQ integer := 100
Definition: migui_arty_mig.vhd:406
migui_arty_mig.PAYLOAD_WIDTH
PAYLOAD_WIDTH integer := 16
Definition: migui_arty_mig.vhd:110
migui_arty_mig.ddr3_cs_n
out ddr3_cs_n std_logic_vector(( CS_WIDTH* nCS_PER_RANK)- 1 downto 0)
Definition: migui_arty_mig.vhd:502
migui_arty_mig.BYTE_LANES_B1
BYTE_LANES_B1 std_logic_vector( 3 downto 0) := "0000"
Definition: migui_arty_mig.vhd:300
migui_arty_mig.nBANK_MACHS
nBANK_MACHS integer := 2
Definition: migui_arty_mig.vhd:120
migui_arty_mig.REFCLK_TYPE
REFCLK_TYPE string := "NO_BUFFER"
Definition: migui_arty_mig.vhd:422
migui_arty_mig.app_cmd
in app_cmd std_logic_vector( 2 downto 0)
Definition: migui_arty_mig.vhd:513
migui_arty_mig.nCK_PER_CLK
nCK_PER_CLK integer := 4
Definition: migui_arty_mig.vhd:456
migui_arty_mig.DIFF_TERM_REFCLK
DIFF_TERM_REFCLK string := "TRUE"
Definition: migui_arty_mig.vhd:447
migui_arty_mig.app_zq_ack
out app_zq_ack std_logic
Definition: migui_arty_mig.vhd:529
migui_arty_mig.DATA_CTL_B4
DATA_CTL_B4 std_logic_vector( 3 downto 0) := "0000"
Definition: migui_arty_mig.vhd:328
migui_arty_mig.DQ_PER_DM
DQ_PER_DM integer := 8
Definition: migui_arty_mig.vhd:97
migui_arty_mig.IDELAY_ADJ
IDELAY_ADJ string := "OFF"
Definition: migui_arty_mig.vhd:407
migui_arty_mig.IBUF_LPWR_MODE
IBUF_LPWR_MODE string := "OFF"
Definition: migui_arty_mig.vhd:382
migui_arty_mig.FINE_PER_BIT
FINE_PER_BIT string := "OFF"
Definition: migui_arty_mig.vhd:408
migui_arty_mig.CLKOUT0_PHASE
CLKOUT0_PHASE real := 0.0
Definition: migui_arty_mig.vhd:231
migui_arty_mig.app_wdf_end
in app_wdf_end std_logic
Definition: migui_arty_mig.vhd:516
migui_arty_mig.BYTE_LANES_B2
BYTE_LANES_B2 std_logic_vector( 3 downto 0) := "0000"
Definition: migui_arty_mig.vhd:302
migui_arty_mig.app_zq_req
in app_zq_req std_logic
Definition: migui_arty_mig.vhd:526
migui_arty_mig.CWL
CWL integer := 5
Definition: migui_arty_mig.vhd:192
migui_arty_mig.tRTP
tRTP integer := 7500
Definition: migui_arty_mig.vhd:270
migui_arty_mig.CENTER_COMP_MODE
CENTER_COMP_MODE string := "OFF"
Definition: migui_arty_mig.vhd:409
migui_arty_mig.RST_ACT_LOW
RST_ACT_LOW integer := 0
Definition: migui_arty_mig.vhd:484
migui_arty_mig.PHY_0_BITLANES
PHY_0_BITLANES std_logic_vector( 47 downto 0) := X"3FE3FEFFFBFF"
Definition: migui_arty_mig.vhd:333
migui_arty_mig.MMCM_DIVCLK_DIVIDE
MMCM_DIVCLK_DIVIDE integer := 1
Definition: migui_arty_mig.vhd:245
migui_arty_mig.device_temp
out device_temp std_logic_vector( 11 downto 0)
Definition: migui_arty_mig.vhd:539
migui_arty_mig.CAS_MAP
CAS_MAP std_logic_vector( 11 downto 0) := X"015"
Definition: migui_arty_mig.vhd:343
migui_arty_mig.DATA3_MAP
DATA3_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: migui_arty_mig.vhd:356
migui_arty_mig.ddr3_dqs_p
inout ddr3_dqs_p std_logic_vector( DQS_WIDTH- 1 downto 0)
Definition: migui_arty_mig.vhd:489
migui_arty_mig.BYTE_LANES_B0
BYTE_LANES_B0 std_logic_vector( 3 downto 0) := "1111"
Definition: migui_arty_mig.vhd:298
migui_arty_mig.DATA_WIDTH
DATA_WIDTH integer := 16
Definition: migui_arty_mig.vhd:109
migui_arty_mig.IODELAY_GRP1
IODELAY_GRP1 string := "MIGUI_ARTY_IODELAY_MIG1"
Definition: migui_arty_mig.vhd:415
migui_arty_mig.DATA0_MAP
DATA0_MAP std_logic_vector( 95 downto 0) := X"034032038035031037036033"
Definition: migui_arty_mig.vhd:353
migui_arty_mig.app_wdf_rdy
out app_wdf_rdy std_logic
Definition: migui_arty_mig.vhd:523
migui_arty_mig.tZQI
tZQI integer := 128000000
Definition: migui_arty_mig.vhd:274
migui_arty_mig.USER_REFRESH
USER_REFRESH string := "OFF"
Definition: migui_arty_mig.vhd:391
migui_arty_mig.DQ_CNT_WIDTH
DQ_CNT_WIDTH integer := 4
Definition: migui_arty_mig.vhd:95
migui_arty_mig.tWTR
tWTR integer := 7500
Definition: migui_arty_mig.vhd:272
migui_arty_mig.DRAM_TYPE
DRAM_TYPE string := "DDR3"
Definition: migui_arty_mig.vhd:436
migui_arty_mig.MEM_DEVICE_WIDTH
MEM_DEVICE_WIDTH integer := 16
Definition: migui_arty_mig.vhd:160
migui_arty_mig.FPGA_VOLT_TYPE
FPGA_VOLT_TYPE string := "N"
Definition: migui_arty_mig.vhd:477
migui_arty_mig.BANK_TYPE
BANK_TYPE string := "HR_IO"
Definition: migui_arty_mig.vhd:386
migui_arty_mig.ddr3_addr
out ddr3_addr std_logic_vector( ROW_WIDTH- 1 downto 0)
Definition: migui_arty_mig.vhd:493
migui_arty_mig.CLKIN_PERIOD
CLKIN_PERIOD integer := 6000
Definition: migui_arty_mig.vhd:225
migui_arty_mig.DATA7_MAP
DATA7_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: migui_arty_mig.vhd:360
migui_arty_mig.MEM_DENSITY
MEM_DENSITY string := "2Gb"
Definition: migui_arty_mig.vhd:154
migui_arty_mig.tZQCS
tZQCS integer := 64
Definition: migui_arty_mig.vhd:276
migui_arty_mig.CKE_ODT_BYTE_MAP
CKE_ODT_BYTE_MAP std_logic_vector( 7 downto 0) := X"00"
Definition: migui_arty_mig.vhd:344
migui_arty_mig.app_rd_data_end
out app_rd_data_end std_logic
Definition: migui_arty_mig.vhd:520
migui_arty_mig.IODELAY_GRP0
IODELAY_GRP0 string := "MIGUI_ARTY_IODELAY_MIG0"
Definition: migui_arty_mig.vhd:411
migui_arty_mig.CLKFBOUT_MULT
CLKFBOUT_MULT integer := 8
Definition: migui_arty_mig.vhd:227
migui_arty_mig.DATA11_MAP
DATA11_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: migui_arty_mig.vhd:364
migui_arty_mig.ddr3_we_n
out ddr3_we_n std_logic
Definition: migui_arty_mig.vhd:497
migui_arty_mig.ddr3_dq
inout ddr3_dq std_logic_vector( DQ_WIDTH- 1 downto 0)
Definition: migui_arty_mig.vhd:488
migui_arty_mig.DRAM_WIDTH
DRAM_WIDTH integer := 8
Definition: migui_arty_mig.vhd:105
migui_arty_mig.ddr3_ras_n
out ddr3_ras_n std_logic
Definition: migui_arty_mig.vhd:495
migui_arty_mig.CKE_WIDTH
CKE_WIDTH integer := 1
Definition: migui_arty_mig.vhd:92
migui_arty_mig.DIVCLK_DIVIDE
DIVCLK_DIVIDE integer := 1
Definition: migui_arty_mig.vhd:229
migui_arty_mig.BURST_TYPE
BURST_TYPE string := "SEQ"
Definition: migui_arty_mig.vhd:183
migui_arty_mig.DATA10_MAP
DATA10_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: migui_arty_mig.vhd:363
migui_arty_mig.WRLVL
WRLVL string := "ON"
Definition: migui_arty_mig.vhd:392
migui_arty_mig.init_calib_complete
out init_calib_complete std_logic
Definition: migui_arty_mig.vhd:534
migui_arty_mig.sys_clk_i
in sys_clk_i std_logic
Definition: migui_arty_mig.vhd:508
migui_arty_mig.CKE_MAP
CKE_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000019"
Definition: migui_arty_mig.vhd:345
migui_arty_mig.CALIB_ROW_ADD
CALIB_ROW_ADD std_logic_vector( 15 downto 0) := X"0000"
Definition: migui_arty_mig.vhd:397
migui_arty_mig.CKE_ODT_AUX
CKE_ODT_AUX string := "FALSE"
Definition: migui_arty_mig.vhd:390
migui_arty_mig.AL
AL string := "0"
Definition: migui_arty_mig.vhd:167
migui_arty_mig.DATA15_MAP
DATA15_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: migui_arty_mig.vhd:368
migui_arty_mig.ROW_WIDTH
ROW_WIDTH integer := 14
Definition: migui_arty_mig.vhd:125
migui_arty_mig.tRCD
tRCD integer := 13500
Definition: migui_arty_mig.vhd:260
migui_arty_mig.tFAW
tFAW integer := 45000
Definition: migui_arty_mig.vhd:254
migui_arty_mig.clk_ref_i
in clk_ref_i std_logic
Definition: migui_arty_mig.vhd:510
migui_arty_mig.app_ref_req
in app_ref_req std_logic
Definition: migui_arty_mig.vhd:525
migui_arty_mig.ddr3_ba
out ddr3_ba std_logic_vector( BANK_WIDTH- 1 downto 0)
Definition: migui_arty_mig.vhd:494
migui_arty_mig.CK_BYTE_MAP
CK_BYTE_MAP std_logic_vector( 143 downto 0) := X"000000000000000000000000000000000000"
Definition: migui_arty_mig.vhd:339
migui_arty_mig.USE_DM_PORT
USE_DM_PORT integer := 1
Definition: migui_arty_mig.vhd:137
migui_arty_mig.DATA_IO_PRIM_TYPE
DATA_IO_PRIM_TYPE string := "DEFAULT"
Definition: migui_arty_mig.vhd:388
migui_arty_mig.app_sr_active
out app_sr_active std_logic
Definition: migui_arty_mig.vhd:527
migui_arty_mig.CAL_WIDTH
CAL_WIDTH string := "HALF"
Definition: migui_arty_mig.vhd:437
migui_arty_mig.DATA12_MAP
DATA12_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: migui_arty_mig.vhd:365
migui_arty_mig.MEM_ADDR_ORDER
MEM_ADDR_ORDER string := "ROW_BANK_COLUMN"
Definition: migui_arty_mig.vhd:111
migui_arty_mig.DATA16_MAP
DATA16_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: migui_arty_mig.vhd:369
migui_arty_mig.app_rd_data_valid
out app_rd_data_valid std_logic
Definition: migui_arty_mig.vhd:521
migui_arty_mig.ADDR_WIDTH
ADDR_WIDTH integer := 28
Definition: migui_arty_mig.vhd:127
migui_arty_mig.RANKS
RANKS integer := 1
Definition: migui_arty_mig.vhd:121
migui_arty_mig.ADDR_MAP
ADDR_MAP std_logic_vector( 191 downto 0) := X"00000000000200400900700100500600301001201401101A"
Definition: migui_arty_mig.vhd:341
migui_arty_mig.nAL
nAL integer := 0
Definition: migui_arty_mig.vhd:173
migui_arty_mig.CA_MIRROR
CA_MIRROR string := "OFF"
Definition: migui_arty_mig.vhd:215
migui_arty_mig.CS_WIDTH
CS_WIDTH integer := 1
Definition: migui_arty_mig.vhd:88
migui_arty_mig.tRAS
tRAS integer := 36000
Definition: migui_arty_mig.vhd:258
migui_arty_mig.tRP
tRP integer := 13500
Definition: migui_arty_mig.vhd:266
migui_arty_mig.STARVE_LIMIT
STARVE_LIMIT integer := 2
Definition: migui_arty_mig.vhd:438
migui_arty_mig.DQS_BYTE_MAP
DQS_BYTE_MAP std_logic_vector( 143 downto 0) := X"000000000000000000000000000000000203"
Definition: migui_arty_mig.vhd:352
migui_arty_mig.ddr3_odt
out ddr3_odt std_logic_vector( ODT_WIDTH- 1 downto 0)
Definition: migui_arty_mig.vhd:504
migui_arty_mig.CLKOUT1_DIVIDE
CLKOUT1_DIVIDE integer := 4
Definition: migui_arty_mig.vhd:235
migui_arty_mig.ECC
ECC string := "OFF"
Definition: migui_arty_mig.vhd:107
migui_arty_mig.ddr3_dm
out ddr3_dm std_logic_vector( DM_WIDTH- 1 downto 0)
Definition: migui_arty_mig.vhd:503
migui_arty_mig.REF_CLK_MMCM_IODELAY_CTRL
REF_CLK_MMCM_IODELAY_CTRL string := "FALSE"
Definition: migui_arty_mig.vhd:440
migui_arty_mig.DATA1_MAP
DATA1_MAP std_logic_vector( 95 downto 0) := X"023026022028025027021024"
Definition: migui_arty_mig.vhd:354
migui_arty_mig.ddr3_ck_p
out ddr3_ck_p std_logic_vector( CK_WIDTH- 1 downto 0)
Definition: migui_arty_mig.vhd:499
migui_arty_mig.TEMP_MON_CONTROL
TEMP_MON_CONTROL string := "EXTERNAL"
Definition: migui_arty_mig.vhd:472
migui_arty_mig.DIFF_TERM_SYSCLK
DIFF_TERM_SYSCLK string := "TRUE"
Definition: migui_arty_mig.vhd:458
migui_arty_mig.PI_VAL_ADJ
PI_VAL_ADJ string := "OFF"
Definition: migui_arty_mig.vhd:410
migui_arty_mig.DATA_CTL_B2
DATA_CTL_B2 std_logic_vector( 3 downto 0) := "0000"
Definition: migui_arty_mig.vhd:318
migui_arty_mig.DATA6_MAP
DATA6_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: migui_arty_mig.vhd:359
migui_arty_mig.sys_rst
in sys_rst std_logic
Definition: migui_arty_mig.vhd:546
migui_arty_mig.CL
CL integer := 5
Definition: migui_arty_mig.vhd:188
migui_arty_mig.app_wdf_mask
in app_wdf_mask std_logic_vector((( nCK_PER_CLK* 2* PAYLOAD_WIDTH)/ 8)- 1 downto 0)
Definition: migui_arty_mig.vhd:517
migui_arty_mig.DQ_WIDTH
DQ_WIDTH integer := 16
Definition: migui_arty_mig.vhd:100
migui_arty_mig.ui_clk
out ui_clk std_logic
Definition: migui_arty_mig.vhd:530
migui_arty_mig.DATA4_MAP
DATA4_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: migui_arty_mig.vhd:357
migui_arty_mig.CLKOUT3_DIVIDE
CLKOUT3_DIVIDE integer := 16
Definition: migui_arty_mig.vhd:239
migui_arty_mig.tCK
tCK integer := 3000
Definition: migui_arty_mig.vhd:453
migui_arty_mig.REFCLK_FREQ
REFCLK_FREQ real := 200.0
Definition: migui_arty_mig.vhd:445
migui_arty_mig.DATA_IO_IDLE_PWRDWN
DATA_IO_IDLE_PWRDWN string := "OFF"
Definition: migui_arty_mig.vhd:384
migui_arty_mig.CK_WIDTH
CK_WIDTH integer := 1
Definition: migui_arty_mig.vhd:84
migui_arty_mig.MASK1_MAP
MASK1_MAP std_logic_vector( 107 downto 0) := X"000000000000000000000000000"
Definition: migui_arty_mig.vhd:372
migui_arty_mig.DATA_BUF_ADDR_WIDTH
DATA_BUF_ADDR_WIDTH integer := 5
Definition: migui_arty_mig.vhd:94
migui_arty_mig.ADDR_CMD_MODE
ADDR_CMD_MODE string := "1T"
Definition: migui_arty_mig.vhd:210
migui_arty_mig.MASK0_MAP
MASK0_MAP std_logic_vector( 107 downto 0) := X"000000000000000000000029039"
Definition: migui_arty_mig.vhd:371
migui_arty_mig.CLKOUT2_DIVIDE
CLKOUT2_DIVIDE integer := 64
Definition: migui_arty_mig.vhd:237
migui_arty_mig.BANK_MAP
BANK_MAP std_logic_vector( 35 downto 0) := X"01B017013"
Definition: migui_arty_mig.vhd:342
migui_arty_mig.BANK_WIDTH
BANK_WIDTH integer := 3
Definition: migui_arty_mig.vhd:82
migui_arty_mig.DATA17_MAP
DATA17_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: migui_arty_mig.vhd:370
migui_arty_mig.ddr3_dqs_n
inout ddr3_dqs_n std_logic_vector( DQS_WIDTH- 1 downto 0)
Definition: migui_arty_mig.vhd:490
migui_arty_mig.app_en
in app_en std_logic
Definition: migui_arty_mig.vhd:514
migui_arty_mig.SYS_RST_PORT
SYS_RST_PORT string := "FALSE"
Definition: migui_arty_mig.vhd:425
migui_arty_mig.MEM_SPEEDGRADE
MEM_SPEEDGRADE string := "15E"
Definition: migui_arty_mig.vhd:157
migui_arty_mig.PHY_CONTROL_MASTER_BANK
PHY_CONTROL_MASTER_BANK integer := 0
Definition: migui_arty_mig.vhd:151
migui_arty_mig.DATA_CTL_B0
DATA_CTL_B0 std_logic_vector( 3 downto 0) := "1100"
Definition: migui_arty_mig.vhd:308
migui_arty_mig.SLOT_0_CONFIG
SLOT_0_CONFIG std_logic_vector( 7 downto 0) := "00000001"
Definition: migui_arty_mig.vhd:374
migui_arty_mig.PHY_2_BITLANES
PHY_2_BITLANES std_logic_vector( 47 downto 0) := X"000000000000"
Definition: migui_arty_mig.vhd:335
migui_arty_mig.ddr3_ck_n
out ddr3_ck_n std_logic_vector( CK_WIDTH- 1 downto 0)
Definition: migui_arty_mig.vhd:500
migui_arty_mig.app_ref_ack
out app_ref_ack std_logic
Definition: migui_arty_mig.vhd:528
migui_arty_mig.CALIB_COL_ADD
CALIB_COL_ADD std_logic_vector( 11 downto 0) := X"000"
Definition: migui_arty_mig.vhd:400
migui_arty_mig.CALIB_BA_ADD
CALIB_BA_ADD std_logic_vector( 2 downto 0) := "000"
Definition: migui_arty_mig.vhd:403
migui_arty_mig.nCS_PER_RANK
nCS_PER_RANK integer := 1
Definition: migui_arty_mig.vhd:90
migui_arty_mig.RTT_NOM
RTT_NOM string := "40"
Definition: migui_arty_mig.vhd:200
migui_arty_mig.app_addr
in app_addr std_logic_vector( ADDR_WIDTH- 1 downto 0)
Definition: migui_arty_mig.vhd:512
migui_arty_mig.ECC_TEST
ECC_TEST string := "OFF"
Definition: migui_arty_mig.vhd:108
migui_arty_mig.DATA8_MAP
DATA8_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: migui_arty_mig.vhd:361
migui_arty_mig.SIM_BYPASS_INIT_CAL
SIM_BYPASS_INIT_CAL string := "OFF"
Definition: migui_arty_mig.vhd:282
migui_arty_mig.ddr3_reset_n
out ddr3_reset_n std_logic
Definition: migui_arty_mig.vhd:498
migui_arty_mig.WE_MAP
WE_MAP std_logic_vector( 11 downto 0) := X"018"
Definition: migui_arty_mig.vhd:350
migui_arty_mig.CLKOUT0_DIVIDE
CLKOUT0_DIVIDE integer := 2
Definition: migui_arty_mig.vhd:233
migui_arty_mig.DATA_CTL_B1
DATA_CTL_B1 std_logic_vector( 3 downto 0) := "0000"
Definition: migui_arty_mig.vhd:313
migui_arty_mig.DEBUG_PORT
DEBUG_PORT string := "OFF"
Definition: migui_arty_mig.vhd:465
migui_arty_mig.DATA2_MAP
DATA2_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: migui_arty_mig.vhd:355
migui_arty_mig.COL_WIDTH
COL_WIDTH integer := 10
Definition: migui_arty_mig.vhd:86
migui_arty_mig.REG_CTRL
REG_CTRL string := "OFF"
Definition: migui_arty_mig.vhd:212
migui_arty_mig.ORDERING
ORDERING string := "STRICT"
Definition: migui_arty_mig.vhd:395
migui_arty_mig.tRRD
tRRD integer := 7500
Definition: migui_arty_mig.vhd:268
migui_arty_mig.DATA14_MAP
DATA14_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: migui_arty_mig.vhd:367
migui_arty_mig.app_wdf_wren
in app_wdf_wren std_logic
Definition: migui_arty_mig.vhd:518
migui_arty_mig.CS_MAP
CS_MAP std_logic_vector( 119 downto 0) := X"00000000000000000000000000000B"
Definition: migui_arty_mig.vhd:347
migui_arty_mig.tRFC
tRFC integer := 160000
Definition: migui_arty_mig.vhd:264
migui_arty_mig.MMCM_VCO
MMCM_VCO integer := 666
Definition: migui_arty_mig.vhd:241
migui_arty_mig.CMD_PIPE_PLUS1
CMD_PIPE_PLUS1 string := "ON"
Definition: migui_arty_mig.vhd:433
migui_arty_mig.PARITY_MAP
PARITY_MAP std_logic_vector( 11 downto 0) := X"000"
Definition: migui_arty_mig.vhd:348
migui_arty_mig.BYTE_LANES_B3
BYTE_LANES_B3 std_logic_vector( 3 downto 0) := "0000"
Definition: migui_arty_mig.vhd:304
migui_arty_mig.DM_WIDTH
DM_WIDTH integer := 2
Definition: migui_arty_mig.vhd:98
migui_arty_mig.tCKE
tCKE integer := 5625
Definition: migui_arty_mig.vhd:252
migui_arty_mig.RAS_MAP
RAS_MAP std_logic_vector( 11 downto 0) := X"016"
Definition: migui_arty_mig.vhd:349
migui_arty_mig.ui_clk_sync_rst
out ui_clk_sync_rst std_logic
Definition: migui_arty_mig.vhd:531
migui_arty_mig.OUTPUT_DRV
OUTPUT_DRV string := "LOW"
Definition: migui_arty_mig.vhd:196
migui_arty_mig.DATA5_MAP
DATA5_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: migui_arty_mig.vhd:358
migui_arty_mig.SYSCLK_TYPE
SYSCLK_TYPE string := "NO_BUFFER"
Definition: migui_arty_mig.vhd:419
migui_arty_mig.DQS_CNT_WIDTH
DQS_CNT_WIDTH integer := 1
Definition: migui_arty_mig.vhd:103
migui_arty_mig.SLOT_1_CONFIG
SLOT_1_CONFIG std_logic_vector( 7 downto 0) := "00000000"
Definition: migui_arty_mig.vhd:376
migui_arty_mig.ODT_WIDTH
ODT_WIDTH integer := 1
Definition: migui_arty_mig.vhd:123
migui_arty_mig.app_wdf_data
in app_wdf_data std_logic_vector(( nCK_PER_CLK* 2* PAYLOAD_WIDTH)- 1 downto 0)
Definition: migui_arty_mig.vhd:515
migui_arty_mig.DATA13_MAP
DATA13_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: migui_arty_mig.vhd:366
migui_arty_mig.tPRDI
tPRDI integer := 1000000
Definition: migui_arty_mig.vhd:256
migui_arty_mig.USE_CS_PORT
USE_CS_PORT integer := 1
Definition: migui_arty_mig.vhd:132
migui_arty_mig.DATA9_MAP
DATA9_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: migui_arty_mig.vhd:362
migui_arty_mig.MMCM_MULT_F
MMCM_MULT_F integer := 8
Definition: migui_arty_mig.vhd:243
migui_arty_mig.BURST_MODE
BURST_MODE string := "8"
Definition: migui_arty_mig.vhd:176
migui_arty_mig.RTT_WR
RTT_WR string := "OFF"
Definition: migui_arty_mig.vhd:205
migui_arty_mig.ODT_MAP
ODT_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000008"
Definition: migui_arty_mig.vhd:346
migui_arty_mig.app_rdy
out app_rdy std_logic
Definition: migui_arty_mig.vhd:522
migui_arty
Definition: migui_arty_gsim.vhd:29
migui_arty.sys_rst
in sys_rst std_logic
Definition: migui_arty.vhd:118