73use ieee.std_logic_1164.
all;
74use ieee.numeric_std.
all;
107 ECC : string := "OFF";
121 RANKS : integer := 1;
252 tCKE : integer := 5625;
254 tFAW : integer := 45000;
256 tPRDI : integer := 1000000;
258 tRAS : integer := 36000;
260 tRCD : integer := 13500;
262 tREFI : integer := 7800000;
264 tRFC : integer := 160000;
266 tRP : integer := 13500;
268 tRRD : integer := 7500;
270 tRTP : integer := 7500;
272 tWTR : integer := 7500;
274 tZQI : integer := 128000000;
276 tZQCS : integer := 64;
308 DATA_CTL_B0 : std_logic_vector(3 downto 0) := "1100";
313 DATA_CTL_B1 : std_logic_vector(3 downto 0) := "0000";
318 DATA_CTL_B2 : std_logic_vector(3 downto 0) := "0000";
323 DATA_CTL_B3 : std_logic_vector(3 downto 0) := "0000";
328 DATA_CTL_B4 : std_logic_vector(3 downto 0) := "0000";
333 PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"3FE3FEFFFBFF";
334 PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
335 PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
339 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
341 : std_logic_vector(191 downto 0) := X"00000000000200400900700100500600301001201401101A";
342 BANK_MAP : std_logic_vector(35 downto 0) := X"01B017013";
343 CAS_MAP : std_logic_vector(11 downto 0) := X"015";
345 CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000019";
346 ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000008";
347 CS_MAP : std_logic_vector(119 downto 0) := X"00000000000000000000000000000B";
348 PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
349 RAS_MAP : std_logic_vector(11 downto 0) := X"016";
350 WE_MAP : std_logic_vector(11 downto 0) := X"018";
352 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000203";
353 DATA0_MAP : std_logic_vector(95 downto 0) := X"034032038035031037036033";
354 DATA1_MAP : std_logic_vector(95 downto 0) := X"023026022028025027021024";
355 DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
356 DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
357 DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
358 DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
359 DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
360 DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
361 DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
362 DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
363 DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
364 DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
365 DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
366 DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
367 DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
368 DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
369 DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
370 DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
371 MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000029039";
372 MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
392 WRLVL : string := "ON";
406 TCQ : integer := 100;
453 tCK : integer := 3000;
513 app_cmd : in std_logic_vector(2 downto 0);
554 function clogb2 (size :
integer)
return integer is
555 variable base : integer := 1;
556 variable inp : integer := 0;
565 function ECCWIDTH return integer is
590 function XWIDTH return integer is
601 function TEMP_MON return string is
614 constant ECC_WIDTH : integer := ECCWIDTH;
639 component mig_7series_v4_2_iodelay_ctrl
is
642 IODELAY_GRP0 :
string;
643 IODELAY_GRP1 :
string;
644 REFCLK_TYPE :
string;
645 SYSCLK_TYPE :
string;
646 SYS_RST_PORT :
string;
647 RST_ACT_LOW :
integer;
648 DIFF_TERM_REFCLK :
string;
649 FPGA_SPEED_GRADE :
integer;
650 REF_CLK_MMCM_IODELAY_CTRL :
string
653 clk_ref_p :
in std_logic;
654 clk_ref_n :
in std_logic;
655 clk_ref_i :
in std_logic;
656 sys_rst :
in std_logic;
657 clk_ref :
out std_logic_vector(
1 downto 0);
658 sys_rst_o :
out std_logic;
659 iodelay_ctrl_rdy :
out std_logic_vector(
1 downto 0)
661 end component mig_7series_v4_2_iodelay_ctrl;
663 component mig_7series_v4_2_clk_ibuf
is
665 SYSCLK_TYPE :
string;
666 DIFF_TERM_SYSCLK :
string
669 sys_clk_p :
in std_logic;
670 sys_clk_n :
in std_logic;
671 sys_clk_i :
in std_logic;
672 mmcm_clk :
out std_logic
674 end component mig_7series_v4_2_clk_ibuf;
676 component mig_7series_v4_2_infrastructure
is
678 SIMULATION :
string :=
"TRUE";
680 CLKIN_PERIOD :
integer;
681 nCK_PER_CLK :
integer;
682 SYSCLK_TYPE :
string;
683 UI_EXTRA_CLOCKS :
string :=
"FALSE";
684 CLKFBOUT_MULT :
integer;
685 DIVCLK_DIVIDE :
integer;
686 CLKOUT0_PHASE :
real;
687 CLKOUT0_DIVIDE :
integer;
688 CLKOUT1_DIVIDE :
integer;
689 CLKOUT2_DIVIDE :
integer;
690 CLKOUT3_DIVIDE :
integer;
692 MMCM_MULT_F :
integer;
693 MMCM_DIVCLK_DIVIDE :
integer;
694 MMCM_CLKOUT0_EN :
string :=
"FALSE";
695 MMCM_CLKOUT1_EN :
string :=
"FALSE";
696 MMCM_CLKOUT2_EN :
string :=
"FALSE";
697 MMCM_CLKOUT3_EN :
string :=
"FALSE";
698 MMCM_CLKOUT4_EN :
string :=
"FALSE";
699 MMCM_CLKOUT0_DIVIDE :
integer :=
1;
700 MMCM_CLKOUT1_DIVIDE :
integer :=
1;
701 MMCM_CLKOUT2_DIVIDE :
integer :=
1;
702 MMCM_CLKOUT3_DIVIDE :
integer :=
1;
703 MMCM_CLKOUT4_DIVIDE :
integer :=
1;
704 RST_ACT_LOW :
integer;
709 mmcm_clk :
in std_logic;
710 sys_rst :
in std_logic;
711 iodelay_ctrl_rdy :
in std_logic_vector(
1 downto 0);
713 psincdec :
in std_logic;
715 clk_div2 :
out std_logic;
716 rst_div2 :
out std_logic;
717 mem_refclk :
out std_logic;
718 freq_refclk :
out std_logic;
719 sync_pulse :
out std_logic;
720 mmcm_ps_clk :
out std_logic;
721 poc_sample_pd :
out std_logic;
722 iddr_rst :
out std_logic;
723 psdone :
out std_logic;
725 ui_addn_clk_0 :
out std_logic;
726 ui_addn_clk_1 :
out std_logic;
727 ui_addn_clk_2 :
out std_logic;
728 ui_addn_clk_3 :
out std_logic;
729 ui_addn_clk_4 :
out std_logic;
730 pll_locked :
out std_logic;
731 mmcm_locked :
out std_logic;
732 rstdiv0 :
out std_logic;
733 rst_phaser_ref :
out std_logic;
734 ref_dll_lock :
in std_logic
736 end component mig_7series_v4_2_infrastructure;
738 component mig_7series_v4_2_tempmon
is
741 TEMP_MON_CONTROL :
string;
742 XADC_CLK_PERIOD :
integer;
743 tTEMPSAMPLE :
integer
747 xadc_clk :
in std_logic;
749 device_temp_i :
in std_logic_vector(
11 downto 0);
750 device_temp :
out std_logic_vector(
11 downto 0)
752 end component mig_7series_v4_2_tempmon;
754 component mig_7series_v4_2_memc_ui_top_std
is
757 DDR3_VDD_OP_VOLT :
string := "
135";
758 PAYLOAD_WIDTH :
integer;
759 ADDR_CMD_MODE :
string;
761 BANK_WIDTH :
integer;
762 BM_CNT_WIDTH :
integer;
769 CMD_PIPE_PLUS1 :
string;
773 DATA_WIDTH :
integer;
774 DATA_BUF_ADDR_WIDTH :
integer;
775 DATA_BUF_OFFSET_WIDTH :
integer :=
1;
776 DDR2_DQSN_ENABLE :
string :=
"YES";
778 DQ_CNT_WIDTH :
integer;
780 DQS_CNT_WIDTH :
integer;
783 DRAM_WIDTH :
integer;
787 MC_ERR_ADDR_WIDTH :
integer;
788 MASTER_PHY_CTL :
integer;
790 nBANK_MACHS :
integer;
791 nCK_PER_CLK :
integer;
792 nCS_PER_RANK :
integer;
794 IBUF_LPWR_MODE :
string;
796 DATA_IO_PRIM_TYPE :
string;
797 DATA_IO_IDLE_PWRDWN :
string;
798 IODELAY_GRP0 :
string;
799 IODELAY_GRP1 :
string;
800 FPGA_SPEED_GRADE :
integer;
805 STARVE_LIMIT :
integer;
820 USER_REFRESH :
string;
821 TEMP_MON_EN :
string;
825 RANK_WIDTH :
integer;
829 ADDR_WIDTH :
integer;
830 APP_MASK_WIDTH :
integer;
831 APP_DATA_WIDTH :
integer;
832 BYTE_LANES_B0 :
std_logic_vector(
3 downto 0);
833 BYTE_LANES_B1 :
std_logic_vector(
3 downto 0);
834 BYTE_LANES_B2 :
std_logic_vector(
3 downto 0);
835 BYTE_LANES_B3 :
std_logic_vector(
3 downto 0);
836 BYTE_LANES_B4 :
std_logic_vector(
3 downto 0);
837 DATA_CTL_B0 :
std_logic_vector(
3 downto 0);
838 DATA_CTL_B1 :
std_logic_vector(
3 downto 0);
839 DATA_CTL_B2 :
std_logic_vector(
3 downto 0);
840 DATA_CTL_B3 :
std_logic_vector(
3 downto 0);
841 DATA_CTL_B4 :
std_logic_vector(
3 downto 0);
842 PHY_0_BITLANES :
std_logic_vector(
47 downto 0);
843 PHY_1_BITLANES :
std_logic_vector(
47 downto 0);
844 PHY_2_BITLANES :
std_logic_vector(
47 downto 0);
845 CK_BYTE_MAP :
std_logic_vector(
143 downto 0);
846 ADDR_MAP :
std_logic_vector(
191 downto 0);
847 BANK_MAP :
std_logic_vector(
35 downto 0);
848 CAS_MAP :
std_logic_vector(
11 downto 0);
849 CKE_ODT_BYTE_MAP :
std_logic_vector(
7 downto 0);
850 CKE_MAP :
std_logic_vector(
95 downto 0);
851 ODT_MAP :
std_logic_vector(
95 downto 0);
852 CKE_ODT_AUX :
string;
853 CS_MAP :
std_logic_vector(
119 downto 0);
854 PARITY_MAP :
std_logic_vector(
11 downto 0);
855 RAS_MAP :
std_logic_vector(
11 downto 0);
856 WE_MAP :
std_logic_vector(
11 downto 0);
857 DQS_BYTE_MAP :
std_logic_vector(
143 downto 0);
858 DATA0_MAP :
std_logic_vector(
95 downto 0);
859 DATA1_MAP :
std_logic_vector(
95 downto 0);
860 DATA2_MAP :
std_logic_vector(
95 downto 0);
861 DATA3_MAP :
std_logic_vector(
95 downto 0);
862 DATA4_MAP :
std_logic_vector(
95 downto 0);
863 DATA5_MAP :
std_logic_vector(
95 downto 0);
864 DATA6_MAP :
std_logic_vector(
95 downto 0);
865 DATA7_MAP :
std_logic_vector(
95 downto 0);
866 DATA8_MAP :
std_logic_vector(
95 downto 0);
867 DATA9_MAP :
std_logic_vector(
95 downto 0);
868 DATA10_MAP :
std_logic_vector(
95 downto 0);
869 DATA11_MAP :
std_logic_vector(
95 downto 0);
870 DATA12_MAP :
std_logic_vector(
95 downto 0);
871 DATA13_MAP :
std_logic_vector(
95 downto 0);
872 DATA14_MAP :
std_logic_vector(
95 downto 0);
873 DATA15_MAP :
std_logic_vector(
95 downto 0);
874 DATA16_MAP :
std_logic_vector(
95 downto 0);
875 DATA17_MAP :
std_logic_vector(
95 downto 0);
876 MASK0_MAP :
std_logic_vector(
107 downto 0);
877 MASK1_MAP :
std_logic_vector(
107 downto 0);
878 SLOT_0_CONFIG :
std_logic_vector(
7 downto 0);
879 SLOT_1_CONFIG :
std_logic_vector(
7 downto 0);
880 MEM_ADDR_ORDER :
string;
881 CALIB_ROW_ADD :
std_logic_vector(
15 downto 0);
882 CALIB_COL_ADD :
std_logic_vector(
11 downto 0);
883 CALIB_BA_ADD :
std_logic_vector(
2 downto 0);
884 SIM_BYPASS_INIT_CAL :
string;
886 USE_CS_PORT :
integer;
887 USE_DM_PORT :
integer;
888 USE_ODT_PORT :
integer;
890 FINE_PER_BIT :
string;
891 CENTER_COMP_MODE :
string;
893 TAPSPERKCLK :
integer;
895 FPGA_VOLT_TYPE :
string
899 clk_div2 :
in std_logic;
900 rst_div2 :
in std_logic;
901 clk_ref :
in std_logic_vector(
1 downto 0);
902 mem_refclk :
in std_logic;
903 freq_refclk :
in std_logic;
904 pll_lock :
in std_logic;
905 sync_pulse :
in std_logic;
906 mmcm_ps_clk :
in std_logic;
907 poc_sample_pd :
in std_logic;
910 ddr_dq :
inout std_logic_vector(DQ_WIDTH
-1 downto 0);
911 ddr_dqs_n :
inout std_logic_vector(DQS_WIDTH
-1 downto 0);
912 ddr_dqs :
inout std_logic_vector(DQS_WIDTH
-1 downto 0);
913 ddr_addr :
out std_logic_vector(ROW_WIDTH
-1 downto 0);
914 ddr_ba :
out std_logic_vector(BANK_WIDTH
-1 downto 0);
915 ddr_cas_n :
out std_logic;
916 ddr_ck_n :
out std_logic_vector(CK_WIDTH
-1 downto 0);
917 ddr_ck :
out std_logic_vector(CK_WIDTH
-1 downto 0);
918 ddr_cke :
out std_logic_vector(CKE_WIDTH
-1 downto 0);
919 ddr_cs_n :
out std_logic_vector((CS_WIDTH*nCS_PER_RANK)
-1 downto 0);
920 ddr_dm :
out std_logic_vector(DM_WIDTH
-1 downto 0);
921 ddr_odt :
out std_logic_vector(ODT_WIDTH
-1 downto 0);
922 ddr_ras_n :
out std_logic;
923 ddr_reset_n :
out std_logic;
924 ddr_parity :
out std_logic;
925 ddr_we_n :
out std_logic;
927 bank_mach_next :
out std_logic_vector(BM_CNT_WIDTH
-1 downto 0);
929 app_addr :
in std_logic_vector(ADDR_WIDTH
-1 downto 0);
930 app_cmd :
in std_logic_vector(
2 downto 0);
931 app_en :
in std_logic;
932 app_hi_pri :
in std_logic;
933 app_wdf_data :
in std_logic_vector((nCK_PER_CLK*
2*PAYLOAD_WIDTH)
-1 downto 0);
934 app_wdf_end :
in std_logic;
935 app_wdf_mask :
in std_logic_vector(((nCK_PER_CLK*
2*PAYLOAD_WIDTH)/
8)
-1 downto 0);
936 app_wdf_wren :
in std_logic;
937 app_correct_en_i :
in std_logic;
938 app_raw_not_ecc :
in std_logic_vector((
2*nCK_PER_CLK)
-1 downto 0);
939 app_ecc_multiple_err :
out std_logic_vector((
2*nCK_PER_CLK)
-1 downto 0);
940 app_ecc_single_err :
out std_logic_vector((
2*nCK_PER_CLK)
-1 downto 0);
941 app_rd_data :
out std_logic_vector((nCK_PER_CLK*
2*PAYLOAD_WIDTH)
-1 downto 0);
942 app_rd_data_end :
out std_logic;
943 app_rd_data_valid :
out std_logic;
944 app_rdy :
out std_logic;
945 app_wdf_rdy :
out std_logic;
946 app_sr_req :
in std_logic;
947 app_sr_active :
out std_logic;
948 app_ref_req :
in std_logic;
949 app_ref_ack :
out std_logic;
950 app_zq_req :
in std_logic;
951 app_zq_ack :
out std_logic;
953 calib_tap_req :
out std_logic;
954 calib_tap_addr :
in std_logic_vector(
6 downto 0);
955 calib_tap_load :
in std_logic;
956 calib_tap_val :
in std_logic_vector(
7 downto 0);
957 calib_tap_load_done :
in std_logic;
959 device_temp :
in std_logic_vector(
11 downto 0);
961 psen :
out std_logic;
962 psincdec :
out std_logic;
963 psdone :
in std_logic;
965 dbg_idel_down_all :
in std_logic;
966 dbg_idel_down_cpt :
in std_logic;
967 dbg_idel_up_all :
in std_logic;
968 dbg_idel_up_cpt :
in std_logic;
969 dbg_sel_all_idel_cpt :
in std_logic;
970 dbg_sel_idel_cpt :
in std_logic_vector(DQS_CNT_WIDTH
-1 downto 0);
971 dbg_cpt_first_edge_cnt :
out std_logic_vector((
6*DQS_WIDTH*RANKS)
-1 downto 0);
972 dbg_cpt_second_edge_cnt :
out std_logic_vector((
6*DQS_WIDTH*RANKS)
-1 downto 0);
973 dbg_rd_data_edge_detect :
out std_logic_vector(DQS_WIDTH
-1 downto 0);
974 dbg_rddata :
out std_logic_vector((
2*nCK_PER_CLK*DQ_WIDTH)
-1 downto 0);
975 dbg_rdlvl_done :
out std_logic_vector(
1 downto 0);
976 dbg_rdlvl_err :
out std_logic_vector(
1 downto 0);
977 dbg_rdlvl_start :
out std_logic_vector(
1 downto 0);
978 dbg_tap_cnt_during_wrlvl :
out std_logic_vector(
5 downto 0);
979 dbg_wl_edge_detect_valid :
out std_logic;
980 dbg_wrlvl_done :
out std_logic;
981 dbg_wrlvl_err :
out std_logic;
982 dbg_wrlvl_start :
out std_logic;
983 dbg_final_po_fine_tap_cnt :
out std_logic_vector((
6*DQS_WIDTH)
-1 downto 0);
984 dbg_final_po_coarse_tap_cnt :
out std_logic_vector((
3*DQS_WIDTH)
-1 downto 0);
985 init_calib_complete :
out std_logic;
986 dbg_sel_pi_incdec :
in std_logic;
987 dbg_sel_po_incdec :
in std_logic;
988 dbg_byte_sel :
in std_logic_vector(DQS_CNT_WIDTH
downto 0);
989 dbg_pi_f_inc :
in std_logic;
990 dbg_pi_f_dec :
in std_logic;
991 dbg_po_f_inc :
in std_logic;
992 dbg_po_f_stg23_sel :
in std_logic;
993 dbg_po_f_dec :
in std_logic;
994 dbg_cpt_tap_cnt :
out std_logic_vector((
6*DQS_WIDTH*RANKS)
-1 downto 0);
995 dbg_dq_idelay_tap_cnt :
out std_logic_vector((
5*DQS_WIDTH*RANKS)
-1 downto 0);
996 dbg_rddata_valid :
out std_logic;
997 dbg_wrlvl_fine_tap_cnt :
out std_logic_vector((
6*DQS_WIDTH)
-1 downto 0);
998 dbg_wrlvl_coarse_tap_cnt :
out std_logic_vector((
3*DQS_WIDTH)
-1 downto 0);
999 rst_phaser_ref :
in std_logic;
1000 ref_dll_lock :
out std_logic;
1001 iddr_rst :
in std_logic;
1002 dbg_rd_data_offset :
out std_logic_vector((
6*RANKS)
-1 downto 0);
1003 dbg_calib_top :
out std_logic_vector(
255 downto 0);
1004 dbg_phy_wrlvl :
out std_logic_vector(
255 downto 0);
1005 dbg_phy_rdlvl :
out std_logic_vector(
255 downto 0);
1006 dbg_phy_wrcal :
out std_logic_vector(
99 downto 0);
1007 dbg_phy_init :
out std_logic_vector(
255 downto 0);
1008 dbg_prbs_rdlvl :
out std_logic_vector(
255 downto 0);
1009 dbg_dqs_found_cal :
out std_logic_vector(
255 downto 0);
1010 dbg_pi_counter_read_val :
out std_logic_vector(
5 downto 0);
1011 dbg_po_counter_read_val :
out std_logic_vector(
8 downto 0);
1012 dbg_pi_phaselock_start :
out std_logic;
1013 dbg_pi_phaselocked_done :
out std_logic;
1014 dbg_pi_phaselock_err :
out std_logic;
1015 dbg_pi_dqsfound_start :
out std_logic;
1016 dbg_pi_dqsfound_done :
out std_logic;
1017 dbg_pi_dqsfound_err :
out std_logic;
1018 dbg_wrcal_start :
out std_logic;
1019 dbg_wrcal_done :
out std_logic;
1020 dbg_wrcal_err :
out std_logic;
1021 dbg_pi_dqs_found_lanes_phy4lanes :
out std_logic_vector(
11 downto 0);
1022 dbg_pi_phase_locked_phy4lanes :
out std_logic_vector(
11 downto 0);
1023 dbg_calib_rd_data_offset_1 :
out std_logic_vector((
6*RANKS)
-1 downto 0);
1024 dbg_calib_rd_data_offset_2 :
out std_logic_vector((
6*RANKS)
-1 downto 0);
1025 dbg_data_offset :
out std_logic_vector(
5 downto 0);
1026 dbg_data_offset_1 :
out std_logic_vector(
5 downto 0);
1027 dbg_data_offset_2 :
out std_logic_vector(
5 downto 0);
1028 dbg_oclkdelay_calib_start :
out std_logic;
1029 dbg_oclkdelay_calib_done :
out std_logic;
1030 dbg_phy_oclkdelay_cal :
out std_logic_vector(
255 downto 0);
1031 dbg_oclkdelay_rd_data :
out std_logic_vector((DRAM_WIDTH*
16)
-1 downto 0);
1032 dbg_prbs_final_dqs_tap_cnt_r :
out std_logic_vector((
6*DQS_WIDTH*RANKS)
-1 downto 0);
1033 dbg_prbs_first_edge_taps :
out std_logic_vector((
6*DQS_WIDTH*RANKS)
-1 downto 0);
1034 dbg_prbs_second_edge_taps :
out std_logic_vector((
6*DQS_WIDTH*RANKS)
-1 downto 0);
1035 dbg_poc :
out std_logic_vector (
1023 downto 0)
1037 end component mig_7series_v4_2_memc_ui_top_std;
1043 signal clk : std_logic;
1044 signal clk_ref : std_logic_vector(1 downto 0);
1056 signal psen : std_logic;
1058 signal psdone : std_logic;
1063 signal rst : std_logic;
1143 signal dbg_dqs : std_logic_vector(4 downto 0);
1144 signal dbg_bit : std_logic_vector(8 downto 0);
1183 clk_ref_in_use_sys_clk : if (REFCLK_TYPE = "USE_SYSTEM_CLOCK") generate
1187 clk_ref_in_others : if (REFCLK_TYPE /= "USE_SYSTEM_CLOCK") generate
1232 temp_mon_enabled : if (TEMP_MON_EN = "ON") generate
1251 temp_mon_disabled : if (TEMP_MON_EN /= "ON") generate
1294 ui_addn_clk_0 =>
open,
1295 ui_addn_clk_1 =>
open,
1296 ui_addn_clk_2 =>
open,
1297 ui_addn_clk_3 =>
open,
1298 ui_addn_clk_4 =>
open,
1300 mmcm_locked =>
open,
1448 SKIP_CALIB =>
"FALSE",
1509 app_correct_en_i => '1',
1517 calib_tap_req =>
open,
1518 calib_tap_addr =>
(others => '0'
),
1519 calib_tap_load => '0',
1520 calib_tap_val =>
(others => '0'
),
1521 calib_tap_load_done => '0',
mig_7series_v4_2_memc_ui_top_std u_memc_ui_top_stdu_memc_ui_top_std
integer := clogb2( nBANK_MACHS ) BM_CNT_WIDTH
std_logic dbg_oclkdelay_calib_start
std_logic_vector( 11 downto 0) dbg_pi_phase_locked_phy4lanes
std_logic dbg_wl_edge_detect_valid
std_logic_vector( 8 downto 0) rd_data_edge_detect_r
std_logic_vector(( 6* DQS_WIDTH)- 1 downto 0) dbg_final_po_fine_tap_cnt
std_logic_vector( 11 downto 0) dbg_prbs_final_dqs_tap_cnt_r
std_logic_vector( 255 downto 0) dbg_prbs_rdlvl
std_logic_vector( 1 downto 0) dbg_rdlvl_err
std_logic_vector( 11 downto 0) dbg_pi_dqs_found_lanes_phy4lanes
std_logic_vector( 11 downto 0) dbg_prbs_first_edge_taps
std_logic dbg_sel_all_idel_cpt
std_logic_vector( 4 downto 0) dbg_dqs
integer := clogb2( RANKS ) RANK_WIDTH
std_logic_vector( 1 downto 0) iodelay_ctrl_rdy
std_logic_vector( 1 downto 0) dbg_rdlvl_done
std_logic_vector( 1 downto 0) clk_ref
std_logic dbg_sel_pi_incdec
mig_7series_v4_2_iodelay_ctrl u_iodelay_ctrlu_iodelay_ctrl
integer := XWIDTH+ BANK_WIDTH+ ROW_WIDTH+ COL_WIDTH+ DATA_BUF_OFFSET_WIDTH MC_ERR_ADDR_WIDTH
std_logic_vector( 119 downto 0) ddr3_ila_basic_int
std_logic_vector( 11 downto 0) device_temp_s
std_logic_vector( 1 downto 0) dbg_rdlvl_start
std_logic_vector( 255 downto 0) dbg_dqs_found_cal
std_logic_vector( DQS_CNT_WIDTH downto 0) dbg_byte_sel
std_logic dbg_idel_up_cpt
std_logic_vector(( 2* nCK_PER_CLK)- 1 downto 0) app_ecc_single_err
std_logic dbg_pi_dqsfound_err
std_logic dbg_sel_po_incdec
std_logic_vector(( DRAM_WIDTH* 16)- 1 downto 0) dbg_oclkdelay_rd_data
std_logic_vector( 53 downto 0) ocal_tap_cnt
std_logic_vector( 63 downto 0) dbg_rddata_r
std_logic_vector(( 5* DQS_WIDTH* RANKS)- 1 downto 0) dbg_dq_idelay_tap_cnt
std_logic dbg_pi_phaselocked_done
std_logic_vector( 255 downto 0) dbg_phy_rdlvl
std_logic_vector( 5 downto 0) dbg_data_offset
std_logic dbg_rddata_valid_r
string := TEMP_MON TEMP_MON_EN
std_logic_vector( 5 downto 0) dbg_pi_counter_read_val
std_logic_vector(( 2* nCK_PER_CLK* DQ_WIDTH)- 1 downto 0) dbg_rddata
std_logic dbg_oclkdelay_calib_done
std_logic dbg_pi_phaselock_start
std_logic_vector(( 6* DQS_WIDTH* RANKS)- 1 downto 0) dbg_cpt_tap_cnt
mig_7series_v4_2_tempmon u_tempmonu_tempmon
integer :=( 56* MMCM_MULT_F)/ nCK_PER_CLK TAPSPERKCLK
std_logic_vector( 1023 downto 0) ddr3_ila_rdpath_int
integer := ECCWIDTH ECC_WIDTH
std_logic dbg_wrlvl_start
std_logic_vector( DQS_WIDTH- 1 downto 0) dbg_rd_data_edge_detect
std_logic_vector( 255 downto 0) dbg_calib_top
std_logic_vector( 255 downto 0) dbg_phy_oclkdelay_cal
std_logic dbg_idel_up_all
std_logic_vector(( 2* nCK_PER_CLK)- 1 downto 0) app_ecc_multiple_err
std_logic dbg_wrcal_start
std_logic_vector( 11 downto 0) dbg_prbs_second_edge_taps_int
integer := 5000 XADC_CLK_PERIOD
std_logic_vector(( 6* RANKS)- 1 downto 0) dbg_calib_rd_data_offset_1
std_logic dbg_pi_phaselock_err
std_logic_vector( 5 downto 0) dbg_data_offset_2
std_logic_vector( 5 downto 0) dbg_tap_cnt_during_wrlvl
std_logic_vector( 255 downto 0) dbg_phy_wrlvl
std_logic_vector( 11 downto 0) dbg_prbs_second_edge_taps
std_logic_vector( 390 downto 0) ddr3_ila_wrpath_int
std_logic_vector(( 6* DQS_WIDTH* RANKS)- 1 downto 0) dbg_cpt_second_edge_cnt
std_logic_vector(( 6* DQS_WIDTH)- 1 downto 0) dbg_wrlvl_fine_tap_cnt
std_logic_vector( 53 downto 0) wl_po_fine_cnt
std_logic_vector(( 3* DQS_WIDTH)- 1 downto 0) dbg_final_po_coarse_tap_cnt
std_logic_vector( BM_CNT_WIDTH- 1 downto 0) bank_mach_next
std_logic_vector(( 6* RANKS)- 1 downto 0) dbg_rd_data_offset
integer := APP_DATA_WIDTH/ 8 APP_MASK_WIDTH
std_logic_vector(( 2* nCK_PER_CLK)- 1 downto 0) :=( others => '0') all_zeros
std_logic dbg_idel_down_all
std_logic_vector(( 3* DQS_WIDTH)- 1 downto 0) dbg_wrlvl_coarse_tap_cnt
mig_7series_v4_2_clk_ibuf u_ddr3_clk_ibufu_ddr3_clk_ibuf
std_logic dbg_idel_down_cpt
std_logic init_calib_complete_i
std_logic_vector( 26 downto 0) wl_po_coarse_cnt
integer := 2* nCK_PER_CLK* PAYLOAD_WIDTH APP_DATA_WIDTH
std_logic_vector(( 6* RANKS)- 1 downto 0) dbg_calib_rd_data_offset_2
std_logic_vector( 11 downto 0) dbg_prbs_first_edge_taps_int
std_logic_vector( 255 downto 0) dbg_phy_init
std_logic dbg_pi_dqsfound_start
std_logic_vector( 99 downto 0) dbg_phy_wrcal
std_logic_vector( 5 downto 0) dbg_data_offset_1
std_logic_vector( 11 downto 0) dbg_prbs_final_dqs_tap_cnt_r_int
std_logic dbg_rddata_valid
integer := 10000000 tTEMPSAMPLE
integer := 1 DATA_BUF_OFFSET_WIDTH
std_logic_vector( DQS_CNT_WIDTH- 1 downto 0) dbg_sel_idel_cpt
std_logic_vector(( 6* DQS_WIDTH* RANKS)- 1 downto 0) dbg_cpt_first_edge_cnt
std_logic dbg_pi_dqsfound_done
std_logic dbg_po_f_stg23_sel
std_logic_vector( 8 downto 0) dbg_bit
std_logic_vector( 8 downto 0) dbg_po_counter_read_val
mig_7series_v4_2_infrastructure u_ddr3_infrastructureu_ddr3_infrastructure
BYTE_LANES_B4 std_logic_vector( 3 downto 0) := "0000"
FPGA_SPEED_GRADE integer := 1
DATA_CTL_B3 std_logic_vector( 3 downto 0) := "0000"
VDD_OP_VOLT string := "135"
in device_temp_i std_logic_vector( 11 downto 0)
SIMULATION string := "FALSE"
USE_ODT_PORT integer := 1
out ddr3_cke std_logic_vector( CKE_WIDTH- 1 downto 0)
PHY_1_BITLANES std_logic_vector( 47 downto 0) := X"000000000000"
out app_rd_data std_logic_vector(( nCK_PER_CLK* 2* PAYLOAD_WIDTH)- 1 downto 0)
PAYLOAD_WIDTH integer := 16
out ddr3_cs_n std_logic_vector(( CS_WIDTH* nCS_PER_RANK)- 1 downto 0)
BYTE_LANES_B1 std_logic_vector( 3 downto 0) := "0000"
REFCLK_TYPE string := "NO_BUFFER"
in app_cmd std_logic_vector( 2 downto 0)
DIFF_TERM_REFCLK string := "TRUE"
DATA_CTL_B4 std_logic_vector( 3 downto 0) := "0000"
IDELAY_ADJ string := "OFF"
IBUF_LPWR_MODE string := "OFF"
FINE_PER_BIT string := "OFF"
CLKOUT0_PHASE real := 0.0
BYTE_LANES_B2 std_logic_vector( 3 downto 0) := "0000"
CENTER_COMP_MODE string := "OFF"
PHY_0_BITLANES std_logic_vector( 47 downto 0) := X"3FE3FEFFFBFF"
MMCM_DIVCLK_DIVIDE integer := 1
out device_temp std_logic_vector( 11 downto 0)
CAS_MAP std_logic_vector( 11 downto 0) := X"015"
DATA3_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
inout ddr3_dqs_p std_logic_vector( DQS_WIDTH- 1 downto 0)
BYTE_LANES_B0 std_logic_vector( 3 downto 0) := "1111"
IODELAY_GRP1 string := "MIGUI_ARTY_IODELAY_MIG1"
DATA0_MAP std_logic_vector( 95 downto 0) := X"034032038035031037036033"
out app_wdf_rdy std_logic
tZQI integer := 128000000
USER_REFRESH string := "OFF"
DQ_CNT_WIDTH integer := 4
DRAM_TYPE string := "DDR3"
MEM_DEVICE_WIDTH integer := 16
FPGA_VOLT_TYPE string := "N"
BANK_TYPE string := "HR_IO"
out ddr3_addr std_logic_vector( ROW_WIDTH- 1 downto 0)
CLKIN_PERIOD integer := 6000
DATA7_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
MEM_DENSITY string := "2Gb"
CKE_ODT_BYTE_MAP std_logic_vector( 7 downto 0) := X"00"
out app_rd_data_end std_logic
IODELAY_GRP0 string := "MIGUI_ARTY_IODELAY_MIG0"
CLKFBOUT_MULT integer := 8
DATA11_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
inout ddr3_dq std_logic_vector( DQ_WIDTH- 1 downto 0)
DIVCLK_DIVIDE integer := 1
BURST_TYPE string := "SEQ"
DATA10_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
out init_calib_complete std_logic
CKE_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000019"
CALIB_ROW_ADD std_logic_vector( 15 downto 0) := X"0000"
CKE_ODT_AUX string := "FALSE"
DATA15_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
out ddr3_ba std_logic_vector( BANK_WIDTH- 1 downto 0)
CK_BYTE_MAP std_logic_vector( 143 downto 0) := X"000000000000000000000000000000000000"
DATA_IO_PRIM_TYPE string := "DEFAULT"
out app_sr_active std_logic
CAL_WIDTH string := "HALF"
DATA12_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
MEM_ADDR_ORDER string := "ROW_BANK_COLUMN"
DATA16_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
out app_rd_data_valid std_logic
ADDR_MAP std_logic_vector( 191 downto 0) := X"00000000000200400900700100500600301001201401101A"
CA_MIRROR string := "OFF"
STARVE_LIMIT integer := 2
DQS_BYTE_MAP std_logic_vector( 143 downto 0) := X"000000000000000000000000000000000203"
out ddr3_odt std_logic_vector( ODT_WIDTH- 1 downto 0)
CLKOUT1_DIVIDE integer := 4
out ddr3_dm std_logic_vector( DM_WIDTH- 1 downto 0)
REF_CLK_MMCM_IODELAY_CTRL string := "FALSE"
DATA1_MAP std_logic_vector( 95 downto 0) := X"023026022028025027021024"
out ddr3_ck_p std_logic_vector( CK_WIDTH- 1 downto 0)
TEMP_MON_CONTROL string := "EXTERNAL"
DIFF_TERM_SYSCLK string := "TRUE"
PI_VAL_ADJ string := "OFF"
DATA_CTL_B2 std_logic_vector( 3 downto 0) := "0000"
DATA6_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
in app_wdf_mask std_logic_vector((( nCK_PER_CLK* 2* PAYLOAD_WIDTH)/ 8)- 1 downto 0)
DATA4_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
CLKOUT3_DIVIDE integer := 16
REFCLK_FREQ real := 200.0
DATA_IO_IDLE_PWRDWN string := "OFF"
MASK1_MAP std_logic_vector( 107 downto 0) := X"000000000000000000000000000"
DATA_BUF_ADDR_WIDTH integer := 5
ADDR_CMD_MODE string := "1T"
MASK0_MAP std_logic_vector( 107 downto 0) := X"000000000000000000000029039"
CLKOUT2_DIVIDE integer := 64
BANK_MAP std_logic_vector( 35 downto 0) := X"01B017013"
DATA17_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
inout ddr3_dqs_n std_logic_vector( DQS_WIDTH- 1 downto 0)
SYS_RST_PORT string := "FALSE"
MEM_SPEEDGRADE string := "15E"
PHY_CONTROL_MASTER_BANK integer := 0
DATA_CTL_B0 std_logic_vector( 3 downto 0) := "1100"
SLOT_0_CONFIG std_logic_vector( 7 downto 0) := "00000001"
PHY_2_BITLANES std_logic_vector( 47 downto 0) := X"000000000000"
out ddr3_ck_n std_logic_vector( CK_WIDTH- 1 downto 0)
out app_ref_ack std_logic
CALIB_COL_ADD std_logic_vector( 11 downto 0) := X"000"
CALIB_BA_ADD std_logic_vector( 2 downto 0) := "000"
nCS_PER_RANK integer := 1
in app_addr std_logic_vector( ADDR_WIDTH- 1 downto 0)
DATA8_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
SIM_BYPASS_INIT_CAL string := "OFF"
out ddr3_reset_n std_logic
WE_MAP std_logic_vector( 11 downto 0) := X"018"
CLKOUT0_DIVIDE integer := 2
DATA_CTL_B1 std_logic_vector( 3 downto 0) := "0000"
DEBUG_PORT string := "OFF"
DATA2_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
ORDERING string := "STRICT"
DATA14_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
in app_wdf_wren std_logic
CS_MAP std_logic_vector( 119 downto 0) := X"00000000000000000000000000000B"
CMD_PIPE_PLUS1 string := "ON"
PARITY_MAP std_logic_vector( 11 downto 0) := X"000"
BYTE_LANES_B3 std_logic_vector( 3 downto 0) := "0000"
RAS_MAP std_logic_vector( 11 downto 0) := X"016"
out ui_clk_sync_rst std_logic
OUTPUT_DRV string := "LOW"
DATA5_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
SYSCLK_TYPE string := "NO_BUFFER"
DQS_CNT_WIDTH integer := 1
SLOT_1_CONFIG std_logic_vector( 7 downto 0) := "00000000"
in app_wdf_data std_logic_vector(( nCK_PER_CLK* 2* PAYLOAD_WIDTH)- 1 downto 0)
DATA13_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
DATA9_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
ODT_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000008"