w11 - vhd 0.794
W11 CPU core and support modules
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Attributes | Processes | Signals
syn Architecture Reference
Architecture >> syn

Processes

proc_master  ( CLKM )
proc_slave  ( CLKS )
proc_pout  ( CLKS )

Signals

RM_REQ  slbit := INIT
RS_REQ_S0  slbit := INIT
RS_REQ_S1  slbit := INIT
RM_ACK_S0  slbit := ' 0 '
RM_ACK_S1  slbit := ' 0 '
RS_ACK_1  slbit := INIT
RS_POUT  slbit := ' 0 '

Attributes

ASYNC_REG  string
ASYNC_REG  signal is " true "

Detailed Description

Definition at line 42 of file cdc_pulse.vhd.

Member Function/Procedure/Process Documentation

◆ proc_master()

proc_master (   CLKM  
)
Process

Definition at line 59 of file cdc_pulse.vhd.

◆ proc_slave()

proc_slave (   CLKS  
)
Process

Definition at line 76 of file cdc_pulse.vhd.

◆ proc_pout()

proc_pout (   CLKS  
)
Process

Definition at line 89 of file cdc_pulse.vhd.

Member Data Documentation

◆ RM_REQ

RM_REQ slbit := INIT
Signal

Definition at line 44 of file cdc_pulse.vhd.

◆ RS_REQ_S0

RS_REQ_S0 slbit := INIT
Signal

Definition at line 45 of file cdc_pulse.vhd.

◆ RS_REQ_S1

RS_REQ_S1 slbit := INIT
Signal

Definition at line 46 of file cdc_pulse.vhd.

◆ RM_ACK_S0

RM_ACK_S0 slbit := ' 0 '
Signal

Definition at line 47 of file cdc_pulse.vhd.

◆ RM_ACK_S1

RM_ACK_S1 slbit := ' 0 '
Signal

Definition at line 48 of file cdc_pulse.vhd.

◆ ASYNC_REG [1/2]

ASYNC_REG string
Attribute

Definition at line 50 of file cdc_pulse.vhd.

◆ ASYNC_REG [2/2]

ASYNC_REG signal is " true "
Attribute

Definition at line 52 of file cdc_pulse.vhd.

◆ RS_ACK_1

RS_ACK_1 slbit := INIT
Signal

Definition at line 86 of file cdc_pulse.vhd.

◆ RS_POUT

RS_POUT slbit := ' 0 '
Signal

Definition at line 87 of file cdc_pulse.vhd.

The documentation for this design unit was generated from the following file: