w11 - vhd 0.794
W11 CPU core and support modules
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Libraries | Ports | Use Clauses
arty_dummy Entity Reference

Entities

syn  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
slvtypes  Package <slvtypes>

Ports

I_CLK100   in   slbit
I_RXD   in   slbit
O_TXD   out   slbit
I_SWI   in   slv4
I_BTN   in   slv4
O_LED   out   slv4
O_RGBLED0   out   slv3
O_RGBLED1   out   slv3
O_RGBLED2   out   slv3
O_RGBLED3   out   slv3
A_VPWRN   in   slv4
A_VPWRP   in   slv4

Detailed Description

Definition at line 25 of file arty_dummy.vhd.

Member Data Documentation

◆ I_CLK100

I_CLK100 in slbit
Port

Definition at line 28 of file arty_dummy.vhd.

◆ I_RXD

I_RXD in slbit
Port

Definition at line 29 of file arty_dummy.vhd.

◆ O_TXD

O_TXD out slbit
Port

Definition at line 30 of file arty_dummy.vhd.

◆ I_SWI

I_SWI in slv4
Port

Definition at line 31 of file arty_dummy.vhd.

◆ I_BTN

I_BTN in slv4
Port

Definition at line 32 of file arty_dummy.vhd.

◆ O_LED

O_LED out slv4
Port

Definition at line 33 of file arty_dummy.vhd.

◆ O_RGBLED0

O_RGBLED0 out slv3
Port

Definition at line 34 of file arty_dummy.vhd.

◆ O_RGBLED1

O_RGBLED1 out slv3
Port

Definition at line 35 of file arty_dummy.vhd.

◆ O_RGBLED2

O_RGBLED2 out slv3
Port

Definition at line 36 of file arty_dummy.vhd.

◆ O_RGBLED3

O_RGBLED3 out slv3
Port

Definition at line 37 of file arty_dummy.vhd.

◆ A_VPWRN

A_VPWRN in slv4
Port

Definition at line 38 of file arty_dummy.vhd.

◆ A_VPWRP

A_VPWRP in slv4
Port

Definition at line 40 of file arty_dummy.vhd.

◆ ieee

ieee
Library

Definition at line 20 of file arty_dummy.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 21 of file arty_dummy.vhd.

◆ slvtypes

slvtypes
use clause

Definition at line 23 of file arty_dummy.vhd.

The documentation for this design unit was generated from the following file: