73use ieee.std_logic_1164.
all;
74use ieee.numeric_std.
all;
85 DATA_MODE : std_logic_vector(3 downto 0) := "0010";
86 ADDR_MODE : std_logic_vector(3 downto 0) := "0011";
102 BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
103 END_ADDRESS : std_logic_vector(31 downto 0) := X"00ffffff";
113 CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
114 WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
115 RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
134 RANKS : integer := 1;
163 TCQ : integer := 100;
194 ddr2_dq : inout std_logic_vector(15 downto 0);
195 ddr2_dqs_p : inout std_logic_vector(1 downto 0);
196 ddr2_dqs_n : inout std_logic_vector(1 downto 0);
199 ddr2_addr : out std_logic_vector(12 downto 0);
200 ddr2_ba : out std_logic_vector(2 downto 0);
204 ddr2_ck_p : out std_logic_vector(0 downto 0);
205 ddr2_ck_n : out std_logic_vector(0 downto 0);
206 ddr2_cke : out std_logic_vector(0 downto 0);
207 ddr2_cs_n : out std_logic_vector(0 downto 0);
208 ddr2_dm : out std_logic_vector(1 downto 0);
209 ddr2_odt : out std_logic_vector(0 downto 0);
236 function clogb2 (size :
integer)
return integer is
237 variable base : integer := 1;
238 variable inp : integer := 0;
246 end function;
function STR_TO_INT(BM : string) return integer is
259 function XWIDTH return integer is
272 constant tPRDI : integer := 1000000;
297 ddr2_dq :
inout std_logic_vector(
15 downto 0);
298 ddr2_dqs_p :
inout std_logic_vector(
1 downto 0);
299 ddr2_dqs_n :
inout std_logic_vector(
1 downto 0);
301 ddr2_addr :
out std_logic_vector(
12 downto 0);
302 ddr2_ba :
out std_logic_vector(
2 downto 0);
306 ddr2_ck_p :
out std_logic_vector(
0 downto 0);
307 ddr2_ck_n :
out std_logic_vector(
0 downto 0);
308 ddr2_cke :
out std_logic_vector(
0 downto 0);
310 ddr2_cs_n :
out std_logic_vector(
0 downto 0);
311 ddr2_dm :
out std_logic_vector(
1 downto 0);
312 ddr2_odt :
out std_logic_vector(
0 downto 0);
313 app_addr :
in std_logic_vector(
26 downto 0);
314 app_cmd :
in std_logic_vector(
2 downto 0);
350 component mig_7series_v4_2_traffic_gen_top
356 TST_MEM_INSTR_MODE :
string;
358 nCK_PER_CLK :
integer;
359 NUM_DQ_PINS :
integer;
360 MEM_BURST_LEN :
integer;
361 MEM_COL_WIDTH :
integer;
362 DATA_WIDTH :
integer;
363 ADDR_WIDTH :
integer;
364 MASK_SIZE :
integer :=
8;
365 DATA_MODE :
std_logic_vector(
3 downto 0);
366 BEGIN_ADDRESS :
std_logic_vector(
31 downto 0);
367 END_ADDRESS :
std_logic_vector(
31 downto 0);
368 PRBS_EADDR_MASK_POS :
std_logic_vector(
31 downto 0);
369 CMDS_GAP_DELAY :
std_logic_vector(
5 downto 0) := "
000000";
370 SEL_VICTIM_LINE :
integer :=
8;
371 CMD_WDT :
std_logic_vector(
31 downto 0) := X"
000003ff";
372 WR_WDT :
std_logic_vector(
31 downto 0) := X"
00001fff";
373 RD_WDT :
std_logic_vector(
31 downto 0) := X"
000003ff";
376 DATA_PATTERN :
string;
382 tg_only_rst :
in std_logic;
383 manual_clear_error :
in std_logic;
384 memc_init_done :
in std_logic;
385 memc_cmd_full :
in std_logic;
386 memc_cmd_en :
out std_logic;
387 memc_cmd_instr :
out std_logic_vector(
2 downto 0);
388 memc_cmd_bl :
out std_logic_vector(
5 downto 0);
389 memc_cmd_addr :
out std_logic_vector(
31 downto 0);
390 memc_wr_en :
out std_logic;
391 memc_wr_end :
out std_logic;
392 memc_wr_mask :
out std_logic_vector((DATA_WIDTH/
8)
-1 downto 0);
393 memc_wr_data :
out std_logic_vector(DATA_WIDTH
-1 downto 0);
394 memc_wr_full :
in std_logic;
395 memc_rd_en :
out std_logic;
396 memc_rd_data :
in std_logic_vector(DATA_WIDTH
-1 downto 0);
397 memc_rd_empty :
in std_logic;
398 qdr_wr_cmd_o :
out std_logic;
399 qdr_rd_cmd_o :
out std_logic;
400 vio_pause_traffic :
in std_logic;
401 vio_modify_enable :
in std_logic;
402 vio_data_mode_value :
in std_logic_vector(
3 downto 0);
403 vio_addr_mode_value :
in std_logic_vector(
2 downto 0);
404 vio_instr_mode_value :
in std_logic_vector(
3 downto 0);
405 vio_bl_mode_value :
in std_logic_vector(
1 downto 0);
406 vio_fixed_bl_value :
in std_logic_vector(
9 downto 0);
407 vio_fixed_instr_value :
in std_logic_vector(
2 downto 0);
408 vio_data_mask_gen :
in std_logic;
409 fixed_addr_i :
in std_logic_vector(
31 downto 0);
410 fixed_data_i :
in std_logic_vector(
31 downto 0);
411 simple_data0 :
in std_logic_vector(
31 downto 0);
412 simple_data1 :
in std_logic_vector(
31 downto 0);
413 simple_data2 :
in std_logic_vector(
31 downto 0);
414 simple_data3 :
in std_logic_vector(
31 downto 0);
415 simple_data4 :
in std_logic_vector(
31 downto 0);
416 simple_data5 :
in std_logic_vector(
31 downto 0);
417 simple_data6 :
in std_logic_vector(
31 downto 0);
418 simple_data7 :
in std_logic_vector(
31 downto 0);
419 wdt_en_i :
in std_logic;
420 bram_cmd_i :
in std_logic_vector(
38 downto 0);
421 bram_valid_i :
in std_logic;
422 bram_rdy_o :
out std_logic;
423 cmp_data :
out std_logic_vector(DATA_WIDTH
-1 downto 0);
424 cmp_data_valid :
out std_logic;
425 cmp_error :
out std_logic;
426 wr_data_counts :
out std_logic_vector(
47 downto 0);
427 rd_data_counts :
out std_logic_vector(
47 downto 0);
428 dq_error_bytelane_cmp :
out std_logic_vector((NUM_DQ_PINS/
8)
-1 downto 0);
429 error :
out std_logic;
430 error_status :
out std_logic_vector((
64+(
2*DATA_WIDTH))
-1 downto 0);
431 cumlative_dq_lane_error :
out std_logic_vector((NUM_DQ_PINS/
8)
-1 downto 0);
432 cmd_wdt_err_o :
out std_logic;
433 wr_wdt_err_o :
out std_logic;
434 rd_wdt_err_o :
out std_logic;
435 mem_pattern_init_done :
out std_logic
437 end component mig_7series_v4_2_traffic_gen_top;
445 signal app_addr_i : std_logic_vector(31 downto 0);
446 signal app_cmd : std_logic_vector(2 downto 0);
447 signal app_en : std_logic;
470 signal cmp_data_r : std_logic_vector(63 downto 0);
479 signal tg_rst : std_logic;
483 signal clk : std_logic;
484 signal rst : std_logic;
496 signal vio_tg_rst : std_logic_vector(0 downto 0);
511 signal all_zeros1 : std_logic_vector(31 downto 0):= (others => '0');
512 signal all_zeros2 : std_logic_vector(38 downto 0):= (others => '0');
513 signal wdt_en_w : std_logic_vector(0 downto 0);
517 signal device_temp : std_logic_vector(11 downto 0);
593 ui_clk_sync_rst =>
rst,
654 memc_wr_mask =>
app_wdf_mask(((PAYLOAD_WIDTH*2*nCK_PER_CLK
)/8
)-
1 downto 0),
655 memc_wr_data =>
app_wdf_data((PAYLOAD_WIDTH*2*nCK_PER_CLK
)-
1 downto 0),
658 memc_rd_data =>
app_rd_data((PAYLOAD_WIDTH*2*nCK_PER_CLK
)-
1 downto 0),
660 qdr_wr_cmd_o =>
open,
661 qdr_rd_cmd_o =>
open,
729end architecture arch_example_top;
string := "ON" CMD_PIPE_PLUS1
std_logic_vector( APP_MASK_WIDTH- 1 downto 0) app_wdf_mask
std_logic_vector( 2 downto 0) data_mode_manual_sel
std_logic_vector( 0 downto 0) manual_clear_error
std_logic_vector( 3 downto 0) vio_instr_mode_value
integer := XWIDTH+ 3+ ROW_WIDTH+ COL_WIDTH TG_ADDR_WIDTH
std_logic_vector(( PAYLOAD_WIDTH/ 8)- 1 downto 0) cumlative_dq_lane_error
std_logic_vector( 31 downto 0) app_addr_i
std_logic_vector( 0 downto 0) vio_data_mask_gen
integer := clogb2( RANKS ) RANK_WIDTH
std_logic_vector( 0 downto 0) dbg_sel_po_incdec
std_logic_vector( 0 downto 0) vio_dbg_po_f_dec
std_logic_vector( 38 downto 0) :=( others => '0') all_zeros2
std_logic_vector( 2 downto 0) vio_fixed_instr_value
std_logic_vector( 0 downto 0) vio_dbg_po_f_stg23_sel
std_logic cmp_data_valid_r
std_logic_vector( 11 downto 0) device_temp
std_logic app_rd_data_end
std_logic_vector( BL_WIDTH- 1 downto 0) vio_fixed_bl_value
std_logic_vector(( 2* nCK_PER_CLK)- 1 downto 0) app_ecc_single_err
std_logic_vector( 0 downto 0) dbg_po_f_inc
std_logic_vector( 1 downto 0) vio_bl_mode_value
std_logic_vector(( PAYLOAD_WIDTH/ 8)- 1 downto 0) dq_error_bytelane_cmp
integer := STR_TO_INT( BURST_MODE ) BURST_LENGTH
integer := DATA_WIDTH PAYLOAD_WIDTH
std_logic_vector( 0 downto 0) vio_tg_rst
std_logic tg_compare_error_i
std_logic_vector( 0 downto 0) dbg_clear_error
std_logic app_rd_data_valid
std_logic modify_enable_sel
std_logic_vector( 0 downto 0) vio_dbg_sel_po_incdec
std_logic_vector( 47 downto 0) tg_rd_data_counts
std_logic_vector( 0 downto 0) vio_dbg_pi_f_dec
migui_nexys4d u_migui_nexys4du_migui_nexys4d
std_logic_vector( 0 downto 0) vio_dbg_pi_f_inc
std_logic_vector(( 2* nCK_PER_CLK)- 1 downto 0) app_ecc_multiple_err
mig_7series_v4_2_traffic_gen_top u_traffic_gen_topu_traffic_gen_top
std_logic_vector( 0 downto 0) dbg_pi_f_dec
std_logic_vector( 47 downto 0) tg_wr_data_counts
std_logic_vector( 2 downto 0) addr_mode_manual_sel
mig_7series_v4_2_traffic_gen_top
std_logic_vector( 0 downto 0) wdt_en_w
std_logic_vector(( PAYLOAD_WIDTH* 2* nCK_PER_CLK)- 1 downto 0) cmp_data
std_logic_vector( APP_DATA_WIDTH- 1 downto 0) app_rd_data
std_logic_vector( 0 downto 0) dbg_pi_f_inc
std_logic_vector( 3 downto 0) vio_data_mode_value
std_logic app_rd_data_valid_i
std_logic_vector( 0 downto 0) vio_modify_enable
std_logic_vector( 0 downto 0) dbg_po_f_stg23_sel
integer := APP_DATA_WIDTH/ 8 APP_MASK_WIDTH
std_logic_vector( 0 downto 0) vio_dbg_po_f_inc
std_logic_vector( 31 downto 0) :=( others => '0') all_zeros1
std_logic init_calib_complete_i
integer := 2* nCK_PER_CLK* PAYLOAD_WIDTH APP_DATA_WIDTH
std_logic_vector( ADDR_WIDTH- 1 downto 0) app_addr
std_logic_vector( 0 downto 0) vio_pause_traffic
std_logic_vector( 2 downto 0) vio_addr_mode_value
std_logic_vector( 0 downto 0) dbg_po_f_dec
std_logic_vector(( 64+( 4* PAYLOAD_WIDTH* nCK_PER_CLK))- 1 downto 0) error_status
std_logic_vector( APP_DATA_WIDTH- 1 downto 0) app_wdf_data
std_logic_vector( 0 downto 0) mem_pattern_init_done
std_logic_vector( 63 downto 0) cmp_data_r
std_logic_vector( 0 downto 0) dbg_sel_pi_incdec
std_logic_vector( 2 downto 0) app_cmd
std_logic_vector( 0 downto 0) vio_dbg_sel_pi_incdec
integer := DATA_WIDTH/ 8 MASK_SIZE
out ddr2_addr std_logic_vector( 12 downto 0)
BEGIN_ADDRESS std_logic_vector( 31 downto 0) := X"00000000"
in device_temp_i std_logic_vector( 11 downto 0)
out ddr2_cs_n std_logic_vector( 0 downto 0)
out ddr2_ba std_logic_vector( 2 downto 0)
out ddr2_odt std_logic_vector( 0 downto 0)
SIMULATION string := "FALSE"
out ddr2_dm std_logic_vector( 1 downto 0)
DATA_PATTERN string := "DGEN_ALL"
END_ADDRESS std_logic_vector( 31 downto 0) := X"00ffffff"
inout ddr2_dqs_n std_logic_vector( 1 downto 0)
CMD_WDT std_logic_vector( 31 downto 0) := X"000003ff"
inout ddr2_dq std_logic_vector( 15 downto 0)
ADDR_MODE std_logic_vector( 3 downto 0) := "0011"
WR_WDT std_logic_vector( 31 downto 0) := X"00001fff"
out init_calib_complete std_logic
CMD_PATTERN string := "CGEN_ALL"
PRBS_EADDR_MASK_POS std_logic_vector( 31 downto 0) := X"ff000000"
EYE_TEST string := "FALSE"
out ddr2_ck_n std_logic_vector( 0 downto 0)
DRAM_TYPE string := "DDR3"
MEM_ADDR_ORDER string := "ROW_BANK_COLUMN"
TEMP_MON_CONTROL string := "EXTERNAL"
RD_WDT std_logic_vector( 31 downto 0) := X"000003ff"
out tg_compare_error std_logic
PORT_MODE string := "BI_MODE"
out ddr2_cke std_logic_vector( 0 downto 0)
inout ddr2_dqs_p std_logic_vector( 1 downto 0)
DATA_MODE std_logic_vector( 3 downto 0) := "0010"
TST_MEM_INSTR_MODE string := "R_W_INSTR_MODE"
DEBUG_PORT string := "OFF"
DQS_CNT_WIDTH integer := 1
out ddr2_ck_p std_logic_vector( 0 downto 0)
out ddr2_addr std_logic_vector( 12 downto 0)
in device_temp_i std_logic_vector( 11 downto 0)
out ddr2_cs_n std_logic_vector( 0 downto 0)
out ddr2_ba std_logic_vector( 2 downto 0)
out ddr2_odt std_logic_vector( 0 downto 0)
in app_cmd std_logic_vector( 2 downto 0)
out ddr2_dm std_logic_vector( 1 downto 0)
out app_wdf_rdy std_logic
inout ddr2_dqs_n std_logic_vector( 1 downto 0)
inout ddr2_dq std_logic_vector( 15 downto 0)
in app_wdf_data std_logic_vector( 127 downto 0)
out app_rd_data_end std_logic
out init_calib_complete std_logic
out ddr2_ck_n std_logic_vector( 0 downto 0)
out app_sr_active std_logic
out app_rd_data_valid std_logic
out app_rd_data std_logic_vector( 127 downto 0)
out ddr2_cke std_logic_vector( 0 downto 0)
inout ddr2_dqs_p std_logic_vector( 1 downto 0)
out app_ref_ack std_logic
in app_addr std_logic_vector( 26 downto 0)
in app_wdf_mask std_logic_vector( 15 downto 0)
in app_wdf_wren std_logic
out ui_clk_sync_rst std_logic
out ddr2_ck_p std_logic_vector( 0 downto 0)