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mig_7series_v4_2_ddr_phy_top.vhd
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48--*****************************************************************************
49-- ____ ____
50-- / /\/ /
51-- /___/ \ / Vendor : Xilinx
52-- \ \ \/ Version : 1.5
53-- \ \ Application : MIG
54-- / / Filename : ddr_phy_top.vhd
55-- /___/ /\ Date Last Modified : $date$
56-- \ \ / \ Date Created : Jan 31 2012
57-- \___\/\___\
58--
59--Device : 7 Series
60--Design Name : DDR3 SDRAM
61--Purpose : Top level memory interface block. Instantiates a clock
62-- and reset generator, the memory controller, the phy and
63-- the user interface blocks.
64--Reference :
65--Revision History :
66--*****************************************************************************
67
68library ieee;
69 use ieee.std_logic_1164.all;
70 use ieee.numeric_std.all;
71
72
73entity mig_7series_v4_2_ddr_phy_top is
74 generic (
75
76 TCQ : integer := 100; -- Register delay (simulation only)
77 DDR3_VDD_OP_VOLT : string := "135"; -- Voltage mode used for DDR3
78 AL : string := "0"; -- Additive Latency option
79 BANK_WIDTH : integer := 3; -- # of bank bits
80 BURST_MODE : string := "8"; -- Burst length
81 BURST_TYPE : string := "SEQ"; -- Burst type
82 CA_MIRROR : string := "OFF"; -- C/A mirror opt for DDR3 dual rank
83 CK_WIDTH : integer := 1; -- # of CK/CK# outputs to memory
84 CL : integer := 5;
85 COL_WIDTH : integer := 12; -- column address width
86 CS_WIDTH : integer := 1; -- # of unique CS outputs
87 CKE_WIDTH : integer := 1; -- # of cke outputs
88 CWL : integer := 5;
89 DM_WIDTH : integer := 8; -- # of DM (data mask)
90 DQ_WIDTH : integer := 64; -- # of DQ (data)
91 DQS_CNT_WIDTH : integer := 3; -- = ceil(log2(DQS_WIDTH))
92 DQS_WIDTH : integer := 8; -- # of DQS (strobe)
93 DRAM_TYPE : string := "DDR3";
94 DRAM_WIDTH : integer := 8; -- # of DQ per DQS
95 MASTER_PHY_CTL : integer := 0; -- The bank number where master PHY_CONTROL resides
96 LP_DDR_CK_WIDTH : integer := 2;
97 -- Hard PHY parameters
98 PHYCTL_CMD_FIFO : string := "FALSE";
99 -- five fields, one per possible I/O bank, 4 bits in each field,
100 -- 1 per lane data=1/ctl=0
101 DATA_CTL_B0 : std_logic_vector(3 downto 0) := X"c";
102 DATA_CTL_B1 : std_logic_vector(3 downto 0) := X"f";
103 DATA_CTL_B2 : std_logic_vector(3 downto 0) := X"f";
104 DATA_CTL_B3 : std_logic_vector(3 downto 0) := X"f";
105 DATA_CTL_B4 : std_logic_vector(3 downto 0) := X"f";
106 -- defines the byte lanes in I/O banks being used in the interface
107 -- 1- Used, 0- Unused
108 BYTE_LANES_B0 : std_logic_vector(3 downto 0) := "1111";
109 BYTE_LANES_B1 : std_logic_vector(3 downto 0) := "0000";
110 BYTE_LANES_B2 : std_logic_vector(3 downto 0) := "0000";
111 BYTE_LANES_B3 : std_logic_vector(3 downto 0) := "0000";
112 BYTE_LANES_B4 : std_logic_vector(3 downto 0) := "0000";
113 -- defines the bit lanes in I/O banks being used in the interface. Each
114 -- = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused
115 PHY_0_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
116 PHY_1_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
117 PHY_2_BITLANES : std_logic_vector(47 downto 0) := X"000000000000";
118
119 -- control/address/data pin mapping parameters
120 CK_BYTE_MAP : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
121 ADDR_MAP : std_logic_vector(191 downto 0) := X"000000000000000000000000000000000000000000000000";
122 BANK_MAP : std_logic_vector(35 downto 0) := X"000000000";
123 CAS_MAP : std_logic_vector(11 downto 0) := X"000";
124 CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0) := X"00";
125 CKE_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
126 ODT_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
127 CKE_ODT_AUX : string := "FALSE";
128 CS_MAP : std_logic_vector(119 downto 0) := X"000000000000000000000000000000";
129 PARITY_MAP : std_logic_vector(11 downto 0) := X"000";
130 RAS_MAP : std_logic_vector(11 downto 0) := X"000";
131 WE_MAP : std_logic_vector(11 downto 0) := X"000";
132 DQS_BYTE_MAP
133 : std_logic_vector(143 downto 0) := X"000000000000000000000000000000000000";
134 DATA0_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
135 DATA1_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
136 DATA2_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
137 DATA3_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
138 DATA4_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
139 DATA5_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
140 DATA6_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
141 DATA7_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
142 DATA8_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
143 DATA9_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
144 DATA10_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
145 DATA11_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
146 DATA12_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
147 DATA13_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
148 DATA14_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
149 DATA15_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
150 DATA16_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
151 DATA17_MAP : std_logic_vector(95 downto 0) := X"000000000000000000000000";
152 MASK0_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
153 MASK1_MAP : std_logic_vector(107 downto 0) := X"000000000000000000000000000";
154
155 -- This parameter must be set based on memory clock frequency
156 -- It must be set to 4 for frequencies above 533 MHz?? (undecided)
157 -- and set to 2 for 533 MHz and below
158 PRE_REV3ES : string := "OFF"; -- Delay O/Ps using Phaser_Out fine dly
159 nCK_PER_CLK : integer := 2; -- # of memory CKs per fabric CLK
160 nCS_PER_RANK : integer := 1; -- # of unique CS outputs per rank
161 ADDR_CMD_MODE : string := "1T"; -- ADDR/CTRL timing: "2T", "1T"
162 BANK_TYPE : string := "HP_IO"; -- # = "HP_LP", "HR_LP", "DEFAULT"
163 DATA_IO_PRIM_TYPE : string := "DEFAULT"; -- # = "HP_LP", "HR_LP", "DEFAULT"
164 DATA_IO_IDLE_PWRDWN : string := "ON"; -- # = "ON" or "OFF"
165 IODELAY_GRP : string := "IODELAY_MIG";
166 FPGA_SPEED_GRADE : integer := 1;
167 IBUF_LPWR_MODE : string := "OFF"; -- input buffer low power option
168 OUTPUT_DRV : string := "HIGH"; -- to calib_top
169 REG_CTRL : string := "OFF"; -- to calib_top
170 RTT_NOM : string := "60"; -- to calib_top
171 RTT_WR : string := "120"; -- to calib_top
172 tCK : integer := 2500; -- pS
173 tRFC : integer := 110000; -- pS
174 tREFI : integer := 7800000; -- pS
175 DDR2_DQSN_ENABLE : string := "YES"; -- Enable differential DQS for DDR2
176 WRLVL : string := "OFF"; -- to calib_top
177 DEBUG_PORT : string := "OFF"; -- to calib_top
178 RANKS : integer := 4;
179 ODT_WIDTH : integer := 1;
180 ROW_WIDTH : integer := 16; -- DRAM address bus width
181 SLOT_1_CONFIG : std_logic_vector(7 downto 0) := "00000000";
182 -- calibration Address. The address given below will be used for calibration
183 -- read and write operations.
184 CALIB_ROW_ADD : std_logic_vector(15 downto 0) := X"0000"; -- Calibration row address
185 CALIB_COL_ADD : std_logic_vector(11 downto 0) := X"000"; -- Calibration column address
186 CALIB_BA_ADD : std_logic_vector(2 downto 0) := "000"; -- Calibration bank address
187 -- Simulation /debug options
188 SIM_BYPASS_INIT_CAL : string := "OFF";
189 -- Parameter used to force skipping
190 -- or abbreviation of initialization
191 -- and calibration. Overrides
192 -- SIM_INIT_OPTION, SIM_CAL_OPTION,
193 -- and disables various other blocks
194 --parameter SIM_INIT_OPTION = "SKIP_PU_DLY", -- Skip various init steps
195 --parameter SIM_CAL_OPTION = "NONE", -- Skip various calib steps
196 REFCLK_FREQ : real := 200.0; -- IODELAY ref clock freq (MHz)
197 USE_CS_PORT : integer := 1; -- Support chip select output
198 USE_DM_PORT : integer := 1; -- Support data mask output
199 USE_ODT_PORT : integer := 1; -- Support ODT output
200 RD_PATH_REG : integer := 0; -- optional registers in the read path
201 -- to MC for timing improvement.
202 -- =1 enabled, = 0 disabled
203 IDELAY_ADJ : string := "ON"; -- ON: IDELAY-1, OFF: No change
204 FINE_PER_BIT : string := "ON"; -- ON: Use per bit calib for complex rdlvl
205 CENTER_COMP_MODE : string := "ON"; -- ON: use PI stg2 tap compensation
206 PI_VAL_ADJ : string := "ON"; -- ON: PI stg2 tap -1 for centering
207 TAPSPERKCLK : integer := 56;
208 SKIP_CALIB : string := "FALSE"; -- skip calibration define
209 POC_USE_METASTABLE_SAMP : string := "FALSE";
210 FPGA_VOLT_TYPE : string := "N"
211 );
212 port (
213 clk : in std_logic; -- Fabric logic clock
214 -- To MC, calib_top, hard PHY
215 clk_div2 : in std_logic; -- mem_refclk divided by 2 for PI indec
216 rst_div2 : in std_logic; -- reset in clk_div2 domain
217 clk_ref : in std_logic; -- Idelay_ctrl reference clock
218 -- To hard PHY (external source)
219 freq_refclk : in std_logic; -- To hard PHY for Phasers
220 mem_refclk : in std_logic; -- Memory clock to hard PHY
221 pll_lock : in std_logic; -- System PLL lock signal
222 sync_pulse : in std_logic; -- 1/N sync pulse used to
223 -- synchronize all PHASERS
224 mmcm_ps_clk : in std_logic;
225 poc_sample_pd : in std_logic;
226 error : in std_logic; -- Support for TG error detect
227 rst_tg_mc : out std_logic; -- Support for TG error detect
228
229 device_temp : in std_logic_vector(11 downto 0);
230 tempmon_sample_en : in std_logic;
231
232 dbg_sel_pi_incdec : in std_logic;
233 dbg_sel_po_incdec : in std_logic;
234 dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
235 dbg_pi_f_inc : in std_logic;
236 dbg_pi_f_dec : in std_logic;
237 dbg_po_f_inc : in std_logic;
238 dbg_po_f_stg23_sel : in std_logic;
239 dbg_po_f_dec : in std_logic;
240 dbg_idel_down_all : in std_logic;
241 dbg_idel_down_cpt : in std_logic;
242 dbg_idel_up_all : in std_logic;
243 dbg_idel_up_cpt : in std_logic;
244 dbg_sel_all_idel_cpt : in std_logic;
245 dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
246 rst : in std_logic;
247 iddr_rst : in std_logic;
248 slot_0_present : in std_logic_vector(7 downto 0);
249 slot_1_present : in std_logic_vector(7 downto 0);
250 -- From MC
251 mc_ras_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
252 mc_cas_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
253 mc_we_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
254 mc_address : in std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
255 mc_bank : in std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
256 mc_cs_n : in std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
257 mc_reset_n : in std_logic;
258 mc_odt : in std_logic_vector(1 downto 0);
259 mc_cke : in std_logic_vector(nCK_PER_CLK-1 downto 0);
260 -- AUX - For ODT and CKE assertion during reads and writes
261 mc_aux_out0 : in std_logic_vector(3 downto 0);
262 mc_aux_out1 : in std_logic_vector(3 downto 0);
263 mc_cmd_wren : in std_logic;
264 mc_ctl_wren : in std_logic;
265 mc_cmd : in std_logic_vector(2 downto 0);
266 mc_cas_slot : in std_logic_vector(1 downto 0);
267 mc_data_offset : in std_logic_vector(5 downto 0);
268 mc_data_offset_1 : in std_logic_vector(5 downto 0);
269 mc_data_offset_2 : in std_logic_vector(5 downto 0);
270 mc_rank_cnt : in std_logic_vector(1 downto 0);
271 -- Write
272 mc_wrdata_en : in std_logic;
273 mc_wrdata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
274 mc_wrdata_mask : in std_logic_vector((2*nCK_PER_CLK*(DQ_WIDTH/8))-1 downto 0);
275 idle : in std_logic;
276 -- DDR bus signals
277 ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
278 ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
279 ddr_cas_n : out std_logic;
280 ddr_ck_n : out std_logic_vector(CK_WIDTH-1 downto 0);
281 ddr_ck : out std_logic_vector(CK_WIDTH-1 downto 0);
282 ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
283 ddr_cs_n : out std_logic_vector((CS_WIDTH*nCS_PER_RANK)-1 downto 0);
284 ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
285 ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
286 ddr_ras_n : out std_logic;
287 ddr_reset_n : out std_logic;
288 ddr_parity : out std_logic;
289 ddr_we_n : out std_logic;
290 ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
291 ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
292 ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
293
294 psen : out std_logic;
295 psincdec : out std_logic;
296 psdone : in std_logic;
297 calib_tap_req : out std_logic;
298 calib_tap_load : in std_logic;
299 calib_tap_addr : in std_logic_vector(6 downto 0);
300 calib_tap_val : in std_logic_vector(7 downto 0);
301 calib_tap_load_done : in std_logic;
302
303 dbg_calib_top : out std_logic_vector(255 downto 0);
304 dbg_cpt_first_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
305 dbg_cpt_second_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
306 dbg_cpt_tap_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
307 dbg_dq_idelay_tap_cnt : out std_logic_vector(5*DQS_WIDTH*RANKS-1 downto 0);
308 dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
309 dbg_phy_wrcal : out std_logic_vector(99 downto 0);
310 dbg_final_po_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
311 dbg_final_po_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
312 dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
313 dbg_rddata : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
314 dbg_rddata_valid : out std_logic;
315 dbg_rdlvl_done : out std_logic_vector(1 downto 0);
316 dbg_rdlvl_err : out std_logic_vector(1 downto 0);
317 dbg_rdlvl_start : out std_logic_vector(1 downto 0);
318 dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
319 dbg_wl_edge_detect_valid : out std_logic;
320 dbg_wrlvl_done : out std_logic;
321 dbg_wrlvl_err : out std_logic;
322 dbg_wrlvl_start : out std_logic;
323 dbg_wrlvl_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
324 dbg_wrlvl_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
325 dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
326 dbg_pi_phaselock_start : out std_logic;
327 dbg_pi_phaselocked_done : out std_logic;
328 dbg_pi_phaselock_err : out std_logic;
329 dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
330 dbg_pi_dqsfound_start : out std_logic;
331 dbg_pi_dqsfound_done : out std_logic;
332 dbg_pi_dqsfound_err : out std_logic;
333 dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
334 dbg_wrcal_start : out std_logic;
335 dbg_wrcal_done : out std_logic;
336 dbg_wrcal_err : out std_logic;
337 dbg_poc : out std_logic_vector(1023 downto 0);
338 -- FIFO status flags
339 phy_mc_ctl_full : out std_logic;
340 phy_mc_cmd_full : out std_logic;
341 phy_mc_data_full : out std_logic;
342 -- Calibration status and resultant outputs
343 init_calib_complete : out std_logic;
344 init_wrcal_complete : out std_logic;
345 calib_rd_data_offset_0 : out std_logic_vector(6*RANKS-1 downto 0);
346 calib_rd_data_offset_1 : out std_logic_vector(6*RANKS-1 downto 0);
347 calib_rd_data_offset_2 : out std_logic_vector(6*RANKS-1 downto 0);
348 phy_rddata_valid : out std_logic;
349 phy_rd_data : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
350
351 ref_dll_lock : out std_logic;
352 rst_phaser_ref : in std_logic;
353 dbg_rd_data_offset : out std_logic_vector(6*RANKS-1 downto 0);
354 dbg_phy_init : out std_logic_vector(255 downto 0);
355 dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
356 dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
357 dbg_pi_counter_read_val : out std_logic_vector(5 downto 0);
358 dbg_po_counter_read_val : out std_logic_vector(8 downto 0);
359 dbg_oclkdelay_calib_start : out std_logic;
360 dbg_oclkdelay_calib_done : out std_logic;
361 dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
362 dbg_oclkdelay_rd_data : out std_logic_vector(DRAM_WIDTH*16-1 downto 0);
363 prbs_final_dqs_tap_cnt_r : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
364 dbg_prbs_first_edge_taps : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
365 dbg_prbs_second_edge_taps : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0)
366
367 );
368
369end entity;
370
371architecture arch_ddr_phy_top of mig_7series_v4_2_ddr_phy_top is
372
373 -- function to OR the bits in a vectored signal
374 function OR_BR (inp_var: std_logic_vector)
375 return std_logic is
376 variable temp: std_logic := '0';
377 begin
378 for idx in inp_var'range loop
379 temp := temp or inp_var(idx);
380 end loop;
381 return temp;
382 end function;
383
384 -- Calculate number of slots in the system
385 function CALC_nSLOTS return integer is
386 begin
387 if (OR_BR(SLOT_1_CONFIG) = '1') then
388 return (2);
389 else
390 return (1);
391 end if;
392 end function;
393
394 function SIM_INIT_OPTION_W return string is
395 begin
396 if (SIM_BYPASS_INIT_CAL = "SKIP") then
397 return ("SKIP_INIT");
398 elsif (SIM_BYPASS_INIT_CAL = "FAST" or
399 SIM_BYPASS_INIT_CAL = "SIM_FULL") then
400 return ("SKIP_PU_DLY");
401 else
402 return ("NONE");
403 end if;
404 end function;
405
406 function SIM_CAL_OPTION_W return string is
407 begin
408 if (SIM_BYPASS_INIT_CAL = "SKIP") then
409 return ("SKIP_CAL");
410 elsif (SIM_BYPASS_INIT_CAL = "FAST") then
411 return ("FAST_CAL");
412 elsif (SIM_BYPASS_INIT_CAL = "SIM_FULL" or
413 SIM_BYPASS_INIT_CAL = "SIM_INIT_CAL_FULL") then
414 return ("FAST_WIN_DETECT");
415 else
416 return ("NONE");
417 end if;
418 end function;
419
420 function CALC_WRLVL_W return string is
421 begin
422 if (SIM_BYPASS_INIT_CAL = "SKIP") then
423 return ("OFF");
424 else
425 return (WRLVL);
426 end if;
427 end function;
428
429 function HIGHEST_BANK_W return integer is
430 begin
431 if (BYTE_LANES_B4 /= "0000") then
432 return (5);
433 elsif (BYTE_LANES_B3 /= "0000") then
434 return (4);
435 elsif (BYTE_LANES_B2 /= "0000") then
436 return (3);
437 elsif (BYTE_LANES_B1 /= "0000") then
438 return (2);
439 else
440 return (1);
441 end if;
442 end function;
443
444 function HIGHEST_LANE_B0_W return integer is
445 begin
446 if (BYTE_LANES_B0(3) = '1') then
447 return (4);
448 elsif (BYTE_LANES_B0(2) = '1') then
449 return (3);
450 elsif (BYTE_LANES_B0(1) = '1') then
451 return (2);
452 elsif (BYTE_LANES_B0(0) = '1') then
453 return (1);
454 else
455 return (0);
456 end if;
457 end function;
458
459 function HIGHEST_LANE_B1_W return integer is
460 begin
461 if (BYTE_LANES_B1(3) = '1') then
462 return (4);
463 elsif (BYTE_LANES_B1(2) = '1') then
464 return (3);
465 elsif (BYTE_LANES_B1(1) = '1') then
466 return (2);
467 elsif (BYTE_LANES_B1(0) = '1') then
468 return (1);
469 else
470 return (0);
471 end if;
472 end function;
473
474 function HIGHEST_LANE_B2_W return integer is
475 begin
476 if (BYTE_LANES_B2(3) = '1') then
477 return (4);
478 elsif (BYTE_LANES_B2(2) = '1') then
479 return (3);
480 elsif (BYTE_LANES_B2(1) = '1') then
481 return (2);
482 elsif (BYTE_LANES_B2(0) = '1') then
483 return (1);
484 else
485 return (0);
486 end if;
487 end function;
488
489 function HIGHEST_LANE_B3_W return integer is
490 begin
491 if (BYTE_LANES_B3(3) = '1') then
492 return (4);
493 elsif (BYTE_LANES_B3(2) = '1') then
494 return (3);
495 elsif (BYTE_LANES_B3(1) = '1') then
496 return (2);
497 elsif (BYTE_LANES_B3(0) = '1') then
498 return (1);
499 else
500 return (0);
501 end if;
502 end function;
503
504 function HIGHEST_LANE_B4_W return integer is
505 begin
506 if (BYTE_LANES_B4(3) = '1') then
507 return (4);
508 elsif (BYTE_LANES_B4(2) = '1') then
509 return (3);
510 elsif (BYTE_LANES_B4(1) = '1') then
511 return (2);
512 elsif (BYTE_LANES_B4(0) = '1') then
513 return (1);
514 else
515 return (0);
516 end if;
517 end function;
518
519 function HIGHEST_LANE_W return integer is
520 begin
521 if (HIGHEST_LANE_B4_W /= 0) then
522 return (HIGHEST_LANE_B4_W+16);
523 elsif (HIGHEST_LANE_B3_W /= 0) then
524 return (HIGHEST_LANE_B3_W+12);
525 elsif (HIGHEST_LANE_B2_W /= 0) then
526 return (HIGHEST_LANE_B2_W+8);
527 elsif (HIGHEST_LANE_B1_W /= 0) then
528 return (HIGHEST_LANE_B1_W+4);
529 else
530 return (HIGHEST_LANE_B0_W);
531 end if;
532 end function;
533
534 function N_CTL_LANES_B0 return integer is
535 variable temp: integer := 0;
536 begin
537 for idx in 0 to 3 loop
538 if (not(DATA_CTL_B0(idx)) = '1' and BYTE_LANES_B0(idx) = '1') then
539 temp := temp + 1;
540 else
541 temp := temp;
542 end if;
543 end loop;
544 return temp;
545 end function;
546
547 function N_CTL_LANES_B1 return integer is
548 variable temp: integer := 0;
549 begin
550 for idx in 0 to 3 loop
551 if (not(DATA_CTL_B1(idx)) = '1' and BYTE_LANES_B1(idx) = '1') then
552 temp := temp + 1;
553 else
554 temp := temp;
555 end if;
556 end loop;
557 return temp;
558 end function;
559
560 function N_CTL_LANES_B2 return integer is
561 variable temp: integer := 0;
562 begin
563 for idx in 0 to 3 loop
564 if (not(DATA_CTL_B2(idx)) = '1' and BYTE_LANES_B2(idx) = '1') then
565 temp := temp + 1;
566 else
567 temp := temp;
568 end if;
569 end loop;
570 return temp;
571 end function;
572
573 function N_CTL_LANES_B3 return integer is
574 variable temp: integer := 0;
575 begin
576 for idx in 0 to 3 loop
577 if (not(DATA_CTL_B3(idx)) = '1' and BYTE_LANES_B3(idx) = '1') then
578 temp := temp + 1;
579 else
580 temp := temp;
581 end if;
582 end loop;
583 return temp;
584 end function;
585
586 function N_CTL_LANES_B4 return integer is
587 variable temp: integer := 0;
588 begin
589 for idx in 0 to 3 loop
590 if (not(DATA_CTL_B4(idx)) = '1' and BYTE_LANES_B4(idx) = '1') then
591 temp := temp + 1;
592 else
593 temp := temp;
594 end if;
595 end loop;
596 return temp;
597 end function;
598
599 function CTL_BANK_B0 return std_logic is
600 begin
601 if ((not(DATA_CTL_B0(0)) = '1' and BYTE_LANES_B0(0) = '1') or
602 (not(DATA_CTL_B0(1)) = '1' and BYTE_LANES_B0(1) = '1') or
603 (not(DATA_CTL_B0(2)) = '1' and BYTE_LANES_B0(2) = '1') or
604 (not(DATA_CTL_B0(3)) = '1' and BYTE_LANES_B0(3) = '1')) then
605 return ('1') ;
606 else
607 return ('0') ;
608 end if;
609 end function;
610
611 function CTL_BANK_B1 return std_logic is
612 begin
613 if ((not(DATA_CTL_B1(0)) = '1' and BYTE_LANES_B1(0) = '1') or
614 (not(DATA_CTL_B1(1)) = '1' and BYTE_LANES_B1(1) = '1') or
615 (not(DATA_CTL_B1(2)) = '1' and BYTE_LANES_B1(2) = '1') or
616 (not(DATA_CTL_B1(3)) = '1' and BYTE_LANES_B1(3) = '1')) then
617 return ('1') ;
618 else
619 return ('0') ;
620 end if;
621 end function;
622
623 function CTL_BANK_B2 return std_logic is
624 begin
625 if ((not(DATA_CTL_B2(0)) = '1' and BYTE_LANES_B2(0) = '1') or
626 (not(DATA_CTL_B2(1)) = '1' and BYTE_LANES_B2(1) = '1') or
627 (not(DATA_CTL_B2(2)) = '1' and BYTE_LANES_B2(2) = '1') or
628 (not(DATA_CTL_B2(3)) = '1' and BYTE_LANES_B2(3) = '1')) then
629 return ('1') ;
630 else
631 return ('0') ;
632 end if;
633 end function;
634
635 function CTL_BANK_B3 return std_logic is
636 begin
637 if ((not(DATA_CTL_B3(0)) = '1' and BYTE_LANES_B3(0) = '1') or
638 (not(DATA_CTL_B3(1)) = '1' and BYTE_LANES_B3(1) = '1') or
639 (not(DATA_CTL_B3(2)) = '1' and BYTE_LANES_B3(2) = '1') or
640 (not(DATA_CTL_B3(3)) = '1' and BYTE_LANES_B3(3) = '1')) then
641 return ('1') ;
642 else
643 return ('0') ;
644 end if;
645 end function;
646
647 function CTL_BANK_B4 return std_logic is
648 begin
649 if ((not(DATA_CTL_B4(0)) = '1' and BYTE_LANES_B4(0) = '1') or
650 (not(DATA_CTL_B4(1)) = '1' and BYTE_LANES_B4(1) = '1') or
651 (not(DATA_CTL_B4(2)) = '1' and BYTE_LANES_B4(2) = '1') or
652 (not(DATA_CTL_B4(3)) = '1' and BYTE_LANES_B4(3) = '1')) then
653 return ('1') ;
654 else
655 return ('0') ;
656 end if;
657 end function;
658
659 function CTL_BANK_W return std_logic_vector is
660 variable ctl_bank_var : std_logic_vector(2 downto 0);
661 begin
662 if (CTL_BANK_B0 = '1') then
663 ctl_bank_var := "000";
664 elsif (CTL_BANK_B1 = '1') then
665 ctl_bank_var := "001";
666 elsif (CTL_BANK_B2 = '1') then
667 ctl_bank_var := "010";
668 elsif (CTL_BANK_B3 = '1') then
669 ctl_bank_var := "011";
670 elsif (CTL_BANK_B4 = '1') then
671 ctl_bank_var := "100";
672 else
673 ctl_bank_var := "000";
674 end if;
675 return (ctl_bank_var);
676 end function;
677
678 function ODD_PARITY (inp_var : std_logic_vector) return std_logic is
679 variable tmp : std_logic := '0';
680 begin
681 for idx in inp_var'range loop
682 tmp := tmp XOR inp_var(idx);
683 end loop;
684 return tmp;
685 end ODD_PARITY;
686
687 -- Calculate number of slots in the system
688 constant nSLOTS : integer := CALC_nSLOTS;
689 constant CLK_PERIOD : integer := tCK * nCK_PER_CLK;
690
691 -- Parameter used to force skipping or abbreviation of initialization
692 -- and calibration. Overrides SIM_INIT_OPTION, SIM_CAL_OPTION, and
693 -- disables various other blocks depending on the option selected
694 -- This option should only be used during simulation. In the case of
695 -- the "SKIP" option, the testbench used should also not be modeling
696 -- propagation delays.
697 -- Allowable options = {"NONE", "SIM_FULL", "SKIP", "FAST"}
698 -- "NONE" = options determined by the individual parameter settings
699 -- "SIM_FULL" = skip power-up delay. FULL calibration performed without
700 -- averaging algorithm turned ON during window detection.
701 -- "SKIP" = skip power-up delay. Skip calibration not yet supported.
702 -- "FAST" = skip power-up delay, and calibrate (read leveling, write
703 -- leveling, and phase detector) only using one DQS group, and
704 -- apply the results to all other DQS groups.
705 constant SIM_INIT_OPTION : string := SIM_INIT_OPTION_W;
706 constant SIM_CAL_OPTION : string := SIM_CAL_OPTION_W;
707 constant WRLVL_W : string := CALC_WRLVL_W;
708
709 constant HIGHEST_BANK : integer := HIGHEST_BANK_W;
710
711 -- constant HIGHEST_LANE_B0 = HIGHEST_LANE_B0_W;
712 -- constant HIGHEST_LANE_B1 = HIGHEST_LANE_B1_W;
713 -- constant HIGHEST_LANE_B2 = HIGHEST_LANE_B2_W;
714 -- constant HIGHEST_LANE_B3 = HIGHEST_LANE_B3_W;
715 -- constant HIGHEST_LANE_B4 = HIGHEST_LANE_B4_W;
716
717 constant HIGHEST_LANE : integer := HIGHEST_LANE_W;
718
719 constant N_CTL_LANES : integer := N_CTL_LANES_B0 + N_CTL_LANES_B1 + N_CTL_LANES_B2 + N_CTL_LANES_B3 + N_CTL_LANES_B4;
720
721 -- Assuming Ck/Addr/Cmd and Control are placed in a single IO Bank
722 -- This should be the case since the PLL should be placed adjacent
723 -- to the same IO Bank as Ck/Addr/Cmd and Control
724 constant CTL_BANK : std_logic_vector(2 downto 0):= CTL_BANK_W;
725
726 function CTL_BYTE_LANE_W return std_logic_vector is
727 variable ctl_byte_lane_var: std_logic_vector(7 downto 0);
728 begin
729 if (N_CTL_LANES = 4) then
730 ctl_byte_lane_var := "11100100";
731 elsif (N_CTL_LANES = 3 and
732 (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
733 (not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
734 (not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or
735 ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
736 (not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
737 (not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or
738 ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
739 (not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
740 (not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or
741 ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
742 (not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
743 (not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or
744 ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
745 (not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
746 (not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then
747 ctl_byte_lane_var := "00100100";
748 elsif (N_CTL_LANES = 3 and
749 (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
750 (not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
751 (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
752 ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
753 (not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
754 (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
755 ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
756 (not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
757 (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
758 ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
759 (not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
760 (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
761 ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
762 (not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
763 (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
764 ctl_byte_lane_var := "00110100";
765 elsif (N_CTL_LANES = 3 and
766 (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
767 (not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and
768 (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
769 ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
770 (not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and
771 (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
772 ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
773 (not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and
774 (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
775 ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
776 (not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and
777 (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
778 ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
779 (not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and
780 (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
781 ctl_byte_lane_var := "00111000";
782 elsif (N_CTL_LANES = 3 and
783 (((not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
784 (not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and
785 (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
786 ((not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
787 (not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and
788 (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
789 ((not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
790 (not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and
791 (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
792 ((not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
793 (not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and
794 (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
795 ((not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
796 (not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and
797 (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
798 ctl_byte_lane_var := "00111001";
799 elsif (N_CTL_LANES = 2 and
800 (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
801 (not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1') or
802 ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
803 (not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1') or
804 ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
805 (not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1') or
806 ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
807 (not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1') or
808 ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
809 (not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1'))) then
810 ctl_byte_lane_var := "00000100";
811 elsif (N_CTL_LANES = 2 and
812 (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
813 (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
814 ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
815 (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
816 ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
817 (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
818 ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
819 (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
820 ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
821 (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
822 ctl_byte_lane_var := "00001100";
823 elsif (N_CTL_LANES = 2 and
824 (((not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1' and
825 (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
826 ((not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1' and
827 (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
828 ((not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1' and
829 (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
830 ((not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1' and
831 (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
832 ((not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1' and
833 (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
834 ctl_byte_lane_var := "00001110";
835 elsif (N_CTL_LANES = 2 and
836 (((not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
837 (not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or
838 ((not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
839 (not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or
840 ((not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
841 (not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or
842 ((not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
843 (not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or
844 ((not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
845 (not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then
846 ctl_byte_lane_var := "00001001";
847 elsif (N_CTL_LANES = 2 and
848 (((not(DATA_CTL_B0(1)) = '1') and BYTE_LANES_B0(1) = '1' and
849 (not(DATA_CTL_B0(3)) = '1') and BYTE_LANES_B0(3) = '1') or
850 ((not(DATA_CTL_B1(1)) = '1') and BYTE_LANES_B1(1) = '1' and
851 (not(DATA_CTL_B1(3)) = '1') and BYTE_LANES_B1(3) = '1') or
852 ((not(DATA_CTL_B2(1)) = '1') and BYTE_LANES_B2(1) = '1' and
853 (not(DATA_CTL_B2(3)) = '1') and BYTE_LANES_B2(3) = '1') or
854 ((not(DATA_CTL_B3(1)) = '1') and BYTE_LANES_B3(1) = '1' and
855 (not(DATA_CTL_B3(3)) = '1') and BYTE_LANES_B3(3) = '1') or
856 ((not(DATA_CTL_B4(1)) = '1') and BYTE_LANES_B4(1) = '1' and
857 (not(DATA_CTL_B4(3)) = '1') and BYTE_LANES_B4(3) = '1'))) then
858 ctl_byte_lane_var := "00001101";
859 elsif (N_CTL_LANES = 2 and
860 (((not(DATA_CTL_B0(0)) = '1') and BYTE_LANES_B0(0) = '1' and
861 (not(DATA_CTL_B0(2)) = '1') and BYTE_LANES_B0(2) = '1') or
862 ((not(DATA_CTL_B1(0)) = '1') and BYTE_LANES_B1(0) = '1' and
863 (not(DATA_CTL_B1(2)) = '1') and BYTE_LANES_B1(2) = '1') or
864 ((not(DATA_CTL_B2(0)) = '1') and BYTE_LANES_B2(0) = '1' and
865 (not(DATA_CTL_B2(2)) = '1') and BYTE_LANES_B2(2) = '1') or
866 ((not(DATA_CTL_B3(0)) = '1') and BYTE_LANES_B3(0) = '1' and
867 (not(DATA_CTL_B3(2)) = '1') and BYTE_LANES_B3(2) = '1') or
868 ((not(DATA_CTL_B4(0)) = '1') and BYTE_LANES_B4(0) = '1' and
869 (not(DATA_CTL_B4(2)) = '1') and BYTE_LANES_B4(2) = '1'))) then
870 ctl_byte_lane_var := "00001000";
871 else
872 ctl_byte_lane_var := "11100100";
873 end if;
874 return (ctl_byte_lane_var);
875 end function;
876
877 constant CTL_BYTE_LANE : std_logic_vector(7 downto 0):= CTL_BYTE_LANE_W;
878
879 function PI_DIV2_INCDEC_FUN return string is
880 begin
881 if (DRAM_TYPE = "DDR2") then
882 return ("FALSE");
883 elsif ((FPGA_VOLT_TYPE = "L") and (nCK_PER_CLK = 4)) then
884 return ("TRUE");
885 else
886 return ("FALSE");
887 end if;
888 end function;
889
890 constant PI_DIV2_INCDEC : string := PI_DIV2_INCDEC_FUN;
891
892 component mig_7series_v4_2_ddr_mc_phy_wrapper is
893 generic (
894 TCQ : integer;
895 tCK : integer;
896 BANK_TYPE : string;
897 DATA_IO_PRIM_TYPE : string;
898 DATA_IO_IDLE_PWRDWN :string;
899 IODELAY_GRP : string;
900 FPGA_SPEED_GRADE : integer;
901 nCK_PER_CLK : integer;
902 nCS_PER_RANK : integer;
903 BANK_WIDTH : integer;
904 CKE_WIDTH : integer;
905 CS_WIDTH : integer;
906 CK_WIDTH : integer;
907 CWL : integer;
908 DDR2_DQSN_ENABLE : string;
909 DM_WIDTH : integer;
910 DQ_WIDTH : integer;
911 DQS_CNT_WIDTH : integer;
912 DQS_WIDTH : integer;
913 DRAM_TYPE : string;
914 RANKS : integer;
915 ODT_WIDTH : integer;
916 REG_CTRL : string;
917 ROW_WIDTH : integer;
918 USE_CS_PORT : integer;
919 USE_DM_PORT : integer;
920 USE_ODT_PORT : integer;
921 IBUF_LPWR_MODE : string;
922 LP_DDR_CK_WIDTH : integer;
923 PHYCTL_CMD_FIFO : string;
924 DATA_CTL_B0 : std_logic_vector(3 downto 0);
925 DATA_CTL_B1 : std_logic_vector(3 downto 0);
926 DATA_CTL_B2 : std_logic_vector(3 downto 0);
927 DATA_CTL_B3 : std_logic_vector(3 downto 0);
928 DATA_CTL_B4 : std_logic_vector(3 downto 0);
929 BYTE_LANES_B0 : std_logic_vector(3 downto 0);
930 BYTE_LANES_B1 : std_logic_vector(3 downto 0);
931 BYTE_LANES_B2 : std_logic_vector(3 downto 0);
932 BYTE_LANES_B3 : std_logic_vector(3 downto 0);
933 BYTE_LANES_B4 : std_logic_vector(3 downto 0);
934 PHY_0_BITLANES : std_logic_vector(47 downto 0);
935 PHY_1_BITLANES : std_logic_vector(47 downto 0);
936 PHY_2_BITLANES : std_logic_vector(47 downto 0);
937 HIGHEST_BANK : integer;
938 HIGHEST_LANE : integer;
939 CK_BYTE_MAP : std_logic_vector(143 downto 0);
940 ADDR_MAP : std_logic_vector(191 downto 0);
941 BANK_MAP : std_logic_vector(35 downto 0);
942 CAS_MAP : std_logic_vector(11 downto 0);
943 CKE_ODT_BYTE_MAP : std_logic_vector(7 downto 0);
944 CKE_MAP : std_logic_vector(95 downto 0);
945 ODT_MAP : std_logic_vector(95 downto 0);
946 CKE_ODT_AUX : string;
947 CS_MAP : std_logic_vector(119 downto 0);
948 PARITY_MAP : std_logic_vector(11 downto 0);
949 RAS_MAP : std_logic_vector(11 downto 0);
950 WE_MAP : std_logic_vector(11 downto 0);
951 DQS_BYTE_MAP : std_logic_vector(143 downto 0);
952 DATA0_MAP : std_logic_vector(95 downto 0);
953 DATA1_MAP : std_logic_vector(95 downto 0);
954 DATA2_MAP : std_logic_vector(95 downto 0);
955 DATA3_MAP : std_logic_vector(95 downto 0);
956 DATA4_MAP : std_logic_vector(95 downto 0);
957 DATA5_MAP : std_logic_vector(95 downto 0);
958 DATA6_MAP : std_logic_vector(95 downto 0);
959 DATA7_MAP : std_logic_vector(95 downto 0);
960 DATA8_MAP : std_logic_vector(95 downto 0);
961 DATA9_MAP : std_logic_vector(95 downto 0);
962 DATA10_MAP : std_logic_vector(95 downto 0);
963 DATA11_MAP : std_logic_vector(95 downto 0);
964 DATA12_MAP : std_logic_vector(95 downto 0);
965 DATA13_MAP : std_logic_vector(95 downto 0);
966 DATA14_MAP : std_logic_vector(95 downto 0);
967 DATA15_MAP : std_logic_vector(95 downto 0);
968 DATA16_MAP : std_logic_vector(95 downto 0);
969 DATA17_MAP : std_logic_vector(95 downto 0);
970 MASK0_MAP : std_logic_vector(107 downto 0);
971 MASK1_MAP : std_logic_vector(107 downto 0);
972 SIM_CAL_OPTION : string;
973 MASTER_PHY_CTL : integer;
974 DRAM_WIDTH : integer;
975 POC_USE_METASTABLE_SAMP : string;
976 PI_DIV2_INCDEC : string
977 );
978 port (
979 rst : in std_logic;
980 iddr_rst : in std_logic;
981 clk : in std_logic;
982 clk_div2 : in std_logic;
983 freq_refclk : in std_logic;
984 mem_refclk : in std_logic;
985 pll_lock : in std_logic;
986 sync_pulse : in std_logic;
987 mmcm_ps_clk : in std_logic;
988 idelayctrl_refclk : in std_logic;
989 phy_cmd_wr_en : in std_logic;
990 phy_data_wr_en : in std_logic;
991 phy_ctl_wd : in std_logic_vector(31 downto 0);
992 phy_ctl_wr : in std_logic;
993 phy_if_empty_def : in std_logic;
994 phy_if_reset : in std_logic;
995 data_offset_1 : in std_logic_vector(5 downto 0);
996 data_offset_2 : in std_logic_vector(5 downto 0);
997 aux_in_1 : in std_logic_vector(3 downto 0);
998 aux_in_2 : in std_logic_vector(3 downto 0);
999 idelaye2_init_val : out std_logic_vector(4 downto 0);
1000 oclkdelay_init_val : out std_logic_vector(5 downto 0);
1001 if_empty : out std_logic;
1002 phy_ctl_full : out std_logic;
1003 phy_cmd_full : out std_logic;
1004 phy_data_full : out std_logic;
1005 phy_pre_data_a_full : out std_logic;
1006 ddr_clk : out std_logic_vector(CK_WIDTH*LP_DDR_CK_WIDTH-1 downto 0);
1007 phy_mc_go : out std_logic;
1008 phy_write_calib : in std_logic;
1009 phy_read_calib : in std_logic;
1010 calib_in_common : in std_logic;
1011 calib_sel : in std_logic_vector(5 downto 0);
1012 calib_zero_inputs : in std_logic_vector(HIGHEST_BANK-1 downto 0);
1013 calib_zero_ctrl : in std_logic_vector(HIGHEST_BANK-1 downto 0);
1014 po_fine_enable : in std_logic_vector(2 downto 0);
1015 po_coarse_enable : in std_logic_vector(2 downto 0);
1016 po_fine_inc : in std_logic_vector(2 downto 0);
1017 po_coarse_inc : in std_logic_vector(2 downto 0);
1018 po_counter_load_en : in std_logic;
1019 po_counter_read_en : in std_logic;
1020 po_sel_fine_oclk_delay : in std_logic_vector(2 downto 0);
1021 po_counter_load_val : in std_logic_vector(8 downto 0);
1022 po_counter_read_val : out std_logic_vector(8 downto 0);
1023 pi_counter_read_val : out std_logic_vector(5 downto 0);
1024 pi_rst_dqs_find : in std_logic_vector(HIGHEST_BANK-1 downto 0);
1025 pi_fine_enable : in std_logic;
1026 pi_fine_inc : in std_logic;
1027 pi_counter_load_en : in std_logic;
1028 pi_counter_load_val : in std_logic_vector(5 downto 0);
1029 idelay_ce : in std_logic;
1030 idelay_inc : in std_logic;
1031 idelay_ld : in std_logic;
1032 idle : in std_logic;
1033 pi_phase_locked : out std_logic;
1034 pi_phase_locked_all : out std_logic;
1035 pi_dqs_found : out std_logic;
1036 pi_dqs_found_all : out std_logic;
1037 pi_dqs_out_of_range : out std_logic;
1038 phy_init_data_sel : in std_logic;
1039 mux_address : in std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
1040 mux_bank : in std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
1041 mux_cas_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
1042 mux_cs_n : in std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
1043 mux_ras_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
1044 mux_odt : in std_logic_vector(1 downto 0);
1045 mux_cke : in std_logic_vector(nCK_PER_CLK-1 downto 0);
1046 mux_we_n : in std_logic_vector(nCK_PER_CLK-1 downto 0);
1047 parity_in : in std_logic_vector(nCK_PER_CLK-1 downto 0);
1048 mux_wrdata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
1049 mux_wrdata_mask : in std_logic_vector(2*nCK_PER_CLK*(DQ_WIDTH/8)-1 downto 0);
1050 mux_reset_n : in std_logic;
1051 rd_data : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
1052 ddr_addr : out std_logic_vector(ROW_WIDTH-1 downto 0);
1053 ddr_ba : out std_logic_vector(BANK_WIDTH-1 downto 0);
1054 ddr_cas_n : out std_logic;
1055 ddr_cke : out std_logic_vector(CKE_WIDTH-1 downto 0);
1056 ddr_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK-1 downto 0);
1057 ddr_dm : out std_logic_vector(DM_WIDTH-1 downto 0);
1058 ddr_odt : out std_logic_vector(ODT_WIDTH-1 downto 0);
1059 ddr_parity : out std_logic;
1060 ddr_ras_n : out std_logic;
1061 ddr_we_n : out std_logic;
1062 ddr_reset_n : out std_logic;
1063 ddr_dq : inout std_logic_vector(DQ_WIDTH-1 downto 0);
1064 ddr_dqs : inout std_logic_vector(DQS_WIDTH-1 downto 0);
1065 ddr_dqs_n : inout std_logic_vector(DQS_WIDTH-1 downto 0);
1066 dbg_pi_counter_read_en : in std_logic;
1067 ref_dll_lock : out std_logic;
1068 rst_phaser_ref : in std_logic;
1069 dbg_pi_phase_locked_phy4lanes : out std_logic_vector(11 downto 0);
1070 dbg_pi_dqs_found_lanes_phy4lanes : out std_logic_vector(11 downto 0);
1071 byte_sel_cnt : in std_logic_vector(DQS_CNT_WIDTH downto 0);
1072 fine_delay_incdec_pb : in std_logic_vector(DRAM_WIDTH-1 downto 0);
1073 fine_delay_sel : in std_logic;
1074 pd_out : out std_logic
1075 );
1076 end component mig_7series_v4_2_ddr_mc_phy_wrapper;
1077
1078 component mig_7series_v4_2_ddr_calib_top is
1079 generic (
1080 TCQ : integer;
1081 nCK_PER_CLK : integer;
1082 tCK : integer;
1083 DDR3_VDD_OP_VOLT : string ;
1084 CLK_PERIOD : integer;
1085 N_CTL_LANES : integer;
1086 DRAM_TYPE : string;
1087 PRBS_WIDTH : integer;
1088 HIGHEST_LANE : integer;
1089 HIGHEST_BANK : integer;
1090 BANK_TYPE : string;
1091 DATA_CTL_B0 : std_logic_vector(3 downto 0);
1092 DATA_CTL_B1 : std_logic_vector(3 downto 0);
1093 DATA_CTL_B2 : std_logic_vector(3 downto 0);
1094 DATA_CTL_B3 : std_logic_vector(3 downto 0);
1095 DATA_CTL_B4 : std_logic_vector(3 downto 0);
1096 BYTE_LANES_B0 : std_logic_vector(3 downto 0);
1097 BYTE_LANES_B1 : std_logic_vector(3 downto 0);
1098 BYTE_LANES_B2 : std_logic_vector(3 downto 0);
1099 BYTE_LANES_B3 : std_logic_vector(3 downto 0);
1100 BYTE_LANES_B4 : std_logic_vector(3 downto 0);
1101 DQS_BYTE_MAP : std_logic_vector(143 downto 0);
1102 CTL_BYTE_LANE : std_logic_vector(7 downto 0);
1103 CTL_BANK : std_logic_vector(2 downto 0);
1104 SLOT_1_CONFIG : std_logic_vector(7 downto 0);
1105 BANK_WIDTH : integer;
1106 CA_MIRROR : string;
1107 COL_WIDTH : integer;
1108 nCS_PER_RANK : integer;
1109 DQ_WIDTH : integer;
1110 DQS_CNT_WIDTH : integer;
1111 DQS_WIDTH : integer;
1112 DRAM_WIDTH : integer;
1113 ROW_WIDTH : integer;
1114 RANKS : integer;
1115 CS_WIDTH : integer;
1116 CKE_WIDTH : integer;
1117 DDR2_DQSN_ENABLE : string;
1118 PER_BIT_DESKEW : string;
1119 NUM_DQSFOUND_CAL : integer := 1020;
1120 CALIB_ROW_ADD : std_logic_vector(15 downto 0);
1121 CALIB_COL_ADD : std_logic_vector(11 downto 0);
1122 CALIB_BA_ADD : std_logic_vector(2 downto 0);
1123 AL : string;
1124 TEST_AL : string := "0";
1125 ADDR_CMD_MODE : string;
1126 BURST_MODE : string;
1127 BURST_TYPE : string;
1128 nCL : integer;
1129 nCWL : integer;
1130 tRFC : integer;
1131 tREFI : integer;
1132 OUTPUT_DRV : string;
1133 REG_CTRL : string;
1134 RTT_NOM : string;
1135 RTT_WR : string;
1136 USE_ODT_PORT : integer;
1137 WRLVL : string;
1138 PRE_REV3ES : string;
1139 SIM_INIT_OPTION : string;
1140 SIM_CAL_OPTION : string;
1141 CKE_ODT_AUX : string;
1142 IDELAY_ADJ : string;
1143 FINE_PER_BIT : string;
1144 CENTER_COMP_MODE : string;
1145 PI_VAL_ADJ : string;
1146 TAPSPERKCLK : integer;
1147 DEBUG_PORT : string;
1148 SKIP_CALIB : string;
1149 POC_USE_METASTABLE_SAMP : string;
1150 PI_DIV2_INCDEC : string
1151 );
1152 port (
1153 clk : in std_logic;
1154 rst : in std_logic;
1155 slot_0_present : in std_logic_vector(7 downto 0);
1156 slot_1_present : in std_logic_vector(7 downto 0);
1157 phy_ctl_ready : in std_logic;
1158 phy_ctl_full : in std_logic;
1159 phy_cmd_full : in std_logic;
1160 phy_data_full : in std_logic;
1161 write_calib : out std_logic;
1162 read_calib : out std_logic;
1163 calib_ctl_wren : out std_logic;
1164 calib_cmd_wren : out std_logic;
1165 calib_seq : out std_logic_vector(1 downto 0);
1166 calib_aux_out : out std_logic_vector(3 downto 0);
1167 calib_cke : out std_logic_vector(nCK_PER_CLK-1 downto 0);
1168 calib_odt : out std_logic_vector(1 downto 0);
1169 calib_cmd : out std_logic_vector(2 downto 0);
1170 calib_wrdata_en : out std_logic;
1171 calib_rank_cnt : out std_logic_vector(1 downto 0);
1172 calib_cas_slot : out std_logic_vector(1 downto 0);
1173 calib_data_offset_0 : out std_logic_vector(5 downto 0);
1174 calib_data_offset_1 : out std_logic_vector(5 downto 0);
1175 calib_data_offset_2 : out std_logic_vector(5 downto 0);
1176 phy_address : out std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
1177 phy_bank : out std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
1178 phy_cs_n : out std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
1179 phy_ras_n : out std_logic_vector(nCK_PER_CLK-1 downto 0);
1180 phy_cas_n : out std_logic_vector(nCK_PER_CLK-1 downto 0);
1181 phy_we_n : out std_logic_vector(nCK_PER_CLK-1 downto 0);
1182 phy_reset_n : out std_logic;
1183 calib_sel : out std_logic_vector(5 downto 0);
1184 calib_in_common : out std_logic;
1185 calib_zero_inputs : out std_logic_vector(HIGHEST_BANK-1 downto 0);
1186 calib_zero_ctrl : out std_logic_vector(HIGHEST_BANK-1 downto 0);
1187 phy_if_empty_def : out std_logic;
1188 phy_if_reset : out std_logic;
1189 pi_phaselocked : in std_logic;
1190 pi_phase_locked_all : in std_logic;
1191 pi_found_dqs : in std_logic;
1192 pi_dqs_found_all : in std_logic;
1193 pi_dqs_found_lanes : in std_logic_vector(HIGHEST_LANE-1 downto 0);
1194 pi_counter_read_val : in std_logic_vector(5 downto 0);
1195 pi_rst_stg1_cal : out std_logic_vector(HIGHEST_BANK-1 downto 0);
1196 pi_en_stg2_f : out std_logic;
1197 pi_stg2_f_incdec : out std_logic;
1198 pi_stg2_load : out std_logic;
1199 pi_stg2_reg_l : out std_logic_vector(5 downto 0);
1200 idelay_ce : out std_logic;
1201 idelay_inc : out std_logic;
1202 idelay_ld : out std_logic;
1203 po_sel_stg2stg3 : out std_logic_vector(2 downto 0);
1204 po_stg2_c_incdec : out std_logic_vector(2 downto 0);
1205 po_en_stg2_c : out std_logic_vector(2 downto 0);
1206 po_stg2_f_incdec : out std_logic_vector(2 downto 0);
1207 po_en_stg2_f : out std_logic_vector(2 downto 0);
1208 po_counter_load_en : out std_logic;
1209 po_counter_read_val : in std_logic_vector(8 downto 0);
1210 device_temp : in std_logic_vector(11 downto 0);
1211 tempmon_sample_en : in std_logic;
1212 phy_if_empty : in std_logic;
1213 idelaye2_init_val : in std_logic_vector(4 downto 0);
1214 oclkdelay_init_val : in std_logic_vector(5 downto 0);
1215 tg_err : in std_logic;
1216 rst_tg_mc : out std_logic;
1217 phy_wrdata : out std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
1218 dlyval_dq : out std_logic_vector(5*RANKS*DQ_WIDTH-1 downto 0);
1219 phy_rddata : in std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
1220 calib_rd_data_offset_0 : out std_logic_vector(6*RANKS-1 downto 0);
1221 calib_rd_data_offset_1 : out std_logic_vector(6*RANKS-1 downto 0);
1222 calib_rd_data_offset_2 : out std_logic_vector(6*RANKS-1 downto 0);
1223 phy_rddata_valid : out std_logic;
1224 calib_writes : out std_logic;
1225 init_calib_complete : out std_logic;
1226 init_wrcal_complete : out std_logic;
1227 pi_phase_locked_err : out std_logic;
1228 pi_dqsfound_err : out std_logic;
1229 wrcal_err : out std_logic;
1230 psen : out std_logic;
1231 psincdec : out std_logic;
1232 psdone : in std_logic;
1233 poc_sample_pd : in std_logic;
1234 calib_tap_req : out std_logic;
1235 calib_tap_load : in std_logic;
1236 calib_tap_addr : in std_logic_vector(6 downto 0);
1237 calib_tap_val : in std_logic_vector(7 downto 0);
1238 calib_tap_load_done : in std_logic;
1239 dbg_pi_phaselock_start : out std_logic;
1240 dbg_pi_dqsfound_start : out std_logic;
1241 dbg_pi_dqsfound_done : out std_logic;
1242 dbg_wrcal_start : out std_logic;
1243 dbg_wrcal_done : out std_logic;
1244 dbg_wrlvl_start : out std_logic;
1245 dbg_wrlvl_done : out std_logic;
1246 dbg_wrlvl_err : out std_logic;
1247 dbg_wrlvl_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
1248 dbg_wrlvl_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
1249 dbg_phy_wrlvl : out std_logic_vector(255 downto 0);
1250 dbg_tap_cnt_during_wrlvl : out std_logic_vector(5 downto 0);
1251 dbg_wl_edge_detect_valid : out std_logic;
1252 dbg_rd_data_edge_detect : out std_logic_vector(DQS_WIDTH-1 downto 0);
1253 dbg_final_po_fine_tap_cnt : out std_logic_vector(6*DQS_WIDTH-1 downto 0);
1254 dbg_final_po_coarse_tap_cnt : out std_logic_vector(3*DQS_WIDTH-1 downto 0);
1255 dbg_phy_wrcal : out std_logic_vector(99 downto 0);
1256 dbg_rdlvl_start : out std_logic_vector(1 downto 0);
1257 dbg_rdlvl_done : out std_logic_vector(1 downto 0);
1258 dbg_rdlvl_err : out std_logic_vector(1 downto 0);
1259 dbg_cpt_first_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
1260 dbg_cpt_second_edge_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
1261 dbg_cpt_tap_cnt : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
1262 dbg_dq_idelay_tap_cnt : out std_logic_vector(5*DQS_WIDTH*RANKS-1 downto 0);
1263 dbg_sel_pi_incdec : in std_logic;
1264 dbg_sel_po_incdec : in std_logic;
1265 dbg_byte_sel : in std_logic_vector(DQS_CNT_WIDTH downto 0);
1266 dbg_pi_f_inc : in std_logic;
1267 dbg_pi_f_dec : in std_logic;
1268 dbg_po_f_inc : in std_logic;
1269 dbg_po_f_stg23_sel : in std_logic;
1270 dbg_po_f_dec : in std_logic;
1271 dbg_idel_up_all : in std_logic;
1272 dbg_idel_down_all : in std_logic;
1273 dbg_idel_up_cpt : in std_logic;
1274 dbg_idel_down_cpt : in std_logic;
1275 dbg_sel_idel_cpt : in std_logic_vector(DQS_CNT_WIDTH-1 downto 0);
1276 dbg_sel_all_idel_cpt : in std_logic;
1277 dbg_phy_rdlvl : out std_logic_vector(255 downto 0);
1278 dbg_calib_top : out std_logic_vector(255 downto 0);
1279 dbg_phy_init : out std_logic_vector(255 downto 0);
1280 dbg_prbs_rdlvl : out std_logic_vector(255 downto 0);
1281 dbg_dqs_found_cal : out std_logic_vector(255 downto 0);
1282 dbg_phy_oclkdelay_cal : out std_logic_vector(255 downto 0);
1283 dbg_oclkdelay_rd_data : out std_logic_vector(DRAM_WIDTH*16-1 downto 0);
1284 dbg_oclkdelay_calib_start : out std_logic;
1285 dbg_oclkdelay_calib_done : out std_logic;
1286 dbg_poc : out std_logic_vector(1023 downto 0);
1287 prbs_final_dqs_tap_cnt_r : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
1288 dbg_prbs_first_edge_taps : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
1289 dbg_prbs_second_edge_taps : out std_logic_vector(6*DQS_WIDTH*RANKS-1 downto 0);
1290 byte_sel_cnt : out std_logic_vector(DQS_CNT_WIDTH downto 0);
1291 fine_delay_incdec_pb : out std_logic_vector(DRAM_WIDTH-1 downto 0);
1292 fine_delay_sel : out std_logic;
1293 pd_out : in std_logic
1294 );
1295 end component mig_7series_v4_2_ddr_calib_top;
1296
1297 signal phy_din : std_logic_vector(HIGHEST_LANE*80-1 downto 0);
1298 signal phy_dout : std_logic_vector(HIGHEST_LANE*80-1 downto 0);
1299 signal ddr_cmd_ctl_data : std_logic_vector(HIGHEST_LANE*12-1 downto 0);
1300 signal aux_out : std_logic_vector((((HIGHEST_LANE+3)/4)*4)-1 downto 0);
1301 signal ddr_clk : std_logic_vector(CK_WIDTH * LP_DDR_CK_WIDTH-1 downto 0);
1302 signal phy_mc_go : std_logic;
1303 signal phy_ctl_full : std_logic;
1304 signal phy_cmd_full : std_logic;
1305 signal phy_data_full : std_logic;
1306 signal phy_pre_data_a_full : std_logic;
1307 signal if_empty : std_logic;
1308 signal phy_write_calib : std_logic;
1309 signal phy_read_calib : std_logic;
1310 signal rst_stg1_cal : std_logic_vector(HIGHEST_BANK-1 downto 0);
1311 signal calib_sel : std_logic_vector(5 downto 0);
1312 signal calib_in_common : std_logic;
1313 signal calib_zero_inputs : std_logic_vector(HIGHEST_BANK-1 downto 0);
1314 signal calib_zero_ctrl : std_logic_vector(HIGHEST_BANK-1 downto 0);
1315 signal pi_phase_locked : std_logic;
1316 signal pi_phase_locked_all : std_logic;
1317 signal pi_found_dqs : std_logic;
1318 signal pi_dqs_found_all : std_logic;
1319 signal pi_dqs_out_of_range : std_logic;
1320 signal pi_enstg2_f : std_logic;
1321 signal pi_stg2_fincdec : std_logic;
1322 signal pi_stg2_load : std_logic;
1323 signal pi_stg2_reg_l : std_logic_vector(5 downto 0);
1324 signal idelay_ce : std_logic;
1325 signal idelay_inc : std_logic;
1326 signal idelay_ld : std_logic;
1327 signal po_sel_stg2stg3 : std_logic_vector(2 downto 0);
1328 signal po_stg2_cincdec : std_logic_vector(2 downto 0);
1329 signal po_enstg2_c : std_logic_vector(2 downto 0);
1330 signal po_stg2_fincdec : std_logic_vector(2 downto 0);
1331 signal po_enstg2_f : std_logic_vector(2 downto 0);
1332 signal po_counter_read_val : std_logic_vector(8 downto 0);
1333 signal pi_counter_read_val : std_logic_vector(5 downto 0);
1334 signal phy_wrdata : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
1335 signal parity : std_logic_vector(nCK_PER_CLK-1 downto 0);
1336 signal phy_address : std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
1337 signal phy_bank : std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
1338 signal phy_cs_n : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
1339 signal phy_ras_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
1340 signal phy_cas_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
1341 signal phy_we_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
1342 signal phy_reset_n : std_logic;
1343 signal calib_aux_out : std_logic_vector(3 downto 0);
1344 signal calib_cke : std_logic_vector(nCK_PER_CLK-1 downto 0);
1345 signal calib_odt : std_logic_vector(1 downto 0);
1346 signal calib_ctl_wren : std_logic;
1347 signal calib_cmd_wren : std_logic;
1348 signal calib_wrdata_en : std_logic;
1349 signal calib_cmd : std_logic_vector(2 downto 0);
1350 signal calib_seq : std_logic_vector(1 downto 0);
1351 signal calib_data_offset_0 : std_logic_vector(5 downto 0);
1352 signal calib_data_offset_1 : std_logic_vector(5 downto 0);
1353 signal calib_data_offset_2 : std_logic_vector(5 downto 0);
1354 signal calib_rank_cnt : std_logic_vector(1 downto 0);
1355 signal calib_cas_slot : std_logic_vector(1 downto 0);
1356 signal mux_address : std_logic_vector(nCK_PER_CLK*ROW_WIDTH-1 downto 0);
1357 signal mux_aux_out : std_logic_vector(3 downto 0);
1358 signal aux_out_map : std_logic_vector(3 downto 0);
1359 signal mux_bank : std_logic_vector(nCK_PER_CLK*BANK_WIDTH-1 downto 0);
1360 signal mux_cmd : std_logic_vector(2 downto 0);
1361 signal mux_cmd_wren : std_logic;
1362 signal mux_cs_n : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
1363 signal mux_ctl_wren : std_logic;
1364 signal mux_cas_slot : std_logic_vector(1 downto 0);
1365 signal mux_data_offset : std_logic_vector(5 downto 0);
1366 signal mux_data_offset_1 : std_logic_vector(5 downto 0);
1367 signal mux_data_offset_2 : std_logic_vector(5 downto 0);
1368 signal mux_ras_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
1369 signal mux_cas_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
1370 signal mux_rank_cnt : std_logic_vector(1 downto 0);
1371 signal mux_reset_n : std_logic;
1372 signal mux_we_n : std_logic_vector(nCK_PER_CLK-1 downto 0);
1373 signal mux_wrdata : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
1374 signal mux_wrdata_mask : std_logic_vector(2*nCK_PER_CLK*(DQ_WIDTH/8)-1 downto 0);
1375 signal mux_wrdata_en : std_logic;
1376 signal mux_cke : std_logic_vector(nCK_PER_CLK-1 downto 0);
1377 signal mux_odt : std_logic_vector(1 downto 0);
1378 signal phy_if_empty_def : std_logic;
1379 signal phy_if_reset : std_logic;
1380 signal phy_init_data_sel : std_logic;
1381 signal rd_data_map : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
1382 signal phy_rddata_valid_w : std_logic;
1383 signal rddata_valid_reg : std_logic;
1384 signal rd_data_reg : std_logic_vector(2*nCK_PER_CLK*DQ_WIDTH-1 downto 0);
1385 signal idelaye2_init_val : std_logic_vector(4 downto 0);
1386 signal oclkdelay_init_val : std_logic_vector(5 downto 0);
1387
1388 signal mc_cs_n_temp : std_logic_vector(CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1 downto 0);
1389
1390 signal calib_rd_data_offset_i0 : std_logic_vector(6*RANKS-1 downto 0);
1391 signal init_wrcal_complete_i : std_logic;
1392 signal phy_ctl_wd_i : std_logic_vector(31 downto 0);
1393 signal po_counter_load_en : std_logic;
1394 signal parity_0_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
1395 signal parity_1_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
1396 signal parity_2_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
1397 signal parity_3_wire : std_logic_vector((ROW_WIDTH+BANK_WIDTH+3)-1 downto 0);
1398 signal dbg_pi_dqs_found_lanes_phy4lanes_i : std_logic_vector(11 downto 0);
1399 signal all_zeros : std_logic_vector(8 downto 0):= (others => '0');
1400
1401 signal byte_sel_cnt : std_logic_vector(DQS_CNT_WIDTH downto 0);
1402 signal fine_delay_incdec_pb : std_logic_vector(DRAM_WIDTH-1 downto 0);
1403 signal fine_delay_sel : std_logic;
1404 signal pd_out : std_logic;
1405
1406 -- 3-stage synchronizer registers
1407 signal pi_fine_enable : std_logic;
1408 signal pi_fine_inc : std_logic;
1409 signal pi_counter_load_en : std_logic;
1410 signal pi_counter_load_val : std_logic_vector(5 downto 0);
1411 signal pi_rst_dqs_find : std_logic_vector(HIGHEST_BANK-1 downto 0);
1412 signal pi_enstg2_f_div2r1 : std_logic;
1413 signal pi_enstg2_f_div2r2 : std_logic;
1414 signal pi_enstg2_f_div2r3 : std_logic;
1415 signal pi_stg2_fincdec_div2r1 : std_logic;
1416 signal pi_stg2_fincdec_div2r2 : std_logic;
1417 signal pi_stg2_fincdec_div2r3 : std_logic;
1418 signal pi_stg2_load_div2r1 : std_logic;
1419 signal pi_stg2_load_div2r2 : std_logic;
1420 signal pi_stg2_load_div2r3 : std_logic;
1421 signal rst_stg1_cal_div2r1 : std_logic_vector(HIGHEST_BANK-1 downto 0);
1422 signal rst_stg1_cal_div2r2 : std_logic_vector(HIGHEST_BANK-1 downto 0);
1423 signal pi_stg2_reg_l_div2r1 : std_logic_vector(5 downto 0);
1424 signal pi_stg2_reg_l_div2r2 : std_logic_vector(5 downto 0);
1425 signal pi_stg2_reg_l_div2r3 : std_logic_vector(5 downto 0);
1426 signal pi_dqs_find_rst : std_logic_vector(HIGHEST_BANK-1 downto 0);
1427
1428 attribute ASYNC_REG : string;
1429 attribute ASYNC_REG of pi_fine_enable : signal is "TRUE";
1430 attribute ASYNC_REG of pi_fine_inc : signal is "TRUE";
1431 attribute ASYNC_REG of pi_counter_load_en : signal is "TRUE";
1432 attribute ASYNC_REG of pi_counter_load_val : signal is "TRUE";
1433 attribute ASYNC_REG of pi_rst_dqs_find : signal is "TRUE";
1434 attribute ASYNC_REG of pi_enstg2_f_div2r1 : signal is "TRUE";
1435 attribute ASYNC_REG of pi_enstg2_f_div2r2 : signal is "TRUE";
1436 attribute ASYNC_REG of pi_enstg2_f_div2r3 : signal is "TRUE";
1437 attribute ASYNC_REG of pi_stg2_fincdec_div2r1 : signal is "TRUE";
1438 attribute ASYNC_REG of pi_stg2_fincdec_div2r2 : signal is "TRUE";
1439 attribute ASYNC_REG of pi_stg2_fincdec_div2r3 : signal is "TRUE";
1440 attribute ASYNC_REG of pi_stg2_load_div2r1 : signal is "TRUE";
1441 attribute ASYNC_REG of pi_stg2_load_div2r2 : signal is "TRUE";
1442 attribute ASYNC_REG of pi_stg2_load_div2r3 : signal is "TRUE";
1443 attribute ASYNC_REG of rst_stg1_cal_div2r1 : signal is "TRUE";
1444 attribute ASYNC_REG of rst_stg1_cal_div2r2 : signal is "TRUE";
1445 attribute ASYNC_REG of pi_stg2_reg_l_div2r1 : signal is "TRUE";
1446 attribute ASYNC_REG of pi_stg2_reg_l_div2r2 : signal is "TRUE";
1447 attribute ASYNC_REG of pi_stg2_reg_l_div2r3 : signal is "TRUE";
1448 attribute ASYNC_REG of pi_dqs_find_rst : signal is "TRUE";
1449
1450 signal pi_stg2_fine_enable, pi_stg2_fine_enable_r1 : std_logic;
1451 signal pi_stg2_fine_inc, pi_stg2_fine_inc_r1 : std_logic;
1452 signal pi_stg2_load_en, pi_stg2_load_en_r1 : std_logic;
1453 signal pi_stg2_load_val : std_logic_vector(5 downto 0);
1454
1455 begin
1456
1457 --***************************************************************************
1458
1459 dbg_rddata_valid <= rddata_valid_reg;
1460 dbg_rddata <= rd_data_reg;
1461
1462 dbg_rd_data_offset <= calib_rd_data_offset_i0;
1463 calib_rd_data_offset_0 <= calib_rd_data_offset_i0;
1464
1465 dbg_pi_phaselocked_done <= pi_phase_locked_all;
1466
1467 dbg_po_counter_read_val <= po_counter_read_val;
1468 dbg_pi_counter_read_val <= pi_counter_read_val;
1469
1470 dbg_pi_dqs_found_lanes_phy4lanes <= dbg_pi_dqs_found_lanes_phy4lanes_i;
1471
1472 init_wrcal_complete <= init_wrcal_complete_i;
1473
1474 --***************************************************************************
1475
1476 --***************************************************************************
1477 -- Clock domain crossing from DIV4 to DIV2 for Phaser_In stage2 incdec
1478 --***************************************************************************
1479
1480
1481 div2_incdec : if (PI_DIV2_INCDEC = "TRUE") generate
1482 -- 3-stage synchronizer
1483 process (clk_div2) begin
1484 if (rising_edge(clk_div2)) then
1485 -- Phaser_In fine enable
1486 pi_enstg2_f_div2r1 <= pi_enstg2_f after (TCQ) * 1 ps;
1487 pi_enstg2_f_div2r2 <= pi_enstg2_f_div2r1 after (TCQ) * 1 ps;
1488 pi_enstg2_f_div2r3 <= pi_enstg2_f_div2r2 after (TCQ) * 1 ps;
1489 -- Phaser_In fine incdec
1490 pi_stg2_fincdec_div2r1 <= pi_stg2_fincdec after (TCQ) * 1 ps;
1491 pi_stg2_fincdec_div2r2 <= pi_stg2_fincdec_div2r1 after (TCQ) * 1 ps;
1492 pi_stg2_fincdec_div2r3 <= pi_stg2_fincdec_div2r2 after (TCQ) * 1 ps;
1493 -- Phaser_In stage2 load
1494 pi_stg2_load_div2r1 <= pi_stg2_load after (TCQ) * 1 ps;
1495 pi_stg2_load_div2r2 <= pi_stg2_load_div2r1 after (TCQ) * 1 ps;
1496 pi_stg2_load_div2r3 <= pi_stg2_load_div2r2 after (TCQ) * 1 ps;
1497 -- Phaser_In stage2 load value
1498 pi_stg2_reg_l_div2r1 <= pi_stg2_reg_l after (TCQ) * 1 ps;
1499 pi_stg2_reg_l_div2r2 <= pi_stg2_reg_l_div2r1 after (TCQ) * 1 ps;
1500 pi_stg2_reg_l_div2r3 <= pi_stg2_reg_l_div2r2 after (TCQ) * 1 ps;
1501 -- Phaser_In reset DQSFOUND
1502 rst_stg1_cal_div2r1 <= rst_stg1_cal after (TCQ) * 1 ps;
1503 rst_stg1_cal_div2r2 <= rst_stg1_cal_div2r1 after (TCQ) * 1 ps;
1504 pi_dqs_find_rst <= rst_stg1_cal_div2r2 after (TCQ) * 1 ps;
1505 end if;
1506 end process;
1507
1508 process (clk_div2) begin
1509 if (rising_edge(clk_div2)) then
1510 pi_stg2_fine_enable_r1 <= pi_stg2_fine_enable after (TCQ) * 1 ps;
1511 pi_stg2_fine_inc_r1 <= pi_stg2_fine_inc after (TCQ) * 1 ps;
1512 pi_stg2_load_en_r1 <= pi_stg2_load_en after (TCQ) * 1 ps;
1513 end if;
1514 end process;
1515
1516 process (clk_div2) begin
1517 if (rising_edge(clk_div2)) then
1518 if ((rst_div2 = '1') or (pi_stg2_fine_enable = '1') or (pi_stg2_fine_enable_r1 = '1')) then
1519 pi_stg2_fine_enable <= '0' after (TCQ) * 1 ps;
1520 elsif (pi_enstg2_f_div2r3 = '1') then
1521 pi_stg2_fine_enable <= '1' after (TCQ) * 1 ps;
1522 end if;
1523 end if;
1524 end process;
1525
1526 process (clk_div2) begin
1527 if (rising_edge(clk_div2)) then
1528 if ((rst_div2 = '1') or (pi_stg2_fine_inc = '1') or (pi_stg2_fine_inc_r1 = '1')) then
1529 pi_stg2_fine_inc <= '0' after (TCQ) * 1 ps;
1530 elsif (pi_stg2_fincdec_div2r3 = '1') then
1531 pi_stg2_fine_inc <= '1' after (TCQ) * 1 ps;
1532 end if;
1533 end if;
1534 end process;
1535
1536 process (clk_div2) begin
1537 if (rising_edge(clk_div2)) then
1538 if ((rst_div2 = '1') or (pi_stg2_load_en = '1') or (pi_stg2_load_en_r1 = '1')) then
1539 pi_stg2_load_en <= '0' after (TCQ) * 1 ps;
1540 elsif (pi_stg2_load_div2r3 = '1') then
1541 pi_stg2_load_en <= '1' after (TCQ) * 1 ps;
1542 end if;
1543 end if;
1544 end process;
1545
1546 process (clk_div2) begin
1547 if (rising_edge(clk_div2)) then
1548 if ((rst_div2 = '1') or (pi_stg2_load_en = '1') or (pi_stg2_load_en_r1 = '1')) then
1549 pi_stg2_load_val <= (others => '0') after (TCQ) * 1 ps;
1550 elsif (pi_stg2_load_div2r3 = '1') then
1551 pi_stg2_load_val <= pi_stg2_reg_l_div2r3 after (TCQ) * 1 ps;
1552 end if;
1553 end if;
1554 end process;
1555
1556 pi_fine_enable <= pi_stg2_fine_enable;
1557 pi_fine_inc <= pi_stg2_fine_inc;
1558 pi_counter_load_en <= pi_stg2_load_en;
1559 pi_counter_load_val <= pi_stg2_load_val;
1560 pi_rst_dqs_find <= pi_dqs_find_rst;
1561 end generate div2_incdec;
1562
1563 div4_incdec : if (PI_DIV2_INCDEC = "FALSE") generate
1564 pi_fine_enable <= pi_enstg2_f;
1565 pi_fine_inc <= pi_stg2_fincdec;
1566 pi_counter_load_en <= pi_stg2_load;
1567 pi_counter_load_val <= pi_stg2_reg_l;
1568 pi_rst_dqs_find <= rst_stg1_cal;
1569 end generate div4_incdec;
1570
1571 --***************************************************************************
1572 clock_gen : for i in 0 to (CK_WIDTH-1) generate
1573 ddr_ck(i) <= ddr_clk(LP_DDR_CK_WIDTH * i);
1574 ddr_ck_n(i) <= ddr_clk((LP_DDR_CK_WIDTH * i) + 1);
1575 end generate;
1576
1577 --***************************************************************************
1578 -- During memory initialization and calibration the calibration logic drives
1579 -- the memory signals. After calibration is complete the memory controller
1580 -- drives the memory signals.
1581 -- Do not expect timing issues in 4:1 mode at 800 MHz/1600 Mbps
1582 --***************************************************************************
1583
1584 cs_rdimm : if((REG_CTRL = "ON") and (DRAM_TYPE = "DDR3") and (RANKS = 1) and (nCS_PER_RANK = 2)) generate
1585 cs_rdimm_gen: for v in 0 to (CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK)-1 generate
1586 cs_rdimm_gen_i : if((v mod (CS_WIDTH*nCS_PER_RANK)) = 0) generate
1587 mc_cs_n_temp(v) <= mc_cs_n(v) ;
1588 end generate;
1589
1590 cs_rdimm_gen_j : if(not((v mod (CS_WIDTH*nCS_PER_RANK)) = 0)) generate
1591 mc_cs_n_temp(v) <= '1' ;
1592 end generate;
1593
1594 end generate;
1595 end generate;
1596
1597 cs_others : if(not(REG_CTRL = "ON") or not(DRAM_TYPE = "DDR3") or not(RANKS = 1) or not(nCS_PER_RANK = 2)) generate
1598 mc_cs_n_temp <= mc_cs_n ;
1599 end generate;
1600
1601 mux_wrdata <= mc_wrdata when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_wrdata;
1602 mux_wrdata_mask <= mc_wrdata_mask when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else (others => '0');
1603 mux_address <= mc_address when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_address;
1604 mux_bank <= mc_bank when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_bank;
1605 mux_cs_n <= mc_cs_n_temp when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_cs_n;
1606 mux_ras_n <= mc_ras_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_ras_n;
1607 mux_cas_n <= mc_cas_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_cas_n;
1608 mux_we_n <= mc_we_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_we_n;
1609 mux_reset_n <= mc_reset_n when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else phy_reset_n;
1610 mux_aux_out <= mc_aux_out0 when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_aux_out;
1611 mux_odt <= mc_odt when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_odt;
1612 mux_cke <= mc_cke when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_cke;
1613 mux_cmd_wren <= mc_cmd_wren when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_cmd_wren;
1614 mux_ctl_wren <= mc_ctl_wren when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_ctl_wren;
1615 mux_wrdata_en <= mc_wrdata_en when (phy_init_data_sel = '1' or init_wrcal_complete_i = '1') else calib_wrdata_en;
1616 mux_cmd <= mc_cmd when (phy_init_data_sel ='1' or init_wrcal_complete_i ='1') else calib_cmd;
1617 mux_cas_slot <= mc_cas_slot when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_cas_slot;
1618 mux_data_offset <= mc_data_offset when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_0;
1619 mux_data_offset_1 <= mc_data_offset_1 when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_1;
1620 mux_data_offset_2 <= mc_data_offset_2 when (phy_init_data_sel ='1' or init_wrcal_complete_i = '1') else calib_data_offset_2;
1621 -- Reserved field. Hard coded to 2'b00 irrespective of the number of ranks. CR 643601
1622 mux_rank_cnt <= "00";
1623
1624
1625 -- Assigning cke & odt for DDR2 & DDR3
1626 -- No changes for DDR3 & DDR2 dual rank
1627 -- DDR2 single rank systems might potentially need 3 odt signals.
1628 -- Aux_out[2] will have the odt toggled by phy and controller
1629 -- wiring aux_out[2] to 0 & 3. Depending upon the odt parameter
1630 -- all of the three odt bits or some of them might be used.
1631 -- mapping done in mc_phy_wrapper module
1632 aux_out_gen : if(CKE_ODT_AUX = "TRUE") generate
1633 aux_out_map <= (mux_aux_out(1) & mux_aux_out(1) & mux_aux_out(1) &
1634 mux_aux_out(0)) when ((DRAM_TYPE = "DDR2") and
1635 (RANKS = 1)) else
1636 mux_aux_out;
1637 end generate;
1638
1639 wo_aux_out_gen : if(not(CKE_ODT_AUX = "TRUE")) generate
1640 aux_out_map <= "0000";
1641 end generate;
1642
1643 init_calib_complete <= phy_init_data_sel;
1644
1645 phy_mc_ctl_full <= phy_ctl_full;
1646 phy_mc_cmd_full <= phy_cmd_full;
1647 phy_mc_data_full <= phy_pre_data_a_full;
1648
1649
1650 --***************************************************************************
1651 -- Generate parity for DDR3 RDIMM.
1652 --***************************************************************************
1653
1654 gen_ddr3_parity : if ((DRAM_TYPE = "DDR3") and (REG_CTRL = "ON")) generate
1655
1656 gen_ddr3_parity_4by1: if (nCK_PER_CLK = 4) generate
1657
1658 parity_0_wire <= (mux_address((ROW_WIDTH*4)-1 downto ROW_WIDTH*3) &
1659 mux_bank((BANK_WIDTH*4)-1 downto BANK_WIDTH*3) &
1660 mux_cas_n(3) & mux_ras_n(3) & mux_we_n(3));
1661 parity_1_wire <= (mux_address(ROW_WIDTH-1 downto 0) &
1662 mux_bank(BANK_WIDTH-1 downto 0) & mux_cas_n(0) &
1663 mux_ras_n(0) & mux_we_n(0));
1664 parity_2_wire <= (mux_address((ROW_WIDTH*2)-1 downto ROW_WIDTH) &
1665 mux_bank((BANK_WIDTH*2)-1 downto BANK_WIDTH) &
1666 mux_cas_n(1) & mux_ras_n(1) & mux_we_n(1));
1667 parity_3_wire <= (mux_address((ROW_WIDTH*3)-1 downto ROW_WIDTH*2) &
1668 mux_bank((BANK_WIDTH*3)-1 downto BANK_WIDTH*2) &
1669 mux_cas_n(2) & mux_ras_n(2) & mux_we_n(2));
1670
1671 process (clk)
1672 begin
1673 if (clk'event and clk = '1') then
1674 parity(0) <= ODD_PARITY(parity_0_wire) after (TCQ) * 1 ps;
1675 end if;
1676 end process;
1677
1678 process (mux_address, mux_bank, mux_cas_n, mux_ras_n, mux_we_n)
1679 begin
1680 parity(1) <= ODD_PARITY(parity_1_wire) after (TCQ) * 1 ps;
1681 parity(2) <= ODD_PARITY(parity_2_wire) after (TCQ) * 1 ps;
1682 parity(3) <= ODD_PARITY(parity_3_wire) after (TCQ) * 1 ps;
1683 end process;
1684 end generate;
1685
1686 gen_ddr3_parity_2by1: if ( not(nCK_PER_CLK = 4)) generate
1687
1688 parity_1_wire <= (mux_address(ROW_WIDTH-1 downto 0) &
1689 mux_bank(BANK_WIDTH-1 downto 0) & mux_cas_n(0) &
1690 mux_ras_n(0) & mux_we_n(0));
1691 parity_2_wire <= (mux_address((ROW_WIDTH*2)-1 downto ROW_WIDTH) &
1692 mux_bank((BANK_WIDTH*2)-1 downto BANK_WIDTH) &
1693 mux_cas_n(1) & mux_ras_n(1) & mux_we_n(1));
1694
1695 process (clk)
1696 begin
1697 if (clk'event and clk='1') then
1698 parity(0) <= ODD_PARITY(parity_2_wire) after (TCQ) * 1 ps;
1699 end if;
1700 end process;
1701
1702 process(mux_address, mux_bank, mux_cas_n, mux_ras_n, mux_we_n)
1703 begin
1704 parity(1) <= ODD_PARITY(parity_1_wire) after (TCQ) * 1 ps;
1705 end process;
1706 end generate;
1707 end generate;
1708
1709 gen_ddr3_noparity : if (not(DRAM_TYPE = "DDR3") or not(REG_CTRL = "ON")) generate
1710 gen_ddr3_noparity_4by1 : if (nCK_PER_CLK = 4) generate
1711 process (clk)
1712 begin
1713 if (clk'event and clk='1') then
1714 parity(0) <= '0' after (TCQ)*1 ps;
1715 parity(1) <= '0' after (TCQ)*1 ps;
1716 parity(2) <= '0' after (TCQ)*1 ps;
1717 parity(3) <= '0' after (TCQ)*1 ps;
1718 end if;
1719 end process;
1720 end generate;
1721
1722 gen_ddr3_noparity_2by1 : if (not(nCK_PER_CLK = 4)) generate
1723 process (clk)
1724 begin
1725 if (clk'event and clk='1') then
1726 parity(0) <= '0' after (TCQ)*1 ps;
1727 parity(1) <= '0' after (TCQ)*1 ps;
1728 end if;
1729 end process;
1730 end generate;
1731
1732 end generate;
1733
1734 --***************************************************************************
1735 -- Code for optional register stage in read path to MC for timing
1736 --***************************************************************************
1737 RD_REG_TIMING : if(RD_PATH_REG = 1) generate
1738 process (clk)
1739 begin
1740 if (clk'event and clk='1') then
1741 rddata_valid_reg <= phy_rddata_valid_w after (TCQ)*1 ps;
1742 rd_data_reg <= rd_data_map after (TCQ)*1 ps;
1743 end if;
1744 end process;
1745 end generate;
1746
1747 RD_REG_NO_TIMING : if( not(RD_PATH_REG = 1)) generate
1748 process (phy_rddata_valid_w, rd_data_map)
1749 begin
1750 rddata_valid_reg <= phy_rddata_valid_w;
1751 rd_data_reg <= rd_data_map;
1752 end process;
1753 end generate;
1754
1755 phy_rddata_valid <= rddata_valid_reg;
1756 phy_rd_data <= rd_data_reg;
1757
1758 --***************************************************************************
1759 -- Hard PHY and accompanying bit mapping logic
1760 --***************************************************************************
1761
1762 phy_ctl_wd_i <= ("00000" & mux_cas_slot & calib_seq & mux_data_offset &
1763 mux_rank_cnt & "000" & aux_out_map & "00000" & mux_cmd);
1764
1765 u_ddr_mc_phy_wrapper : mig_7series_v4_2_ddr_mc_phy_wrapper
1766 generic map (
1767 TCQ => TCQ,
1768 tCK => tCK,
1769 BANK_TYPE => BANK_TYPE,
1770 DATA_IO_PRIM_TYPE => DATA_IO_PRIM_TYPE,
1771 IODELAY_GRP => IODELAY_GRP,
1772 FPGA_SPEED_GRADE => FPGA_SPEED_GRADE,
1773 DATA_IO_IDLE_PWRDWN=> DATA_IO_IDLE_PWRDWN,
1774 nCK_PER_CLK => nCK_PER_CLK,
1775 nCS_PER_RANK => nCS_PER_RANK,
1776 BANK_WIDTH => BANK_WIDTH,
1777 CKE_WIDTH => CKE_WIDTH,
1778 CS_WIDTH => CS_WIDTH,
1779 CK_WIDTH => CK_WIDTH,
1780 CWL => CWL,
1781 DDR2_DQSN_ENABLE => DDR2_DQSN_ENABLE,
1782 DM_WIDTH => DM_WIDTH,
1783 DQ_WIDTH => DQ_WIDTH,
1784 DQS_CNT_WIDTH => DQS_CNT_WIDTH,
1785 DQS_WIDTH => DQS_WIDTH,
1786 DRAM_TYPE => DRAM_TYPE,
1787 RANKS => RANKS,
1788 ODT_WIDTH => ODT_WIDTH,
1789 REG_CTRL => REG_CTRL,
1790 ROW_WIDTH => ROW_WIDTH,
1791 USE_CS_PORT => USE_CS_PORT,
1792 USE_DM_PORT => USE_DM_PORT,
1793 USE_ODT_PORT => USE_ODT_PORT,
1794 IBUF_LPWR_MODE => IBUF_LPWR_MODE,
1795 LP_DDR_CK_WIDTH => LP_DDR_CK_WIDTH,
1796 PHYCTL_CMD_FIFO => PHYCTL_CMD_FIFO,
1797 DATA_CTL_B0 => DATA_CTL_B0,
1798 DATA_CTL_B1 => DATA_CTL_B1,
1799 DATA_CTL_B2 => DATA_CTL_B2,
1800 DATA_CTL_B3 => DATA_CTL_B3,
1801 DATA_CTL_B4 => DATA_CTL_B4,
1802 BYTE_LANES_B0 => BYTE_LANES_B0,
1803 BYTE_LANES_B1 => BYTE_LANES_B1,
1804 BYTE_LANES_B2 => BYTE_LANES_B2,
1805 BYTE_LANES_B3 => BYTE_LANES_B3,
1806 BYTE_LANES_B4 => BYTE_LANES_B4,
1807 PHY_0_BITLANES => PHY_0_BITLANES,
1808 PHY_1_BITLANES => PHY_1_BITLANES,
1809 PHY_2_BITLANES => PHY_2_BITLANES,
1810 HIGHEST_BANK => HIGHEST_BANK,
1811 HIGHEST_LANE => HIGHEST_LANE,
1812 CK_BYTE_MAP => CK_BYTE_MAP,
1813 ADDR_MAP => ADDR_MAP,
1814 BANK_MAP => BANK_MAP,
1815 CAS_MAP => CAS_MAP,
1816 CKE_ODT_BYTE_MAP => CKE_ODT_BYTE_MAP,
1817 CKE_MAP => CKE_MAP,
1818 ODT_MAP => ODT_MAP,
1819 CKE_ODT_AUX => CKE_ODT_AUX,
1820 CS_MAP => CS_MAP,
1821 PARITY_MAP => PARITY_MAP,
1822 RAS_MAP => RAS_MAP,
1823 WE_MAP => WE_MAP,
1824 DQS_BYTE_MAP => DQS_BYTE_MAP,
1825 DATA0_MAP => DATA0_MAP,
1826 DATA1_MAP => DATA1_MAP,
1827 DATA2_MAP => DATA2_MAP,
1828 DATA3_MAP => DATA3_MAP,
1829 DATA4_MAP => DATA4_MAP,
1830 DATA5_MAP => DATA5_MAP,
1831 DATA6_MAP => DATA6_MAP,
1832 DATA7_MAP => DATA7_MAP,
1833 DATA8_MAP => DATA8_MAP,
1834 DATA9_MAP => DATA9_MAP,
1835 DATA10_MAP => DATA10_MAP,
1836 DATA11_MAP => DATA11_MAP,
1837 DATA12_MAP => DATA12_MAP,
1838 DATA13_MAP => DATA13_MAP,
1839 DATA14_MAP => DATA14_MAP,
1840 DATA15_MAP => DATA15_MAP,
1841 DATA16_MAP => DATA16_MAP,
1842 DATA17_MAP => DATA17_MAP,
1843 MASK0_MAP => MASK0_MAP,
1844 MASK1_MAP => MASK1_MAP,
1845 SIM_CAL_OPTION => SIM_CAL_OPTION,
1846 MASTER_PHY_CTL => MASTER_PHY_CTL,
1847 DRAM_WIDTH => DRAM_WIDTH,
1848 POC_USE_METASTABLE_SAMP => POC_USE_METASTABLE_SAMP,
1849 PI_DIV2_INCDEC => PI_DIV2_INCDEC
1850 )
1851 port map (
1852 rst => rst,
1853 iddr_rst => iddr_rst,
1854 clk => clk,
1855 clk_div2 => clk_div2,
1856 -- For memory frequencies between 400~1066 MHz freq_refclk = mem_refclk
1857 -- For memory frequencies below 400 MHz mem_refclk = mem_refclk and
1858 -- freq_refclk = 2x or 4x mem_refclk such that it remains in the
1859 -- 400~1066 MHz range
1860 freq_refclk => freq_refclk,
1861 mem_refclk => mem_refclk,
1862 pll_lock => pll_lock,
1863 sync_pulse => sync_pulse,
1864 mmcm_ps_clk => mmcm_ps_clk,
1865 idelayctrl_refclk => clk_ref,
1866 phy_cmd_wr_en => mux_cmd_wren,
1867 phy_data_wr_en => mux_wrdata_en,
1868 -- phy_ctl_wd = {ACTPRE[31:30],EventDelay[29:25],seq[24:23],
1869 -- DataOffset[22:17],HiIndex[16:15],LowIndex[14:12],
1870 -- AuxOut[11:8],ControlOffset[7:3],PHYCmd[2:0]}
1871 -- The fields ACTPRE, and BankCount are only used
1872 -- when the hard PHY counters are used by the MC.
1873 phy_ctl_wd => phy_ctl_wd_i,
1874 phy_ctl_wr => mux_ctl_wren,
1875 phy_if_empty_def => phy_if_empty_def,
1876 phy_if_reset => phy_if_reset,
1877 data_offset_1 => mux_data_offset_1,
1878 data_offset_2 => mux_data_offset_2,
1879 aux_in_1 => aux_out_map,
1880 aux_in_2 => aux_out_map,
1881 idelaye2_init_val => idelaye2_init_val,
1882 oclkdelay_init_val => oclkdelay_init_val,
1883 if_empty => if_empty,
1884 phy_ctl_full => phy_ctl_full,
1885 phy_cmd_full => phy_cmd_full,
1886 phy_data_full => phy_data_full,
1887 phy_pre_data_a_full => phy_pre_data_a_full,
1888 ddr_clk => ddr_clk,
1889 phy_mc_go => phy_mc_go,
1890 phy_write_calib => phy_write_calib,
1891 phy_read_calib => phy_read_calib,
1892 calib_in_common => calib_in_common,
1893 calib_sel => calib_sel,
1894 calib_zero_inputs => calib_zero_inputs,
1895 calib_zero_ctrl => calib_zero_ctrl,
1896 po_fine_enable => po_enstg2_f,
1897 po_coarse_enable => po_enstg2_c,
1898 po_fine_inc => po_stg2_fincdec,
1899 po_coarse_inc => po_stg2_cincdec,
1900 po_counter_load_en => po_counter_load_en,
1901 po_counter_read_en => '1',
1902 po_sel_fine_oclk_delay => po_sel_stg2stg3,
1903 po_counter_load_val => all_zeros,
1904 po_counter_read_val => po_counter_read_val,
1905 pi_counter_read_val => pi_counter_read_val,
1906 pi_rst_dqs_find => pi_rst_dqs_find,
1907 pi_fine_enable => pi_fine_enable,
1908 pi_fine_inc => pi_fine_inc,
1909 pi_counter_load_en => pi_counter_load_en,
1910 pi_counter_load_val => pi_counter_load_val,
1911 idelay_ce => idelay_ce,
1912 idelay_inc => idelay_inc,
1913 idelay_ld => idelay_ld,
1914 idle => idle,
1915 pi_phase_locked => pi_phase_locked,
1916 pi_phase_locked_all => pi_phase_locked_all,
1917 pi_dqs_found => pi_found_dqs,
1918 pi_dqs_found_all => pi_dqs_found_all,
1919 -- Currently not being used. May be used in future if periodic reads
1920 -- become a requirement. This output could also be used to signal a
1921 -- catastrophic failure in read capture and the need for re-cal
1922 pi_dqs_out_of_range => pi_dqs_out_of_range,
1923 phy_init_data_sel => phy_init_data_sel,
1924 mux_address => mux_address,
1925 mux_bank => mux_bank,
1926 mux_cas_n => mux_cas_n,
1927 mux_cs_n => mux_cs_n,
1928 mux_ras_n => mux_ras_n,
1929 mux_odt => mux_odt,
1930 mux_cke => mux_cke,
1931 mux_we_n => mux_we_n,
1932 parity_in => parity,
1933 mux_wrdata => mux_wrdata,
1934 mux_wrdata_mask => mux_wrdata_mask,
1935 mux_reset_n => mux_reset_n,
1936 rd_data => rd_data_map,
1937 ddr_addr => ddr_addr,
1938 ddr_ba => ddr_ba,
1939 ddr_cas_n => ddr_cas_n,
1940 ddr_cke => ddr_cke,
1941 ddr_cs_n => ddr_cs_n,
1942 ddr_dm => ddr_dm,
1943 ddr_odt => ddr_odt,
1944 ddr_parity => ddr_parity,
1945 ddr_ras_n => ddr_ras_n,
1946 ddr_we_n => ddr_we_n,
1947 ddr_reset_n => ddr_reset_n,
1948 ddr_dq => ddr_dq,
1949 ddr_dqs => ddr_dqs,
1950 ddr_dqs_n => ddr_dqs_n,
1951 dbg_pi_counter_read_en => '1',
1952 ref_dll_lock => ref_dll_lock,
1953 rst_phaser_ref => rst_phaser_ref,
1954 dbg_pi_phase_locked_phy4lanes => dbg_pi_phase_locked_phy4lanes,
1955 dbg_pi_dqs_found_lanes_phy4lanes => dbg_pi_dqs_found_lanes_phy4lanes_i,
1956 byte_sel_cnt => byte_sel_cnt,
1957 fine_delay_incdec_pb => fine_delay_incdec_pb,
1958 fine_delay_sel => fine_delay_sel,
1959 pd_out => pd_out
1960 );
1961
1962 --***************************************************************************
1963 -- Soft memory initialization and calibration logic
1964 --***************************************************************************
1965
1966 u_ddr_calib_top : mig_7series_v4_2_ddr_calib_top
1967 generic map (
1968 TCQ => TCQ,
1969 DDR3_VDD_OP_VOLT => DDR3_VDD_OP_VOLT,
1970 nCK_PER_CLK => nCK_PER_CLK,
1971 tCK => tCK,
1972 CLK_PERIOD => CLK_PERIOD,
1973 N_CTL_LANES => N_CTL_LANES,
1974 DRAM_TYPE => DRAM_TYPE,
1975 PRBS_WIDTH => 8,
1976 HIGHEST_LANE => HIGHEST_LANE,
1977 HIGHEST_BANK => HIGHEST_BANK,
1978 BANK_TYPE => BANK_TYPE,
1979 BYTE_LANES_B0 => BYTE_LANES_B0,
1980 BYTE_LANES_B1 => BYTE_LANES_B1,
1981 BYTE_LANES_B2 => BYTE_LANES_B2,
1982 BYTE_LANES_B3 => BYTE_LANES_B3,
1983 BYTE_LANES_B4 => BYTE_LANES_B4,
1984 DATA_CTL_B0 => DATA_CTL_B0,
1985 DATA_CTL_B1 => DATA_CTL_B1,
1986 DATA_CTL_B2 => DATA_CTL_B2,
1987 DATA_CTL_B3 => DATA_CTL_B3,
1988 DATA_CTL_B4 => DATA_CTL_B4,
1989 DQS_BYTE_MAP => DQS_BYTE_MAP,
1990 CTL_BYTE_LANE => CTL_BYTE_LANE,
1991 CTL_BANK => CTL_BANK,
1992 SLOT_1_CONFIG => SLOT_1_CONFIG,
1993 BANK_WIDTH => BANK_WIDTH,
1994 CA_MIRROR => CA_MIRROR,
1995 COL_WIDTH => COL_WIDTH,
1996 nCS_PER_RANK => nCS_PER_RANK,
1997 DQ_WIDTH => DQ_WIDTH,
1998 DQS_CNT_WIDTH => DQS_CNT_WIDTH,
1999 DQS_WIDTH => DQS_WIDTH,
2000 DRAM_WIDTH => DRAM_WIDTH,
2001 ROW_WIDTH => ROW_WIDTH,
2002 RANKS => RANKS,
2003 CS_WIDTH => CS_WIDTH,
2004 CKE_WIDTH => CKE_WIDTH,
2005 DDR2_DQSN_ENABLE => DDR2_DQSN_ENABLE,
2006 PER_BIT_DESKEW => "OFF",
2007 CALIB_ROW_ADD => CALIB_ROW_ADD,
2008 CALIB_COL_ADD => CALIB_COL_ADD,
2009 CALIB_BA_ADD => CALIB_BA_ADD,
2010 AL => AL,
2011 ADDR_CMD_MODE => ADDR_CMD_MODE,
2012 BURST_MODE => BURST_MODE,
2013 BURST_TYPE => BURST_TYPE,
2014 nCL => CL,
2015 nCWL => CWL,
2016 tRFC => tRFC,
2017 tREFI => tREFI,
2018 OUTPUT_DRV => OUTPUT_DRV,
2019 REG_CTRL => REG_CTRL,
2020 RTT_NOM => RTT_NOM,
2021 RTT_WR => RTT_WR,
2022 USE_ODT_PORT => USE_ODT_PORT,
2023 WRLVL => WRLVL_W,
2024 PRE_REV3ES => PRE_REV3ES,
2025 SIM_INIT_OPTION => SIM_INIT_OPTION,
2026 SIM_CAL_OPTION => SIM_CAL_OPTION,
2027 CKE_ODT_AUX => CKE_ODT_AUX,
2028 DEBUG_PORT => DEBUG_PORT,
2029 IDELAY_ADJ => IDELAY_ADJ,
2030 FINE_PER_BIT => FINE_PER_BIT,
2031 CENTER_COMP_MODE => CENTER_COMP_MODE,
2032 PI_VAL_ADJ => PI_VAL_ADJ,
2033 TAPSPERKCLK => TAPSPERKCLK,
2034 SKIP_CALIB => SKIP_CALIB,
2035 POC_USE_METASTABLE_SAMP => POC_USE_METASTABLE_SAMP,
2036 PI_DIV2_INCDEC => PI_DIV2_INCDEC
2037 )
2038 port map (
2039 clk => clk,
2040 rst => rst,
2041
2042 slot_0_present => slot_0_present,
2043 slot_1_present => slot_1_present,
2044 -- PHY Control Block and IN_FIFO status
2045 phy_ctl_ready => phy_mc_go,
2046 phy_ctl_full => '0',
2047 phy_cmd_full => '0',
2048 phy_data_full => '0',
2049 -- hard PHY calibration modes
2050 write_calib => phy_write_calib,
2051 read_calib => phy_read_calib,
2052 -- Signals from calib logic to be MUXED with MC
2053 -- signals before sending to hard PHY
2054 calib_ctl_wren => calib_ctl_wren,
2055 calib_cmd_wren => calib_cmd_wren,
2056 calib_seq => calib_seq,
2057 calib_aux_out => calib_aux_out,
2058 calib_odt => calib_odt,
2059 calib_cke => calib_cke,
2060 calib_cmd => calib_cmd,
2061 calib_wrdata_en => calib_wrdata_en,
2062 calib_rank_cnt => calib_rank_cnt,
2063 calib_cas_slot => calib_cas_slot,
2064 calib_data_offset_0 => calib_data_offset_0,
2065 calib_data_offset_1 => calib_data_offset_1,
2066 calib_data_offset_2 => calib_data_offset_2,
2067 phy_address => phy_address,
2068 phy_bank => phy_bank,
2069 phy_cs_n => phy_cs_n,
2070 phy_ras_n => phy_ras_n,
2071 phy_cas_n => phy_cas_n,
2072 phy_we_n => phy_we_n,
2073 phy_reset_n => phy_reset_n,
2074 -- DQS count and ck/addr/cmd to be mapped to calib_sel
2075 -- based on parameter that defines placement of ctl lanes
2076 -- and DQS byte groups in each bank. When phy_write_calib
2077 -- is de-asserted calib_sel should select CK/addr/cmd/ctl.
2078 calib_sel => calib_sel,
2079 calib_in_common => calib_in_common,
2080 calib_zero_inputs => calib_zero_inputs,
2081 calib_zero_ctrl => calib_zero_ctrl,
2082 phy_if_empty_def => phy_if_empty_def,
2083 phy_if_reset => phy_if_reset,
2084 -- DQS Phaser_IN calibration/status signals
2085 pi_phaselocked => pi_phase_locked,
2086 pi_phase_locked_all => pi_phase_locked_all,
2087 pi_found_dqs => pi_found_dqs,
2088 pi_dqs_found_all => pi_dqs_found_all,
2089 pi_dqs_found_lanes => dbg_pi_dqs_found_lanes_phy4lanes_i(HIGHEST_LANE-1 downto 0),
2090 pi_rst_stg1_cal => rst_stg1_cal,
2091 pi_en_stg2_f => pi_enstg2_f,
2092 pi_stg2_f_incdec => pi_stg2_fincdec,
2093 pi_stg2_load => pi_stg2_load,
2094 pi_stg2_reg_l => pi_stg2_reg_l,
2095 pi_counter_read_val => pi_counter_read_val,
2096 device_temp => device_temp,
2097 tempmon_sample_en => tempmon_sample_en,
2098 -- IDELAY tap enable and inc signals
2099 idelay_ce => idelay_ce,
2100 idelay_inc => idelay_inc,
2101 idelay_ld => idelay_ld,
2102 -- DQS Phaser_OUT calibration/status signals
2103 po_sel_stg2stg3 => po_sel_stg2stg3,
2104 po_stg2_c_incdec => po_stg2_cincdec,
2105 po_en_stg2_c => po_enstg2_c,
2106 po_stg2_f_incdec => po_stg2_fincdec,
2107 po_en_stg2_f => po_enstg2_f,
2108 po_counter_load_en => po_counter_load_en,
2109 po_counter_read_val => po_counter_read_val,
2110 phy_if_empty => if_empty,
2111 idelaye2_init_val => idelaye2_init_val,
2112 oclkdelay_init_val => oclkdelay_init_val,
2113 tg_err => error,
2114 rst_tg_mc => rst_tg_mc,
2115 phy_wrdata => phy_wrdata,
2116 -- From calib logic To data IN_FIFO
2117 -- DQ IDELAY tap value from Calib logic
2118 -- port to be added to mc_phy by Gary
2119 dlyval_dq => open,
2120 -- From data IN_FIFO To Calib logic and MC/UI
2121 phy_rddata => rd_data_map,
2122 -- From calib logic To MC
2123 phy_rddata_valid => phy_rddata_valid_w,
2124 calib_rd_data_offset_0 => calib_rd_data_offset_i0,
2125 calib_rd_data_offset_1 => calib_rd_data_offset_1,
2126 calib_rd_data_offset_2 => calib_rd_data_offset_2,
2127 calib_writes => open,
2128 -- Mem Init and Calibration status To MC
2129 init_calib_complete => phy_init_data_sel,
2130 init_wrcal_complete => init_wrcal_complete_i,
2131 -- Debug Error signals
2132 pi_phase_locked_err => dbg_pi_phaselock_err,
2133 pi_dqsfound_err => dbg_pi_dqsfound_err,
2134 wrcal_err => dbg_wrcal_err,
2135 -- MMCM phase shift clock control
2136 psen => psen,
2137 psincdec => psincdec,
2138 psdone => psdone,
2139 poc_sample_pd => poc_sample_pd,
2140 -- skip calibration
2141 calib_tap_req => calib_tap_req,
2142 calib_tap_load => calib_tap_load,
2143 calib_tap_addr => calib_tap_addr,
2144 calib_tap_val => calib_tap_val,
2145 calib_tap_load_done => calib_tap_load_done,
2146 -- Debug Signals
2147 dbg_pi_phaselock_start => dbg_pi_phaselock_start,
2148 dbg_pi_dqsfound_start => dbg_pi_dqsfound_start,
2149 dbg_pi_dqsfound_done => dbg_pi_dqsfound_done,
2150 dbg_wrcal_start => dbg_wrcal_start,
2151 dbg_wrcal_done => dbg_wrcal_done,
2152 dbg_wrlvl_start => dbg_wrlvl_start,
2153 dbg_wrlvl_done => dbg_wrlvl_done,
2154 dbg_wrlvl_err => dbg_wrlvl_err,
2155 dbg_wrlvl_fine_tap_cnt => dbg_wrlvl_fine_tap_cnt,
2156 dbg_wrlvl_coarse_tap_cnt => dbg_wrlvl_coarse_tap_cnt,
2157 dbg_phy_wrlvl => dbg_phy_wrlvl,
2158 dbg_tap_cnt_during_wrlvl => dbg_tap_cnt_during_wrlvl,
2159 dbg_wl_edge_detect_valid => dbg_wl_edge_detect_valid,
2160 dbg_rd_data_edge_detect => dbg_rd_data_edge_detect,
2161 dbg_final_po_fine_tap_cnt => dbg_final_po_fine_tap_cnt,
2162 dbg_final_po_coarse_tap_cnt => dbg_final_po_coarse_tap_cnt,
2163 dbg_phy_wrcal => dbg_phy_wrcal,
2164 dbg_rdlvl_start => dbg_rdlvl_start,
2165 dbg_rdlvl_done => dbg_rdlvl_done,
2166 dbg_rdlvl_err => dbg_rdlvl_err,
2167 dbg_cpt_first_edge_cnt => dbg_cpt_first_edge_cnt,
2168 dbg_cpt_second_edge_cnt => dbg_cpt_second_edge_cnt,
2169 dbg_cpt_tap_cnt => dbg_cpt_tap_cnt,
2170 dbg_dq_idelay_tap_cnt => dbg_dq_idelay_tap_cnt,
2171 dbg_sel_pi_incdec => dbg_sel_pi_incdec,
2172 dbg_sel_po_incdec => dbg_sel_po_incdec,
2173 dbg_byte_sel => dbg_byte_sel,
2174 dbg_pi_f_inc => dbg_pi_f_inc,
2175 dbg_pi_f_dec => dbg_pi_f_dec,
2176 dbg_po_f_inc => dbg_po_f_inc,
2177 dbg_po_f_stg23_sel => dbg_po_f_stg23_sel,
2178 dbg_po_f_dec => dbg_po_f_dec,
2179 dbg_idel_up_all => dbg_idel_up_all,
2180 dbg_idel_down_all => dbg_idel_down_all,
2181 dbg_idel_up_cpt => dbg_idel_up_cpt,
2182 dbg_idel_down_cpt => dbg_idel_down_cpt,
2183 dbg_sel_idel_cpt => dbg_sel_idel_cpt,
2184 dbg_sel_all_idel_cpt => dbg_sel_all_idel_cpt,
2185 dbg_phy_rdlvl => dbg_phy_rdlvl,
2186 dbg_calib_top => dbg_calib_top,
2187 dbg_phy_init => dbg_phy_init,
2188 dbg_prbs_rdlvl => dbg_prbs_rdlvl,
2189 dbg_dqs_found_cal => dbg_dqs_found_cal,
2190 dbg_phy_oclkdelay_cal => dbg_phy_oclkdelay_cal,
2191 dbg_oclkdelay_rd_data => dbg_oclkdelay_rd_data,
2192 dbg_oclkdelay_calib_start => dbg_oclkdelay_calib_start,
2193 dbg_oclkdelay_calib_done => dbg_oclkdelay_calib_done,
2194 dbg_poc => dbg_poc,
2195 prbs_final_dqs_tap_cnt_r => prbs_final_dqs_tap_cnt_r,
2196 dbg_prbs_first_edge_taps => dbg_prbs_first_edge_taps,
2197 dbg_prbs_second_edge_taps => dbg_prbs_second_edge_taps,
2198 byte_sel_cnt => byte_sel_cnt,
2199 fine_delay_incdec_pb => fine_delay_incdec_pb,
2200 fine_delay_sel => fine_delay_sel,
2201 pd_out => pd_out
2202 );
2203
2204end architecture arch_ddr_phy_top;
2205
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top
Definition: mig_7series_v4_2_ddr_phy_top.vhd:371
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.po_counter_read_val
std_logic_vector( 8 downto 0) po_counter_read_val
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1332
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_if_empty_def
std_logic phy_if_empty_def
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1378
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_data_offset_2
std_logic_vector( 5 downto 0) mux_data_offset_2
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1367
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_cas_slot
std_logic_vector( 1 downto 0) mux_cas_slot
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1364
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.rst_stg1_cal_div2r2
std_logic_vector( HIGHEST_BANK- 1 downto 0) rst_stg1_cal_div2r2
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1422
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_dqs_found_all
std_logic pi_dqs_found_all
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1318
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_bank
std_logic_vector( nCK_PER_CLK* BANK_WIDTH- 1 downto 0) mux_bank
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1359
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.po_enstg2_c
std_logic_vector( 2 downto 0) po_enstg2_c
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1329
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.CTL_BYTE_LANE
std_logic_vector( 7 downto 0) := CTL_BYTE_LANE_W CTL_BYTE_LANE
Definition: mig_7series_v4_2_ddr_phy_top.vhd:877
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.SIM_CAL_OPTION
string := SIM_CAL_OPTION_W SIM_CAL_OPTION
Definition: mig_7series_v4_2_ddr_phy_top.vhd:706
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_cas_n
std_logic_vector( nCK_PER_CLK- 1 downto 0) mux_cas_n
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1369
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_load_div2r2
std_logic pi_stg2_load_div2r2
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1419
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_sel
std_logic_vector( 5 downto 0) calib_sel
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1311
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_ctl_wd_i
std_logic_vector( 31 downto 0) phy_ctl_wd_i
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1392
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_din
std_logic_vector( HIGHEST_LANE* 80- 1 downto 0) phy_din
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1297
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_load
std_logic pi_stg2_load
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1322
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.OR_BR
std_logic OR_BRinp_var,
Definition: mig_7series_v4_2_ddr_phy_top.vhd:374
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_dout
std_logic_vector( HIGHEST_LANE* 80- 1 downto 0) phy_dout
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1298
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_cmd_full
std_logic phy_cmd_full
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1304
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_pre_data_a_full
std_logic phy_pre_data_a_full
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1306
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_fincdec_div2r3
std_logic pi_stg2_fincdec_div2r3
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1417
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.idelaye2_init_val
std_logic_vector( 4 downto 0) idelaye2_init_val
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1385
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.parity_1_wire
std_logic_vector(( ROW_WIDTH+ BANK_WIDTH+ 3)- 1 downto 0) parity_1_wire
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1395
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_wrdata_en
std_logic calib_wrdata_en
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1348
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.parity
std_logic_vector( nCK_PER_CLK- 1 downto 0) parity
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1335
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.dbg_pi_dqs_found_lanes_phy4lanes_i
std_logic_vector( 11 downto 0) dbg_pi_dqs_found_lanes_phy4lanes_i
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1398
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_cas_n
std_logic_vector( nCK_PER_CLK- 1 downto 0) phy_cas_n
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1340
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_wrdata_mask
std_logic_vector( 2* nCK_PER_CLK*( DQ_WIDTH/ 8)- 1 downto 0) mux_wrdata_mask
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1374
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_zero_ctrl
std_logic_vector( HIGHEST_BANK- 1 downto 0) calib_zero_ctrl
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1314
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.nSLOTS
integer := CALC_nSLOTS nSLOTS
Definition: mig_7series_v4_2_ddr_phy_top.vhd:688
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_rst_dqs_find
std_logic_vector( HIGHEST_BANK- 1 downto 0) pi_rst_dqs_find
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1411
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_fincdec_div2r1
std_logic pi_stg2_fincdec_div2r1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1415
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_aux_out
std_logic_vector( 3 downto 0) mux_aux_out
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1357
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_read_calib
std_logic phy_read_calib
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1309
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_reg_l
std_logic_vector( 5 downto 0) pi_stg2_reg_l
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1323
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_fine_inc_r1
std_logic pi_stg2_fine_inc_r1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1451
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.fine_delay_sel
std_logic fine_delay_sel
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1403
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.rddata_valid_reg
std_logic rddata_valid_reg
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1383
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.po_enstg2_f
std_logic_vector( 2 downto 0) po_enstg2_f
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1331
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_dqs_find_rst
std_logic_vector( HIGHEST_BANK- 1 downto 0) pi_dqs_find_rst
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1426
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_counter_read_val
std_logic_vector( 5 downto 0) pi_counter_read_val
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1333
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_we_n
std_logic_vector( nCK_PER_CLK- 1 downto 0) phy_we_n
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1341
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_ras_n
std_logic_vector( nCK_PER_CLK- 1 downto 0) phy_ras_n
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1339
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_reg_l_div2r2
std_logic_vector( 5 downto 0) pi_stg2_reg_l_div2r2
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1424
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.parity_0_wire
std_logic_vector(( ROW_WIDTH+ BANK_WIDTH+ 3)- 1 downto 0) parity_0_wire
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1394
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.idelay_ce
std_logic idelay_ce
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1324
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_cke
std_logic_vector( nCK_PER_CLK- 1 downto 0) mux_cke
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1376
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_cas_slot
std_logic_vector( 1 downto 0) calib_cas_slot
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1355
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.init_wrcal_complete_i
std_logic init_wrcal_complete_i
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1391
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.HIGHEST_LANE
integer := HIGHEST_LANE_W HIGHEST_LANE
Definition: mig_7series_v4_2_ddr_phy_top.vhd:717
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_reg_l_div2r1
std_logic_vector( 5 downto 0) pi_stg2_reg_l_div2r1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1423
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_rddata_valid_w
std_logic phy_rddata_valid_w
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1382
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_fincdec
std_logic pi_stg2_fincdec
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1321
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_init_data_sel
std_logic phy_init_data_sel
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1380
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_data_offset_2
std_logic_vector( 5 downto 0) calib_data_offset_2
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1353
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_reg_l_div2r3
std_logic_vector( 5 downto 0) pi_stg2_reg_l_div2r3
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1425
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_ctl_full
std_logic phy_ctl_full
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1303
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_load_div2r3
std_logic pi_stg2_load_div2r3
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1420
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.if_empty
std_logic if_empty
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1307
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.all_zeros
std_logic_vector( 8 downto 0) :=( others => '0') all_zeros
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1399
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.ODD_PARITY
std_logic ODD_PARITYinp_var,
Definition: mig_7series_v4_2_ddr_phy_top.vhd:678
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_ras_n
std_logic_vector( nCK_PER_CLK- 1 downto 0) mux_ras_n
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1368
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_cmd_wren
std_logic mux_cmd_wren
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1361
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_reset_n
std_logic mux_reset_n
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1371
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.HIGHEST_BANK
integer := HIGHEST_BANK_W HIGHEST_BANK
Definition: mig_7series_v4_2_ddr_phy_top.vhd:709
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_fine_enable_r1
std_logic pi_stg2_fine_enable_r1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1450
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.ASYNC_REG
string ASYNC_REG
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1428
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_ctl_wren
std_logic mux_ctl_wren
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1363
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.CTL_BANK
std_logic_vector( 2 downto 0) := CTL_BANK_W CTL_BANK
Definition: mig_7series_v4_2_ddr_phy_top.vhd:724
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_rank_cnt
std_logic_vector( 1 downto 0) mux_rank_cnt
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1370
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_rd_data_offset_i0
std_logic_vector( 6* RANKS- 1 downto 0) calib_rd_data_offset_i0
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1390
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_wrdata
std_logic_vector( 2* nCK_PER_CLK* DQ_WIDTH- 1 downto 0) mux_wrdata
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1373
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.oclkdelay_init_val
std_logic_vector( 5 downto 0) oclkdelay_init_val
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1386
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_enstg2_f
std_logic pi_enstg2_f
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1320
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_found_dqs
std_logic pi_found_dqs
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1317
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.rst_stg1_cal
std_logic_vector( HIGHEST_BANK- 1 downto 0) rst_stg1_cal
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1310
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_fine_inc
std_logic pi_fine_inc
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1408
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_load_div2r1
std_logic pi_stg2_load_div2r1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1418
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.parity_3_wire
std_logic_vector(( ROW_WIDTH+ BANK_WIDTH+ 3)- 1 downto 0) parity_3_wire
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1397
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_cs_n
std_logic_vector( CS_WIDTH* nCS_PER_RANK* nCK_PER_CLK- 1 downto 0) mux_cs_n
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1362
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_in_common
std_logic calib_in_common
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1312
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_reset_n
std_logic phy_reset_n
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1342
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_fine_enable
std_logic pi_fine_enable
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1407
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.WRLVL_W
string := CALC_WRLVL_W WRLVL_W
Definition: mig_7series_v4_2_ddr_phy_top.vhd:707
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_odt
std_logic_vector( 1 downto 0) mux_odt
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1377
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.fine_delay_incdec_pb
std_logic_vector( DRAM_WIDTH- 1 downto 0) fine_delay_incdec_pb
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1402
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_odt
std_logic_vector( 1 downto 0) calib_odt
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1345
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_load_en
std_logic pi_stg2_load_en
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1452
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.po_stg2_cincdec
std_logic_vector( 2 downto 0) po_stg2_cincdec
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1328
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_load_val
std_logic_vector( 5 downto 0) pi_stg2_load_val
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1453
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_address
std_logic_vector( nCK_PER_CLK* ROW_WIDTH- 1 downto 0) phy_address
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1336
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_address
std_logic_vector( nCK_PER_CLK* ROW_WIDTH- 1 downto 0) mux_address
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1356
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_cmd
std_logic_vector( 2 downto 0) mux_cmd
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1360
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.ddr_cmd_ctl_data
std_logic_vector( HIGHEST_LANE* 12- 1 downto 0) ddr_cmd_ctl_data
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1299
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_fincdec_div2r2
std_logic pi_stg2_fincdec_div2r2
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1416
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.PI_DIV2_INCDEC
string := PI_DIV2_INCDEC_FUN PI_DIV2_INCDEC
Definition: mig_7series_v4_2_ddr_phy_top.vhd:890
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.idelay_inc
std_logic idelay_inc
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1325
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.po_stg2_fincdec
std_logic_vector( 2 downto 0) po_stg2_fincdec
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1330
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.ddr_clk
std_logic_vector( CK_WIDTH* LP_DDR_CK_WIDTH- 1 downto 0) ddr_clk
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1301
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_enstg2_f_div2r2
std_logic pi_enstg2_f_div2r2
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1413
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_ctl_wren
std_logic calib_ctl_wren
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1346
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_rank_cnt
std_logic_vector( 1 downto 0) calib_rank_cnt
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1354
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_counter_load_val
std_logic_vector( 5 downto 0) pi_counter_load_val
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1410
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mc_cs_n_temp
std_logic_vector( CS_WIDTH* nCS_PER_RANK* nCK_PER_CLK- 1 downto 0) mc_cs_n_temp
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1388
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_seq
std_logic_vector( 1 downto 0) calib_seq
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1350
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_data_offset_0
std_logic_vector( 5 downto 0) calib_data_offset_0
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1351
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_aux_out
std_logic_vector( 3 downto 0) calib_aux_out
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1343
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_bank
std_logic_vector( nCK_PER_CLK* BANK_WIDTH- 1 downto 0) phy_bank
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1337
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.SIM_INIT_OPTION
string := SIM_INIT_OPTION_W SIM_INIT_OPTION
Definition: mig_7series_v4_2_ddr_phy_top.vhd:705
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_phase_locked_all
std_logic pi_phase_locked_all
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1316
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_zero_inputs
std_logic_vector( HIGHEST_BANK- 1 downto 0) calib_zero_inputs
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1313
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.aux_out
std_logic_vector(((( HIGHEST_LANE+ 3)/ 4)* 4)- 1 downto 0) aux_out
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1300
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_cmd_wren
std_logic calib_cmd_wren
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1347
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.CLK_PERIOD
integer := tCK* nCK_PER_CLK CLK_PERIOD
Definition: mig_7series_v4_2_ddr_phy_top.vhd:689
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_fine_inc
std_logic pi_stg2_fine_inc
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1451
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_counter_load_en
std_logic pi_counter_load_en
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1409
u_ddr_mc_phy_wrapper
mig_7series_v4_2_ddr_mc_phy_wrapper u_ddr_mc_phy_wrapperu_ddr_mc_phy_wrapper
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1960
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.po_counter_load_en
std_logic po_counter_load_en
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1393
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.rd_data_map
std_logic_vector( 2* nCK_PER_CLK* DQ_WIDTH- 1 downto 0) rd_data_map
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1381
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_write_calib
std_logic phy_write_calib
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1308
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_data_offset
std_logic_vector( 5 downto 0) mux_data_offset
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1365
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.byte_sel_cnt
std_logic_vector( DQS_CNT_WIDTH downto 0) byte_sel_cnt
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1401
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_fine_enable
std_logic pi_stg2_fine_enable
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1450
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_data_offset_1
std_logic_vector( 5 downto 0) calib_data_offset_1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1352
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.po_sel_stg2stg3
std_logic_vector( 2 downto 0) po_sel_stg2stg3
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1327
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_phase_locked
std_logic pi_phase_locked
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1315
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_if_reset
std_logic phy_if_reset
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1379
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_wrdata_en
std_logic mux_wrdata_en
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1375
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.rd_data_reg
std_logic_vector( 2* nCK_PER_CLK* DQ_WIDTH- 1 downto 0) rd_data_reg
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1384
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_stg2_load_en_r1
std_logic pi_stg2_load_en_r1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1452
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_data_offset_1
std_logic_vector( 5 downto 0) mux_data_offset_1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1366
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_enstg2_f_div2r3
std_logic pi_enstg2_f_div2r3
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1414
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_cke
std_logic_vector( nCK_PER_CLK- 1 downto 0) calib_cke
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1344
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_wrdata
std_logic_vector( 2* nCK_PER_CLK* DQ_WIDTH- 1 downto 0) phy_wrdata
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1334
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.parity_2_wire
std_logic_vector(( ROW_WIDTH+ BANK_WIDTH+ 3)- 1 downto 0) parity_2_wire
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1396
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.idelay_ld
std_logic idelay_ld
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1326
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_mc_go
std_logic phy_mc_go
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1302
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.aux_out_map
std_logic_vector( 3 downto 0) aux_out_map
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1358
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_enstg2_f_div2r1
std_logic pi_enstg2_f_div2r1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1412
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.N_CTL_LANES
integer := N_CTL_LANES_B0+ N_CTL_LANES_B1+ N_CTL_LANES_B2+ N_CTL_LANES_B3+ N_CTL_LANES_B4 N_CTL_LANES
Definition: mig_7series_v4_2_ddr_phy_top.vhd:719
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pi_dqs_out_of_range
std_logic pi_dqs_out_of_range
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1319
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_data_full
std_logic phy_data_full
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1305
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.rst_stg1_cal_div2r1
std_logic_vector( HIGHEST_BANK- 1 downto 0) rst_stg1_cal_div2r1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1421
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.calib_cmd
std_logic_vector( 2 downto 0) calib_cmd
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1349
u_ddr_calib_top
mig_7series_v4_2_ddr_calib_top u_ddr_calib_topu_ddr_calib_top
Definition: mig_7series_v4_2_ddr_phy_top.vhd:2202
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.phy_cs_n
std_logic_vector( CS_WIDTH* nCS_PER_RANK* nCK_PER_CLK- 1 downto 0) phy_cs_n
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1338
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.mux_we_n
std_logic_vector( nCK_PER_CLK- 1 downto 0) mux_we_n
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1372
mig_7series_v4_2_ddr_phy_top.arch_ddr_phy_top.pd_out
std_logic pd_out
Definition: mig_7series_v4_2_ddr_phy_top.vhd:1404
mig_7series_v4_2_ddr_phy_top
Definition: mig_7series_v4_2_ddr_phy_top.vhd:73
mig_7series_v4_2_ddr_phy_top.BYTE_LANES_B4
BYTE_LANES_B4 std_logic_vector( 3 downto 0) := "0000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:112
mig_7series_v4_2_ddr_phy_top.FPGA_SPEED_GRADE
FPGA_SPEED_GRADE integer := 1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:166
mig_7series_v4_2_ddr_phy_top.psdone
in psdone std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:296
mig_7series_v4_2_ddr_phy_top.DQ_WIDTH
DQ_WIDTH integer := 64
Definition: mig_7series_v4_2_ddr_phy_top.vhd:90
mig_7series_v4_2_ddr_phy_top.PI_VAL_ADJ
PI_VAL_ADJ string := "ON"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:206
mig_7series_v4_2_ddr_phy_top.PRE_REV3ES
PRE_REV3ES string := "OFF"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:158
mig_7series_v4_2_ddr_phy_top.USE_ODT_PORT
USE_ODT_PORT integer := 1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:199
mig_7series_v4_2_ddr_phy_top.PHY_1_BITLANES
PHY_1_BITLANES std_logic_vector( 47 downto 0) := X"000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:116
mig_7series_v4_2_ddr_phy_top.tREFI
tREFI integer := 7800000
Definition: mig_7series_v4_2_ddr_phy_top.vhd:174
mig_7series_v4_2_ddr_phy_top.slot_1_present
in slot_1_present std_logic_vector( 7 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:249
mig_7series_v4_2_ddr_phy_top.LP_DDR_CK_WIDTH
LP_DDR_CK_WIDTH integer := 2
Definition: mig_7series_v4_2_ddr_phy_top.vhd:96
mig_7series_v4_2_ddr_phy_top.mc_cmd
in mc_cmd std_logic_vector( 2 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:265
mig_7series_v4_2_ddr_phy_top.mc_cke
in mc_cke std_logic_vector( nCK_PER_CLK- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:259
mig_7series_v4_2_ddr_phy_top.ddr_parity
out ddr_parity std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:288
mig_7series_v4_2_ddr_phy_top.TCQ
TCQ integer := 100
Definition: mig_7series_v4_2_ddr_phy_top.vhd:76
mig_7series_v4_2_ddr_phy_top.RAS_MAP
RAS_MAP std_logic_vector( 11 downto 0) := X"000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:130
mig_7series_v4_2_ddr_phy_top.BYTE_LANES_B1
BYTE_LANES_B1 std_logic_vector( 3 downto 0) := "0000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:109
mig_7series_v4_2_ddr_phy_top.DATA1_MAP
DATA1_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:135
mig_7series_v4_2_ddr_phy_top.mc_aux_out0
in mc_aux_out0 std_logic_vector( 3 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:261
mig_7series_v4_2_ddr_phy_top.TAPSPERKCLK
TAPSPERKCLK integer := 56
Definition: mig_7series_v4_2_ddr_phy_top.vhd:207
mig_7series_v4_2_ddr_phy_top.RANKS
RANKS integer := 4
Definition: mig_7series_v4_2_ddr_phy_top.vhd:178
mig_7series_v4_2_ddr_phy_top.SIM_BYPASS_INIT_CAL
SIM_BYPASS_INIT_CAL string := "OFF"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:188
mig_7series_v4_2_ddr_phy_top.dbg_po_counter_read_val
out dbg_po_counter_read_val std_logic_vector( 8 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:358
mig_7series_v4_2_ddr_phy_top.IBUF_LPWR_MODE
IBUF_LPWR_MODE string := "OFF"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:167
mig_7series_v4_2_ddr_phy_top.mmcm_ps_clk
in mmcm_ps_clk std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:224
mig_7series_v4_2_ddr_phy_top.dbg_rddata
out dbg_rddata std_logic_vector( 2* nCK_PER_CLK* DQ_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:313
mig_7series_v4_2_ddr_phy_top.dbg_sel_po_incdec
in dbg_sel_po_incdec std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:233
mig_7series_v4_2_ddr_phy_top.DQS_WIDTH
DQS_WIDTH integer := 8
Definition: mig_7series_v4_2_ddr_phy_top.vhd:92
mig_7series_v4_2_ddr_phy_top.pll_lock
in pll_lock std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:221
mig_7series_v4_2_ddr_phy_top.dbg_prbs_rdlvl
out dbg_prbs_rdlvl std_logic_vector( 255 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:355
mig_7series_v4_2_ddr_phy_top.ddr_cke
out ddr_cke std_logic_vector( CKE_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:282
mig_7series_v4_2_ddr_phy_top.mc_address
in mc_address std_logic_vector( nCK_PER_CLK* ROW_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:254
mig_7series_v4_2_ddr_phy_top.ddr_ck_n
out ddr_ck_n std_logic_vector( CK_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:280
mig_7series_v4_2_ddr_phy_top.DATA_CTL_B2
DATA_CTL_B2 std_logic_vector( 3 downto 0) := X"f"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:103
mig_7series_v4_2_ddr_phy_top.mc_cs_n
in mc_cs_n std_logic_vector( CS_WIDTH* nCS_PER_RANK* nCK_PER_CLK- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:256
mig_7series_v4_2_ddr_phy_top.IODELAY_GRP
IODELAY_GRP string := "IODELAY_MIG"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:165
mig_7series_v4_2_ddr_phy_top.BYTE_LANES_B2
BYTE_LANES_B2 std_logic_vector( 3 downto 0) := "0000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:110
mig_7series_v4_2_ddr_phy_top.dbg_idel_down_cpt
in dbg_idel_down_cpt std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:241
mig_7series_v4_2_ddr_phy_top.DATA_CTL_B4
DATA_CTL_B4 std_logic_vector( 3 downto 0) := X"f"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:105
mig_7series_v4_2_ddr_phy_top.ddr_dqs
inout ddr_dqs std_logic_vector( DQS_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:292
mig_7series_v4_2_ddr_phy_top.CWL
CWL integer := 5
Definition: mig_7series_v4_2_ddr_phy_top.vhd:88
mig_7series_v4_2_ddr_phy_top.dbg_byte_sel
in dbg_byte_sel std_logic_vector( DQS_CNT_WIDTH downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:234
mig_7series_v4_2_ddr_phy_top.mc_aux_out1
in mc_aux_out1 std_logic_vector( 3 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:262
mig_7series_v4_2_ddr_phy_top.rst_tg_mc
out rst_tg_mc std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:227
mig_7series_v4_2_ddr_phy_top.dbg_wrlvl_err
out dbg_wrlvl_err std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:321
mig_7series_v4_2_ddr_phy_top.DM_WIDTH
DM_WIDTH integer := 8
Definition: mig_7series_v4_2_ddr_phy_top.vhd:89
mig_7series_v4_2_ddr_phy_top.mc_bank
in mc_bank std_logic_vector( nCK_PER_CLK* BANK_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:255
mig_7series_v4_2_ddr_phy_top.ddr_reset_n
out ddr_reset_n std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:287
mig_7series_v4_2_ddr_phy_top.mc_we_n
in mc_we_n std_logic_vector( nCK_PER_CLK- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:253
mig_7series_v4_2_ddr_phy_top.DATA3_MAP
DATA3_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:137
mig_7series_v4_2_ddr_phy_top.device_temp
in device_temp std_logic_vector( 11 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:229
mig_7series_v4_2_ddr_phy_top.ddr_dm
out ddr_dm std_logic_vector( DM_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:284
mig_7series_v4_2_ddr_phy_top.BYTE_LANES_B0
BYTE_LANES_B0 std_logic_vector( 3 downto 0) := "1111"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:108
mig_7series_v4_2_ddr_phy_top.dbg_cpt_tap_cnt
out dbg_cpt_tap_cnt std_logic_vector( 6* DQS_WIDTH* RANKS- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:306
mig_7series_v4_2_ddr_phy_top.rst_div2
in rst_div2 std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:216
mig_7series_v4_2_ddr_phy_top.dbg_oclkdelay_calib_done
out dbg_oclkdelay_calib_done std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:360
mig_7series_v4_2_ddr_phy_top.dbg_wrlvl_done
out dbg_wrlvl_done std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:320
mig_7series_v4_2_ddr_phy_top.phy_rd_data
out phy_rd_data std_logic_vector( 2* nCK_PER_CLK* DQ_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:349
mig_7series_v4_2_ddr_phy_top.dbg_sel_idel_cpt
in dbg_sel_idel_cpt std_logic_vector( DQS_CNT_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:245
mig_7series_v4_2_ddr_phy_top.prbs_final_dqs_tap_cnt_r
out prbs_final_dqs_tap_cnt_r std_logic_vector( 6* DQS_WIDTH* RANKS- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:363
mig_7series_v4_2_ddr_phy_top.DDR2_DQSN_ENABLE
DDR2_DQSN_ENABLE string := "YES"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:175
mig_7series_v4_2_ddr_phy_top.dbg_wrcal_start
out dbg_wrcal_start std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:334
mig_7series_v4_2_ddr_phy_top.phy_mc_ctl_full
out phy_mc_ctl_full std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:339
mig_7series_v4_2_ddr_phy_top.CAS_MAP
CAS_MAP std_logic_vector( 11 downto 0) := X"000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:123
mig_7series_v4_2_ddr_phy_top.DQS_BYTE_MAP
DQS_BYTE_MAP std_logic_vector( 143 downto 0) := X"000000000000000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:133
mig_7series_v4_2_ddr_phy_top.DDR3_VDD_OP_VOLT
DDR3_VDD_OP_VOLT string := "135"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:77
mig_7series_v4_2_ddr_phy_top.DRAM_TYPE
DRAM_TYPE string := "DDR3"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:93
mig_7series_v4_2_ddr_phy_top.dbg_wrcal_done
out dbg_wrcal_done std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:335
mig_7series_v4_2_ddr_phy_top.BANK_TYPE
BANK_TYPE string := "HP_IO"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:162
mig_7series_v4_2_ddr_phy_top.FPGA_VOLT_TYPE
FPGA_VOLT_TYPE string := "N"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:211
mig_7series_v4_2_ddr_phy_top.clk_ref
in clk_ref std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:217
mig_7series_v4_2_ddr_phy_top.dbg_phy_wrcal
out dbg_phy_wrcal std_logic_vector( 99 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:309
mig_7series_v4_2_ddr_phy_top.calib_tap_val
in calib_tap_val std_logic_vector( 7 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:300
mig_7series_v4_2_ddr_phy_top.DATA7_MAP
DATA7_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:141
mig_7series_v4_2_ddr_phy_top.clk
in clk std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:213
mig_7series_v4_2_ddr_phy_top.dbg_poc
out dbg_poc std_logic_vector( 1023 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:337
mig_7series_v4_2_ddr_phy_top.iddr_rst
in iddr_rst std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:247
mig_7series_v4_2_ddr_phy_top.mc_data_offset
in mc_data_offset std_logic_vector( 5 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:267
mig_7series_v4_2_ddr_phy_top.dbg_oclkdelay_rd_data
out dbg_oclkdelay_rd_data std_logic_vector( DRAM_WIDTH* 16- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:362
mig_7series_v4_2_ddr_phy_top.calib_rd_data_offset_0
out calib_rd_data_offset_0 std_logic_vector( 6* RANKS- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:345
mig_7series_v4_2_ddr_phy_top.CKE_ODT_BYTE_MAP
CKE_ODT_BYTE_MAP std_logic_vector( 7 downto 0) := X"00"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:124
mig_7series_v4_2_ddr_phy_top.mc_wrdata
in mc_wrdata std_logic_vector( 2* nCK_PER_CLK* DQ_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:273
mig_7series_v4_2_ddr_phy_top.dbg_pi_phaselocked_done
out dbg_pi_phaselocked_done std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:327
mig_7series_v4_2_ddr_phy_top.DATA11_MAP
DATA11_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:145
mig_7series_v4_2_ddr_phy_top.ddr_addr
out ddr_addr std_logic_vector( ROW_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:277
mig_7series_v4_2_ddr_phy_top.dbg_phy_oclkdelay_cal
out dbg_phy_oclkdelay_cal std_logic_vector( 255 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:361
mig_7series_v4_2_ddr_phy_top.dbg_po_f_stg23_sel
in dbg_po_f_stg23_sel std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:238
mig_7series_v4_2_ddr_phy_top.ddr_ras_n
out ddr_ras_n std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:286
mig_7series_v4_2_ddr_phy_top.dbg_sel_pi_incdec
in dbg_sel_pi_incdec std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:232
mig_7series_v4_2_ddr_phy_top.DRAM_WIDTH
DRAM_WIDTH integer := 8
Definition: mig_7series_v4_2_ddr_phy_top.vhd:94
mig_7series_v4_2_ddr_phy_top.CKE_WIDTH
CKE_WIDTH integer := 1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:87
mig_7series_v4_2_ddr_phy_top.phy_rddata_valid
out phy_rddata_valid std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:348
mig_7series_v4_2_ddr_phy_top.BURST_TYPE
BURST_TYPE string := "SEQ"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:81
mig_7series_v4_2_ddr_phy_top.DATA10_MAP
DATA10_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:144
mig_7series_v4_2_ddr_phy_top.idle
in idle std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:275
mig_7series_v4_2_ddr_phy_top.DATA_CTL_B0
DATA_CTL_B0 std_logic_vector( 3 downto 0) := X"c"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:101
mig_7series_v4_2_ddr_phy_top.init_calib_complete
out init_calib_complete std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:343
mig_7series_v4_2_ddr_phy_top.CALIB_ROW_ADD
CALIB_ROW_ADD std_logic_vector( 15 downto 0) := X"0000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:184
mig_7series_v4_2_ddr_phy_top.CKE_ODT_AUX
CKE_ODT_AUX string := "FALSE"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:127
mig_7series_v4_2_ddr_phy_top.PHY_0_BITLANES
PHY_0_BITLANES std_logic_vector( 47 downto 0) := X"000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:115
mig_7series_v4_2_ddr_phy_top.BANK_MAP
BANK_MAP std_logic_vector( 35 downto 0) := X"000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:122
mig_7series_v4_2_ddr_phy_top.dbg_pi_dqsfound_done
out dbg_pi_dqsfound_done std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:331
mig_7series_v4_2_ddr_phy_top.dbg_rdlvl_err
out dbg_rdlvl_err std_logic_vector( 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:316
mig_7series_v4_2_ddr_phy_top.slot_0_present
in slot_0_present std_logic_vector( 7 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:248
mig_7series_v4_2_ddr_phy_top.mc_cas_n
in mc_cas_n std_logic_vector( nCK_PER_CLK- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:252
mig_7series_v4_2_ddr_phy_top.init_wrcal_complete
out init_wrcal_complete std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:344
mig_7series_v4_2_ddr_phy_top.dbg_calib_top
out dbg_calib_top std_logic_vector( 255 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:303
mig_7series_v4_2_ddr_phy_top.AL
AL string := "0"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:78
mig_7series_v4_2_ddr_phy_top.DATA15_MAP
DATA15_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:149
mig_7series_v4_2_ddr_phy_top.POC_USE_METASTABLE_SAMP
POC_USE_METASTABLE_SAMP string := "FALSE"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:209
mig_7series_v4_2_ddr_phy_top.CKE_MAP
CKE_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:125
mig_7series_v4_2_ddr_phy_top.dbg_pi_phase_locked_phy4lanes
out dbg_pi_phase_locked_phy4lanes std_logic_vector( 11 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:329
mig_7series_v4_2_ddr_phy_top.CK_BYTE_MAP
CK_BYTE_MAP std_logic_vector( 143 downto 0) := X"000000000000000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:120
mig_7series_v4_2_ddr_phy_top.USE_DM_PORT
USE_DM_PORT integer := 1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:198
mig_7series_v4_2_ddr_phy_top.dbg_wrlvl_coarse_tap_cnt
out dbg_wrlvl_coarse_tap_cnt std_logic_vector( 3* DQS_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:324
mig_7series_v4_2_ddr_phy_top.DATA_IO_IDLE_PWRDWN
DATA_IO_IDLE_PWRDWN string := "ON"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:164
mig_7series_v4_2_ddr_phy_top.DATA_IO_PRIM_TYPE
DATA_IO_PRIM_TYPE string := "DEFAULT"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:163
mig_7series_v4_2_ddr_phy_top.ref_dll_lock
out ref_dll_lock std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:351
mig_7series_v4_2_ddr_phy_top.DATA12_MAP
DATA12_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:146
mig_7series_v4_2_ddr_phy_top.ROW_WIDTH
ROW_WIDTH integer := 16
Definition: mig_7series_v4_2_ddr_phy_top.vhd:180
mig_7series_v4_2_ddr_phy_top.mc_reset_n
in mc_reset_n std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:257
mig_7series_v4_2_ddr_phy_top.DATA16_MAP
DATA16_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:150
mig_7series_v4_2_ddr_phy_top.rst_phaser_ref
in rst_phaser_ref std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:352
mig_7series_v4_2_ddr_phy_top.mem_refclk
in mem_refclk std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:220
mig_7series_v4_2_ddr_phy_top.dbg_sel_all_idel_cpt
in dbg_sel_all_idel_cpt std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:244
mig_7series_v4_2_ddr_phy_top.dbg_wrcal_err
out dbg_wrcal_err std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:336
mig_7series_v4_2_ddr_phy_top.dbg_idel_up_cpt
in dbg_idel_up_cpt std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:243
mig_7series_v4_2_ddr_phy_top.CA_MIRROR
CA_MIRROR string := "OFF"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:82
mig_7series_v4_2_ddr_phy_top.RD_PATH_REG
RD_PATH_REG integer := 0
Definition: mig_7series_v4_2_ddr_phy_top.vhd:200
mig_7series_v4_2_ddr_phy_top.dbg_tap_cnt_during_wrlvl
out dbg_tap_cnt_during_wrlvl std_logic_vector( 5 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:318
mig_7series_v4_2_ddr_phy_top.DATA_CTL_B3
DATA_CTL_B3 std_logic_vector( 3 downto 0) := X"f"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:104
mig_7series_v4_2_ddr_phy_top.COL_WIDTH
COL_WIDTH integer := 12
Definition: mig_7series_v4_2_ddr_phy_top.vhd:85
mig_7series_v4_2_ddr_phy_top.CS_WIDTH
CS_WIDTH integer := 1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:86
mig_7series_v4_2_ddr_phy_top.RTT_WR
RTT_WR string := "120"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:171
mig_7series_v4_2_ddr_phy_top.CS_MAP
CS_MAP std_logic_vector( 119 downto 0) := X"000000000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:128
mig_7series_v4_2_ddr_phy_top.dbg_final_po_coarse_tap_cnt
out dbg_final_po_coarse_tap_cnt std_logic_vector( 3* DQS_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:311
mig_7series_v4_2_ddr_phy_top.dbg_pi_phaselock_start
out dbg_pi_phaselock_start std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:326
mig_7series_v4_2_ddr_phy_top.WE_MAP
WE_MAP std_logic_vector( 11 downto 0) := X"000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:131
mig_7series_v4_2_ddr_phy_top.WRLVL
WRLVL string := "OFF"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:176
mig_7series_v4_2_ddr_phy_top.psen
out psen std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:294
mig_7series_v4_2_ddr_phy_top.calib_tap_addr
in calib_tap_addr std_logic_vector( 6 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:299
mig_7series_v4_2_ddr_phy_top.sync_pulse
in sync_pulse std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:222
mig_7series_v4_2_ddr_phy_top.ddr_cas_n
out ddr_cas_n std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:279
mig_7series_v4_2_ddr_phy_top.freq_refclk
in freq_refclk std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:219
mig_7series_v4_2_ddr_phy_top.IDELAY_ADJ
IDELAY_ADJ string := "ON"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:203
mig_7series_v4_2_ddr_phy_top.tempmon_sample_en
in tempmon_sample_en std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:230
mig_7series_v4_2_ddr_phy_top.ADDR_MAP
ADDR_MAP std_logic_vector( 191 downto 0) := X"000000000000000000000000000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:121
mig_7series_v4_2_ddr_phy_top.calib_rd_data_offset_1
out calib_rd_data_offset_1 std_logic_vector( 6* RANKS- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:346
mig_7series_v4_2_ddr_phy_top.MASK0_MAP
MASK0_MAP std_logic_vector( 107 downto 0) := X"000000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:152
mig_7series_v4_2_ddr_phy_top.dbg_pi_dqsfound_err
out dbg_pi_dqsfound_err std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:332
mig_7series_v4_2_ddr_phy_top.dbg_phy_rdlvl
out dbg_phy_rdlvl std_logic_vector( 255 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:308
mig_7series_v4_2_ddr_phy_top.dbg_pi_phaselock_err
out dbg_pi_phaselock_err std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:328
mig_7series_v4_2_ddr_phy_top.DATA6_MAP
DATA6_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:140
mig_7series_v4_2_ddr_phy_top.dbg_pi_f_inc
in dbg_pi_f_inc std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:235
mig_7series_v4_2_ddr_phy_top.CL
CL integer := 5
Definition: mig_7series_v4_2_ddr_phy_top.vhd:84
mig_7series_v4_2_ddr_phy_top.calib_tap_load_done
in calib_tap_load_done std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:301
mig_7series_v4_2_ddr_phy_top.mc_rank_cnt
in mc_rank_cnt std_logic_vector( 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:270
mig_7series_v4_2_ddr_phy_top.dbg_idel_up_all
in dbg_idel_up_all std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:242
mig_7series_v4_2_ddr_phy_top.mc_data_offset_2
in mc_data_offset_2 std_logic_vector( 5 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:269
mig_7series_v4_2_ddr_phy_top.ddr_we_n
out ddr_we_n std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:289
mig_7series_v4_2_ddr_phy_top.mc_ras_n
in mc_ras_n std_logic_vector( nCK_PER_CLK- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:251
mig_7series_v4_2_ddr_phy_top.dbg_wl_edge_detect_valid
out dbg_wl_edge_detect_valid std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:319
mig_7series_v4_2_ddr_phy_top.dbg_pi_counter_read_val
out dbg_pi_counter_read_val std_logic_vector( 5 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:357
mig_7series_v4_2_ddr_phy_top.dbg_dq_idelay_tap_cnt
out dbg_dq_idelay_tap_cnt std_logic_vector( 5* DQS_WIDTH* RANKS- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:307
mig_7series_v4_2_ddr_phy_top.DATA4_MAP
DATA4_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:138
mig_7series_v4_2_ddr_phy_top.error
in error std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:226
mig_7series_v4_2_ddr_phy_top.DATA_CTL_B1
DATA_CTL_B1 std_logic_vector( 3 downto 0) := X"f"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:102
mig_7series_v4_2_ddr_phy_top.dbg_cpt_second_edge_cnt
out dbg_cpt_second_edge_cnt std_logic_vector( 6* DQS_WIDTH* RANKS- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:305
mig_7series_v4_2_ddr_phy_top.psincdec
out psincdec std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:295
mig_7series_v4_2_ddr_phy_top.dbg_wrlvl_fine_tap_cnt
out dbg_wrlvl_fine_tap_cnt std_logic_vector( 6* DQS_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:323
mig_7series_v4_2_ddr_phy_top.MASTER_PHY_CTL
MASTER_PHY_CTL integer := 0
Definition: mig_7series_v4_2_ddr_phy_top.vhd:95
mig_7series_v4_2_ddr_phy_top.mc_wrdata_mask
in mc_wrdata_mask std_logic_vector(( 2* nCK_PER_CLK*( DQ_WIDTH/ 8))- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:274
mig_7series_v4_2_ddr_phy_top.REFCLK_FREQ
REFCLK_FREQ real := 200.0
Definition: mig_7series_v4_2_ddr_phy_top.vhd:196
mig_7series_v4_2_ddr_phy_top.CK_WIDTH
CK_WIDTH integer := 1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:83
mig_7series_v4_2_ddr_phy_top.ddr_ck
out ddr_ck std_logic_vector( CK_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:281
mig_7series_v4_2_ddr_phy_top.phy_mc_cmd_full
out phy_mc_cmd_full std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:340
mig_7series_v4_2_ddr_phy_top.MASK1_MAP
MASK1_MAP std_logic_vector( 107 downto 0) := X"000000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:153
mig_7series_v4_2_ddr_phy_top.mc_data_offset_1
in mc_data_offset_1 std_logic_vector( 5 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:268
mig_7series_v4_2_ddr_phy_top.OUTPUT_DRV
OUTPUT_DRV string := "HIGH"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:168
mig_7series_v4_2_ddr_phy_top.dbg_pi_dqsfound_start
out dbg_pi_dqsfound_start std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:330
mig_7series_v4_2_ddr_phy_top.ADDR_CMD_MODE
ADDR_CMD_MODE string := "1T"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:161
mig_7series_v4_2_ddr_phy_top.calib_tap_load
in calib_tap_load std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:298
mig_7series_v4_2_ddr_phy_top.dbg_po_f_inc
in dbg_po_f_inc std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:237
mig_7series_v4_2_ddr_phy_top.BANK_WIDTH
BANK_WIDTH integer := 3
Definition: mig_7series_v4_2_ddr_phy_top.vhd:79
mig_7series_v4_2_ddr_phy_top.DATA17_MAP
DATA17_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:151
mig_7series_v4_2_ddr_phy_top.tRFC
tRFC integer := 110000
Definition: mig_7series_v4_2_ddr_phy_top.vhd:173
mig_7series_v4_2_ddr_phy_top.mc_odt
in mc_odt std_logic_vector( 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:258
mig_7series_v4_2_ddr_phy_top.PHYCTL_CMD_FIFO
PHYCTL_CMD_FIFO string := "FALSE"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:98
mig_7series_v4_2_ddr_phy_top.clk_div2
in clk_div2 std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:215
mig_7series_v4_2_ddr_phy_top.PHY_2_BITLANES
PHY_2_BITLANES std_logic_vector( 47 downto 0) := X"000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:117
mig_7series_v4_2_ddr_phy_top.calib_tap_req
out calib_tap_req std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:297
mig_7series_v4_2_ddr_phy_top.ODT_MAP
ODT_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:126
mig_7series_v4_2_ddr_phy_top.CALIB_COL_ADD
CALIB_COL_ADD std_logic_vector( 11 downto 0) := X"000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:185
mig_7series_v4_2_ddr_phy_top.DQS_CNT_WIDTH
DQS_CNT_WIDTH integer := 3
Definition: mig_7series_v4_2_ddr_phy_top.vhd:91
mig_7series_v4_2_ddr_phy_top.CALIB_BA_ADD
CALIB_BA_ADD std_logic_vector( 2 downto 0) := "000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:186
mig_7series_v4_2_ddr_phy_top.dbg_cpt_first_edge_cnt
out dbg_cpt_first_edge_cnt std_logic_vector( 6* DQS_WIDTH* RANKS- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:304
mig_7series_v4_2_ddr_phy_top.nCS_PER_RANK
nCS_PER_RANK integer := 1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:160
mig_7series_v4_2_ddr_phy_top.dbg_pi_f_dec
in dbg_pi_f_dec std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:236
mig_7series_v4_2_ddr_phy_top.DATA8_MAP
DATA8_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:142
mig_7series_v4_2_ddr_phy_top.dbg_prbs_second_edge_taps
out dbg_prbs_second_edge_taps std_logic_vector( 6* DQS_WIDTH* RANKS- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:367
mig_7series_v4_2_ddr_phy_top.dbg_rddata_valid
out dbg_rddata_valid std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:314
mig_7series_v4_2_ddr_phy_top.dbg_dqs_found_cal
out dbg_dqs_found_cal std_logic_vector( 255 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:356
mig_7series_v4_2_ddr_phy_top.mc_cmd_wren
in mc_cmd_wren std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:263
mig_7series_v4_2_ddr_phy_top.dbg_phy_wrlvl
out dbg_phy_wrlvl std_logic_vector( 255 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:325
mig_7series_v4_2_ddr_phy_top.poc_sample_pd
in poc_sample_pd std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:225
mig_7series_v4_2_ddr_phy_top.ddr_dq
inout ddr_dq std_logic_vector( DQ_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:290
mig_7series_v4_2_ddr_phy_top.calib_rd_data_offset_2
out calib_rd_data_offset_2 std_logic_vector( 6* RANKS- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:347
mig_7series_v4_2_ddr_phy_top.dbg_wrlvl_start
out dbg_wrlvl_start std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:322
mig_7series_v4_2_ddr_phy_top.FINE_PER_BIT
FINE_PER_BIT string := "ON"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:204
mig_7series_v4_2_ddr_phy_top.DEBUG_PORT
DEBUG_PORT string := "OFF"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:177
mig_7series_v4_2_ddr_phy_top.DATA2_MAP
DATA2_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:136
mig_7series_v4_2_ddr_phy_top.SKIP_CALIB
SKIP_CALIB string := "FALSE"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:208
mig_7series_v4_2_ddr_phy_top.nCK_PER_CLK
nCK_PER_CLK integer := 2
Definition: mig_7series_v4_2_ddr_phy_top.vhd:159
mig_7series_v4_2_ddr_phy_top.REG_CTRL
REG_CTRL string := "OFF"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:169
mig_7series_v4_2_ddr_phy_top.mc_cas_slot
in mc_cas_slot std_logic_vector( 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:266
mig_7series_v4_2_ddr_phy_top.dbg_rdlvl_start
out dbg_rdlvl_start std_logic_vector( 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:317
mig_7series_v4_2_ddr_phy_top.rst
in rst std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:246
mig_7series_v4_2_ddr_phy_top.DATA14_MAP
DATA14_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:148
mig_7series_v4_2_ddr_phy_top.ddr_odt
out ddr_odt std_logic_vector( ODT_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:285
mig_7series_v4_2_ddr_phy_top.mc_ctl_wren
in mc_ctl_wren std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:264
mig_7series_v4_2_ddr_phy_top.dbg_final_po_fine_tap_cnt
out dbg_final_po_fine_tap_cnt std_logic_vector( 6* DQS_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:310
mig_7series_v4_2_ddr_phy_top.mc_wrdata_en
in mc_wrdata_en std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:272
mig_7series_v4_2_ddr_phy_top.dbg_pi_dqs_found_lanes_phy4lanes
out dbg_pi_dqs_found_lanes_phy4lanes std_logic_vector( 11 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:333
mig_7series_v4_2_ddr_phy_top.PARITY_MAP
PARITY_MAP std_logic_vector( 11 downto 0) := X"000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:129
mig_7series_v4_2_ddr_phy_top.dbg_rd_data_edge_detect
out dbg_rd_data_edge_detect std_logic_vector( DQS_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:312
mig_7series_v4_2_ddr_phy_top.BYTE_LANES_B3
BYTE_LANES_B3 std_logic_vector( 3 downto 0) := "0000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:111
mig_7series_v4_2_ddr_phy_top.dbg_prbs_first_edge_taps
out dbg_prbs_first_edge_taps std_logic_vector( 6* DQS_WIDTH* RANKS- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:364
mig_7series_v4_2_ddr_phy_top.RTT_NOM
RTT_NOM string := "60"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:170
mig_7series_v4_2_ddr_phy_top.dbg_po_f_dec
in dbg_po_f_dec std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:239
mig_7series_v4_2_ddr_phy_top.phy_mc_data_full
out phy_mc_data_full std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:341
mig_7series_v4_2_ddr_phy_top.DATA5_MAP
DATA5_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:139
mig_7series_v4_2_ddr_phy_top.dbg_rd_data_offset
out dbg_rd_data_offset std_logic_vector( 6* RANKS- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:353
mig_7series_v4_2_ddr_phy_top.dbg_phy_init
out dbg_phy_init std_logic_vector( 255 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:354
mig_7series_v4_2_ddr_phy_top.ddr_dqs_n
inout ddr_dqs_n std_logic_vector( DQS_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:291
mig_7series_v4_2_ddr_phy_top.ddr_cs_n
out ddr_cs_n std_logic_vector(( CS_WIDTH* nCS_PER_RANK)- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:283
mig_7series_v4_2_ddr_phy_top.SLOT_1_CONFIG
SLOT_1_CONFIG std_logic_vector( 7 downto 0) := "00000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:181
mig_7series_v4_2_ddr_phy_top.tCK
tCK integer := 2500
Definition: mig_7series_v4_2_ddr_phy_top.vhd:172
mig_7series_v4_2_ddr_phy_top.dbg_rdlvl_done
out dbg_rdlvl_done std_logic_vector( 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:315
mig_7series_v4_2_ddr_phy_top.ODT_WIDTH
ODT_WIDTH integer := 1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:179
mig_7series_v4_2_ddr_phy_top.dbg_idel_down_all
in dbg_idel_down_all std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:240
mig_7series_v4_2_ddr_phy_top.dbg_oclkdelay_calib_start
out dbg_oclkdelay_calib_start std_logic
Definition: mig_7series_v4_2_ddr_phy_top.vhd:359
mig_7series_v4_2_ddr_phy_top.ddr_ba
out ddr_ba std_logic_vector( BANK_WIDTH- 1 downto 0)
Definition: mig_7series_v4_2_ddr_phy_top.vhd:278
mig_7series_v4_2_ddr_phy_top.DATA13_MAP
DATA13_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:147
mig_7series_v4_2_ddr_phy_top.USE_CS_PORT
USE_CS_PORT integer := 1
Definition: mig_7series_v4_2_ddr_phy_top.vhd:197
mig_7series_v4_2_ddr_phy_top.DATA9_MAP
DATA9_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:143
mig_7series_v4_2_ddr_phy_top.BURST_MODE
BURST_MODE string := "8"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:80
mig_7series_v4_2_ddr_phy_top.CENTER_COMP_MODE
CENTER_COMP_MODE string := "ON"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:205
mig_7series_v4_2_ddr_phy_top.DATA0_MAP
DATA0_MAP std_logic_vector( 95 downto 0) := X"000000000000000000000000"
Definition: mig_7series_v4_2_ddr_phy_top.vhd:134