w11 - vhd 0.794
W11 CPU core and support modules
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Attributes | Components | Constants | Functions | Instantiations | Processes | Signals
arch_ddr_phy_top Architecture Reference
Architecture >> arch_ddr_phy_top

Functions

std_logic   OR_BR ( inp_var: in std_logic_vector )
integer   CALC_nSLOTS
string   SIM_INIT_OPTION_W
string   SIM_CAL_OPTION_W
string   CALC_WRLVL_W
integer   HIGHEST_BANK_W
integer   HIGHEST_LANE_B0_W
integer   HIGHEST_LANE_B1_W
integer   HIGHEST_LANE_B2_W
integer   HIGHEST_LANE_B3_W
integer   HIGHEST_LANE_B4_W
integer   HIGHEST_LANE_W
integer   N_CTL_LANES_B0
integer   N_CTL_LANES_B1
integer   N_CTL_LANES_B2
integer   N_CTL_LANES_B3
integer   N_CTL_LANES_B4
std_logic   CTL_BANK_B0
std_logic   CTL_BANK_B1
std_logic   CTL_BANK_B2
std_logic   CTL_BANK_B3
std_logic   CTL_BANK_B4
std_logic_vector   CTL_BANK_W
std_logic   ODD_PARITY ( inp_var: in std_logic_vector )
std_logic_vector   CTL_BYTE_LANE_W
string   PI_DIV2_INCDEC_FUN
std_logic   OR_BR ( inp_var: in std_logic_vector )
integer   CALC_nSLOTS
string   SIM_INIT_OPTION_W
string   SIM_CAL_OPTION_W
string   CALC_WRLVL_W
integer   HIGHEST_BANK_W
integer   HIGHEST_LANE_B0_W
integer   HIGHEST_LANE_B1_W
integer   HIGHEST_LANE_B2_W
integer   HIGHEST_LANE_B3_W
integer   HIGHEST_LANE_B4_W
integer   HIGHEST_LANE_W
integer   N_CTL_LANES_B0
integer   N_CTL_LANES_B1
integer   N_CTL_LANES_B2
integer   N_CTL_LANES_B3
integer   N_CTL_LANES_B4
std_logic   CTL_BANK_B0
std_logic   CTL_BANK_B1
std_logic   CTL_BANK_B2
std_logic   CTL_BANK_B3
std_logic   CTL_BANK_B4
std_logic_vector   CTL_BANK_W
std_logic   ODD_PARITY ( inp_var: in std_logic_vector )
std_logic_vector   CTL_BYTE_LANE_W
string   PI_DIV2_INCDEC_FUN
std_logic   OR_BR ( inp_var: in std_logic_vector )
integer   CALC_nSLOTS
string   SIM_INIT_OPTION_W
string   SIM_CAL_OPTION_W
string   CALC_WRLVL_W
integer   HIGHEST_BANK_W
integer   HIGHEST_LANE_B0_W
integer   HIGHEST_LANE_B1_W
integer   HIGHEST_LANE_B2_W
integer   HIGHEST_LANE_B3_W
integer   HIGHEST_LANE_B4_W
integer   HIGHEST_LANE_W
integer   N_CTL_LANES_B0
integer   N_CTL_LANES_B1
integer   N_CTL_LANES_B2
integer   N_CTL_LANES_B3
integer   N_CTL_LANES_B4
std_logic   CTL_BANK_B0
std_logic   CTL_BANK_B1
std_logic   CTL_BANK_B2
std_logic   CTL_BANK_B3
std_logic   CTL_BANK_B4
std_logic_vector   CTL_BANK_W
std_logic   ODD_PARITY ( inp_var: in std_logic_vector )
std_logic_vector   CTL_BYTE_LANE_W
string   PI_DIV2_INCDEC_FUN
std_logic   OR_BR ( inp_var: in std_logic_vector )
integer   CALC_nSLOTS
string   SIM_INIT_OPTION_W
string   SIM_CAL_OPTION_W
string   CALC_WRLVL_W
integer   HIGHEST_BANK_W
integer   HIGHEST_LANE_B0_W
integer   HIGHEST_LANE_B1_W
integer   HIGHEST_LANE_B2_W
integer   HIGHEST_LANE_B3_W
integer   HIGHEST_LANE_B4_W
integer   HIGHEST_LANE_W
integer   N_CTL_LANES_B0
integer   N_CTL_LANES_B1
integer   N_CTL_LANES_B2
integer   N_CTL_LANES_B3
integer   N_CTL_LANES_B4
std_logic   CTL_BANK_B0
std_logic   CTL_BANK_B1
std_logic   CTL_BANK_B2
std_logic   CTL_BANK_B3
std_logic   CTL_BANK_B4
std_logic_vector   CTL_BANK_W
std_logic   ODD_PARITY ( inp_var: in std_logic_vector )
std_logic_vector   CTL_BYTE_LANE_W
string   PI_DIV2_INCDEC_FUN
std_logic   OR_BR ( inp_var: in std_logic_vector )
integer   CALC_nSLOTS
string   SIM_INIT_OPTION_W
string   SIM_CAL_OPTION_W
string   CALC_WRLVL_W
integer   HIGHEST_BANK_W
integer   HIGHEST_LANE_B0_W
integer   HIGHEST_LANE_B1_W
integer   HIGHEST_LANE_B2_W
integer   HIGHEST_LANE_B3_W
integer   HIGHEST_LANE_B4_W
integer   HIGHEST_LANE_W
integer   N_CTL_LANES_B0
integer   N_CTL_LANES_B1
integer   N_CTL_LANES_B2
integer   N_CTL_LANES_B3
integer   N_CTL_LANES_B4
std_logic   CTL_BANK_B0
std_logic   CTL_BANK_B1
std_logic   CTL_BANK_B2
std_logic   CTL_BANK_B3
std_logic   CTL_BANK_B4
std_logic_vector   CTL_BANK_W
std_logic   ODD_PARITY ( inp_var: in std_logic_vector )
std_logic_vector   CTL_BYTE_LANE_W
string   PI_DIV2_INCDEC_FUN

Processes

PROCESS_0  ( clk_div2 )
PROCESS_1  ( clk_div2 )
PROCESS_2  ( clk_div2 )
PROCESS_3  ( clk_div2 )
PROCESS_4  ( clk_div2 )
PROCESS_5  ( clk_div2 )
PROCESS_6  ( clk )
PROCESS_7  ( mux_address , mux_bank , mux_cas_n , mux_ras_n , mux_we_n )
PROCESS_8  ( clk )
PROCESS_9  ( mux_address , mux_bank , mux_cas_n , mux_ras_n , mux_we_n )
PROCESS_10  ( clk )
PROCESS_11  ( clk )
PROCESS_12  ( clk )
PROCESS_13  ( phy_rddata_valid_w , rd_data_map )
PROCESS_14  ( clk_div2 )
PROCESS_15  ( clk_div2 )
PROCESS_16  ( clk_div2 )
PROCESS_17  ( clk_div2 )
PROCESS_18  ( clk_div2 )
PROCESS_19  ( clk_div2 )
PROCESS_20  ( clk )
PROCESS_21  ( mux_address , mux_bank , mux_cas_n , mux_ras_n , mux_we_n )
PROCESS_22  ( clk )
PROCESS_23  ( mux_address , mux_bank , mux_cas_n , mux_ras_n , mux_we_n )
PROCESS_24  ( clk )
PROCESS_25  ( clk )
PROCESS_26  ( clk )
PROCESS_27  ( phy_rddata_valid_w , rd_data_map )
PROCESS_28  ( clk_div2 )
PROCESS_29  ( clk_div2 )
PROCESS_30  ( clk_div2 )
PROCESS_31  ( clk_div2 )
PROCESS_32  ( clk_div2 )
PROCESS_33  ( clk_div2 )
PROCESS_34  ( clk )
PROCESS_35  ( mux_address , mux_bank , mux_cas_n , mux_ras_n , mux_we_n )
PROCESS_36  ( clk )
PROCESS_37  ( mux_address , mux_bank , mux_cas_n , mux_ras_n , mux_we_n )
PROCESS_38  ( clk )
PROCESS_39  ( clk )
PROCESS_40  ( clk )
PROCESS_41  ( phy_rddata_valid_w , rd_data_map )
PROCESS_42  ( clk_div2 )
PROCESS_43  ( clk_div2 )
PROCESS_44  ( clk_div2 )
PROCESS_45  ( clk_div2 )
PROCESS_46  ( clk_div2 )
PROCESS_47  ( clk_div2 )
PROCESS_48  ( clk )
PROCESS_49  ( mux_address , mux_bank , mux_cas_n , mux_ras_n , mux_we_n )
PROCESS_50  ( clk )
PROCESS_51  ( mux_address , mux_bank , mux_cas_n , mux_ras_n , mux_we_n )
PROCESS_52  ( clk )
PROCESS_53  ( clk )
PROCESS_54  ( clk )
PROCESS_55  ( phy_rddata_valid_w , rd_data_map )
PROCESS_56  ( clk_div2 )
PROCESS_57  ( clk_div2 )
PROCESS_58  ( clk_div2 )
PROCESS_59  ( clk_div2 )
PROCESS_60  ( clk_div2 )
PROCESS_61  ( clk_div2 )
PROCESS_62  ( clk )
PROCESS_63  ( mux_address , mux_bank , mux_cas_n , mux_ras_n , mux_we_n )
PROCESS_64  ( clk )
PROCESS_65  ( mux_address , mux_bank , mux_cas_n , mux_ras_n , mux_we_n )
PROCESS_66  ( clk )
PROCESS_67  ( clk )
PROCESS_68  ( clk )
PROCESS_69  ( phy_rddata_valid_w , rd_data_map )

Components

mig_7series_v4_2_ddr_mc_phy_wrapper 
mig_7series_v4_2_ddr_calib_top 

Constants

nSLOTS  integer := CALC_nSLOTS
CLK_PERIOD  integer := tCK * nCK_PER_CLK
SIM_INIT_OPTION  string := SIM_INIT_OPTION_W
SIM_CAL_OPTION  string := SIM_CAL_OPTION_W
WRLVL_W  string := CALC_WRLVL_W
HIGHEST_BANK  integer := HIGHEST_BANK_W
HIGHEST_LANE  integer := HIGHEST_LANE_W
N_CTL_LANES  integer := N_CTL_LANES_B0+ N_CTL_LANES_B1+ N_CTL_LANES_B2+ N_CTL_LANES_B3+ N_CTL_LANES_B4
CTL_BANK  std_logic_vector ( 2 downto 0 ) := CTL_BANK_W
CTL_BYTE_LANE  std_logic_vector ( 7 downto 0 ) := CTL_BYTE_LANE_W
PI_DIV2_INCDEC  string := PI_DIV2_INCDEC_FUN

Signals

phy_din  std_logic_vector ( HIGHEST_LANE * 80 - 1 downto 0 )
phy_dout  std_logic_vector ( HIGHEST_LANE * 80 - 1 downto 0 )
ddr_cmd_ctl_data  std_logic_vector ( HIGHEST_LANE * 12 - 1 downto 0 )
aux_out  std_logic_vector ( ( ( ( HIGHEST_LANE + 3 ) / 4 ) * 4 ) - 1 downto 0 )
ddr_clk  std_logic_vector ( CK_WIDTH * LP_DDR_CK_WIDTH - 1 downto 0 )
phy_mc_go  std_logic
phy_ctl_full  std_logic
phy_cmd_full  std_logic
phy_data_full  std_logic
phy_pre_data_a_full  std_logic
if_empty  std_logic
phy_write_calib  std_logic
phy_read_calib  std_logic
rst_stg1_cal  std_logic_vector ( HIGHEST_BANK - 1 downto 0 )
calib_sel  std_logic_vector ( 5 downto 0 )
calib_in_common  std_logic
calib_zero_inputs  std_logic_vector ( HIGHEST_BANK - 1 downto 0 )
calib_zero_ctrl  std_logic_vector ( HIGHEST_BANK - 1 downto 0 )
pi_phase_locked  std_logic
pi_phase_locked_all  std_logic
pi_found_dqs  std_logic
pi_dqs_found_all  std_logic
pi_dqs_out_of_range  std_logic
pi_enstg2_f  std_logic
pi_stg2_fincdec  std_logic
pi_stg2_load  std_logic
pi_stg2_reg_l  std_logic_vector ( 5 downto 0 )
idelay_ce  std_logic
idelay_inc  std_logic
idelay_ld  std_logic
po_sel_stg2stg3  std_logic_vector ( 2 downto 0 )
po_stg2_cincdec  std_logic_vector ( 2 downto 0 )
po_enstg2_c  std_logic_vector ( 2 downto 0 )
po_stg2_fincdec  std_logic_vector ( 2 downto 0 )
po_enstg2_f  std_logic_vector ( 2 downto 0 )
po_counter_read_val  std_logic_vector ( 8 downto 0 )
pi_counter_read_val  std_logic_vector ( 5 downto 0 )
phy_wrdata  std_logic_vector ( 2 * nCK_PER_CLK * DQ_WIDTH - 1 downto 0 )
parity  std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
phy_address  std_logic_vector ( nCK_PER_CLK * ROW_WIDTH - 1 downto 0 )
phy_bank  std_logic_vector ( nCK_PER_CLK * BANK_WIDTH - 1 downto 0 )
phy_cs_n  std_logic_vector ( CS_WIDTH * nCS_PER_RANK * nCK_PER_CLK - 1 downto 0 )
phy_ras_n  std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
phy_cas_n  std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
phy_we_n  std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
phy_reset_n  std_logic
calib_aux_out  std_logic_vector ( 3 downto 0 )
calib_cke  std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
calib_odt  std_logic_vector ( 1 downto 0 )
calib_ctl_wren  std_logic
calib_cmd_wren  std_logic
calib_wrdata_en  std_logic
calib_cmd  std_logic_vector ( 2 downto 0 )
calib_seq  std_logic_vector ( 1 downto 0 )
calib_data_offset_0  std_logic_vector ( 5 downto 0 )
calib_data_offset_1  std_logic_vector ( 5 downto 0 )
calib_data_offset_2  std_logic_vector ( 5 downto 0 )
calib_rank_cnt  std_logic_vector ( 1 downto 0 )
calib_cas_slot  std_logic_vector ( 1 downto 0 )
mux_address  std_logic_vector ( nCK_PER_CLK * ROW_WIDTH - 1 downto 0 )
mux_aux_out  std_logic_vector ( 3 downto 0 )
aux_out_map  std_logic_vector ( 3 downto 0 )
mux_bank  std_logic_vector ( nCK_PER_CLK * BANK_WIDTH - 1 downto 0 )
mux_cmd  std_logic_vector ( 2 downto 0 )
mux_cmd_wren  std_logic
mux_cs_n  std_logic_vector ( CS_WIDTH * nCS_PER_RANK * nCK_PER_CLK - 1 downto 0 )
mux_ctl_wren  std_logic
mux_cas_slot  std_logic_vector ( 1 downto 0 )
mux_data_offset  std_logic_vector ( 5 downto 0 )
mux_data_offset_1  std_logic_vector ( 5 downto 0 )
mux_data_offset_2  std_logic_vector ( 5 downto 0 )
mux_ras_n  std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
mux_cas_n  std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
mux_rank_cnt  std_logic_vector ( 1 downto 0 )
mux_reset_n  std_logic
mux_we_n  std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
mux_wrdata  std_logic_vector ( 2 * nCK_PER_CLK * DQ_WIDTH - 1 downto 0 )
mux_wrdata_mask  std_logic_vector ( 2 * nCK_PER_CLK * ( DQ_WIDTH / 8 ) - 1 downto 0 )
mux_wrdata_en  std_logic
mux_cke  std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
mux_odt  std_logic_vector ( 1 downto 0 )
phy_if_empty_def  std_logic
phy_if_reset  std_logic
phy_init_data_sel  std_logic
rd_data_map  std_logic_vector ( 2 * nCK_PER_CLK * DQ_WIDTH - 1 downto 0 )
phy_rddata_valid_w  std_logic
rddata_valid_reg  std_logic
rd_data_reg  std_logic_vector ( 2 * nCK_PER_CLK * DQ_WIDTH - 1 downto 0 )
idelaye2_init_val  std_logic_vector ( 4 downto 0 )
oclkdelay_init_val  std_logic_vector ( 5 downto 0 )
mc_cs_n_temp  std_logic_vector ( CS_WIDTH * nCS_PER_RANK * nCK_PER_CLK - 1 downto 0 )
calib_rd_data_offset_i0  std_logic_vector ( 6 * RANKS - 1 downto 0 )
init_wrcal_complete_i  std_logic
phy_ctl_wd_i  std_logic_vector ( 31 downto 0 )
po_counter_load_en  std_logic
parity_0_wire  std_logic_vector ( ( ROW_WIDTH + BANK_WIDTH + 3 ) - 1 downto 0 )
parity_1_wire  std_logic_vector ( ( ROW_WIDTH + BANK_WIDTH + 3 ) - 1 downto 0 )
parity_2_wire  std_logic_vector ( ( ROW_WIDTH + BANK_WIDTH + 3 ) - 1 downto 0 )
parity_3_wire  std_logic_vector ( ( ROW_WIDTH + BANK_WIDTH + 3 ) - 1 downto 0 )
dbg_pi_dqs_found_lanes_phy4lanes_i  std_logic_vector ( 11 downto 0 )
all_zeros  std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
byte_sel_cnt  std_logic_vector ( DQS_CNT_WIDTH downto 0 )
fine_delay_incdec_pb  std_logic_vector ( DRAM_WIDTH - 1 downto 0 )
fine_delay_sel  std_logic
pd_out  std_logic
pi_fine_enable  std_logic
pi_fine_inc  std_logic
pi_counter_load_en  std_logic
pi_counter_load_val  std_logic_vector ( 5 downto 0 )
pi_rst_dqs_find  std_logic_vector ( HIGHEST_BANK - 1 downto 0 )
pi_enstg2_f_div2r1  std_logic
pi_enstg2_f_div2r2  std_logic
pi_enstg2_f_div2r3  std_logic
pi_stg2_fincdec_div2r1  std_logic
pi_stg2_fincdec_div2r2  std_logic
pi_stg2_fincdec_div2r3  std_logic
pi_stg2_load_div2r1  std_logic
pi_stg2_load_div2r2  std_logic
pi_stg2_load_div2r3  std_logic
rst_stg1_cal_div2r1  std_logic_vector ( HIGHEST_BANK - 1 downto 0 )
rst_stg1_cal_div2r2  std_logic_vector ( HIGHEST_BANK - 1 downto 0 )
pi_stg2_reg_l_div2r1  std_logic_vector ( 5 downto 0 )
pi_stg2_reg_l_div2r2  std_logic_vector ( 5 downto 0 )
pi_stg2_reg_l_div2r3  std_logic_vector ( 5 downto 0 )
pi_dqs_find_rst  std_logic_vector ( HIGHEST_BANK - 1 downto 0 )
pi_stg2_fine_enable  std_logic
pi_stg2_fine_enable_r1  std_logic
pi_stg2_fine_inc  std_logic
pi_stg2_fine_inc_r1  std_logic
pi_stg2_load_en  std_logic
pi_stg2_load_en_r1  std_logic
pi_stg2_load_val  std_logic_vector ( 5 downto 0 )

Attributes

ASYNC_REG  string
ASYNC_REG  signal is " TRUE "

Instantiations

u_ddr_mc_phy_wrapper  mig_7series_v4_2_ddr_mc_phy_wrapper
u_ddr_calib_top  mig_7series_v4_2_ddr_calib_top
u_ddr_mc_phy_wrapper  mig_7series_v4_2_ddr_mc_phy_wrapper
u_ddr_calib_top  mig_7series_v4_2_ddr_calib_top
u_ddr_mc_phy_wrapper  mig_7series_v4_2_ddr_mc_phy_wrapper
u_ddr_calib_top  mig_7series_v4_2_ddr_calib_top
u_ddr_mc_phy_wrapper  mig_7series_v4_2_ddr_mc_phy_wrapper
u_ddr_calib_top  mig_7series_v4_2_ddr_calib_top
u_ddr_mc_phy_wrapper  mig_7series_v4_2_ddr_mc_phy_wrapper
u_ddr_calib_top  mig_7series_v4_2_ddr_calib_top

Detailed Description

Definition at line 371 of file mig_7series_v4_2_ddr_phy_top.vhd.

Member Function/Procedure/Process Documentation

◆ OR_BR() [1/5]

std_logic OR_BR (   inp_var in std_logic_vector  
)
Function

Definition at line 374 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CALC_nSLOTS() [1/5]

integer CALC_nSLOTS ( )
Function

Definition at line 385 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ SIM_INIT_OPTION_W() [1/5]

string SIM_INIT_OPTION_W ( )
Function

Definition at line 394 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ SIM_CAL_OPTION_W() [1/5]

string SIM_CAL_OPTION_W ( )
Function

Definition at line 406 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CALC_WRLVL_W() [1/5]

string CALC_WRLVL_W ( )
Function

Definition at line 420 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_BANK_W() [1/5]

integer HIGHEST_BANK_W ( )
Function

Definition at line 429 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B0_W() [1/5]

integer HIGHEST_LANE_B0_W ( )
Function

Definition at line 444 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B1_W() [1/5]

integer HIGHEST_LANE_B1_W ( )
Function

Definition at line 459 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B2_W() [1/5]

integer HIGHEST_LANE_B2_W ( )
Function

Definition at line 474 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B3_W() [1/5]

integer HIGHEST_LANE_B3_W ( )
Function

Definition at line 489 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B4_W() [1/5]

integer HIGHEST_LANE_B4_W ( )
Function

Definition at line 504 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_W() [1/5]

integer HIGHEST_LANE_W ( )
Function

Definition at line 519 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B0() [1/5]

integer N_CTL_LANES_B0 ( )
Function

Definition at line 534 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B1() [1/5]

integer N_CTL_LANES_B1 ( )
Function

Definition at line 547 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B2() [1/5]

integer N_CTL_LANES_B2 ( )
Function

Definition at line 560 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B3() [1/5]

integer N_CTL_LANES_B3 ( )
Function

Definition at line 573 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B4() [1/5]

integer N_CTL_LANES_B4 ( )
Function

Definition at line 586 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B0() [1/5]

std_logic CTL_BANK_B0 ( )
Function

Definition at line 599 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B1() [1/5]

std_logic CTL_BANK_B1 ( )
Function

Definition at line 611 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B2() [1/5]

std_logic CTL_BANK_B2 ( )
Function

Definition at line 623 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B3() [1/5]

std_logic CTL_BANK_B3 ( )
Function

Definition at line 635 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B4() [1/5]

std_logic CTL_BANK_B4 ( )
Function

Definition at line 647 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_W() [1/5]

std_logic_vector CTL_BANK_W ( )
Function

Definition at line 659 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ODD_PARITY() [1/5]

std_logic ODD_PARITY (   inp_var in std_logic_vector  
)
Function

Definition at line 678 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BYTE_LANE_W() [1/5]

std_logic_vector CTL_BYTE_LANE_W ( )
Function

Definition at line 726 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PI_DIV2_INCDEC_FUN() [1/5]

string PI_DIV2_INCDEC_FUN ( )
Function

Definition at line 879 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_0()

PROCESS_0 (   clk_div2  
)
Process

Definition at line 1483 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_1()

PROCESS_1 (   clk_div2  
)
Process

Definition at line 1508 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_2()

PROCESS_2 (   clk_div2  
)
Process

Definition at line 1516 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_3()

PROCESS_3 (   clk_div2  
)
Process

Definition at line 1526 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_4()

PROCESS_4 (   clk_div2  
)
Process

Definition at line 1536 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_5()

PROCESS_5 (   clk_div2  
)
Process

Definition at line 1546 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_6()

PROCESS_6 (   clk  
)
Process

Definition at line 1671 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_7()

PROCESS_7 (   mux_address ,
  mux_bank ,
  mux_cas_n ,
  mux_ras_n ,
  mux_we_n  
)
Process

Definition at line 1678 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_8()

PROCESS_8 (   clk  
)
Process

Definition at line 1695 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_9()

PROCESS_9 (   mux_address ,
  mux_bank ,
  mux_cas_n ,
  mux_ras_n ,
  mux_we_n  
)
Process

Definition at line 1702 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_10()

PROCESS_10 (   clk  
)
Process

Definition at line 1711 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_11()

PROCESS_11 (   clk  
)
Process

Definition at line 1723 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_12()

PROCESS_12 (   clk  
)
Process

Definition at line 1738 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_13()

PROCESS_13 (   phy_rddata_valid_w ,
  rd_data_map  
)
Process

Definition at line 1748 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ OR_BR() [2/5]

std_logic OR_BR (   inp_var in std_logic_vector  
)
Function

Definition at line 374 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CALC_nSLOTS() [2/5]

integer CALC_nSLOTS ( )
Function

Definition at line 385 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ SIM_INIT_OPTION_W() [2/5]

string SIM_INIT_OPTION_W ( )
Function

Definition at line 394 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ SIM_CAL_OPTION_W() [2/5]

string SIM_CAL_OPTION_W ( )
Function

Definition at line 406 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CALC_WRLVL_W() [2/5]

string CALC_WRLVL_W ( )
Function

Definition at line 420 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_BANK_W() [2/5]

integer HIGHEST_BANK_W ( )
Function

Definition at line 429 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B0_W() [2/5]

integer HIGHEST_LANE_B0_W ( )
Function

Definition at line 444 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B1_W() [2/5]

integer HIGHEST_LANE_B1_W ( )
Function

Definition at line 459 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B2_W() [2/5]

integer HIGHEST_LANE_B2_W ( )
Function

Definition at line 474 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B3_W() [2/5]

integer HIGHEST_LANE_B3_W ( )
Function

Definition at line 489 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B4_W() [2/5]

integer HIGHEST_LANE_B4_W ( )
Function

Definition at line 504 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_W() [2/5]

integer HIGHEST_LANE_W ( )
Function

Definition at line 519 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B0() [2/5]

integer N_CTL_LANES_B0 ( )
Function

Definition at line 534 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B1() [2/5]

integer N_CTL_LANES_B1 ( )
Function

Definition at line 547 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B2() [2/5]

integer N_CTL_LANES_B2 ( )
Function

Definition at line 560 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B3() [2/5]

integer N_CTL_LANES_B3 ( )
Function

Definition at line 573 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B4() [2/5]

integer N_CTL_LANES_B4 ( )
Function

Definition at line 586 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B0() [2/5]

std_logic CTL_BANK_B0 ( )
Function

Definition at line 599 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B1() [2/5]

std_logic CTL_BANK_B1 ( )
Function

Definition at line 611 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B2() [2/5]

std_logic CTL_BANK_B2 ( )
Function

Definition at line 623 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B3() [2/5]

std_logic CTL_BANK_B3 ( )
Function

Definition at line 635 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B4() [2/5]

std_logic CTL_BANK_B4 ( )
Function

Definition at line 647 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_W() [2/5]

std_logic_vector CTL_BANK_W ( )
Function

Definition at line 659 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ODD_PARITY() [2/5]

std_logic ODD_PARITY (   inp_var in std_logic_vector  
)
Function

Definition at line 678 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BYTE_LANE_W() [2/5]

std_logic_vector CTL_BYTE_LANE_W ( )
Function

Definition at line 726 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PI_DIV2_INCDEC_FUN() [2/5]

string PI_DIV2_INCDEC_FUN ( )
Function

Definition at line 879 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_14()

PROCESS_14 (   clk_div2  
)
Process

Definition at line 1483 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_15()

PROCESS_15 (   clk_div2  
)
Process

Definition at line 1508 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_16()

PROCESS_16 (   clk_div2  
)
Process

Definition at line 1516 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_17()

PROCESS_17 (   clk_div2  
)
Process

Definition at line 1526 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_18()

PROCESS_18 (   clk_div2  
)
Process

Definition at line 1536 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_19()

PROCESS_19 (   clk_div2  
)
Process

Definition at line 1546 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_20()

PROCESS_20 (   clk  
)
Process

Definition at line 1671 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_21()

PROCESS_21 (   mux_address ,
  mux_bank ,
  mux_cas_n ,
  mux_ras_n ,
  mux_we_n  
)
Process

Definition at line 1678 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_22()

PROCESS_22 (   clk  
)
Process

Definition at line 1695 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_23()

PROCESS_23 (   mux_address ,
  mux_bank ,
  mux_cas_n ,
  mux_ras_n ,
  mux_we_n  
)
Process

Definition at line 1702 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_24()

PROCESS_24 (   clk  
)
Process

Definition at line 1711 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_25()

PROCESS_25 (   clk  
)
Process

Definition at line 1723 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_26()

PROCESS_26 (   clk  
)
Process

Definition at line 1738 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_27()

PROCESS_27 (   phy_rddata_valid_w ,
  rd_data_map  
)
Process

Definition at line 1748 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ OR_BR() [3/5]

std_logic OR_BR (   inp_var in std_logic_vector  
)
Function

Definition at line 374 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CALC_nSLOTS() [3/5]

integer CALC_nSLOTS ( )
Function

Definition at line 385 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ SIM_INIT_OPTION_W() [3/5]

string SIM_INIT_OPTION_W ( )
Function

Definition at line 394 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ SIM_CAL_OPTION_W() [3/5]

string SIM_CAL_OPTION_W ( )
Function

Definition at line 406 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CALC_WRLVL_W() [3/5]

string CALC_WRLVL_W ( )
Function

Definition at line 420 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_BANK_W() [3/5]

integer HIGHEST_BANK_W ( )
Function

Definition at line 429 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B0_W() [3/5]

integer HIGHEST_LANE_B0_W ( )
Function

Definition at line 444 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B1_W() [3/5]

integer HIGHEST_LANE_B1_W ( )
Function

Definition at line 459 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B2_W() [3/5]

integer HIGHEST_LANE_B2_W ( )
Function

Definition at line 474 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B3_W() [3/5]

integer HIGHEST_LANE_B3_W ( )
Function

Definition at line 489 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B4_W() [3/5]

integer HIGHEST_LANE_B4_W ( )
Function

Definition at line 504 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_W() [3/5]

integer HIGHEST_LANE_W ( )
Function

Definition at line 519 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B0() [3/5]

integer N_CTL_LANES_B0 ( )
Function

Definition at line 534 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B1() [3/5]

integer N_CTL_LANES_B1 ( )
Function

Definition at line 547 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B2() [3/5]

integer N_CTL_LANES_B2 ( )
Function

Definition at line 560 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B3() [3/5]

integer N_CTL_LANES_B3 ( )
Function

Definition at line 573 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B4() [3/5]

integer N_CTL_LANES_B4 ( )
Function

Definition at line 586 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B0() [3/5]

std_logic CTL_BANK_B0 ( )
Function

Definition at line 599 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B1() [3/5]

std_logic CTL_BANK_B1 ( )
Function

Definition at line 611 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B2() [3/5]

std_logic CTL_BANK_B2 ( )
Function

Definition at line 623 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B3() [3/5]

std_logic CTL_BANK_B3 ( )
Function

Definition at line 635 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B4() [3/5]

std_logic CTL_BANK_B4 ( )
Function

Definition at line 647 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_W() [3/5]

std_logic_vector CTL_BANK_W ( )
Function

Definition at line 659 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ODD_PARITY() [3/5]

std_logic ODD_PARITY (   inp_var in std_logic_vector  
)
Function

Definition at line 678 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BYTE_LANE_W() [3/5]

std_logic_vector CTL_BYTE_LANE_W ( )
Function

Definition at line 726 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PI_DIV2_INCDEC_FUN() [3/5]

string PI_DIV2_INCDEC_FUN ( )
Function

Definition at line 879 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_28()

PROCESS_28 (   clk_div2  
)
Process

Definition at line 1483 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_29()

PROCESS_29 (   clk_div2  
)
Process

Definition at line 1508 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_30()

PROCESS_30 (   clk_div2  
)
Process

Definition at line 1516 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_31()

PROCESS_31 (   clk_div2  
)
Process

Definition at line 1526 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_32()

PROCESS_32 (   clk_div2  
)
Process

Definition at line 1536 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_33()

PROCESS_33 (   clk_div2  
)
Process

Definition at line 1546 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_34()

PROCESS_34 (   clk  
)
Process

Definition at line 1671 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_35()

PROCESS_35 (   mux_address ,
  mux_bank ,
  mux_cas_n ,
  mux_ras_n ,
  mux_we_n  
)
Process

Definition at line 1678 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_36()

PROCESS_36 (   clk  
)
Process

Definition at line 1695 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_37()

PROCESS_37 (   mux_address ,
  mux_bank ,
  mux_cas_n ,
  mux_ras_n ,
  mux_we_n  
)
Process

Definition at line 1702 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_38()

PROCESS_38 (   clk  
)
Process

Definition at line 1711 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_39()

PROCESS_39 (   clk  
)
Process

Definition at line 1723 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_40()

PROCESS_40 (   clk  
)
Process

Definition at line 1738 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_41()

PROCESS_41 (   phy_rddata_valid_w ,
  rd_data_map  
)
Process

Definition at line 1748 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ OR_BR() [4/5]

std_logic OR_BR (   inp_var in std_logic_vector  
)
Function

Definition at line 374 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CALC_nSLOTS() [4/5]

integer CALC_nSLOTS ( )
Function

Definition at line 385 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ SIM_INIT_OPTION_W() [4/5]

string SIM_INIT_OPTION_W ( )
Function

Definition at line 394 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ SIM_CAL_OPTION_W() [4/5]

string SIM_CAL_OPTION_W ( )
Function

Definition at line 406 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CALC_WRLVL_W() [4/5]

string CALC_WRLVL_W ( )
Function

Definition at line 420 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_BANK_W() [4/5]

integer HIGHEST_BANK_W ( )
Function

Definition at line 429 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B0_W() [4/5]

integer HIGHEST_LANE_B0_W ( )
Function

Definition at line 444 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B1_W() [4/5]

integer HIGHEST_LANE_B1_W ( )
Function

Definition at line 459 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B2_W() [4/5]

integer HIGHEST_LANE_B2_W ( )
Function

Definition at line 474 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B3_W() [4/5]

integer HIGHEST_LANE_B3_W ( )
Function

Definition at line 489 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B4_W() [4/5]

integer HIGHEST_LANE_B4_W ( )
Function

Definition at line 504 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_W() [4/5]

integer HIGHEST_LANE_W ( )
Function

Definition at line 519 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B0() [4/5]

integer N_CTL_LANES_B0 ( )
Function

Definition at line 534 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B1() [4/5]

integer N_CTL_LANES_B1 ( )
Function

Definition at line 547 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B2() [4/5]

integer N_CTL_LANES_B2 ( )
Function

Definition at line 560 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B3() [4/5]

integer N_CTL_LANES_B3 ( )
Function

Definition at line 573 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B4() [4/5]

integer N_CTL_LANES_B4 ( )
Function

Definition at line 586 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B0() [4/5]

std_logic CTL_BANK_B0 ( )
Function

Definition at line 599 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B1() [4/5]

std_logic CTL_BANK_B1 ( )
Function

Definition at line 611 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B2() [4/5]

std_logic CTL_BANK_B2 ( )
Function

Definition at line 623 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B3() [4/5]

std_logic CTL_BANK_B3 ( )
Function

Definition at line 635 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B4() [4/5]

std_logic CTL_BANK_B4 ( )
Function

Definition at line 647 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_W() [4/5]

std_logic_vector CTL_BANK_W ( )
Function

Definition at line 659 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ODD_PARITY() [4/5]

std_logic ODD_PARITY (   inp_var in std_logic_vector  
)
Function

Definition at line 678 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BYTE_LANE_W() [4/5]

std_logic_vector CTL_BYTE_LANE_W ( )
Function

Definition at line 726 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PI_DIV2_INCDEC_FUN() [4/5]

string PI_DIV2_INCDEC_FUN ( )
Function

Definition at line 879 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_42()

PROCESS_42 (   clk_div2  
)
Process

Definition at line 1483 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_43()

PROCESS_43 (   clk_div2  
)
Process

Definition at line 1508 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_44()

PROCESS_44 (   clk_div2  
)
Process

Definition at line 1516 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_45()

PROCESS_45 (   clk_div2  
)
Process

Definition at line 1526 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_46()

PROCESS_46 (   clk_div2  
)
Process

Definition at line 1536 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_47()

PROCESS_47 (   clk_div2  
)
Process

Definition at line 1546 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_48()

PROCESS_48 (   clk  
)
Process

Definition at line 1671 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_49()

PROCESS_49 (   mux_address ,
  mux_bank ,
  mux_cas_n ,
  mux_ras_n ,
  mux_we_n  
)
Process

Definition at line 1678 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_50()

PROCESS_50 (   clk  
)
Process

Definition at line 1695 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_51()

PROCESS_51 (   mux_address ,
  mux_bank ,
  mux_cas_n ,
  mux_ras_n ,
  mux_we_n  
)
Process

Definition at line 1702 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_52()

PROCESS_52 (   clk  
)
Process

Definition at line 1711 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_53()

PROCESS_53 (   clk  
)
Process

Definition at line 1723 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_54()

PROCESS_54 (   clk  
)
Process

Definition at line 1738 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_55()

PROCESS_55 (   phy_rddata_valid_w ,
  rd_data_map  
)
Process

Definition at line 1748 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ OR_BR() [5/5]

std_logic OR_BR (   inp_var in std_logic_vector  
)
Function

Definition at line 374 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CALC_nSLOTS() [5/5]

integer CALC_nSLOTS ( )
Function

Definition at line 385 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ SIM_INIT_OPTION_W() [5/5]

string SIM_INIT_OPTION_W ( )
Function

Definition at line 394 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ SIM_CAL_OPTION_W() [5/5]

string SIM_CAL_OPTION_W ( )
Function

Definition at line 406 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CALC_WRLVL_W() [5/5]

string CALC_WRLVL_W ( )
Function

Definition at line 420 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_BANK_W() [5/5]

integer HIGHEST_BANK_W ( )
Function

Definition at line 429 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B0_W() [5/5]

integer HIGHEST_LANE_B0_W ( )
Function

Definition at line 444 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B1_W() [5/5]

integer HIGHEST_LANE_B1_W ( )
Function

Definition at line 459 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B2_W() [5/5]

integer HIGHEST_LANE_B2_W ( )
Function

Definition at line 474 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B3_W() [5/5]

integer HIGHEST_LANE_B3_W ( )
Function

Definition at line 489 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_B4_W() [5/5]

integer HIGHEST_LANE_B4_W ( )
Function

Definition at line 504 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE_W() [5/5]

integer HIGHEST_LANE_W ( )
Function

Definition at line 519 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B0() [5/5]

integer N_CTL_LANES_B0 ( )
Function

Definition at line 534 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B1() [5/5]

integer N_CTL_LANES_B1 ( )
Function

Definition at line 547 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B2() [5/5]

integer N_CTL_LANES_B2 ( )
Function

Definition at line 560 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B3() [5/5]

integer N_CTL_LANES_B3 ( )
Function

Definition at line 573 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES_B4() [5/5]

integer N_CTL_LANES_B4 ( )
Function

Definition at line 586 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B0() [5/5]

std_logic CTL_BANK_B0 ( )
Function

Definition at line 599 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B1() [5/5]

std_logic CTL_BANK_B1 ( )
Function

Definition at line 611 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B2() [5/5]

std_logic CTL_BANK_B2 ( )
Function

Definition at line 623 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B3() [5/5]

std_logic CTL_BANK_B3 ( )
Function

Definition at line 635 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_B4() [5/5]

std_logic CTL_BANK_B4 ( )
Function

Definition at line 647 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK_W() [5/5]

std_logic_vector CTL_BANK_W ( )
Function

Definition at line 659 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ODD_PARITY() [5/5]

std_logic ODD_PARITY (   inp_var in std_logic_vector  
)
Function

Definition at line 678 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BYTE_LANE_W() [5/5]

std_logic_vector CTL_BYTE_LANE_W ( )
Function

Definition at line 726 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PI_DIV2_INCDEC_FUN() [5/5]

string PI_DIV2_INCDEC_FUN ( )
Function

Definition at line 879 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_56()

PROCESS_56 (   clk_div2  
)
Process

Definition at line 1483 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_57()

PROCESS_57 (   clk_div2  
)
Process

Definition at line 1508 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_58()

PROCESS_58 (   clk_div2  
)
Process

Definition at line 1516 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_59()

PROCESS_59 (   clk_div2  
)
Process

Definition at line 1526 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_60()

PROCESS_60 (   clk_div2  
)
Process

Definition at line 1536 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_61()

PROCESS_61 (   clk_div2  
)
Process

Definition at line 1546 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_62()

PROCESS_62 (   clk  
)
Process

Definition at line 1671 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_63()

PROCESS_63 (   mux_address ,
  mux_bank ,
  mux_cas_n ,
  mux_ras_n ,
  mux_we_n  
)
Process

Definition at line 1678 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_64()

PROCESS_64 (   clk  
)
Process

Definition at line 1695 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_65()

PROCESS_65 (   mux_address ,
  mux_bank ,
  mux_cas_n ,
  mux_ras_n ,
  mux_we_n  
)
Process

Definition at line 1702 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_66()

PROCESS_66 (   clk  
)
Process

Definition at line 1711 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_67()

PROCESS_67 (   clk  
)
Process

Definition at line 1723 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_68()

PROCESS_68 (   clk  
)
Process

Definition at line 1738 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PROCESS_69()

PROCESS_69 (   phy_rddata_valid_w ,
  rd_data_map  
)
Process

Definition at line 1748 of file mig_7series_v4_2_ddr_phy_top.vhd.

Member Data Documentation

◆ nSLOTS

nSLOTS integer := CALC_nSLOTS
Constant

Definition at line 688 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CLK_PERIOD

CLK_PERIOD integer := tCK * nCK_PER_CLK
Constant

Definition at line 689 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ SIM_INIT_OPTION

SIM_INIT_OPTION string := SIM_INIT_OPTION_W
Constant

Definition at line 705 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ SIM_CAL_OPTION

SIM_CAL_OPTION string := SIM_CAL_OPTION_W
Constant

Definition at line 706 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ WRLVL_W

WRLVL_W string := CALC_WRLVL_W
Constant

Definition at line 707 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_BANK

HIGHEST_BANK integer := HIGHEST_BANK_W
Constant

Definition at line 709 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ HIGHEST_LANE

HIGHEST_LANE integer := HIGHEST_LANE_W
Constant

Definition at line 717 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ N_CTL_LANES

N_CTL_LANES integer := N_CTL_LANES_B0+ N_CTL_LANES_B1+ N_CTL_LANES_B2+ N_CTL_LANES_B3+ N_CTL_LANES_B4
Constant

Definition at line 719 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BANK

CTL_BANK std_logic_vector ( 2 downto 0 ) := CTL_BANK_W
Constant

Definition at line 724 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ CTL_BYTE_LANE

CTL_BYTE_LANE std_logic_vector ( 7 downto 0 ) := CTL_BYTE_LANE_W
Constant

Definition at line 877 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ PI_DIV2_INCDEC

PI_DIV2_INCDEC string := PI_DIV2_INCDEC_FUN
Constant

Definition at line 890 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mig_7series_v4_2_ddr_mc_phy_wrapper

mig_7series_v4_2_ddr_mc_phy_wrapper
Component

Definition at line 892 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mig_7series_v4_2_ddr_calib_top

mig_7series_v4_2_ddr_calib_top
Component

Definition at line 1078 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_din

phy_din std_logic_vector ( HIGHEST_LANE * 80 - 1 downto 0 )
Signal

Definition at line 1297 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_dout

phy_dout std_logic_vector ( HIGHEST_LANE * 80 - 1 downto 0 )
Signal

Definition at line 1298 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_cmd_ctl_data

ddr_cmd_ctl_data std_logic_vector ( HIGHEST_LANE * 12 - 1 downto 0 )
Signal

Definition at line 1299 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ aux_out

aux_out std_logic_vector ( ( ( ( HIGHEST_LANE + 3 ) / 4 ) * 4 ) - 1 downto 0 )
Signal

Definition at line 1300 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ddr_clk

ddr_clk std_logic_vector ( CK_WIDTH * LP_DDR_CK_WIDTH - 1 downto 0 )
Signal

Definition at line 1301 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_mc_go

phy_mc_go std_logic
Signal

Definition at line 1302 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_ctl_full

phy_ctl_full std_logic
Signal

Definition at line 1303 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_cmd_full

phy_cmd_full std_logic
Signal

Definition at line 1304 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_data_full

phy_data_full std_logic
Signal

Definition at line 1305 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_pre_data_a_full

phy_pre_data_a_full std_logic
Signal

Definition at line 1306 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ if_empty

if_empty std_logic
Signal

Definition at line 1307 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_write_calib

phy_write_calib std_logic
Signal

Definition at line 1308 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_read_calib

phy_read_calib std_logic
Signal

Definition at line 1309 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ rst_stg1_cal

rst_stg1_cal std_logic_vector ( HIGHEST_BANK - 1 downto 0 )
Signal

Definition at line 1310 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_sel

calib_sel std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1311 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_in_common

calib_in_common std_logic
Signal

Definition at line 1312 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_zero_inputs

calib_zero_inputs std_logic_vector ( HIGHEST_BANK - 1 downto 0 )
Signal

Definition at line 1313 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_zero_ctrl

calib_zero_ctrl std_logic_vector ( HIGHEST_BANK - 1 downto 0 )
Signal

Definition at line 1314 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_phase_locked

pi_phase_locked std_logic
Signal

Definition at line 1315 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_phase_locked_all

pi_phase_locked_all std_logic
Signal

Definition at line 1316 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_found_dqs

pi_found_dqs std_logic
Signal

Definition at line 1317 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_dqs_found_all

pi_dqs_found_all std_logic
Signal

Definition at line 1318 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_dqs_out_of_range

pi_dqs_out_of_range std_logic
Signal

Definition at line 1319 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_enstg2_f

pi_enstg2_f std_logic
Signal

Definition at line 1320 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_fincdec

pi_stg2_fincdec std_logic
Signal

Definition at line 1321 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_load

pi_stg2_load std_logic
Signal

Definition at line 1322 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_reg_l

pi_stg2_reg_l std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1323 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ idelay_ce

idelay_ce std_logic
Signal

Definition at line 1324 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ idelay_inc

idelay_inc std_logic
Signal

Definition at line 1325 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ idelay_ld

idelay_ld std_logic
Signal

Definition at line 1326 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ po_sel_stg2stg3

po_sel_stg2stg3 std_logic_vector ( 2 downto 0 )
Signal

Definition at line 1327 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ po_stg2_cincdec

po_stg2_cincdec std_logic_vector ( 2 downto 0 )
Signal

Definition at line 1328 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ po_enstg2_c

po_enstg2_c std_logic_vector ( 2 downto 0 )
Signal

Definition at line 1329 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ po_stg2_fincdec

po_stg2_fincdec std_logic_vector ( 2 downto 0 )
Signal

Definition at line 1330 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ po_enstg2_f

po_enstg2_f std_logic_vector ( 2 downto 0 )
Signal

Definition at line 1331 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ po_counter_read_val

po_counter_read_val std_logic_vector ( 8 downto 0 )
Signal

Definition at line 1332 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_counter_read_val

pi_counter_read_val std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1333 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_wrdata

phy_wrdata std_logic_vector ( 2 * nCK_PER_CLK * DQ_WIDTH - 1 downto 0 )
Signal

Definition at line 1334 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ parity

parity std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
Signal

Definition at line 1335 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_address

phy_address std_logic_vector ( nCK_PER_CLK * ROW_WIDTH - 1 downto 0 )
Signal

Definition at line 1336 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_bank

phy_bank std_logic_vector ( nCK_PER_CLK * BANK_WIDTH - 1 downto 0 )
Signal

Definition at line 1337 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_cs_n

phy_cs_n std_logic_vector ( CS_WIDTH * nCS_PER_RANK * nCK_PER_CLK - 1 downto 0 )
Signal

Definition at line 1338 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_ras_n

phy_ras_n std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
Signal

Definition at line 1339 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_cas_n

phy_cas_n std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
Signal

Definition at line 1340 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_we_n

phy_we_n std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
Signal

Definition at line 1341 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_reset_n

phy_reset_n std_logic
Signal

Definition at line 1342 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_aux_out

calib_aux_out std_logic_vector ( 3 downto 0 )
Signal

Definition at line 1343 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_cke

calib_cke std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
Signal

Definition at line 1344 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_odt

calib_odt std_logic_vector ( 1 downto 0 )
Signal

Definition at line 1345 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_ctl_wren

calib_ctl_wren std_logic
Signal

Definition at line 1346 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_cmd_wren

calib_cmd_wren std_logic
Signal

Definition at line 1347 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_wrdata_en

calib_wrdata_en std_logic
Signal

Definition at line 1348 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_cmd

calib_cmd std_logic_vector ( 2 downto 0 )
Signal

Definition at line 1349 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_seq

calib_seq std_logic_vector ( 1 downto 0 )
Signal

Definition at line 1350 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_data_offset_0

calib_data_offset_0 std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1351 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_data_offset_1

calib_data_offset_1 std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1352 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_data_offset_2

calib_data_offset_2 std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1353 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_rank_cnt

calib_rank_cnt std_logic_vector ( 1 downto 0 )
Signal

Definition at line 1354 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_cas_slot

calib_cas_slot std_logic_vector ( 1 downto 0 )
Signal

Definition at line 1355 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_address

mux_address std_logic_vector ( nCK_PER_CLK * ROW_WIDTH - 1 downto 0 )
Signal

Definition at line 1356 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_aux_out

mux_aux_out std_logic_vector ( 3 downto 0 )
Signal

Definition at line 1357 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ aux_out_map

aux_out_map std_logic_vector ( 3 downto 0 )
Signal

Definition at line 1358 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_bank

mux_bank std_logic_vector ( nCK_PER_CLK * BANK_WIDTH - 1 downto 0 )
Signal

Definition at line 1359 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_cmd

mux_cmd std_logic_vector ( 2 downto 0 )
Signal

Definition at line 1360 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_cmd_wren

mux_cmd_wren std_logic
Signal

Definition at line 1361 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_cs_n

mux_cs_n std_logic_vector ( CS_WIDTH * nCS_PER_RANK * nCK_PER_CLK - 1 downto 0 )
Signal

Definition at line 1362 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_ctl_wren

mux_ctl_wren std_logic
Signal

Definition at line 1363 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_cas_slot

mux_cas_slot std_logic_vector ( 1 downto 0 )
Signal

Definition at line 1364 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_data_offset

mux_data_offset std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1365 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_data_offset_1

mux_data_offset_1 std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1366 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_data_offset_2

mux_data_offset_2 std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1367 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_ras_n

mux_ras_n std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
Signal

Definition at line 1368 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_cas_n

mux_cas_n std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
Signal

Definition at line 1369 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_rank_cnt

mux_rank_cnt std_logic_vector ( 1 downto 0 )
Signal

Definition at line 1370 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_reset_n

mux_reset_n std_logic
Signal

Definition at line 1371 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_we_n

mux_we_n std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
Signal

Definition at line 1372 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_wrdata

mux_wrdata std_logic_vector ( 2 * nCK_PER_CLK * DQ_WIDTH - 1 downto 0 )
Signal

Definition at line 1373 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_wrdata_mask

mux_wrdata_mask std_logic_vector ( 2 * nCK_PER_CLK * ( DQ_WIDTH / 8 ) - 1 downto 0 )
Signal

Definition at line 1374 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_wrdata_en

mux_wrdata_en std_logic
Signal

Definition at line 1375 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_cke

mux_cke std_logic_vector ( nCK_PER_CLK - 1 downto 0 )
Signal

Definition at line 1376 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mux_odt

mux_odt std_logic_vector ( 1 downto 0 )
Signal

Definition at line 1377 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_if_empty_def

phy_if_empty_def std_logic
Signal

Definition at line 1378 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_if_reset

phy_if_reset std_logic
Signal

Definition at line 1379 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_init_data_sel

phy_init_data_sel std_logic
Signal

Definition at line 1380 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ rd_data_map

rd_data_map std_logic_vector ( 2 * nCK_PER_CLK * DQ_WIDTH - 1 downto 0 )
Signal

Definition at line 1381 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_rddata_valid_w

phy_rddata_valid_w std_logic
Signal

Definition at line 1382 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ rddata_valid_reg

rddata_valid_reg std_logic
Signal

Definition at line 1383 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ rd_data_reg

rd_data_reg std_logic_vector ( 2 * nCK_PER_CLK * DQ_WIDTH - 1 downto 0 )
Signal

Definition at line 1384 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ idelaye2_init_val

idelaye2_init_val std_logic_vector ( 4 downto 0 )
Signal

Definition at line 1385 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ oclkdelay_init_val

oclkdelay_init_val std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1386 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ mc_cs_n_temp

mc_cs_n_temp std_logic_vector ( CS_WIDTH * nCS_PER_RANK * nCK_PER_CLK - 1 downto 0 )
Signal

Definition at line 1388 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ calib_rd_data_offset_i0

calib_rd_data_offset_i0 std_logic_vector ( 6 * RANKS - 1 downto 0 )
Signal

Definition at line 1390 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ init_wrcal_complete_i

init_wrcal_complete_i std_logic
Signal

Definition at line 1391 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ phy_ctl_wd_i

phy_ctl_wd_i std_logic_vector ( 31 downto 0 )
Signal

Definition at line 1392 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ po_counter_load_en

po_counter_load_en std_logic
Signal

Definition at line 1393 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ parity_0_wire

parity_0_wire std_logic_vector ( ( ROW_WIDTH + BANK_WIDTH + 3 ) - 1 downto 0 )
Signal

Definition at line 1394 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ parity_1_wire

parity_1_wire std_logic_vector ( ( ROW_WIDTH + BANK_WIDTH + 3 ) - 1 downto 0 )
Signal

Definition at line 1395 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ parity_2_wire

parity_2_wire std_logic_vector ( ( ROW_WIDTH + BANK_WIDTH + 3 ) - 1 downto 0 )
Signal

Definition at line 1396 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ parity_3_wire

parity_3_wire std_logic_vector ( ( ROW_WIDTH + BANK_WIDTH + 3 ) - 1 downto 0 )
Signal

Definition at line 1397 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ dbg_pi_dqs_found_lanes_phy4lanes_i

dbg_pi_dqs_found_lanes_phy4lanes_i std_logic_vector ( 11 downto 0 )
Signal

Definition at line 1398 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ all_zeros

all_zeros std_logic_vector ( 8 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 1399 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ byte_sel_cnt

byte_sel_cnt std_logic_vector ( DQS_CNT_WIDTH downto 0 )
Signal

Definition at line 1401 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ fine_delay_incdec_pb

fine_delay_incdec_pb std_logic_vector ( DRAM_WIDTH - 1 downto 0 )
Signal

Definition at line 1402 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ fine_delay_sel

fine_delay_sel std_logic
Signal

Definition at line 1403 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pd_out

pd_out std_logic
Signal

Definition at line 1404 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_fine_enable

pi_fine_enable std_logic
Signal

Definition at line 1407 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_fine_inc

pi_fine_inc std_logic
Signal

Definition at line 1408 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_counter_load_en

pi_counter_load_en std_logic
Signal

Definition at line 1409 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_counter_load_val

pi_counter_load_val std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1410 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_rst_dqs_find

pi_rst_dqs_find std_logic_vector ( HIGHEST_BANK - 1 downto 0 )
Signal

Definition at line 1411 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_enstg2_f_div2r1

pi_enstg2_f_div2r1 std_logic
Signal

Definition at line 1412 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_enstg2_f_div2r2

pi_enstg2_f_div2r2 std_logic
Signal

Definition at line 1413 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_enstg2_f_div2r3

pi_enstg2_f_div2r3 std_logic
Signal

Definition at line 1414 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_fincdec_div2r1

pi_stg2_fincdec_div2r1 std_logic
Signal

Definition at line 1415 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_fincdec_div2r2

pi_stg2_fincdec_div2r2 std_logic
Signal

Definition at line 1416 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_fincdec_div2r3

pi_stg2_fincdec_div2r3 std_logic
Signal

Definition at line 1417 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_load_div2r1

pi_stg2_load_div2r1 std_logic
Signal

Definition at line 1418 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_load_div2r2

pi_stg2_load_div2r2 std_logic
Signal

Definition at line 1419 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_load_div2r3

pi_stg2_load_div2r3 std_logic
Signal

Definition at line 1420 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ rst_stg1_cal_div2r1

rst_stg1_cal_div2r1 std_logic_vector ( HIGHEST_BANK - 1 downto 0 )
Signal

Definition at line 1421 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ rst_stg1_cal_div2r2

rst_stg1_cal_div2r2 std_logic_vector ( HIGHEST_BANK - 1 downto 0 )
Signal

Definition at line 1422 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_reg_l_div2r1

pi_stg2_reg_l_div2r1 std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1423 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_reg_l_div2r2

pi_stg2_reg_l_div2r2 std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1424 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_reg_l_div2r3

pi_stg2_reg_l_div2r3 std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1425 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_dqs_find_rst

pi_dqs_find_rst std_logic_vector ( HIGHEST_BANK - 1 downto 0 )
Signal

Definition at line 1426 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ASYNC_REG [1/2]

ASYNC_REG string
Attribute

Definition at line 1428 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ ASYNC_REG [2/2]

ASYNC_REG signal is " TRUE "
Attribute

Definition at line 1429 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_fine_enable

pi_stg2_fine_enable std_logic
Signal

Definition at line 1450 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_fine_enable_r1

pi_stg2_fine_enable_r1 std_logic
Signal

Definition at line 1450 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_fine_inc

pi_stg2_fine_inc std_logic
Signal

Definition at line 1451 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_fine_inc_r1

pi_stg2_fine_inc_r1 std_logic
Signal

Definition at line 1451 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_load_en

pi_stg2_load_en std_logic
Signal

Definition at line 1452 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_load_en_r1

pi_stg2_load_en_r1 std_logic
Signal

Definition at line 1452 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ pi_stg2_load_val

pi_stg2_load_val std_logic_vector ( 5 downto 0 )
Signal

Definition at line 1453 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ u_ddr_mc_phy_wrapper [1/5]

u_ddr_mc_phy_wrapper mig_7series_v4_2_ddr_mc_phy_wrapper
Instantiation

Definition at line 1960 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ u_ddr_calib_top [1/5]

u_ddr_calib_top mig_7series_v4_2_ddr_calib_top
Instantiation

Definition at line 2202 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ u_ddr_mc_phy_wrapper [2/5]

u_ddr_mc_phy_wrapper mig_7series_v4_2_ddr_mc_phy_wrapper
Instantiation

Definition at line 1960 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ u_ddr_calib_top [2/5]

u_ddr_calib_top mig_7series_v4_2_ddr_calib_top
Instantiation

Definition at line 2202 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ u_ddr_mc_phy_wrapper [3/5]

u_ddr_mc_phy_wrapper mig_7series_v4_2_ddr_mc_phy_wrapper
Instantiation

Definition at line 1960 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ u_ddr_calib_top [3/5]

u_ddr_calib_top mig_7series_v4_2_ddr_calib_top
Instantiation

Definition at line 2202 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ u_ddr_mc_phy_wrapper [4/5]

u_ddr_mc_phy_wrapper mig_7series_v4_2_ddr_mc_phy_wrapper
Instantiation

Definition at line 1960 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ u_ddr_calib_top [4/5]

u_ddr_calib_top mig_7series_v4_2_ddr_calib_top
Instantiation

Definition at line 2202 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ u_ddr_mc_phy_wrapper [5/5]

u_ddr_mc_phy_wrapper mig_7series_v4_2_ddr_mc_phy_wrapper
Instantiation

Definition at line 1960 of file mig_7series_v4_2_ddr_phy_top.vhd.

◆ u_ddr_calib_top [5/5]

u_ddr_calib_top mig_7series_v4_2_ddr_calib_top
Instantiation

Definition at line 2202 of file mig_7series_v4_2_ddr_phy_top.vhd.

The documentation for this design unit was generated from the following files: