sim Architecture Reference

Architecture >> sim

Processes
proc_simbus	( SB_VAL )

Constants
sbaddr_swi	slv8 := slv ( to_unsigned ( 16 , 8 ) )
sbaddr_btn	slv8 := slv ( to_unsigned ( 17 , 8 ) )

Signals
R_SWI	slv4 := ( others = > ' 0 ' )
R_BTN	slv4 := ( others = > ' 0 ' )

Detailed Description

Definition at line 36 of file tb_artys7_core.vhd.

Member Function/Procedure/Process Documentation

proc_simbus()

proc_simbus (   SB_VAL   )

Process

Definition at line 46 of file tb_artys7_core.vhd.

Member Data Documentation

R_SWI

R_SWI slv4 := ( others = > ' 0 ' )

Signal

Definition at line 38 of file tb_artys7_core.vhd.

R_BTN

R_BTN slv4 := ( others = > ' 0 ' )

Signal

Definition at line 39 of file tb_artys7_core.vhd.

sbaddr_swi

sbaddr_swi slv8 := slv ( to_unsigned ( 16 , 8 ) )

Constant

Definition at line 41 of file tb_artys7_core.vhd.

sbaddr_btn

sbaddr_btn slv8 := slv ( to_unsigned ( 17 , 8 ) )

Constant

Definition at line 42 of file tb_artys7_core.vhd.

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The documentation for this design unit was generated from the following file:

• bplib/artys7/tb/tb_artys7_core.vhd