w11 - vhd 0.794
W11 CPU core and support modules
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Instantiations | Signals
syn Architecture Reference
Architecture >> syn

Signals

CLK  slbit := ' 0 '
RESET  slbit := ' 0 '
CE_USEC  slbit := ' 0 '
CE_MSEC  slbit := ' 0 '
RXD  slbit := ' 0 '
TXD  slbit := ' 0 '
SWI  slv16 := ( others = > ' 0 ' )
BTN  slv5 := ( others = > ' 0 ' )
LED  slv16 := ( others = > ' 0 ' )
DSP_DAT  slv16 := ( others = > ' 0 ' )
DSP_DP  slv4 := ( others = > ' 0 ' )
HIO_CNTL  hio_cntl_type := hio_cntl_init
HIO_STAT  hio_stat_type := hio_stat_init
RXDATA  slv8 := ( others = > ' 0 ' )
RXVAL  slbit := ' 0 '
RXHOLD  slbit := ' 0 '
TXDATA  slv8 := ( others = > ' 0 ' )
TXENA  slbit := ' 0 '
TXBUSY  slbit := ' 0 '
SER_MONI  serport_moni_type := serport_moni_init

Instantiations

gen_clksys  s7_cmt_sfs <Entity s7_cmt_sfs>
clkdiv  clkdivce <Entity clkdivce>
hio  sn_humanio <Entity sn_humanio>
hiomap  tst_serloop_hiomap <Entity tst_serloop_hiomap>
iob_rs232  bp_rs232_2line_iob <Entity bp_rs232_2line_iob>
serport  serport_1clock <Entity serport_1clock>
tester  tst_serloop <Entity tst_serloop>

Detailed Description

Definition at line 60 of file sys_tst_serloop1_b3.vhd.

Member Data Documentation

◆ CLK

CLK slbit := ' 0 '
Signal

Definition at line 62 of file sys_tst_serloop1_b3.vhd.

◆ RESET

RESET slbit := ' 0 '
Signal

Definition at line 63 of file sys_tst_serloop1_b3.vhd.

◆ CE_USEC

CE_USEC slbit := ' 0 '
Signal

Definition at line 65 of file sys_tst_serloop1_b3.vhd.

◆ CE_MSEC

CE_MSEC slbit := ' 0 '
Signal

Definition at line 66 of file sys_tst_serloop1_b3.vhd.

◆ RXD

RXD slbit := ' 0 '
Signal

Definition at line 68 of file sys_tst_serloop1_b3.vhd.

◆ TXD

TXD slbit := ' 0 '
Signal

Definition at line 69 of file sys_tst_serloop1_b3.vhd.

◆ SWI

SWI slv16 := ( others = > ' 0 ' )
Signal

Definition at line 71 of file sys_tst_serloop1_b3.vhd.

◆ BTN

BTN slv5 := ( others = > ' 0 ' )
Signal

Definition at line 72 of file sys_tst_serloop1_b3.vhd.

◆ LED

LED slv16 := ( others = > ' 0 ' )
Signal

Definition at line 73 of file sys_tst_serloop1_b3.vhd.

◆ DSP_DAT

DSP_DAT slv16 := ( others = > ' 0 ' )
Signal

Definition at line 74 of file sys_tst_serloop1_b3.vhd.

◆ DSP_DP

DSP_DP slv4 := ( others = > ' 0 ' )
Signal

Definition at line 75 of file sys_tst_serloop1_b3.vhd.

◆ HIO_CNTL

HIO_CNTL hio_cntl_type := hio_cntl_init
Signal

Definition at line 77 of file sys_tst_serloop1_b3.vhd.

◆ HIO_STAT

HIO_STAT hio_stat_type := hio_stat_init
Signal

Definition at line 78 of file sys_tst_serloop1_b3.vhd.

◆ RXDATA

RXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 80 of file sys_tst_serloop1_b3.vhd.

◆ RXVAL

RXVAL slbit := ' 0 '
Signal

Definition at line 81 of file sys_tst_serloop1_b3.vhd.

◆ RXHOLD

RXHOLD slbit := ' 0 '
Signal

Definition at line 82 of file sys_tst_serloop1_b3.vhd.

◆ TXDATA

TXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 83 of file sys_tst_serloop1_b3.vhd.

◆ TXENA

TXENA slbit := ' 0 '
Signal

Definition at line 84 of file sys_tst_serloop1_b3.vhd.

◆ TXBUSY

TXBUSY slbit := ' 0 '
Signal

Definition at line 85 of file sys_tst_serloop1_b3.vhd.

◆ SER_MONI

SER_MONI serport_moni_type := serport_moni_init
Signal

Definition at line 87 of file sys_tst_serloop1_b3.vhd.

◆ gen_clksys

gen_clksys s7_cmt_sfs
Instantiation

Definition at line 104 of file sys_tst_serloop1_b3.vhd.

◆ clkdiv

clkdiv clkdivce
Instantiation

Definition at line 115 of file sys_tst_serloop1_b3.vhd.

◆ hio

hio sn_humanio
Instantiation

Definition at line 137 of file sys_tst_serloop1_b3.vhd.

◆ hiomap

hiomap tst_serloop_hiomap
Instantiation

Definition at line 153 of file sys_tst_serloop1_b3.vhd.

◆ iob_rs232

iob_rs232 bp_rs232_2line_iob
Instantiation

Definition at line 162 of file sys_tst_serloop1_b3.vhd.

◆ serport

serport serport_1clock
Instantiation

Definition at line 187 of file sys_tst_serloop1_b3.vhd.

◆ tester

tester tst_serloop
Instantiation

Definition at line 203 of file sys_tst_serloop1_b3.vhd.

The documentation for this design unit was generated from the following file: