w11 - vhd 0.794
W11 CPU core and support modules
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Constants | Processes | Records | Signals | Types
syn Architecture Reference
Architecture >> syn

Processes

proc_regs  ( CLK )
proc_next  ( R_REGS , CHEX , CDP )
proc_mux  ( R_REGS , DIN , DP )

Constants

regs_init  regs_type := ( slv ( to_unsigned ( 0 , CDWIDTH ) ) , slv ( to_unsigned ( 0 , DCWIDTH ) ) )
hex2segtbl  hex2segtbl_type := ( " 0111111 " , " 0000110 " , " 1011011 " , " 1001111 " , " 1100110 " , " 1101101 " , " 1111101 " , " 0000111 " , " 1111111 " , " 1101111 " , " 1110111 " , " 1111100 " , " 0111001 " , " 1011110 " , " 1111001 " , " 1110001 " )

Types

hex2segtbl_type  ( 0 to 15 ) slv7

Signals

R_REGS  regs_type := regs_init
N_REGS  regs_type := regs_init
CHEX  slv4 := ( others = > ' 0 ' )
CDP  slbit := ' 0 '

Records

regs_type 
cdiv slv ( CDWIDTH - 1 downto 0 )
dcnt slv ( DCWIDTH - 1 downto 0 )

Detailed Description

Definition at line 53 of file sn_7segctl.vhd.

Member Function/Procedure/Process Documentation

◆ proc_regs()

proc_regs (   CLK  
)
Process

Definition at line 100 of file sn_7segctl.vhd.

◆ proc_next()

proc_next (   R_REGS ,
  CHEX ,
  CDP  
)
Process

Definition at line 110 of file sn_7segctl.vhd.

◆ proc_mux()

proc_mux (   R_REGS ,
  DIN ,
  DP  
)
Process

Definition at line 149 of file sn_7segctl.vhd.

Member Data Documentation

◆ regs_type

regs_type
Record

Definition at line 54 of file sn_7segctl.vhd.

◆ cdiv

cdiv slv ( CDWIDTH - 1 downto 0 )
Record

Definition at line 55 of file sn_7segctl.vhd.

◆ dcnt

dcnt slv ( DCWIDTH - 1 downto 0 )
Record

Definition at line 56 of file sn_7segctl.vhd.

◆ regs_init

regs_init regs_type := ( slv ( to_unsigned ( 0 , CDWIDTH ) ) , slv ( to_unsigned ( 0 , DCWIDTH ) ) )
Constant

Definition at line 59 of file sn_7segctl.vhd.

◆ hex2segtbl_type

hex2segtbl_type ( 0 to 15 ) slv7
Type

Definition at line 64 of file sn_7segctl.vhd.

◆ hex2segtbl

hex2segtbl hex2segtbl_type := ( " 0111111 " , " 0000110 " , " 1011011 " , " 1001111 " , " 1100110 " , " 1101101 " , " 1111101 " , " 0000111 " , " 1111111 " , " 1101111 " , " 1110111 " , " 1111100 " , " 0111001 " , " 1011110 " , " 1111001 " , " 1110001 " )
Constant

Definition at line 66 of file sn_7segctl.vhd.

◆ R_REGS

R_REGS regs_type := regs_init
Signal

Definition at line 85 of file sn_7segctl.vhd.

◆ N_REGS

N_REGS regs_type := regs_init
Signal

Definition at line 86 of file sn_7segctl.vhd.

◆ CHEX

CHEX slv4 := ( others = > ' 0 ' )
Signal

Definition at line 87 of file sn_7segctl.vhd.

◆ CDP

CDP slbit := ' 0 '
Signal

Definition at line 88 of file sn_7segctl.vhd.

The documentation for this design unit was generated from the following file: