sim Architecture Reference

Architecture >> sim

Processes
proc_regs	( CLK )
proc_next	( R_REGS , RESET , CLKDIV , TXDATA , TXENA )

Constants
cntzero	slv ( CDWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
regs_init	regs_type := ( cntzero , ( others = > ' 0 ' ) , ( others = > ' 1 ' ) , ' 0 ' )

Signals
R_REGS	regs_type := regs_init
N_REGS	regs_type := regs_init

Records
regs_type
ccnt	slv ( CDWIDTH - 1 downto 0 )
bcnt	slv4
sreg	slv9
busy	slbit

Detailed Description

Definition at line 38 of file serport_uart_tx_tb.vhd.

Member Function/Procedure/Process Documentation

proc_regs()

proc_regs (   CLK   )

Process

Definition at line 60 of file serport_uart_tx_tb.vhd.

proc_next()

proc_next (   R_REGS ,   RESET ,   CLKDIV ,   TXDATA ,   TXENA   )

Process

Definition at line 69 of file serport_uart_tx_tb.vhd.

Member Data Documentation

regs_type

regs_type

Record

Definition at line 40 of file serport_uart_tx_tb.vhd.

ccnt

ccnt slv ( CDWIDTH - 1 downto 0 )

Record

Definition at line 41 of file serport_uart_tx_tb.vhd.

bcnt

bcnt slv4

Record

Definition at line 42 of file serport_uart_tx_tb.vhd.

sreg

sreg slv9

Record

Definition at line 43 of file serport_uart_tx_tb.vhd.

busy

busy slbit

Record

Definition at line 44 of file serport_uart_tx_tb.vhd.

cntzero

cntzero slv ( CDWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Constant

Definition at line 47 of file serport_uart_tx_tb.vhd.

regs_init

regs_init regs_type := ( cntzero , ( others = > ' 0 ' ) , ( others = > ' 1 ' ) , ' 0 ' )

Constant

Definition at line 48 of file serport_uart_tx_tb.vhd.

R_REGS

R_REGS regs_type := regs_init

Signal

Definition at line 55 of file serport_uart_tx_tb.vhd.

N_REGS

N_REGS regs_type := regs_init

Signal

Definition at line 56 of file serport_uart_tx_tb.vhd.

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The documentation for this design unit was generated from the following file:

• vlib/serport/tb/serport_uart_tx_tb.vhd