w11 - vhd 0.794
W11 CPU core and support modules
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Instantiations | Processes | Signals
syn Architecture Reference
Architecture >> syn

Processes

proc_rxok  ( CLK )
proc_cts  ( TXCTS_N , XONTX_TXENA , UART_TXBUSY )
proc_abclkdiv  ( ABCLKDIV , ABCLKDIV_F )
proc_check  ( CLK )

Signals

R_RXOK  slbit := ' 1 '
RESET_INT  slbit := ' 0 '
UART_RXDATA  slv8 := ( others = > ' 0 ' )
UART_RXVAL  slbit := ' 0 '
UART_TXDATA  slv8 := ( others = > ' 0 ' )
UART_TXENA  slbit := ' 0 '
UART_TXBUSY  slbit := ' 0 '
XONTX_TXENA  slbit := ' 0 '
XONTX_TXBUSY  slbit := ' 0 '
RXFIFO_DI  slv8 := ( others = > ' 0 ' )
RXFIFO_ENA  slbit := ' 0 '
RXFIFO_BUSY  slbit := ' 0 '
RXFIFO_SIZE  slv ( RXFAWIDTH downto 0 ) := ( others = > ' 0 ' )
TXFIFO_DO  slv8 := ( others = > ' 0 ' )
TXFIFO_VAL  slbit := ' 0 '
TXFIFO_HOLD  slbit := ' 0 '
RXERR  slbit := ' 0 '
RXOVR  slbit := ' 0 '
RXACT  slbit := ' 0 '
ABACT  slbit := ' 0 '
ABDONE  slbit := ' 0 '
ABCLKDIV  slv ( CDWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
ABCLKDIV_F  slv3 := ( others = > ' 0 ' )
TXOK  slbit := ' 0 '
RXOK  slbit := ' 0 '

Instantiations

uart  serport_uart_rxtx_ab <Entity serport_uart_rxtx_ab>
xonrx  serport_xonrx <Entity serport_xonrx>
xontx  serport_xontx <Entity serport_xontx>
rxfifo  fifo_1c_dram <Entity fifo_1c_dram>
txfifo  fifo_1c_dram <Entity fifo_1c_dram>

Detailed Description

Definition at line 67 of file serport_1clock.vhd.

Member Function/Procedure/Process Documentation

◆ proc_rxok()

proc_rxok (   CLK)

Definition at line 198 of file serport_1clock.vhd.

◆ proc_cts()

proc_cts (   TXCTS_N ,
  XONTX_TXENA ,
  UART_TXBUSY  
)
Process

Definition at line 220 of file serport_1clock.vhd.

◆ proc_abclkdiv()

proc_abclkdiv (   ABCLKDIV ,
  ABCLKDIV_F  
)
Process

Definition at line 240 of file serport_1clock.vhd.

◆ proc_check()

proc_check (   CLK  
)
Process

Definition at line 249 of file serport_1clock.vhd.

Member Data Documentation

◆ R_RXOK

R_RXOK slbit := ' 1 '
Signal

Definition at line 69 of file serport_1clock.vhd.

◆ RESET_INT

RESET_INT slbit := ' 0 '
Signal

Definition at line 71 of file serport_1clock.vhd.

◆ UART_RXDATA

UART_RXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 73 of file serport_1clock.vhd.

◆ UART_RXVAL

UART_RXVAL slbit := ' 0 '
Signal

Definition at line 74 of file serport_1clock.vhd.

◆ UART_TXDATA

UART_TXDATA slv8 := ( others = > ' 0 ' )
Signal

Definition at line 75 of file serport_1clock.vhd.

◆ UART_TXENA

UART_TXENA slbit := ' 0 '
Signal

Definition at line 76 of file serport_1clock.vhd.

◆ UART_TXBUSY

UART_TXBUSY slbit := ' 0 '
Signal

Definition at line 77 of file serport_1clock.vhd.

◆ XONTX_TXENA

XONTX_TXENA slbit := ' 0 '
Signal

Definition at line 79 of file serport_1clock.vhd.

◆ XONTX_TXBUSY

XONTX_TXBUSY slbit := ' 0 '
Signal

Definition at line 80 of file serport_1clock.vhd.

◆ RXFIFO_DI

RXFIFO_DI slv8 := ( others = > ' 0 ' )
Signal

Definition at line 82 of file serport_1clock.vhd.

◆ RXFIFO_ENA

RXFIFO_ENA slbit := ' 0 '
Signal

Definition at line 83 of file serport_1clock.vhd.

◆ RXFIFO_BUSY

RXFIFO_BUSY slbit := ' 0 '
Signal

Definition at line 84 of file serport_1clock.vhd.

◆ RXFIFO_SIZE

RXFIFO_SIZE slv ( RXFAWIDTH downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 85 of file serport_1clock.vhd.

◆ TXFIFO_DO

TXFIFO_DO slv8 := ( others = > ' 0 ' )
Signal

Definition at line 86 of file serport_1clock.vhd.

◆ TXFIFO_VAL

TXFIFO_VAL slbit := ' 0 '
Signal

Definition at line 87 of file serport_1clock.vhd.

◆ TXFIFO_HOLD

TXFIFO_HOLD slbit := ' 0 '
Signal

Definition at line 88 of file serport_1clock.vhd.

◆ RXERR

RXERR slbit := ' 0 '
Signal

Definition at line 90 of file serport_1clock.vhd.

◆ RXOVR

RXOVR slbit := ' 0 '
Signal

Definition at line 91 of file serport_1clock.vhd.

◆ RXACT

RXACT slbit := ' 0 '
Signal

Definition at line 92 of file serport_1clock.vhd.

◆ ABACT

ABACT slbit := ' 0 '
Signal

Definition at line 93 of file serport_1clock.vhd.

◆ ABDONE

ABDONE slbit := ' 0 '
Signal

Definition at line 94 of file serport_1clock.vhd.

◆ ABCLKDIV

ABCLKDIV slv ( CDWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 95 of file serport_1clock.vhd.

◆ ABCLKDIV_F

ABCLKDIV_F slv3 := ( others = > ' 0 ' )
Signal

Definition at line 96 of file serport_1clock.vhd.

◆ TXOK

TXOK slbit := ' 0 '
Signal

Definition at line 98 of file serport_1clock.vhd.

◆ RXOK

RXOK slbit := ' 0 '
Signal

Definition at line 99 of file serport_1clock.vhd.

◆ uart

uart serport_uart_rxtx_ab
Instantiation

Definition at line 128 of file serport_1clock.vhd.

◆ xonrx

xonrx serport_xonrx
Instantiation

Definition at line 145 of file serport_1clock.vhd.

◆ xontx

xontx serport_xontx
Instantiation

Definition at line 161 of file serport_1clock.vhd.

◆ rxfifo

rxfifo fifo_1c_dram
Instantiation

Definition at line 177 of file serport_1clock.vhd.

◆ txfifo

txfifo fifo_1c_dram
Instantiation

Definition at line 193 of file serport_1clock.vhd.

The documentation for this design unit was generated from the following file: