syn Architecture Reference

Architecture >> syn

Signals
CLK0_L	slbit := ' 0 '
CLK1_L	slbit := ' 0 '
LOCKED0	slbit := ' 0 '
LOCKED1	slbit := ' 0 '

Instantiations
gen_clk0	s7_cmt_sfs <Entity s7_cmt_sfs>
div_clk0	clkdivce <Entity clkdivce>
gen_clk1	s7_cmt_sfs <Entity s7_cmt_sfs>
div_clk1	clkdivce <Entity clkdivce>

Detailed Description

Definition at line 58 of file s7_cmt_1ce1ce.vhd.

Member Data Documentation

CLK0_L

CLK0_L slbit := ' 0 '

Signal

Definition at line 60 of file s7_cmt_1ce1ce.vhd.

CLK1_L

CLK1_L slbit := ' 0 '

Signal

Definition at line 61 of file s7_cmt_1ce1ce.vhd.

LOCKED0

LOCKED0 slbit := ' 0 '

Signal

Definition at line 62 of file s7_cmt_1ce1ce.vhd.

LOCKED1

LOCKED1 slbit := ' 0 '

Signal

Definition at line 63 of file s7_cmt_1ce1ce.vhd.

gen_clk0

gen_clk0 s7_cmt_sfs

Instantiation

Definition at line 80 of file s7_cmt_1ce1ce.vhd.

div_clk0

div_clk0 clkdivce

Instantiation

Definition at line 91 of file s7_cmt_1ce1ce.vhd.

gen_clk1

gen_clk1 s7_cmt_sfs

Instantiation

Definition at line 106 of file s7_cmt_1ce1ce.vhd.

div_clk1

div_clk1 clkdivce

Instantiation

Definition at line 117 of file s7_cmt_1ce1ce.vhd.

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The documentation for this design unit was generated from the following file:

• bplib/bpgen/s7_cmt_1ce1ce.vhd