w11 - vhd 0.794
W11 CPU core and support modules
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Constants | Instantiations | Processes | Records | Signals | Types
syn Architecture Reference
Architecture >> syn

Processes

proc_regs  ( CLK )
proc_next  ( R_REGS , REQ , WE , BE )

Constants

regs_init  regs_type := ( s_idle , ' 0 ' )

Types

state_type  ( s_idle , s_read , s_write1 , s_write2 , s_bta_r2w , s_bta_w2r )

Signals

R_REGS  regs_type := regs_init
N_REGS  regs_type := regs_init
CLK_180  slbit := ' 0 '
MEM_CE_N  slv2 := " 00 "
MEM_BE_N  slv4 := " 0000 "
MEM_WE_N  slbit := ' 0 '
MEM_OE_N  slbit := ' 0 '
ADDR_CE  slbit := ' 0 '
DATA_CEI  slbit := ' 0 '
DATA_CEO  slbit := ' 0 '
DATA_OE  slbit := ' 0 '

Records

regs_type 
state state_type
ackr slbit

Instantiations

iob_mem_ce  iob_reg_o_gen <Entity iob_reg_o_gen>
iob_mem_be  iob_reg_o_gen <Entity iob_reg_o_gen>
iob_mem_we  iob_reg_o <Entity iob_reg_o>
iob_mem_oe  iob_reg_o <Entity iob_reg_o>
iob_mem_addr  iob_reg_o_gen <Entity iob_reg_o_gen>
iob_mem_data  iob_reg_io_gen <Entity iob_reg_io_gen>

Detailed Description

Definition at line 103 of file s3_sram_memctl.vhd.

Member Function/Procedure/Process Documentation

◆ proc_regs()

proc_regs (   CLK)

Definition at line 207 of file s3_sram_memctl.vhd.

◆ proc_next()

proc_next (   R_REGS ,
  REQ ,
  WE ,
  BE  
)
Process

Definition at line 220 of file s3_sram_memctl.vhd.

Member Data Documentation

◆ state_type

state_type ( s_idle , s_read , s_write1 , s_write2 , s_bta_r2w , s_bta_w2r )
Type

Definition at line 105 of file s3_sram_memctl.vhd.

◆ regs_type

regs_type
Record

Definition at line 114 of file s3_sram_memctl.vhd.

◆ state

state state_type
Record

Definition at line 115 of file s3_sram_memctl.vhd.

◆ ackr

ackr slbit
Record

Definition at line 116 of file s3_sram_memctl.vhd.

◆ regs_init

regs_init regs_type := ( s_idle , ' 0 ' )
Constant

Definition at line 119 of file s3_sram_memctl.vhd.

◆ R_REGS

R_REGS regs_type := regs_init
Signal

Definition at line 124 of file s3_sram_memctl.vhd.

◆ N_REGS

N_REGS regs_type := regs_init
Signal

Definition at line 125 of file s3_sram_memctl.vhd.

◆ CLK_180

CLK_180 slbit := ' 0 '
Signal

Definition at line 127 of file s3_sram_memctl.vhd.

◆ MEM_CE_N

MEM_CE_N slv2 := " 00 "
Signal

Definition at line 128 of file s3_sram_memctl.vhd.

◆ MEM_BE_N

MEM_BE_N slv4 := " 0000 "
Signal

Definition at line 129 of file s3_sram_memctl.vhd.

◆ MEM_WE_N

MEM_WE_N slbit := ' 0 '
Signal

Definition at line 130 of file s3_sram_memctl.vhd.

◆ MEM_OE_N

MEM_OE_N slbit := ' 0 '
Signal

Definition at line 131 of file s3_sram_memctl.vhd.

◆ ADDR_CE

ADDR_CE slbit := ' 0 '
Signal

Definition at line 132 of file s3_sram_memctl.vhd.

◆ DATA_CEI

DATA_CEI slbit := ' 0 '
Signal

Definition at line 133 of file s3_sram_memctl.vhd.

◆ DATA_CEO

DATA_CEO slbit := ' 0 '
Signal

Definition at line 134 of file s3_sram_memctl.vhd.

◆ DATA_OE

DATA_OE slbit := ' 0 '
Signal

Definition at line 135 of file s3_sram_memctl.vhd.

◆ iob_mem_ce

iob_mem_ce iob_reg_o_gen
Instantiation

Definition at line 150 of file s3_sram_memctl.vhd.

◆ iob_mem_be

iob_mem_be iob_reg_o_gen
Instantiation

Definition at line 161 of file s3_sram_memctl.vhd.

◆ iob_mem_we

iob_mem_we iob_reg_o
Instantiation

Definition at line 171 of file s3_sram_memctl.vhd.

◆ iob_mem_oe

iob_mem_oe iob_reg_o
Instantiation

Definition at line 181 of file s3_sram_memctl.vhd.

◆ iob_mem_addr

iob_mem_addr iob_reg_o_gen
Instantiation

Definition at line 191 of file s3_sram_memctl.vhd.

◆ iob_mem_data

iob_mem_data iob_reg_io_gen
Instantiation

Definition at line 205 of file s3_sram_memctl.vhd.

The documentation for this design unit was generated from the following file: