sim Architecture Reference

Architecture >> sim

Processes
proc_put	( CLK )
proc_get	( CLK )

Signals
R_RXDATA	slv32 := ( others = > ' 1 ' )
R_RXVAL	slbit := ' 0 '

Detailed Description

Definition at line 41 of file rlink_cext_iface_vhpi.vhd.

Member Function/Procedure/Process Documentation

proc_put()

proc_put (   CLK   )

Process

Definition at line 46 of file rlink_cext_iface_vhpi.vhd.

proc_get()

proc_get (   CLK   )

Process

Definition at line 61 of file rlink_cext_iface_vhpi.vhd.

Member Data Documentation

R_RXDATA

R_RXDATA slv32 := ( others = > ' 1 ' )

Signal

Definition at line 42 of file rlink_cext_iface_vhpi.vhd.

R_RXVAL

R_RXVAL slbit := ' 0 '

Signal

Definition at line 43 of file rlink_cext_iface_vhpi.vhd.

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The documentation for this design unit was generated from the following file:

• vlib/rlink/tbcore/rlink_cext_iface_vhpi.vhd