syn Architecture Reference

Architecture >> syn

Processes
proc_regs	( CLK )
proc_next	( R_RGB , RGBCNTL , DIMCNTL , DIMR , DIMG , DIMB )

Signals
R_RGB	slv3 := ( others = > ' 0 ' )
N_RGB	slv3 := ( others = > ' 0 ' )

Instantiations
iob_rgb	iob_reg_o_gen <Entity iob_reg_o_gen>

Detailed Description

Definition at line 43 of file rgbdrv_analog.vhd.

Member Function/Procedure/Process Documentation

proc_regs()

proc_regs

(

CLK

)

Definition at line 54 of file rgbdrv_analog.vhd.

proc_next()

proc_next (   R_RGB ,   RGBCNTL ,   DIMCNTL ,   DIMR ,   DIMG ,   DIMB   )

Process

Definition at line 68 of file rgbdrv_analog.vhd.

Member Data Documentation

R_RGB

R_RGB slv3 := ( others = > ' 0 ' )

Signal

Definition at line 45 of file rgbdrv_analog.vhd.

N_RGB

N_RGB slv3 := ( others = > ' 0 ' )

Signal

Definition at line 46 of file rgbdrv_analog.vhd.

iob_rgb

iob_rgb iob_reg_o_gen

Instantiation

Definition at line 52 of file rgbdrv_analog.vhd.

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The documentation for this design unit was generated from the following file:

• bplib/bpgen/rgbdrv_analog.vhd