w11 - vhd 0.794
W11 CPU core and support modules
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Constants | Instantiations | Processes | Records | Signals | Subtypes
syn Architecture Reference
Architecture >> syn

Processes

proc_regs  ( CLK )
proc_next  ( R_REGS , RB_MREQ , FIFO_EMPTY , FIFO_FULL , FIFO_DO )

Constants

awidth  positive := 4
rbaddr_cntl  slv3 := " 000 "
rbaddr_stat  slv3 := " 001 "
rbaddr_attn  slv3 := " 010 "
rbaddr_ncyc  slv3 := " 011 "
rbaddr_data  slv3 := " 100 "
rbaddr_dinc  slv3 := " 101 "
rbaddr_fifo  slv3 := " 110 "
rbaddr_lnak  slv3 := " 111 "
cntl_rbf_wchk  integer := 15
init_rbf_cntl  integer := 0
init_rbf_data  integer := 1
init_rbf_fifo  integer := 2
regs_init  regs_type := ( ' 0 ' , ' 0 ' , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ' 0 ' , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )
cntcyc_max  slv ( regs_init .cntcyc ' range ) := ( others = > ' 1 ' )

Subtypes

cntl_rbf_nbusy  integer range 9 downto 0

Signals

R_REGS  regs_type := regs_init
N_REGS  regs_type := regs_init
FIFO_RESET  slbit := ' 0 '
FIFO_CE  slbit := ' 0 '
FIFO_WE  slbit := ' 0 '
FIFO_EMPTY  slbit := ' 0 '
FIFO_FULL  slbit := ' 0 '
FIFO_SIZE  slv ( awidth - 1 downto 0 ) := ( others = > ' 0 ' )
FIFO_DO  slv16 := ( others = > ' 0 ' )

Records

regs_type 
rbsel slbit
wchk slbit
stat slv4
nbusy slv10
data slv16
act_1 slbit
ncyc slv10
cntbusy slv10
cntcyc slv10

Instantiations

fifo  fifo_simple_dram <Entity fifo_simple_dram>

Detailed Description

Definition at line 75 of file rbd_tester.vhd.

Member Function/Procedure/Process Documentation

◆ proc_regs()

proc_regs (   CLK)

Definition at line 149 of file rbd_tester.vhd.

◆ proc_next()

proc_next (   R_REGS ,
  RB_MREQ ,
  FIFO_EMPTY ,
  FIFO_FULL ,
  FIFO_DO  
)
Process

Definition at line 160 of file rbd_tester.vhd.

Member Data Documentation

◆ awidth

awidth positive := 4
Constant

Definition at line 77 of file rbd_tester.vhd.

◆ rbaddr_cntl

rbaddr_cntl slv3 := " 000 "
Constant

Definition at line 79 of file rbd_tester.vhd.

◆ rbaddr_stat

rbaddr_stat slv3 := " 001 "
Constant

Definition at line 80 of file rbd_tester.vhd.

◆ rbaddr_attn

rbaddr_attn slv3 := " 010 "
Constant

Definition at line 81 of file rbd_tester.vhd.

◆ rbaddr_ncyc

rbaddr_ncyc slv3 := " 011 "
Constant

Definition at line 82 of file rbd_tester.vhd.

◆ rbaddr_data

rbaddr_data slv3 := " 100 "
Constant

Definition at line 83 of file rbd_tester.vhd.

◆ rbaddr_dinc

rbaddr_dinc slv3 := " 101 "
Constant

Definition at line 84 of file rbd_tester.vhd.

◆ rbaddr_fifo

rbaddr_fifo slv3 := " 110 "
Constant

Definition at line 85 of file rbd_tester.vhd.

◆ rbaddr_lnak

rbaddr_lnak slv3 := " 111 "
Constant

Definition at line 86 of file rbd_tester.vhd.

◆ cntl_rbf_wchk

cntl_rbf_wchk integer := 15
Constant

Definition at line 88 of file rbd_tester.vhd.

◆ cntl_rbf_nbusy

cntl_rbf_nbusy integer range 9 downto 0
Subtype

Definition at line 89 of file rbd_tester.vhd.

◆ init_rbf_cntl

init_rbf_cntl integer := 0
Constant

Definition at line 91 of file rbd_tester.vhd.

◆ init_rbf_data

init_rbf_data integer := 1
Constant

Definition at line 92 of file rbd_tester.vhd.

◆ init_rbf_fifo

init_rbf_fifo integer := 2
Constant

Definition at line 93 of file rbd_tester.vhd.

◆ regs_type

regs_type
Record

Definition at line 95 of file rbd_tester.vhd.

◆ rbsel

rbsel slbit
Record

Definition at line 96 of file rbd_tester.vhd.

◆ wchk

wchk slbit
Record

Definition at line 97 of file rbd_tester.vhd.

◆ stat

stat slv4
Record

Definition at line 98 of file rbd_tester.vhd.

◆ nbusy

nbusy slv10
Record

Definition at line 99 of file rbd_tester.vhd.

◆ data

data slv16
Record

Definition at line 100 of file rbd_tester.vhd.

◆ act_1

act_1 slbit
Record

Definition at line 101 of file rbd_tester.vhd.

◆ ncyc

ncyc slv10
Record

Definition at line 102 of file rbd_tester.vhd.

◆ cntbusy

cntbusy slv10
Record

Definition at line 103 of file rbd_tester.vhd.

◆ cntcyc

cntcyc slv10
Record

Definition at line 104 of file rbd_tester.vhd.

◆ regs_init

regs_init regs_type := ( ' 0 ' , ' 0 ' , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ' 0 ' , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) )
Constant

Definition at line 107 of file rbd_tester.vhd.

◆ cntcyc_max

cntcyc_max slv ( regs_init .cntcyc ' range ) := ( others = > ' 1 ' )
Constant

Definition at line 118 of file rbd_tester.vhd.

◆ R_REGS

R_REGS regs_type := regs_init
Signal

Definition at line 120 of file rbd_tester.vhd.

◆ N_REGS

N_REGS regs_type := regs_init
Signal

Definition at line 121 of file rbd_tester.vhd.

◆ FIFO_RESET

FIFO_RESET slbit := ' 0 '
Signal

Definition at line 123 of file rbd_tester.vhd.

◆ FIFO_CE

FIFO_CE slbit := ' 0 '
Signal

Definition at line 124 of file rbd_tester.vhd.

◆ FIFO_WE

FIFO_WE slbit := ' 0 '
Signal

Definition at line 125 of file rbd_tester.vhd.

◆ FIFO_EMPTY

FIFO_EMPTY slbit := ' 0 '
Signal

Definition at line 126 of file rbd_tester.vhd.

◆ FIFO_FULL

FIFO_FULL slbit := ' 0 '
Signal

Definition at line 127 of file rbd_tester.vhd.

◆ FIFO_SIZE

FIFO_SIZE slv ( awidth - 1 downto 0 ) := ( others = > ' 0 ' )
Signal

Definition at line 128 of file rbd_tester.vhd.

◆ FIFO_DO

FIFO_DO slv16 := ( others = > ' 0 ' )
Signal

Definition at line 129 of file rbd_tester.vhd.

◆ fifo

fifo fifo_simple_dram
Instantiation

Definition at line 147 of file rbd_tester.vhd.

The documentation for this design unit was generated from the following file: