syn Architecture Reference

Architecture >> syn

Processes
proc_clk	( CLK )

Constants
memsize	positive := 2 ** AWIDTH
datzero	slv ( DWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Types
ram_type	( memsize - 1 downto 0 ) slv ( DWIDTH - 1 downto 0 )

Signals
RAM	ram_type := ( others = > datzero )
WE0	slbit := ' 0 '
WE1	slbit := ' 0 '
DOA0	slv ( DWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
DOA1	slv ( DWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
DOB0	slv ( DWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )
DOB1	slv ( DWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Attributes
ram_style	string
ram_style	signal is " distributed "

Instantiations
mem	ram16x1d
mem0	ram16x1d
mem1	ram16x1d

Detailed Description

Definition at line 57 of file ram_1swar_1ar_gen.vhd.

Member Function/Procedure/Process Documentation

proc_clk()

proc_clk (   CLK   )

Process

Definition at line 68 of file ram_1swar_1ar_gen.vhd.

Member Data Documentation

memsize

memsize positive := 2 ** AWIDTH

Constant

Definition at line 58 of file ram_1swar_1ar_gen.vhd.

datzero

datzero slv ( DWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Constant

Definition at line 59 of file ram_1swar_1ar_gen.vhd.

ram_type

ram_type ( memsize - 1 downto 0 ) slv ( DWIDTH - 1 downto 0 )

Type

Definition at line 60 of file ram_1swar_1ar_gen.vhd.

RAM

RAM ram_type := ( others = > datzero )

Signal

Definition at line 61 of file ram_1swar_1ar_gen.vhd.

ram_style [1/2]

ram_style string

Attribute

Definition at line 63 of file ram_1swar_1ar_gen.vhd.

ram_style [2/2]

ram_style signal is " distributed "

Attribute

Definition at line 64 of file ram_1swar_1ar_gen.vhd.

WE0

slbit := '0' WE0

Definition at line 79 of file ram_1swar_1ar_gen_unisim.vhd.

WE1

WE1 slbit := ' 0 '

Signal

Definition at line 80 of file ram_1swar_1ar_gen_unisim.vhd.

DOA0

DOA0 slv ( DWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Definition at line 81 of file ram_1swar_1ar_gen_unisim.vhd.

DOA1

DOA1 slv ( DWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Definition at line 82 of file ram_1swar_1ar_gen_unisim.vhd.

DOB0

DOB0 slv ( DWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Definition at line 83 of file ram_1swar_1ar_gen_unisim.vhd.

DOB1

DOB1 slv ( DWIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

Definition at line 84 of file ram_1swar_1ar_gen_unisim.vhd.

mem

mem ram16x1d

Instantiation

Definition at line 73 of file ram_1swar_1ar_gen_unisim.vhd.

mem0

mem0 ram16x1d

Instantiation

Definition at line 106 of file ram_1swar_1ar_gen_unisim.vhd.

mem1

mem1 ram16x1d

Instantiation

Definition at line 124 of file ram_1swar_1ar_gen_unisim.vhd.

---

The documentation for this design unit was generated from the following files:

• vlib/memlib/ram_1swar_1ar_gen.vhd
• vlib/memlib/ram_1swar_1ar_gen_unisim.vhd