w11 - vhd 0.794
W11 CPU core and support modules
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Libraries | Ports | Use Clauses
nexys4d_dram_dummy Entity Reference

Entities

syn  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
slvtypes  Package <slvtypes>

Ports

I_CLK100   in   slbit
I_RXD   in   slbit
O_TXD   out   slbit
O_RTS_N   out   slbit
I_CTS_N   in   slbit
I_SWI   in   slv16
I_BTN   in   slv5
I_BTNRST_N   in   slbit
O_LED   out   slv16
O_RGBLED0   out   slv3
O_RGBLED1   out   slv3
O_ANO_N   out   slv8
O_SEG_N   out   slv8
DDR2_DQ   inout   slv16
DDR2_DQS_P   inout   slv2
DDR2_DQS_N   inout   slv2
DDR2_ADDR   out   slv13
DDR2_BA   out   slv3
DDR2_RAS_N   out   slbit
DDR2_CAS_N   out   slbit
DDR2_WE_N   out   slbit
DDR2_CK_P   out   slv1
DDR2_CK_N   out   slv1
DDR2_CKE   out   slv1
DDR2_CS_N   out   slv1
DDR2_DM   out   slv2
DDR2_ODT   out   slv1

Detailed Description

Definition at line 24 of file nexys4d_dram_dummy.vhd.

Member Data Documentation

◆ I_CLK100

I_CLK100 in slbit
Port

Definition at line 27 of file nexys4d_dram_dummy.vhd.

◆ I_RXD

I_RXD in slbit
Port

Definition at line 28 of file nexys4d_dram_dummy.vhd.

◆ O_TXD

O_TXD out slbit
Port

Definition at line 29 of file nexys4d_dram_dummy.vhd.

◆ O_RTS_N

O_RTS_N out slbit
Port

Definition at line 30 of file nexys4d_dram_dummy.vhd.

◆ I_CTS_N

I_CTS_N in slbit
Port

Definition at line 31 of file nexys4d_dram_dummy.vhd.

◆ I_SWI

I_SWI in slv16
Port

Definition at line 32 of file nexys4d_dram_dummy.vhd.

◆ I_BTN

I_BTN in slv5
Port

Definition at line 33 of file nexys4d_dram_dummy.vhd.

◆ I_BTNRST_N

I_BTNRST_N in slbit
Port

Definition at line 34 of file nexys4d_dram_dummy.vhd.

◆ O_LED

O_LED out slv16
Port

Definition at line 35 of file nexys4d_dram_dummy.vhd.

◆ O_RGBLED0

O_RGBLED0 out slv3
Port

Definition at line 36 of file nexys4d_dram_dummy.vhd.

◆ O_RGBLED1

O_RGBLED1 out slv3
Port

Definition at line 37 of file nexys4d_dram_dummy.vhd.

◆ O_ANO_N

O_ANO_N out slv8
Port

Definition at line 38 of file nexys4d_dram_dummy.vhd.

◆ O_SEG_N

O_SEG_N out slv8
Port

Definition at line 39 of file nexys4d_dram_dummy.vhd.

◆ DDR2_DQ

DDR2_DQ inout slv16
Port

Definition at line 40 of file nexys4d_dram_dummy.vhd.

◆ DDR2_DQS_P

DDR2_DQS_P inout slv2
Port

Definition at line 41 of file nexys4d_dram_dummy.vhd.

◆ DDR2_DQS_N

DDR2_DQS_N inout slv2
Port

Definition at line 42 of file nexys4d_dram_dummy.vhd.

◆ DDR2_ADDR

DDR2_ADDR out slv13
Port

Definition at line 43 of file nexys4d_dram_dummy.vhd.

◆ DDR2_BA

DDR2_BA out slv3
Port

Definition at line 44 of file nexys4d_dram_dummy.vhd.

◆ DDR2_RAS_N

DDR2_RAS_N out slbit
Port

Definition at line 45 of file nexys4d_dram_dummy.vhd.

◆ DDR2_CAS_N

DDR2_CAS_N out slbit
Port

Definition at line 46 of file nexys4d_dram_dummy.vhd.

◆ DDR2_WE_N

DDR2_WE_N out slbit
Port

Definition at line 47 of file nexys4d_dram_dummy.vhd.

◆ DDR2_CK_P

DDR2_CK_P out slv1
Port

Definition at line 48 of file nexys4d_dram_dummy.vhd.

◆ DDR2_CK_N

DDR2_CK_N out slv1
Port

Definition at line 49 of file nexys4d_dram_dummy.vhd.

◆ DDR2_CKE

DDR2_CKE out slv1
Port

Definition at line 50 of file nexys4d_dram_dummy.vhd.

◆ DDR2_CS_N

DDR2_CS_N out slv1
Port

Definition at line 51 of file nexys4d_dram_dummy.vhd.

◆ DDR2_DM

DDR2_DM out slv2
Port

Definition at line 52 of file nexys4d_dram_dummy.vhd.

◆ DDR2_ODT

DDR2_ODT out slv1
Port

Definition at line 54 of file nexys4d_dram_dummy.vhd.

◆ ieee

ieee
Library

Definition at line 19 of file nexys4d_dram_dummy.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 20 of file nexys4d_dram_dummy.vhd.

◆ slvtypes

slvtypes
use clause

Definition at line 22 of file nexys4d_dram_dummy.vhd.

The documentation for this design unit was generated from the following file: