sim Architecture Reference

Architecture >> sim

Components
is61lv25616al_bank	<Entity is61lv25616al_bank>

Signals
CE	slbit := ' 0 '
OE	slbit := ' 0 '
WE	slbit := ' 0 '
BE_L	slbit := ' 0 '
BE_U	slbit := ' 0 '

Instantiations
bank_l	is61lv25616al_bank <Entity is61lv25616al_bank>
bank_u	is61lv25616al_bank <Entity is61lv25616al_bank>

Detailed Description

Definition at line 54 of file is61lv25616al.vhd.

Member Data Documentation

CE

CE slbit := ' 0 '

Signal

Definition at line 56 of file is61lv25616al.vhd.

OE

OE slbit := ' 0 '

Signal

Definition at line 57 of file is61lv25616al.vhd.

WE

WE slbit := ' 0 '

Signal

Definition at line 58 of file is61lv25616al.vhd.

BE_L

BE_L slbit := ' 0 '

Signal

Definition at line 59 of file is61lv25616al.vhd.

BE_U

BE_U slbit := ' 0 '

Signal

Definition at line 60 of file is61lv25616al.vhd.

is61lv25616al_bank

is61lv25616al_bank

Component

Definition at line 62 of file is61lv25616al.vhd.

bank_l

bank_l 61lv25616al_bank

Instantiation

Definition at line 87 of file is61lv25616al.vhd.

bank_u

bank_u 61lv25616al_bank

Instantiation

Definition at line 95 of file is61lv25616al.vhd.

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The documentation for this design unit was generated from the following file:

• bplib/issi/is61lv25616al.vhd