syn Architecture Reference

Architecture >> syn

Processes
proc_regs	( CLK )
proc_next	( R_REGS )

Constants
regs_init	regs_type := ( slv ( to_unsigned ( USECDIV - 1 , CDUWIDTH ) ) , slv ( to_unsigned ( MSECDIV - 1 , 10 ) ) , ' 0 ' , ' 0 ' )

Signals
R_REGS	regs_type := regs_init
N_REGS	regs_type := regs_init

Records
regs_type
ucnt	slv ( CDUWIDTH - 1 downto 0 )
mcnt	slv10
usec	slbit
msec	slbit

Detailed Description

Definition at line 43 of file clkdivce.vhd.

Member Function/Procedure/Process Documentation

proc_regs()

proc_regs (   CLK   )

Process

Definition at line 68 of file clkdivce.vhd.

proc_next()

proc_next (   R_REGS   )

Process

Definition at line 77 of file clkdivce.vhd.

Member Data Documentation

regs_type

regs_type

Record

Definition at line 45 of file clkdivce.vhd.

ucnt

ucnt slv ( CDUWIDTH - 1 downto 0 )

Record

Definition at line 46 of file clkdivce.vhd.

mcnt

mcnt slv10

Record

Definition at line 47 of file clkdivce.vhd.

usec

usec slbit

Record

Definition at line 48 of file clkdivce.vhd.

msec

msec slbit

Record

Definition at line 49 of file clkdivce.vhd.

regs_init

regs_init regs_type := ( slv ( to_unsigned ( USECDIV - 1 , CDUWIDTH ) ) , slv ( to_unsigned ( MSECDIV - 1 , 10 ) ) , ' 0 ' , ' 0 ' )

Constant

Definition at line 52 of file clkdivce.vhd.

R_REGS

R_REGS regs_type := regs_init

Signal

Definition at line 58 of file clkdivce.vhd.

N_REGS

N_REGS regs_type := regs_init

Signal

Definition at line 59 of file clkdivce.vhd.

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The documentation for this design unit was generated from the following file:

• vlib/genlib/clkdivce.vhd