w11 - vhd 0.794
W11 CPU core and support modules
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s7_cmt_1ce1ce Entity Reference
Inheritance diagram for s7_cmt_1ce1ce:
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Collaboration diagram for s7_cmt_1ce1ce:
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Entities

syn  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
slvtypes  Package <slvtypes>
xlib  Package <xlib>
genlib  Package <genlib>

Generics

CLKIN_PERIOD  real := 10 . 0
CLKIN_JITTER  real := 0 . 01
STARTUP_WAIT  boolean := false
CLK0_VCODIV  positive := 1
CLK0_VCOMUL  positive := 1
CLK0_OUTDIV  positive := 1
CLK0_GENTYPE  string := " PLL "
CLK0_CDUWIDTH  positive := 7
CLK0_USECDIV  positive := 50
CLK0_MSECDIV  positive := 1000
CLK1_VCODIV  positive := 1
CLK1_VCOMUL  positive := 1
CLK1_OUTDIV  positive := 1
CLK1_GENTYPE  string := " MMCM "
CLK1_CDUWIDTH  positive := 7
CLK1_USECDIV  positive := 50
CLK1_MSECDIV  positive := 1000

Ports

CLKIN   in   slbit
CLK0   out   slbit
CE0_USEC   out   slbit
CE0_MSEC   out   slbit
CLK1   out   slbit
CE1_USEC   out   slbit
CE1_MSEC   out   slbit
LOCKED   out   slbit

Detailed Description

Definition at line 27 of file s7_cmt_1ce1ce.vhd.

Member Data Documentation

◆ CLKIN_PERIOD

CLKIN_PERIOD real := 10 . 0
Generic

Definition at line 29 of file s7_cmt_1ce1ce.vhd.

◆ CLKIN_JITTER

CLKIN_JITTER real := 0 . 01
Generic

Definition at line 30 of file s7_cmt_1ce1ce.vhd.

◆ STARTUP_WAIT

STARTUP_WAIT boolean := false
Generic

Definition at line 31 of file s7_cmt_1ce1ce.vhd.

◆ CLK0_VCODIV

CLK0_VCODIV positive := 1
Generic

Definition at line 32 of file s7_cmt_1ce1ce.vhd.

◆ CLK0_VCOMUL

CLK0_VCOMUL positive := 1
Generic

Definition at line 33 of file s7_cmt_1ce1ce.vhd.

◆ CLK0_OUTDIV

CLK0_OUTDIV positive := 1
Generic

Definition at line 34 of file s7_cmt_1ce1ce.vhd.

◆ CLK0_GENTYPE

CLK0_GENTYPE string := " PLL "
Generic

Definition at line 35 of file s7_cmt_1ce1ce.vhd.

◆ CLK0_CDUWIDTH

CLK0_CDUWIDTH positive := 7
Generic

Definition at line 36 of file s7_cmt_1ce1ce.vhd.

◆ CLK0_USECDIV

CLK0_USECDIV positive := 50
Generic

Definition at line 37 of file s7_cmt_1ce1ce.vhd.

◆ CLK0_MSECDIV

CLK0_MSECDIV positive := 1000
Generic

Definition at line 38 of file s7_cmt_1ce1ce.vhd.

◆ CLK1_VCODIV

CLK1_VCODIV positive := 1
Generic

Definition at line 39 of file s7_cmt_1ce1ce.vhd.

◆ CLK1_VCOMUL

CLK1_VCOMUL positive := 1
Generic

Definition at line 40 of file s7_cmt_1ce1ce.vhd.

◆ CLK1_OUTDIV

CLK1_OUTDIV positive := 1
Generic

Definition at line 41 of file s7_cmt_1ce1ce.vhd.

◆ CLK1_GENTYPE

CLK1_GENTYPE string := " MMCM "
Generic

Definition at line 42 of file s7_cmt_1ce1ce.vhd.

◆ CLK1_CDUWIDTH

CLK1_CDUWIDTH positive := 7
Generic

Definition at line 43 of file s7_cmt_1ce1ce.vhd.

◆ CLK1_USECDIV

CLK1_USECDIV positive := 50
Generic

Definition at line 44 of file s7_cmt_1ce1ce.vhd.

◆ CLK1_MSECDIV

CLK1_MSECDIV positive := 1000
Generic

Definition at line 45 of file s7_cmt_1ce1ce.vhd.

◆ CLKIN

CLKIN in slbit
Port

Definition at line 47 of file s7_cmt_1ce1ce.vhd.

◆ CLK0

CLK0 out slbit
Port

Definition at line 48 of file s7_cmt_1ce1ce.vhd.

◆ CE0_USEC

CE0_USEC out slbit
Port

Definition at line 49 of file s7_cmt_1ce1ce.vhd.

◆ CE0_MSEC

CE0_MSEC out slbit
Port

Definition at line 50 of file s7_cmt_1ce1ce.vhd.

◆ CLK1

CLK1 out slbit
Port

Definition at line 51 of file s7_cmt_1ce1ce.vhd.

◆ CE1_USEC

CE1_USEC out slbit
Port

Definition at line 52 of file s7_cmt_1ce1ce.vhd.

◆ CE1_MSEC

CE1_MSEC out slbit
Port

Definition at line 53 of file s7_cmt_1ce1ce.vhd.

◆ LOCKED

LOCKED out slbit
Port

Definition at line 55 of file s7_cmt_1ce1ce.vhd.

◆ ieee

ieee
Library

Definition at line 20 of file s7_cmt_1ce1ce.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 21 of file s7_cmt_1ce1ce.vhd.

◆ slvtypes

slvtypes
use clause

Definition at line 23 of file s7_cmt_1ce1ce.vhd.

◆ xlib

xlib
use clause

Definition at line 24 of file s7_cmt_1ce1ce.vhd.

◆ genlib

genlib
use clause

Definition at line 25 of file s7_cmt_1ce1ce.vhd.


The documentation for this design unit was generated from the following file: