artys7_dummy Entity Reference

Entities
syn	architecture

Libraries
ieee

Use Clauses
std_logic_1164
slvtypes	Package <slvtypes>

Ports
I_CLK100	in	slbit
I_RXD	in	slbit
O_TXD	out	slbit
I_SWI	in	slv4
I_BTN	in	slv4
O_LED	out	slv4
O_RGBLED0	out	slv3
O_RGBLED1	out	slv3

Detailed Description

Definition at line 24 of file artys7_dummy.vhd.

Member Data Documentation

I_CLK100

I_CLK100 in slbit

Port

Definition at line 27 of file artys7_dummy.vhd.

I_RXD

I_RXD in slbit

Port

Definition at line 28 of file artys7_dummy.vhd.

O_TXD

O_TXD out slbit

Port

Definition at line 29 of file artys7_dummy.vhd.

I_SWI

I_SWI in slv4

Port

Definition at line 30 of file artys7_dummy.vhd.

I_BTN

I_BTN in slv4

Port

Definition at line 31 of file artys7_dummy.vhd.

O_LED

O_LED out slv4

Port

Definition at line 32 of file artys7_dummy.vhd.

O_RGBLED0

O_RGBLED0 out slv3

Port

Definition at line 33 of file artys7_dummy.vhd.

O_RGBLED1

O_RGBLED1 out slv3

Port

Definition at line 35 of file artys7_dummy.vhd.

ieee

ieee

Library

Definition at line 19 of file artys7_dummy.vhd.

std_logic_1164

std_logic_1164

use clause

Definition at line 20 of file artys7_dummy.vhd.

slvtypes

slvtypes

use clause

Definition at line 22 of file artys7_dummy.vhd.

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The documentation for this design unit was generated from the following file:

• bplib/artys7/tb/artys7_dummy.vhd