w11 - vhd 0.794
W11 CPU core and support modules
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Libraries | Ports | Use Clauses
artys7_dram_dummy Entity Reference

Entities

syn  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
slvtypes  Package <slvtypes>

Ports

I_CLK100   in   slbit
I_RXD   in   slbit
O_TXD   out   slbit
I_SWI   in   slv4
I_BTN   in   slv4
O_LED   out   slv4
O_RGBLED0   out   slv3
O_RGBLED1   out   slv3
DDR3_DQ   inout   slv16
DDR3_DQS_P   inout   slv2
DDR3_DQS_N   inout   slv2
DDR3_ADDR   out   slv14
DDR3_BA   out   slv3
DDR3_RAS_N   out   slbit
DDR3_CAS_N   out   slbit
DDR3_WE_N   out   slbit
DDR3_RESET_N   out   slbit
DDR3_CK_P   out   slv1
DDR3_CK_N   out   slv1
DDR3_CKE   out   slv1
DDR3_CS_N   out   slv1
DDR3_DM   out   slv2
DDR3_ODT   out   slv1

Detailed Description

Definition at line 24 of file artys7_dram_dummy.vhd.

Member Data Documentation

◆ I_CLK100

I_CLK100 in slbit
Port

Definition at line 27 of file artys7_dram_dummy.vhd.

◆ I_RXD

I_RXD in slbit
Port

Definition at line 28 of file artys7_dram_dummy.vhd.

◆ O_TXD

O_TXD out slbit
Port

Definition at line 29 of file artys7_dram_dummy.vhd.

◆ I_SWI

I_SWI in slv4
Port

Definition at line 30 of file artys7_dram_dummy.vhd.

◆ I_BTN

I_BTN in slv4
Port

Definition at line 31 of file artys7_dram_dummy.vhd.

◆ O_LED

O_LED out slv4
Port

Definition at line 32 of file artys7_dram_dummy.vhd.

◆ O_RGBLED0

O_RGBLED0 out slv3
Port

Definition at line 33 of file artys7_dram_dummy.vhd.

◆ O_RGBLED1

O_RGBLED1 out slv3
Port

Definition at line 34 of file artys7_dram_dummy.vhd.

◆ DDR3_DQ

DDR3_DQ inout slv16
Port

Definition at line 35 of file artys7_dram_dummy.vhd.

◆ DDR3_DQS_P

DDR3_DQS_P inout slv2
Port

Definition at line 36 of file artys7_dram_dummy.vhd.

◆ DDR3_DQS_N

DDR3_DQS_N inout slv2
Port

Definition at line 37 of file artys7_dram_dummy.vhd.

◆ DDR3_ADDR

DDR3_ADDR out slv14
Port

Definition at line 38 of file artys7_dram_dummy.vhd.

◆ DDR3_BA

DDR3_BA out slv3
Port

Definition at line 39 of file artys7_dram_dummy.vhd.

◆ DDR3_RAS_N

DDR3_RAS_N out slbit
Port

Definition at line 40 of file artys7_dram_dummy.vhd.

◆ DDR3_CAS_N

DDR3_CAS_N out slbit
Port

Definition at line 41 of file artys7_dram_dummy.vhd.

◆ DDR3_WE_N

DDR3_WE_N out slbit
Port

Definition at line 42 of file artys7_dram_dummy.vhd.

◆ DDR3_RESET_N

DDR3_RESET_N out slbit
Port

Definition at line 43 of file artys7_dram_dummy.vhd.

◆ DDR3_CK_P

DDR3_CK_P out slv1
Port

Definition at line 44 of file artys7_dram_dummy.vhd.

◆ DDR3_CK_N

DDR3_CK_N out slv1
Port

Definition at line 45 of file artys7_dram_dummy.vhd.

◆ DDR3_CKE

DDR3_CKE out slv1
Port

Definition at line 46 of file artys7_dram_dummy.vhd.

◆ DDR3_CS_N

DDR3_CS_N out slv1
Port

Definition at line 47 of file artys7_dram_dummy.vhd.

◆ DDR3_DM

DDR3_DM out slv2
Port

Definition at line 48 of file artys7_dram_dummy.vhd.

◆ DDR3_ODT

DDR3_ODT out slv1
Port

Definition at line 50 of file artys7_dram_dummy.vhd.

◆ ieee

ieee
Library

Definition at line 19 of file artys7_dram_dummy.vhd.

◆ std_logic_1164

std_logic_1164
use clause

Definition at line 20 of file artys7_dram_dummy.vhd.

◆ slvtypes

slvtypes
use clause

Definition at line 22 of file artys7_dram_dummy.vhd.

The documentation for this design unit was generated from the following file: