1: /*
   2:  * Copyright (c) 1982, 1986 Regents of the University of California.
   3:  * All rights reserved.  The Berkeley software License Agreement
   4:  * specifies the terms and conditions for redistribution.
   5:  *
   6:  *	@(#)mtpr.h	7.1 (Berkeley) 6/5/86
   7:  */
   8: 
   9: /*
  10:  * VAX processor register numbers
  11:  */
  12: 
  13: #define KSP 0x0     /* kernel stack pointer */
  14: #define ESP 0x1     /* exec stack pointer */
  15: #define SSP 0x2     /* supervisor stack pointer */
  16: #define USP 0x3     /* user stack pointer */
  17: #define ISP 0x4     /* interrupt stack pointer */
  18: #define P0BR    0x8     /* p0 base register */
  19: #define P0LR    0x9     /* p0 length register */
  20: #define P1BR    0xa     /* p1 base register */
  21: #define P1LR    0xb     /* p1 length register */
  22: #define SBR 0xc     /* system segment base register */
  23: #define SLR 0xd     /* system segment length register */
  24: #define PCBB    0x10        /* process control block base */
  25: #define SCBB    0x11        /* system control block base */
  26: #define IPL 0x12        /* interrupt priority level */
  27: #define ASTLVL  0x13        /* async. system trap level */
  28: #define SIRR    0x14        /* software interrupt request */
  29: #define SISR    0x15        /* software interrupt summary */
  30: #define ICCS    0x18        /* interval clock control */
  31: #define NICR    0x19        /* next interval count */
  32: #define ICR 0x1a        /* interval count */
  33: #define TODR    0x1b        /* time of year (day) */
  34: #define RXCS    0x20        /* console receiver control and status */
  35: #define RXDB    0x21        /* console receiver data buffer */
  36: #define TXCS    0x22        /* console transmitter control and status */
  37: #define TXDB    0x23        /* console transmitter data buffer */
  38: #define MAPEN   0x38        /* memory management enable */
  39: #define TBIA    0x39        /* translation buffer invalidate all */
  40: #define TBIS    0x3a        /* translation buffer invalidate single */
  41: #define PMR 0x3d        /* performance monitor enable */
  42: #define SID 0x3e        /* system identification */
  43: 
  44: #if defined(VAX780) || defined(VAX8600)
  45: #define ACCS    0x28        /* accelerator control and status */
  46: #endif
  47: 
  48: #if defined(VAX8600)
  49: #define TBCHK   0x3f        /* Translation Buffer Check */
  50: #define PAMACC  0x40        /* PAMM access */
  51: #define PAMLOC  0x41        /* PAMM location */
  52: #define CSWP    0x42        /* Cache sweep */
  53: #define MDECC   0x43        /* MBOX data ecc register */
  54: #define MENA    0x44        /* MBOX error enable register */
  55: #define MDCTL   0x45        /* MBOX data control register */
  56: #define MCCTL   0x46        /* MBOX mcc control register */
  57: #define MERG    0x47        /* MBOX	error generator register */
  58: #define CRBT    0x48        /* Console reboot */
  59: #define DFI 0x49        /* Diag fault insertion register */
  60: #define EHSR    0x4a        /* Error handling status register */
  61: #define STXCS   0x4c        /* Console block storage C/S */
  62: #define STXDB   0x4d        /* Console block storage D/B */
  63: #define ESPA    0x4e        /* EBOX scratchpad address */
  64: #define ESPD    0x4f        /* EBOX sratchpad data */
  65: #endif
  66: 
  67: #if defined(VAX780)
  68: #define ACCR    0x29        /* accelerator maintenance */
  69: #define WCSA    0x2c        /* WCS address */
  70: #define WCSD    0x2d        /* WCS data */
  71: #define SBIFS   0x30        /* SBI fault and status */
  72: #define SBIS    0x31        /* SBI silo */
  73: #define SBISC   0x32        /* SBI silo comparator */
  74: #define SBIMT   0x33        /* SBI maintenance */
  75: #define SBIER   0x34        /* SBI error register */
  76: #define SBITA   0x35        /* SBI timeout address */
  77: #define SBIQC   0x36        /* SBI quadword clear */
  78: #define MBRK    0x3c        /* micro-program breakpoint */
  79: #endif
  80: 
  81: #if defined(VAX750) || defined(VAX730)
  82: #define MCSR    0x17        /* machine check status register */
  83: #define CSRS    0x1c        /* console storage receive status register */
  84: #define CSRD    0x1d        /* console storage receive data register */
  85: #define CSTS    0x1e        /* console storage transmit status register */
  86: #define CSTD    0x1f        /* console storage transmit data register */
  87: #define TBDR    0x24        /* translation buffer disable register */
  88: #define CADR    0x25        /* cache disable register */
  89: #define MCESR   0x26        /* machine check error summary register */
  90: #define CAER    0x27        /* cache error */
  91: #define IUR 0x37        /* init unibus register */
  92: #define TB  0x3b        /* translation buffer */
  93: #endif

Defined macros

ACCR defined in line 68; never used
ACCS defined in line 45; used 2 times
ASTLVL defined in line 27; never used
CADR defined in line 88; used 1 times
CAER defined in line 90; never used
CRBT defined in line 58; never used
CSRD defined in line 84; used 9 times
CSRS defined in line 83; used 13 times
CSTD defined in line 86; used 2 times
CSTS defined in line 85; used 10 times
CSWP defined in line 52; used 1 times
DFI defined in line 59; never used
EHSR defined in line 60; used 2 times
ESP defined in line 14; never used
ESPA defined in line 63; never used
ESPD defined in line 64; never used
ICCS defined in line 30; used 6 times
IPL defined in line 26; used 19 times
ISP defined in line 17; never used
IUR defined in line 91; used 2 times
KSP defined in line 13; never used
MAPEN defined in line 38; used 4 times
MBRK defined in line 78; never used
MCCTL defined in line 56; never used
MCESR defined in line 89; used 4 times
MCSR defined in line 82; used 1 times
MDCTL defined in line 55; never used
MDECC defined in line 53; never used
MENA defined in line 54; never used
MERG defined in line 57; never used
NICR defined in line 31; used 1 times
P0LR defined in line 19; used 5 times
P1BR defined in line 20; used 4 times
P1LR defined in line 21; used 4 times
PAMACC defined in line 50; never used
PAMLOC defined in line 51; never used
PCBB defined in line 24; used 3 times
PMR defined in line 41; never used
RXCS defined in line 34; used 4 times
RXDB defined in line 35; used 3 times
SBIER defined in line 75; used 2 times
SBIFS defined in line 71; used 3 times
SBIMT defined in line 74; used 1 times
SBIQC defined in line 77; never used
SBIS defined in line 72; never used
SBISC defined in line 73; never used
SBITA defined in line 76; never used
SBR defined in line 22; used 2 times
SCBB defined in line 25; used 1 times
SIRR defined in line 28; never used
SISR defined in line 29; never used
SLR defined in line 23; used 2 times
SSP defined in line 15; never used
STXCS defined in line 61; used 9 times
STXDB defined in line 62; used 4 times
TB defined in line 92; never used
TBCHK defined in line 49; never used
TBDR defined in line 87; never used
TODR defined in line 33; used 14 times
TXCS defined in line 36; used 16 times
TXDB defined in line 37; used 13 times
USP defined in line 16; used 4 times
WCSA defined in line 69; never used
WCSD defined in line 70; never used

Usage of this include

mtpr.h used 58 times
Last modified: 1986-06-05
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