w11 - vhd  0.72
W11 CPU core and support modules
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syn Architecture Reference

Processes

proc_regs  ( CLK )
proc_next  ( R_REGS , CE_MSEC , HIO_CNTL , FX2_MONI , RXWDATA , RXWVAL , TXWBUSY , TX2WBUSY , RXHOLD_L , TXBUSY , TX2BUSY )

Constants

regs_init  regs_type := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ' 0 ' )

Types

record: regs_type RXDATA : slv16%
%%txdata : slv16%
%tx2data : slv16%
%rxsecnt : slv16%
%rxcnt : slv32%
%txcnt : slv32%
%tx2cnt : slv32%
%rxthrottle : slbit%

Signals

R_REGS  regs_type := regs_init
N_REGS  regs_type := regs_init
RXWDATA  slv16 := ( others = > ' 0 ' )
RXWVAL  slbit := ' 0 '
RXWHOLD  slbit := ' 0 '
RXODD  slbit := ' 0 '
TXWDATA  slv16 := ( others = > ' 0 ' )
TXWENA  slbit := ' 0 '
TXWBUSY  slbit := ' 0 '
TXODD  slbit := ' 0 '
TX2WDATA  slv16 := ( others = > ' 0 ' )
TX2WENA  slbit := ' 0 '
TX2WBUSY  slbit := ' 0 '
TX2ODD  slbit := ' 0 '
RXHOLD_L  slbit := ' 0 '
TXENA_L  slbit := ' 0 '
TX2ENA_L  slbit := ' 0 '
CNTL_RESET_L  slbit := ' 0 '

Instantiations

rxb2w  byte2word <Entity byte2word>
tx1w2b  word2byte <Entity word2byte>
tx2w2b  word2byte <Entity word2byte>

Detailed Description

Definition at line 63 of file tst_fx2loop.vhd.

Member Function Documentation

proc_regs (   CLK )

Definition at line 152 of file tst_fx2loop.vhd.

proc_next (   R_REGS ,
  CE_MSEC ,
  HIO_CNTL ,
  FX2_MONI ,
  RXWDATA ,
  RXWVAL ,
  TXWBUSY ,
  TX2WBUSY ,
  RXHOLD_L ,
  TXBUSY ,
  TX2BUSY  
)
Process

Definition at line 165 of file tst_fx2loop.vhd.

Member Data Documentation

regs_type (   RXDATA : slv16%
  %%txdata : slv16%
  %tx2data : slv16%
  %rxsecnt : slv16%
  %rxcnt : slv32%
  %txcnt : slv32%
  %tx2cnt : slv32%
  %rxthrottle : slbit%  
)
Type

Definition at line 65 of file tst_fx2loop.vhd.

regs_init regs_type := ( ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ( others = > ' 0 ' ) , ' 0 ' )
Constant

Definition at line 76 of file tst_fx2loop.vhd.

R_REGS regs_type := regs_init
Signal

Definition at line 87 of file tst_fx2loop.vhd.

N_REGS regs_type := regs_init
Signal

Definition at line 88 of file tst_fx2loop.vhd.

RXWDATA slv16 := ( others = > ' 0 ' )
Signal

Definition at line 90 of file tst_fx2loop.vhd.

RXWVAL slbit := ' 0 '
Signal

Definition at line 91 of file tst_fx2loop.vhd.

RXWHOLD slbit := ' 0 '
Signal

Definition at line 92 of file tst_fx2loop.vhd.

RXODD slbit := ' 0 '
Signal

Definition at line 93 of file tst_fx2loop.vhd.

TXWDATA slv16 := ( others = > ' 0 ' )
Signal

Definition at line 95 of file tst_fx2loop.vhd.

TXWENA slbit := ' 0 '
Signal

Definition at line 96 of file tst_fx2loop.vhd.

TXWBUSY slbit := ' 0 '
Signal

Definition at line 97 of file tst_fx2loop.vhd.

TXODD slbit := ' 0 '
Signal

Definition at line 98 of file tst_fx2loop.vhd.

TX2WDATA slv16 := ( others = > ' 0 ' )
Signal

Definition at line 99 of file tst_fx2loop.vhd.

TX2WENA slbit := ' 0 '
Signal

Definition at line 100 of file tst_fx2loop.vhd.

TX2WBUSY slbit := ' 0 '
Signal

Definition at line 101 of file tst_fx2loop.vhd.

TX2ODD slbit := ' 0 '
Signal

Definition at line 102 of file tst_fx2loop.vhd.

RXHOLD_L slbit := ' 0 '
Signal

Definition at line 104 of file tst_fx2loop.vhd.

TXENA_L slbit := ' 0 '
Signal

Definition at line 105 of file tst_fx2loop.vhd.

TX2ENA_L slbit := ' 0 '
Signal

Definition at line 106 of file tst_fx2loop.vhd.

CNTL_RESET_L slbit := ' 0 '
Signal

Definition at line 107 of file tst_fx2loop.vhd.

rxb2w byte2word
Instantiation

Definition at line 113 of file tst_fx2loop.vhd.

tx1w2b word2byte
Instantiation

Definition at line 126 of file tst_fx2loop.vhd.

tx2w2b word2byte
Instantiation

Definition at line 139 of file tst_fx2loop.vhd.

The documentation for this class was generated from the following file: