1: /*	@(#)if_qtreg.h	1.0 (GTE) 10/12/92 */
   2: 
   3: /*
   4:  * Modification History
   5:  *  26 Feb 93 -- sms
   6:  *	Add defines for number of receive and transmit ring descriptors.
   7:  *
   8:  *  12 Oct 92 -- Steven M. Schultz (sms)
   9:  *	Created from the DELQA-PLUS Addendum to the DELQA User's Guide.
  10: */
  11: 
  12: #define QT_MAX_RCV  32
  13: #define QT_MAX_XMT  12
  14: 
  15: /* Receive ring descriptor and bit/field definitions */
  16: 
  17:     struct  qt_rring
  18:         {
  19:         short   rmd0;
  20:         short   rmd1;
  21:         short   rmd2;
  22:         short   rmd3;
  23:         short   rmd4;
  24:         short   rmd5;
  25:         struct  qt_uba  *rhost0;
  26:         short   rhost1;
  27:         };
  28: 
  29: #define RMD0_ERR3   0x4000      /* Error summary. FRA|CRC|OFL|BUF */
  30: #define RMD0_FRA    0x2000      /* Framing error */
  31: #define RMD0_OFL    0x1000      /* Overflow error.  Oversized packet */
  32: #define RMD0_CRC    0x0800      /* CRC error */
  33: #define RMD0_BUF    0x0400      /* Internal device buffer error */
  34: #define RMD0_STP    0x0200      /* Start of packet */
  35: #define RMD0_ENP    0x0100      /* End of packet */
  36: 
  37: #define RMD1_MCNT   0x0fff      /* Message byte count */
  38: 
  39: #define RMD2_ERR4   0x8000      /* Error summary.  BBL|CER|MIS */
  40: #define RMD2_BBL    0x4000      /* Babble error on transmit */
  41: #define RMD2_CER    0x2000      /* Collision error on transmit */
  42: #define RMD2_MIS    0x1000      /* Packet lost on receive */
  43: #define RMD2_EOR    0x0800      /* End of receive ring */
  44: #define RMD2_RON    0x0020      /* Receiver on */
  45: #define RMD2_TON    0x0010      /* Transmitter on */
  46: 
  47: #define RMD3_OWN    0x8000      /* Ownership field. */
  48: 
  49: #define RMD4_LADR   0xfff8      /* Octabyte aligned low address bits */
  50: 
  51: #define RMD5_HADR   0x003f      /* High 6 bits of buffer address */
  52: 
  53: #define RMD0_BITS   "\010\016FRA\015OFL\014CRC\013BUF\012STP\011ENP"
  54: #define RMD2_BITS   "\010\017BBL\014CER\013MIS\012EOR\06RON\05TON"
  55: 
  56: /* Transmit ring descriptor and bit/field definitions */
  57: 
  58:     struct  qt_tring
  59:         {
  60:         short   tmd0;
  61:         short   tmd1;
  62:         short   tmd2;
  63:         short   tmd3;
  64:         short   tmd4;
  65:         short   tmd5;
  66:         struct  qt_uba  *thost0;
  67:         short   thost1;
  68:         };
  69: 
  70: #define TMD0_ERR1   0x4000      /* Error summary.  LCO|LCA|RTR */
  71: #define TMD0_MOR    0x1000      /* More than one retry on transmit */
  72: #define TMD0_ONE    0x0800      /* One retry on transmit */
  73: #define TMD0_DEF    0x0400      /* Deferral during transmit */
  74: 
  75: #define TMD1_LCO    0x1000      /* Late collision on transmit */
  76: #define TMD1_LCA    0x0800      /* Loss of carrier on transmit */
  77: #define TMD1_RTR    0x0400      /* Retry error on transmit */
  78: #define TMD1_TDR    0x03ff      /* Time Domain Reflectometry value */
  79: 
  80: #define TMD2_ERR2   0x8000      /* Error summary.  BBL|CER|MIS */
  81: #define TMD2_BBL    0x4000      /* Babble error on transmit */
  82: #define TMD2_CER    0x2000      /* Collision error on transmit */
  83: #define TMD2_MIS    0x1000      /* Packet lost on receive */
  84: #define TMD2_EOR    0x0800      /* Endof Receive ring reached */
  85: #define TMD2_RON    0x0020      /* Receiver on */
  86: #define TMD2_TON    0x0010      /* Transmitter on */
  87: 
  88: #define TMD3_OWN    0x8000      /* Ownership field */
  89: #define TMD3_FOT    0x4000      /* First of two flag */
  90: #define TMD3_BCT    0x0fff      /* Byte count */
  91: 
  92: #define TMD4_LADR   0xfff8      /* Octabyte aligned low address bits */
  93: 
  94: #define TMD5_HADR   0x003f      /* High 6 bits of buffer address */
  95: 
  96: #define TMD1_BITS   "\010\015LCO\014LCA\013RTR"
  97: #define TMD2_BITS   "\010\017BBL\016CER\015MIS\014EOR\06RON\05TON"
  98: 
  99: /* DELQA-YM CSR layout */
 100: 
 101:     struct  qtcsr0
 102:         {
 103:         short   Ibal;
 104:         short   Ibah;
 105:         short   Icr;
 106:         short   pad0;
 107:         short   Srqr;
 108:         short   pad1;
 109:         };
 110: 
 111:     struct  qtdevice
 112:         {
 113:         union   {
 114:             u_char  Sarom[12];
 115:             struct  qtcsr0  csr0;
 116:             } qt_un0;
 117:         short   srr;
 118:         short   arqr;
 119:         };
 120: 
 121: #define ibal    qt_un0.csr0.Ibal
 122: #define ibah    qt_un0.csr0.Ibah
 123: #define srqr    qt_un0.csr0.Srqr
 124: #define icr qt_un0.csr0.Icr
 125: #define sarom   qt_un0.Sarom
 126: 
 127: /* SRR definitions */
 128: 
 129: #define SRR_FES     0x8000
 130: #define SRR_CHN     0x4000
 131: #define SRR_NXM     0x1000
 132: #define SRR_PER     0x0800
 133: #define SRR_IME     0x0400
 134: #define SRR_TBL     0x0200
 135: #define SRR_RESP    0x0003
 136: #define SRR_BITS    "\010\017CHN\015NXM\014PER\013IME\012TBL"
 137: 
 138: /* SRQR definitions */
 139: 
 140: #define SRQR_REQ    0x0003
 141: 
 142: /* ARQR definitions */
 143: 
 144: #define ARQR_TRQ    0x8000
 145: #define ARQR_RRQ    0x0080
 146: #define ARQR_SR     0x0002
 147: 
 148: /* define ICR definitions */
 149: 
 150: #define ICR_CMD     0x0001
 151: 
 152: /* DELQA registers used to shift into -T mode */
 153: 
 154: #define xcr0    qt_un0.csr0.Ibal
 155: #define xcr1    qt_un0.csr0.Ibah
 156: 
 157: /* INIT block structure and definitions */
 158: 
 159:     struct  qt_init
 160:         {
 161:         short   mode;
 162:         u_char  paddr[6];   /* 48 bit physical address */
 163:         u_char  laddr[8];   /* 64 bit logical address filter */
 164:         u_short rx_lo;      /* low 16 bits of receive ring addr */
 165:         u_short rx_hi;      /* high 6 bits of receive ring addr */
 166:         u_short tx_lo;      /* low 16 bits of transmit ring addr */
 167:         u_short tx_hi;      /* high 6 bits of transmit ring addr */
 168:         u_short options;
 169:         u_short vector;
 170:         u_short hit;
 171:         char    passwd[6];
 172:         };
 173: 
 174: #define INIT_MODE_PRO   0x8000      /* Promiscuous mode */
 175: #define INIT_MODE_INT   0x0040      /* Internal Loopback */
 176: #define INIT_MODE_DRT   0x0020      /* Disable Retry */
 177: #define INIT_MODE_DTC   0x0008      /* Disable Transmit CRC */
 178: #define INIT_MODE_LOP   0x0004      /* Loopback */
 179: 
 180: #define INIT_OPTIONS_HIT 0x0002     /* Host Inactivity Timeout Flag */
 181: #define INIT_OPTIONS_INT 0x0001     /* Interrupt Enable Flag */

Defined struct's

qt_init defined in line 159; used 16 times
qt_rring defined in line 17; used 10 times
qt_tring defined in line 58; used 12 times
qtcsr0 defined in line 101; used 2 times
  • in line 115(2)
qtdevice defined in line 111; used 8 times

Defined macros

ARQR_RRQ defined in line 145; used 1 times
ARQR_SR defined in line 146; used 1 times
ARQR_TRQ defined in line 144; used 1 times
ICR_CMD defined in line 150; never used
INIT_MODE_DRT defined in line 176; never used
INIT_MODE_DTC defined in line 177; never used
INIT_MODE_INT defined in line 175; never used
INIT_MODE_LOP defined in line 178; never used
INIT_MODE_PRO defined in line 174; never used
INIT_OPTIONS_HIT defined in line 180; never used
INIT_OPTIONS_INT defined in line 181; used 1 times
QT_MAX_RCV defined in line 12; used 4 times
QT_MAX_XMT defined in line 13; used 4 times
RMD0_BITS defined in line 53; used 1 times
RMD0_BUF defined in line 33; never used
RMD0_CRC defined in line 32; never used
RMD0_ENP defined in line 35; used 2 times
RMD0_ERR3 defined in line 29; used 1 times
RMD0_FRA defined in line 30; never used
RMD0_OFL defined in line 31; never used
RMD0_STP defined in line 34; used 2 times
RMD1_MCNT defined in line 37; used 1 times
RMD2_BBL defined in line 40; never used
RMD2_BITS defined in line 54; used 1 times
RMD2_CER defined in line 41; never used
RMD2_EOR defined in line 43; never used
RMD2_ERR4 defined in line 39; used 1 times
RMD2_MIS defined in line 42; never used
RMD2_RON defined in line 44; never used
RMD2_TON defined in line 45; never used
RMD3_OWN defined in line 47; used 3 times
RMD4_LADR defined in line 49; never used
RMD5_HADR defined in line 51; never used
SRQR_REQ defined in line 140; never used
SRR_BITS defined in line 136; used 1 times
SRR_CHN defined in line 130; never used
SRR_FES defined in line 129; never used
SRR_IME defined in line 133; never used
SRR_NXM defined in line 131; never used
SRR_PER defined in line 132; never used
SRR_RESP defined in line 135; used 2 times
SRR_TBL defined in line 134; never used
TMD0_DEF defined in line 73; never used
TMD0_ERR1 defined in line 70; used 1 times
TMD0_MOR defined in line 71; never used
TMD0_ONE defined in line 72; never used
TMD1_BITS defined in line 96; never used
TMD1_LCA defined in line 76; never used
TMD1_LCO defined in line 75; never used
TMD1_RTR defined in line 77; never used
TMD1_TDR defined in line 78; never used
TMD2_BBL defined in line 81; used 1 times
TMD2_BITS defined in line 97; used 1 times
TMD2_CER defined in line 82; used 1 times
TMD2_EOR defined in line 84; never used
TMD2_ERR2 defined in line 80; used 1 times
TMD2_MIS defined in line 83; used 1 times
TMD2_RON defined in line 85; never used
TMD2_TON defined in line 86; never used
TMD3_BCT defined in line 90; used 1 times
TMD3_FOT defined in line 89; never used
TMD3_OWN defined in line 88; used 3 times
TMD4_LADR defined in line 92; never used
TMD5_HADR defined in line 94; used 1 times
ibah defined in line 122; used 1 times
ibal defined in line 121; used 1 times
icr defined in line 124; never used
sarom defined in line 125; used 6 times
srqr defined in line 123; used 1 times
xcr0 defined in line 154; used 1 times
xcr1 defined in line 155; used 1 times

Usage of this include

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