1: /*	@(#)if_qereg.h	7.1.1 (2.11BSD) 1997/2/16 */
   2: 
   3: /* @(#)if_qereg.h	1.2 (ULTRIX) 1/3/85 */
   4: 
   5: /****************************************************************
   6:  *								*
   7:  *        Licensed from Digital Equipment Corporation 		*
   8:  *                       Copyright (c) 				*
   9:  *               Digital Equipment Corporation			*
  10:  *                   Maynard, Massachusetts 			*
  11:  *                         1985, 1986 				*
  12:  *                    All rights reserved. 			*
  13:  *								*
  14:  *        The Information in this software is subject to change *
  15:  *   without notice and should not be construed as a commitment *
  16:  *   by  Digital  Equipment  Corporation.   Digital   makes  no *
  17:  *   representations about the suitability of this software for *
  18:  *   any purpose.  It is supplied "As Is" without expressed  or *
  19:  *   implied  warranty. 					*
  20:  *								*
  21:  *        If the Regents of the University of California or its *
  22:  *   licensees modify the software in a manner creating  	*
  23:  *   diriviative copyright rights, appropriate copyright  	*
  24:  *   legends may be placed on  the drivative work in addition   *
  25:  *   to that set forth above. 					*
  26:  *								*
  27:  ****************************************************************/
  28: /* ---------------------------------------------------------------------
  29:  * Modification History
  30:  *
  31:  *  16 Feb. 1997 -- sms
  32:  *	Add DELQA mode select and Identity test bit definitions.
  33:  *
  34:  *  13 Feb. 84 -- rjl
  35:  *
  36:  *	Initial version of driver. derived from IL driver.
  37:  * ---------------------------------------------------------------------
  38:  */
  39: 
  40: /*
  41:  * Digital Q-BUS to NI Adapter
  42:  */
  43: 
  44: #ifdef  pdp11
  45: #define qe_rcvlist_lo       qe_LOrcv
  46: #define qe_rcvlist_hi       qe_HIrcv
  47: #define qe_xmtlist_lo       qe_LOxmt
  48: #define qe_xmtlist_hi       qe_HIxmt
  49: #define qe_status1      qe_stat1
  50: #define qe_status2      qe_stat2
  51: #define qe_odd_begin        qe_begin_odd
  52: #define qe_odd_end      qe_end_odd
  53: #define qe_addr_hi      qe_HIaddr
  54: #define qe_addr_lo      qe_LOaddr
  55: #endif	pdp11
  56: 
  57: struct qedevice {
  58:     u_short qe_sta_addr[2];     /* Station address (actually 6 	*/
  59:     u_short qe_rcvlist_lo;      /* Receive list lo address 	*/
  60:     u_short qe_rcvlist_hi;      /* Receive list hi address 	*/
  61:     u_short qe_xmtlist_lo;      /* Transmit list lo address 	*/
  62:     u_short qe_xmtlist_hi;      /* Transmit list hi address 	*/
  63:     u_short qe_vector;      /* Interrupt vector 		*/
  64:     u_short qe_csr;         /* Command and Status Register 	*/
  65: };
  66: 
  67: /*
  68:  * Command and status bits (csr)
  69:  */
  70: #define QE_RCV_ENABLE   0x0001      /* Receiver enable		*/
  71: #define QE_RESET    0x0002      /* Software reset		*/
  72: #define QE_NEX_MEM_INT  0x0004      /* Non existant mem interrupt	*/
  73: #define QE_LOAD_ROM 0x0008      /* Load boot/diag from rom	*/
  74: #define QE_XL_INVALID   0x0010      /* Transmit list invalid	*/
  75: #define QE_RL_INVALID   0x0020      /* Receive list invalid		*/
  76: #define QE_INT_ENABLE   0x0040      /* Interrupt enable		*/
  77: #define QE_XMIT_INT 0x0080      /* Transmit interrupt		*/
  78: #define QE_ILOOP    0x0100      /* Internal loopback		*/
  79: #define QE_ELOOP    0x0200      /* External loopback		*/
  80: #define QE_STIM_ENABLE  0x0400      /* Sanity timer enable		*/
  81: #define QE_POWERUP  0x1000      /* Tranceiver power on		*/
  82: #define QE_CARRIER  0x2000      /* Carrier detect		*/
  83: #define QE_RCV_INT  0x8000      /* Receiver interrupt		*/
  84: 
  85: #define QE_VEC_MS   0x8000      /* DELQA mode select (1=LQA)	*/
  86: #define QE_VEC_ID   0x0001      /* Identity test bit		*/
  87: 
  88: /*
  89:  * Transmit and receive ring discriptor ---------------------------
  90:  *
  91:  * The QNA uses the flag, status1 and the valid bit as a handshake/semiphore
  92:  * mechinism.
  93:  *
  94:  * The flag word is written on ( bits 15,15 set to 1 ) when it reads the
  95:  * descriptor. If the valid bit is set it considers the address to be valid.
  96:  * When it uses the buffer pointed to by the valid address it sets status word
  97:  * one.
  98:  */
  99: struct qe_ring  {
 100:     u_short qe_flag;        /* Buffer utilization flags	*/
 101:     u_short qe_addr_hi:6,       /* Hi order bits of buffer addr	*/
 102:           qe_odd_begin:1,       /* Odd byte begin and end (xmit)*/
 103:           qe_odd_end:1,
 104:           qe_fill1:4,
 105:           qe_setup:1,       /* Setup packet			*/
 106:           qe_eomsg:1,       /* End of message flag		*/
 107:           qe_chain:1,       /* Chain address instead of buf */
 108:           qe_valid:1;       /* Address field is valid	*/
 109:     u_short qe_addr_lo;     /* Low order bits of address	*/
 110:     short qe_buf_len;       /* Negative buffer length	*/
 111:     u_short qe_status1;     /* Status word one		*/
 112:     u_short qe_status2;     /* Status word two		*/
 113: };
 114: 
 115: /*
 116:  * Status word definations (receive)
 117:  *	word1
 118:  */
 119: #define QE_OVF          0x0001  /* Receiver overflow		*/
 120: #define QE_CRCERR       0x0002  /* CRC error			*/
 121: #define QE_FRAME        0x0004  /* Framing alignment error	*/
 122: #define QE_SHORT        0x0008  /* Packet size < 10 bytes	*/
 123: #define QE_RBL_HI       0x0700  /* Hi bits of receive len	*/
 124: #define QE_RUNT         0x0800  /* Runt packet			*/
 125: #define QE_DISCARD      0x1000  /* Discard the packet		*/
 126: #define QE_ESETUP       0x2000  /* Looped back setup or eloop	*/
 127: #define QE_ERROR        0x4000  /* Receiver error		*/
 128: #define QE_LASTNOT      0x8000  /* Not the last in the packet	*/
 129: /*	word2								*/
 130: #define QE_RBL_LO       0x00ff  /* Low bits of receive len	*/
 131: 
 132: /*
 133:  * Status word definations (transmit)
 134:  *	word1
 135:  */
 136: #define QE_CCNT         0x00f0  /* Collision count this packet	*/
 137: #define QE_FAIL         0x0100  /* Heart beat check failure	*/
 138: #define QE_ABORT        0x0200  /* Transmission abort		*/
 139: #define QE_STE16        0x0400  /* Sanity timer default on	*/
 140: #define QE_NOCAR        0x0800  /* No carrier			*/
 141: #define QE_LOSS         0x1000  /* Loss of carrier while xmit	*/
 142: /*	word2								*/
 143: #define QE_TDR          0x3fff  /* Time domain reflectometry	*/
 144: 
 145: /*
 146:  * General constant definations
 147:  */
 148: #define QEALLOC         0   /* Allocate an mbuf		*/
 149: #define QENOALLOC       1   /* No mbuf allocation		*/
 150: #define QEDEALLOC       2   /* Release an mbuf chain	*/
 151: #define QEREALLOC       3   /* Reallocate an mbuf		*/
 152: 
 153: #define QE_NOTYET       0x8000  /* Descriptor not in use yet	*/
 154: #define QE_INUSE        0x4000  /* Descriptor being used by QNA	*/
 155: #define QE_MASK         0xc000  /* Lastnot/error/used mask	*/

Defined struct's

qe_ring defined in line 99; used 24 times
qedevice defined in line 57; used 22 times

Defined macros

QEALLOC defined in line 148; never used
QEDEALLOC defined in line 150; never used
QENOALLOC defined in line 149; never used
QEREALLOC defined in line 151; never used
QE_ABORT defined in line 138; never used
QE_CARRIER defined in line 82; never used
QE_CCNT defined in line 136; used 1 times
QE_CRCERR defined in line 120; never used
QE_DISCARD defined in line 125; never used
QE_ELOOP defined in line 79; never used
QE_ERROR defined in line 127; used 2 times
QE_ESETUP defined in line 126; used 1 times
QE_FAIL defined in line 137; never used
QE_FRAME defined in line 121; never used
QE_ILOOP defined in line 78; used 3 times
QE_INT_ENABLE defined in line 76; used 3 times
QE_INUSE defined in line 154; never used
QE_LASTNOT defined in line 128; never used
QE_LOAD_ROM defined in line 73; never used
QE_LOSS defined in line 141; never used
QE_MASK defined in line 155; used 2 times
QE_NEX_MEM_INT defined in line 72; used 1 times
QE_NOCAR defined in line 140; never used
QE_NOTYET defined in line 153; used 10 times
QE_OVF defined in line 119; never used
QE_POWERUP defined in line 81; never used
QE_RBL_HI defined in line 123; used 1 times
QE_RBL_LO defined in line 130; used 1 times
QE_RCV_ENABLE defined in line 70; used 3 times
QE_RCV_INT defined in line 83; used 4 times
QE_RESET defined in line 71; used 3 times
QE_RL_INVALID defined in line 75; used 1 times
QE_RUNT defined in line 124; never used
QE_SHORT defined in line 122; never used
QE_STE16 defined in line 139; never used
QE_STIM_ENABLE defined in line 80; never used
QE_TDR defined in line 143; never used
QE_VEC_ID defined in line 86; used 3 times
QE_VEC_MS defined in line 85; never used
QE_XL_INVALID defined in line 74; used 1 times
QE_XMIT_INT defined in line 77; used 4 times
qe_addr_hi defined in line 53; used 5 times
qe_addr_lo defined in line 54; used 6 times
qe_odd_begin defined in line 51; never used
qe_odd_end defined in line 52; used 2 times
qe_rcvlist_hi defined in line 46; used 4 times
qe_rcvlist_lo defined in line 45; used 4 times
qe_status1 defined in line 49; used 13 times
qe_status2 defined in line 50; used 2 times
qe_xmtlist_hi defined in line 48; used 2 times
qe_xmtlist_lo defined in line 47; used 2 times

Usage of this include

Last modified: 1997-02-16
Generated: 2016-12-26
Generated by src2html V0.67
page hit count: 1061
Valid CSS Valid XHTML 1.0 Strict