1: /*
   2:  * SCCSID: @(#)if_dereg.h	1.1	(2.11BSD GTE)	12/31/93
   3:  *
   4:  * DEC DEUNA interface
   5:  */
   6: 
   7: /*
   8:  * Define unibus ehternet controller types
   9:  */
  10: #define DEUNA 0
  11: #define DELUA 1
  12: 
  13: struct dedevice {
  14:     union {
  15:         short   p0_w;
  16:         char    p0_b[2];
  17:     } u_p0;
  18: #define pcsr0       u_p0.p0_w
  19: #define pclow       u_p0.p0_b[0]
  20: #define pchigh      u_p0.p0_b[1]
  21:     short   pcsr1;
  22:     short   pcsr2;
  23:     short   pcsr3;
  24: };
  25: 
  26: /*
  27:  * PCSR 0 bit descriptions
  28:  */
  29: #define PCSR0_SERI  0x8000      /* Status error interrupt */
  30: #define PCSR0_PCEI  0x4000      /* Port command error interrupt */
  31: #define PCSR0_RXI   0x2000      /* Receive done interrupt */
  32: #define PCSR0_TXI   0x1000      /* Transmit done interrupt */
  33: #define PCSR0_DNI   0x0800      /* Done interrupt */
  34: #define PCSR0_RCBI  0x0400      /* Receive buffer unavail intrpt */
  35: #define PCSR0_FATI  0x0100      /* Fatal error interrupt */
  36: #define PCSR0_INTR  0x0080      /* Interrupt summary */
  37: #define PCSR0_INTE  0x0040      /* Interrupt enable */
  38: #define PCSR0_RSET  0x0020      /* DEUNA reset */
  39: #define PCSR0_CMASK 0x000f      /* command mask */
  40: 
  41: #define PCSR0_BITS  "\20\20SERI\17PCEI\16RXI\15TXI\14DNI\13RCBI\11FATI\10INTR\7INTE\6RSET"
  42: 
  43: /* bits 0-3 are for the PORT_COMMAND */
  44: #define CMD_NOOP    0x0
  45: #define CMD_GETPCBB 0x1     /* Get PCB Block */
  46: #define CMD_GETCMD  0x2     /* Execute command in PCB */
  47: #define CMD_STEST   0x3     /* Self test mode */
  48: #define CMD_START   0x4     /* Reset xmit and receive ring ptrs */
  49: #define CMD_BOOT    0x5     /* Boot DEUNA */
  50: #define CMD_PDMD    0x8     /* Polling demand */
  51: #define CMD_TMRO    0x9     /* Sanity timer on */
  52: #define CMD_TMRF    0xa     /* Sanity timer off */
  53: #define CMD_RSTT    0xb     /* Reset sanity timer */
  54: #define CMD_STOP    0xf     /* Suspend operation */
  55: 
  56: /*
  57:  * PCSR 1 bit descriptions
  58:  */
  59: #define PCSR1_XPWR  0x8000      /* Transceiver power BAD */
  60: #define PCSR1_ICAB  0x4000      /* Interconnect cabling BAD */
  61: #define PCSR1_STCODE    0x3f00      /* Self test error code */
  62: #define PCSR1_PCTO  0x0080      /* Port command timed out */
  63: #define PCSR1_DEVID 0x0070      /* Device id DEUNA=0, DELUA=1 */
  64: #define PCSR1_STMASK    0x0007      /* State */
  65: 
  66: /* bit 0-3 are for STATE */
  67: #define STAT_RESET  0x0
  68: #define STAT_PRIMLD 0x1     /* Primary load */
  69: #define STAT_READY  0x2
  70: #define STAT_RUN    0x3
  71: #define STAT_UHALT  0x5     /* UNIBUS halted */
  72: #define STAT_NIHALT 0x6     /* NI halted */
  73: #define STAT_NIUHALT    0x7     /* NI and UNIBUS Halted */
  74: 
  75: #define PCSR1_BITS  "\20\20XPWR\17ICAB\10PCTO"
  76: #define PCSR1_BITS_DELUA "\10\10PCTO"
  77: 
  78: /*
  79:  * Port Control Block Base
  80:  */
  81: struct de_pcbb {
  82:     short   pcbb0;      /* function */
  83:     short   pcbb2;      /* command specific */
  84:     short   pcbb4;
  85:     short   pcbb6;
  86: };
  87: 
  88: /* PCBB function codes */
  89: #define FC_NOOP     0x00        /* NO-OP */
  90: #define FC_LSUADDR  0x01        /* Load and start microaddress */
  91: #define FC_RDDEFAULT    0x02        /* Read default physical address */
  92: #define FC_RDPHYAD  0x04        /* Read physical address */
  93: #define FC_WTPHYAD  0x05        /* Write physical address */
  94: #define FC_RDMULTI  0x06        /* Read multicast address list */
  95: #define FC_WTMULTI  0x07        /* Read multicast address list */
  96: #define FC_RDRING   0x08        /* Read ring format */
  97: #define FC_WTRING   0x09        /* Write ring format */
  98: #define FC_RDCNTS   0x0a        /* Read counters */
  99: #define FC_RCCNTS   0x0b        /* Read and clear counters */
 100: #define FC_RDMODE   0x0c        /* Read mode */
 101: #define FC_WTMODE   0x0d        /* Write mode */
 102: #define FC_RDSTATUS 0x0e        /* Read port status */
 103: #define FC_RCSTATUS 0x0f        /* Read and clear port status */
 104: #define FC_DUMPMEM  0x10        /* Dump internal memory */
 105: #define FC_LOADMEM  0x11        /* Load internal memory */
 106: #define FC_RDSYSID  0x12        /* Read system ID parameters */
 107: #define FC_WTSYSID  0x13        /* Write system ID parameters */
 108: #define FC_RDSERAD  0x14        /* Read load server address */
 109: #define FC_WTSERAD  0x15        /* Write load server address */
 110: 
 111: /*
 112:  * Unibus Data Block Base (UDBB) for ring buffers
 113:  */
 114: struct de_udbbuf {
 115:     short   b_tdrbl;    /* Transmit desc ring base low 16 bits */
 116:     char    b_tdrbh;    /* Transmit desc ring base high 2 bits */
 117:     char    b_telen;    /* Length of each transmit entry */
 118:     short   b_trlen;    /* Number of entries in the XMIT desc ring */
 119:     short   b_rdrbl;    /* Receive desc ring base low 16 bits */
 120:     char    b_rdrbh;    /* Receive desc ring base high 2 bits */
 121:     char    b_relen;    /* Length of each receive entry */
 122:     short   b_rrlen;    /* Number of entries in the RECV desc ring */
 123: };
 124: 
 125: /*
 126:  * Transmit/Receive Ring Entry
 127:  */
 128: struct de_ring {
 129:     short   r_slen;         /* Segment length */
 130:     short   r_segbl;        /* Segment address (low 16 bits) */
 131:     char    r_segbh;        /* Segment address (hi 2 bits) */
 132:     u_char  r_flags;        /* Status flags */
 133:     u_short r_tdrerr;       /* Errors */
 134: #define r_lenerr    r_tdrerr
 135:     short   r_rid;          /* Request ID */
 136: };
 137: 
 138: #define XFLG_OWN    0x80        /* If 0 then owned by driver */
 139: #define XFLG_ERRS   0x40        /* Error summary */
 140: #define XFLG_MTCH   0x20        /* Address match on xmit request */
 141: #define XFLG_MORE   0x10        /* More than one entry required */
 142: #define XFLG_ONE    0x08        /* One collision encountered */
 143: #define XFLG_DEF    0x04        /* Transmit deferred */
 144: #define XFLG_STP    0x02        /* Start of packet */
 145: #define XFLG_ENP    0x01        /* End of packet */
 146: 
 147: #define XFLG_BITS   "\10\10OWN\7ERRS\6MTCH\5MORE\4ONE\3DEF\2STP\1ENP"
 148: 
 149: #define XERR_BUFL   0x8000      /* Buffer length error */
 150: #define XERR_UBTO   0x4000      /* UNIBUS tiemout
 151: #define	XERR_UFLO	0x2000		/* Underflow transmit */
 152: #define XERR_LCOL   0x1000      /* Late collision */
 153: #define XERR_LCAR   0x0800      /* Loss of carrier */
 154: #define XERR_RTRY   0x0400      /* Failed after 16 retries */
 155: #define XERR_TDR    0x03ff      /* TDR value */
 156: 
 157: #define XERR_BITS   "\20\20BUFL\17UBTO\16UFLO\15LCOL\14LCAR\13RTRY"
 158: 
 159: #define RFLG_OWN    0x80        /* If 0 then owned by driver */
 160: #define RFLG_ERRS   0x40        /* Error summary */
 161: #define RFLG_FRAM   0x20        /* Framing error */
 162: #define RFLG_OFLO   0x10        /* Message overflow */
 163: #define RFLG_CRC    0x08        /* CRC error */
 164: #define RFLG_STP    0x02        /* Start of packet */
 165: #define RFLG_ENP    0x01        /* End of packet */
 166: 
 167: #define RFLG_BITS   "\10\10OWN\7ERRS\6FRAM\5OFLO\4CRC\2STP\1ENP"
 168: 
 169: #define RERR_BUFL   0x8000      /* Buffer length error */
 170: #define RERR_UBTO   0x4000      /* UNIBUS tiemout */
 171: #define RERR_NCHN   0x2000      /* No data chaining */
 172: #define RERR_OVRN   0x1000      /* overrun message error */
 173: #define RERR_MLEN   0x0fff      /* Message length */
 174: 
 175: #define RERR_BITS   "\20\20BUFL\17UBTO\16NCHN\15OVRN"
 176: 
 177: /* mode description bits */
 178: #define MOD_HDX     0x0001      /* Half duplex mode */
 179: #define MOD_LOOP    0x0004      /* Enable loopback */
 180: #define MOD_DTCR    0x0008      /* Disables CRC generation */
 181: #define MOD_INTL    0x0040      /* Internal loopback enable */
 182: #define MOD_DMNT    0x0200      /* Disable maintenance features */
 183: #define MOD_ECT     0x0400      /* Enable collision test */
 184: #define MOD_TPAD    0x1000      /* Transmit message pad enable */
 185: #define MOD_DRDC    0x2000      /* Disable data chaining */
 186: #define MOD_ENAL    0x4000      /* Enable all multicast */
 187: #define MOD_PROM    0x8000      /* Enable promiscuous mode */
 188: 
 189: struct  de_buf {
 190:     struct ether_header db_head;    /* header */
 191:     char    db_data[ETHERMTU];  /* packet data */
 192:     long    db_crc;         /* CRC - on receive only */
 193: };
 194: 
 195: #ifdef  DE_DO_PHYSADDR
 196: /*
 197:  * structure used to query de and qe for physical addresses
 198:  */
 199: struct ifdevea {
 200:         char    ifr_name[IFNAMSIZ];             /* if name, e.g. "en0" */
 201:         u_char default_pa[6];                   /* default hardware address */
 202:         u_char current_pa[6];                   /* current physical address */
 203: };
 204: #endif		/* DE_DO_PHYSADDR */
 205: 
 206: #ifdef  DE_DO_BCTRS
 207: /*
 208:  * Counter list
 209:  */
 210: struct de_counters {
 211:     short   c_length;       /* returned data block length */
 212:     u_short c_seconds;      /* seconds since last zeroed */
 213:     u_short c_prcvd[2];     /* packets received */
 214:     u_short c_mprcvd[2];        /* multicast packets received */
 215:     u_short c_rbm;          /* receive error bitmap */
 216:     u_short c_rcverr;       /* packets received with error */
 217:     u_short c_brcvd[2];     /* bytes received */
 218:     u_short c_mbrcvd[2];        /* multicast bytes received */
 219:     u_short c_ibuferr;      /* packets lost - internal buffer error */
 220:     u_short c_lbuferr;      /* packets lost - local buffer error */
 221:     u_short c_psent[2];     /* packets sent */
 222:     u_short c_mpsent[2];        /* multicast packets sent */
 223:     u_short c_multiple[2];      /* packets sent - multiple collisions */
 224:     u_short c_single[2];        /* packets sent - single collision */
 225:     u_short c_defer[2];     /* packets sent - initially deferred */
 226:     u_short c_bsent[2];     /* bytes sent */
 227:     u_short c_mbsent[2];        /* multicast bytes sent */
 228:     u_short c_sbm;          /* send error bitmap */
 229:     u_short c_snderr;       /* send packet errors */
 230:     u_short c_collis;       /* collision check failure */
 231:     u_short c_rsvd;         /* reserved field */
 232: };
 233: 
 234: /*
 235:  * interface statistics structures
 236:  */
 237: struct estat {              /* Ethernet interface statistics */
 238:     u_short est_seconds;        /* seconds since last zeroed */
 239:     u_long  est_byrcvd;     /* bytes received */
 240:     u_long  est_bysent;     /* bytes sent */
 241:     u_long  est_blrcvd;     /* data blocks received */
 242:     u_long  est_blsent;     /* data blocks sent */
 243:     u_long  est_mbyrcvd;        /* multicast bytes received */
 244:     u_long  est_mblrcvd;        /* multicast blocks received */
 245:     u_long  est_deferred;       /* blocks sent, initially deferred */
 246:     u_long  est_single;     /* blocks sent, single collision */
 247:     u_long  est_multiple;       /* blocks sent, multiple collisions */
 248:     u_short est_sfbm;       /*	0 - Excessive collisions */
 249:                     /*	1 - Carrier check failed */
 250:                     /*	2 - Short circuit */
 251:                     /*	3 - Open circuit */
 252:                     /*	4 - Frame too long */
 253:                     /*	5 - Remote failure to defer */
 254:     u_short est_sf;         /* send failures: (bit map)*/
 255:     u_short est_collis;     /* Collision detect check failure */
 256:     u_short est_rfbm;       /*	0 - Block check error */
 257:                     /*	1 - Framing error */
 258:                     /*	2 - Frame too long */
 259:     u_short est_rf;         /* receive failure: (bit map) */
 260:     u_short est_unrecog;        /* unrecognized frame destination */
 261:     u_short est_overrun;        /* data overrun */
 262:     u_short est_sysbuf;     /* system buffer unavailable */
 263:     u_short est_userbuf;        /* user buffer unavailable */
 264: };
 265: 
 266: /*
 267:  * interface counter ioctl request
 268:  */
 269: struct ctrreq {
 270:     char    ctr_name[IFNAMSIZ]; /* if name */
 271:     char    ctr_type;       /* type of interface */
 272:     struct estat ctr_ether;/* ethernet counters */
 273: };
 274: 
 275: #define CTR_ETHER 0         /* Ethernet interface */
 276: #define CTR_DDCMP 1         /* DDCMP pt-to-pt interface */
 277: #define CTR_HDRCRC  0       /* header crc bit index */
 278: #define CTR_DATCRC  1       /* data crc bit index */
 279: #define CTR_BUFUNAVAIL  0       /* buffer unavailable bit index */
 280: #endif		/* DE_DO_BCTRS */

Defined struct's

ctrreq defined in line 269; used 4 times
de_buf defined in line 189; used 2 times
de_counters defined in line 210; used 4 times
de_pcbb defined in line 81; used 2 times
de_ring defined in line 128; used 16 times
de_udbbuf defined in line 114; used 2 times
dedevice defined in line 13; used 36 times
estat defined in line 237; used 4 times
ifdevea defined in line 199; used 4 times

Defined macros

CMD_BOOT defined in line 49; never used
CMD_GETCMD defined in line 46; used 10 times
CMD_GETPCBB defined in line 45; used 3 times
CMD_NOOP defined in line 44; never used
CMD_PDMD defined in line 50; used 3 times
CMD_RSTT defined in line 53; never used
CMD_START defined in line 48; used 1 times
CMD_STEST defined in line 47; never used
CMD_STOP defined in line 54; never used
CMD_TMRF defined in line 52; never used
CMD_TMRO defined in line 51; never used
CTR_BUFUNAVAIL defined in line 279; never used
CTR_DATCRC defined in line 278; never used
CTR_DDCMP defined in line 276; never used
CTR_ETHER defined in line 275; used 1 times
CTR_HDRCRC defined in line 277; never used
DELUA defined in line 11; used 3 times
DEUNA defined in line 10; used 5 times
FC_DUMPMEM defined in line 104; never used
FC_LOADMEM defined in line 105; never used
FC_LSUADDR defined in line 90; never used
FC_NOOP defined in line 89; never used
FC_RCCNTS defined in line 99; used 1 times
FC_RCSTATUS defined in line 103; never used
FC_RDCNTS defined in line 98; used 1 times
FC_RDDEFAULT defined in line 91; used 1 times
FC_RDMODE defined in line 100; used 1 times
FC_RDMULTI defined in line 94; never used
FC_RDPHYAD defined in line 92; used 1 times
FC_RDRING defined in line 96; never used
FC_RDSERAD defined in line 108; never used
FC_RDSTATUS defined in line 102; never used
FC_RDSYSID defined in line 106; never used
FC_WTMODE defined in line 101; used 2 times
FC_WTMULTI defined in line 95; used 1 times
FC_WTPHYAD defined in line 93; used 2 times
FC_WTRING defined in line 97; used 1 times
FC_WTSERAD defined in line 109; never used
FC_WTSYSID defined in line 107; never used
MOD_DMNT defined in line 182; never used
MOD_DRDC defined in line 185; never used
MOD_DTCR defined in line 180; never used
MOD_ECT defined in line 183; never used
MOD_ENAL defined in line 186; never used
MOD_HDX defined in line 178; used 3 times
MOD_INTL defined in line 181; used 2 times
MOD_LOOP defined in line 179; used 2 times
MOD_PROM defined in line 187; never used
MOD_TPAD defined in line 184; used 1 times
PCSR0_BITS defined in line 41; used 6 times
PCSR0_CMASK defined in line 39; never used
PCSR0_DNI defined in line 33; used 2 times
PCSR0_FATI defined in line 35; used 3 times
PCSR0_INTE defined in line 37; used 14 times
PCSR0_INTR defined in line 36; used 3 times
PCSR0_PCEI defined in line 30; used 2 times
PCSR0_RCBI defined in line 34; used 1 times
PCSR0_RSET defined in line 38; used 3 times
PCSR0_RXI defined in line 31; never used
PCSR0_SERI defined in line 29; used 1 times
PCSR0_TXI defined in line 32; never used
PCSR1_BITS defined in line 75; used 4 times
PCSR1_BITS_DELUA defined in line 76; used 4 times
PCSR1_DEVID defined in line 63; used 1 times
PCSR1_ICAB defined in line 60; never used
PCSR1_PCTO defined in line 62; never used
PCSR1_STCODE defined in line 61; never used
PCSR1_STMASK defined in line 64; used 2 times
PCSR1_XPWR defined in line 59; never used
RERR_BITS defined in line 175; used 1 times
RERR_BUFL defined in line 169; used 1 times
RERR_MLEN defined in line 173; used 1 times
RERR_NCHN defined in line 171; used 1 times
RERR_OVRN defined in line 172; never used
RERR_UBTO defined in line 170; used 1 times
RFLG_BITS defined in line 167; used 1 times
RFLG_CRC defined in line 163; used 1 times
RFLG_ENP defined in line 165; used 2 times
RFLG_ERRS defined in line 160; used 1 times
RFLG_FRAM defined in line 161; used 1 times
RFLG_OFLO defined in line 162; used 1 times
RFLG_OWN defined in line 159; used 4 times
RFLG_STP defined in line 164; used 2 times
STAT_NIHALT defined in line 72; never used
STAT_NIUHALT defined in line 73; never used
STAT_PRIMLD defined in line 68; never used
STAT_READY defined in line 69; used 1 times
STAT_RESET defined in line 67; used 1 times
STAT_RUN defined in line 70; never used
STAT_UHALT defined in line 71; never used
XERR_BITS defined in line 157; used 1 times
XERR_BUFL defined in line 149; never used
XERR_LCAR defined in line 153; never used
XERR_LCOL defined in line 152; never used
XERR_RTRY defined in line 154; never used
XERR_TDR defined in line 155; never used
XERR_UBTO defined in line 150; never used
XFLG_BITS defined in line 147; used 1 times
XFLG_DEF defined in line 143; never used
XFLG_ENP defined in line 145; used 1 times
XFLG_ERRS defined in line 139; used 2 times
XFLG_MORE defined in line 141; used 2 times
XFLG_MTCH defined in line 140; used 2 times
XFLG_ONE defined in line 142; used 2 times
XFLG_OWN defined in line 138; used 3 times
XFLG_STP defined in line 144; used 1 times
pchigh defined in line 20; used 2 times
pclow defined in line 19; used 18 times
pcsr0 defined in line 18; used 13 times
r_lenerr defined in line 134; used 4 times

Usage of this include

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