Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date         : Thu Feb  9 12:13:31 2023
| Host         : athome2 running 64-bit Ubuntu 20.04.5 LTS
| Command      : report_timing_summary -max_paths 10 -report_unconstrained -file sys_tst_rlink_n4d_timing_summary_routed.rpt -pb sys_tst_rlink_n4d_timing_summary_routed.pb -rpx sys_tst_rlink_n4d_timing_summary_routed.rpx -warn_on_violation
| Design       : sys_tst_rlink_n4d
| Device       : 7a100t-csg324
| Speed File   : -1  PRODUCTION 1.23 2018-06-13
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

Rule     Severity  Description                                      Violations  
-------  --------  -----------------------------------------------  ----------  
SYNTH-6  Warning   Timing of a RAM block might be sub-optimal       5           
XDCC-5   Warning   User Non-Timing constraint/property overwritten  2           

Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (23)
6. checking no_output_delay (40)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (23)
-------------------------------
 There are 23 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (40)
--------------------------------
 There are 40 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.543        0.000                      0                 2963        0.013        0.000                      0                 2963        2.917        0.000                       0                  1312  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock               Waveform(ns)         Period(ns)      Frequency(MHz)
-----               ------------         ----------      --------------
I_CLK100            {0.000 5.000}        10.000          100.000         
  USEMMCM.CLKFBOUT  {0.000 5.000}        10.000          100.000         
  USEMMCM.CLKOUT0   {0.000 4.167}        8.333           120.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                   WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                   -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
I_CLK100                                                                                                                                                              3.000        0.000                       0                     1  
  USEMMCM.CLKFBOUT                                                                                                                                                    7.845        0.000                       0                     3  
  USEMMCM.CLKOUT0         0.543        0.000                      0                 2963        0.013        0.000                      0                 2963        2.917        0.000                       0                  1308  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock    
----------    ----------    --------    


------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------

Path Group        From Clock        To Clock        
----------        ----------        --------        
(none)            USEMMCM.CLKFBOUT                    
(none)            USEMMCM.CLKOUT0                     
(none)                              USEMMCM.CLKOUT0   


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  I_CLK100
  To Clock:  I_CLK100

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        3.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         I_CLK100
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { I_CLK100 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     MMCME2_ADV/CLKIN1  n/a            1.249         10.000      8.751      MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
Max Period        n/a     MMCME2_ADV/CLKIN1  n/a            100.000       10.000      90.000     MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
Low Pulse Width   Slow    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
Low Pulse Width   Fast    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
High Pulse Width  Slow    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
High Pulse Width  Fast    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  USEMMCM.CLKFBOUT
  To Clock:  USEMMCM.CLKFBOUT

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        7.845ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         USEMMCM.CLKFBOUT
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFG/I               n/a            2.155         10.000      7.845      BUFGCTRL_X0Y17   GEN_CLKSYS/USEMMCM.BUFG_CLKFB/I
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         10.000      8.751      MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT
Min Period  n/a     MMCME2_ADV/CLKFBIN   n/a            1.249         10.000      8.751      MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKFBIN
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       10.000      90.000     MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKFBIN
Max Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            213.360       10.000      203.360    MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT



---------------------------------------------------------------------------------------------------
From Clock:  USEMMCM.CLKOUT0
  To Clock:  USEMMCM.CLKOUT0

Setup :            0  Failing Endpoints,  Worst Slack        0.543ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.013ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.917ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.543ns  (required time - arrival time)
  Source:                 RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKARDCLK
                            (rising edge-triggered cell RAMB36E1 clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/CD2B/R_REGS_reg[ecode][2]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (USEMMCM.CLKOUT0 rise@8.333ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        7.664ns  (logic 3.419ns (44.614%)  route 4.245ns (55.386%))
  Logic Levels:           4  (LUT4=1 LUT5=1 LUT6=2)
  Clock Path Skew:        -0.090ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.533ns = ( 6.800 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.883ns
    Clock Pessimism Removal (CPR):    0.560ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.657    -0.883    RLINK/CORE/RL/RTBUF/CLKFX
    RAMB36_X1Y21         RAMB36E1                                     r  RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X1Y21         RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[2])
                                                      2.454     1.571 r  RLINK/CORE/RL/RTBUF/sv_ram_reg/DOADO[2]
                         net (fo=3, routed)           1.453     3.024    RLINK/CORE/RL/RTBUF/DOADO[2]
    SLICE_X59Y112        LUT6 (Prop_lut6_I4_O)        0.124     3.148 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_23/O
                         net (fo=16, routed)          1.309     4.458    RLINK/CORE/RL/RTBUF/RL_DO[2]
    SLICE_X52Y104        LUT4 (Prop_lut4_I3_O)        0.154     4.612 r  RLINK/CORE/RL/RTBUF/R_REGS[ecode][2]_i_7/O
                         net (fo=2, routed)           0.867     5.478    RLINK/CORE/RL/RTBUF/R_REGS[ecode][2]_i_7_n_0
    SLICE_X52Y104        LUT5 (Prop_lut5_I1_O)        0.355     5.833 r  RLINK/CORE/RL/RTBUF/R_REGS[ecode][2]_i_3/O
                         net (fo=1, routed)           0.616     6.449    RLINK/CORE/CD2B/R_REGS_reg[ecode][2]_1
    SLICE_X52Y104        LUT6 (Prop_lut6_I1_O)        0.332     6.781 r  RLINK/CORE/CD2B/R_REGS[ecode][2]_i_1/O
                         net (fo=1, routed)           0.000     6.781    RLINK/CORE/CD2B/R_REGS[ecode][2]_i_1_n_0
    SLICE_X52Y104        FDRE                                         r  RLINK/CORE/CD2B/R_REGS_reg[ecode][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     9.745 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.906    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324     3.583 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639     5.222    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.313 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.488     6.800    RLINK/CORE/CD2B/CLKFX
    SLICE_X52Y104        FDRE                                         r  RLINK/CORE/CD2B/R_REGS_reg[ecode][2]/C
                         clock pessimism              0.560     7.360    
                         clock uncertainty           -0.066     7.295    
    SLICE_X52Y104        FDRE (Setup_fdre_C_D)        0.029     7.324    RLINK/CORE/CD2B/R_REGS_reg[ecode][2]
  -------------------------------------------------------------------
                         required time                          7.324    
                         arrival time                          -6.781    
  -------------------------------------------------------------------
                         slack                                  0.543    

Slack (MET) :             0.752ns  (required time - arrival time)
  Source:                 RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKARDCLK
                            (rising edge-triggered cell RAMB36E1 clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/CD2B/R_REGS_reg[ecode][0]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (USEMMCM.CLKOUT0 rise@8.333ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        7.392ns  (logic 2.950ns (39.907%)  route 4.442ns (60.093%))
  Logic Levels:           4  (LUT5=1 LUT6=3)
  Clock Path Skew:        -0.155ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.526ns = ( 6.807 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.883ns
    Clock Pessimism Removal (CPR):    0.488ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.657    -0.883    RLINK/CORE/RL/RTBUF/CLKFX
    RAMB36_X1Y21         RAMB36E1                                     r  RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB36_X1Y21         RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[4])
                                                      2.454     1.571 r  RLINK/CORE/RL/RTBUF/sv_ram_reg/DOADO[4]
                         net (fo=3, routed)           1.617     3.188    RLINK/CORE/RL/OCRC/DOADO[1]
    SLICE_X56Y112        LUT6 (Prop_lut6_I3_O)        0.124     3.312 r  RLINK/CORE/RL/OCRC/sv_ram_reg_i_21/O
                         net (fo=11, routed)          1.438     4.751    RLINK/CORE/RL/RTBUF/R_REGS_reg[ecode][2]
    SLICE_X52Y104        LUT6 (Prop_lut6_I1_O)        0.124     4.875 r  RLINK/CORE/RL/RTBUF/R_REGS[ecode][2]_i_2/O
                         net (fo=2, routed)           0.955     5.830    RLINK/CORE/RL/RTBUF/sv_ram_reg_2
    SLICE_X51Y104        LUT6 (Prop_lut6_I2_O)        0.124     5.954 r  RLINK/CORE/RL/RTBUF/R_REGS[ecode][0]_i_2/O
                         net (fo=1, routed)           0.432     6.386    RLINK/CORE/CD2B/R_REGS_reg[ecode][0]_1
    SLICE_X51Y105        LUT5 (Prop_lut5_I0_O)        0.124     6.510 r  RLINK/CORE/CD2B/R_REGS[ecode][0]_i_1/O
                         net (fo=1, routed)           0.000     6.510    RLINK/CORE/CD2B/R_REGS[ecode][0]_i_1_n_0
    SLICE_X51Y105        FDRE                                         r  RLINK/CORE/CD2B/R_REGS_reg[ecode][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     9.745 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.906    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324     3.583 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639     5.222    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.313 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.495     6.807    RLINK/CORE/CD2B/CLKFX
    SLICE_X51Y105        FDRE                                         r  RLINK/CORE/CD2B/R_REGS_reg[ecode][0]/C
                         clock pessimism              0.488     7.296    
                         clock uncertainty           -0.066     7.230    
    SLICE_X51Y105        FDRE (Setup_fdre_C_D)        0.031     7.261    RLINK/CORE/CD2B/R_REGS_reg[ecode][0]
  -------------------------------------------------------------------
                         required time                          7.261    
                         arrival time                          -6.510    
  -------------------------------------------------------------------
                         slack                                  0.752    

Slack (MET) :             0.968ns  (required time - arrival time)
  Source:                 RBDTST/TEST/R_REGS_reg[cntbusy][4]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/MON/R_REGS_reg[rbdata][0]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (USEMMCM.CLKOUT0 rise@8.333ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        7.299ns  (logic 2.037ns (27.909%)  route 5.262ns (72.091%))
  Logic Levels:           9  (LUT3=1 LUT4=1 LUT5=1 LUT6=5 RAMS32=1)
  Clock Path Skew:        -0.030ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.523ns = ( 6.810 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.933ns
    Clock Pessimism Removal (CPR):    0.560ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.607    -0.933    RBDTST/TEST/CLKFX
    SLICE_X48Y118        FDRE                                         r  RBDTST/TEST/R_REGS_reg[cntbusy][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y118        FDRE (Prop_fdre_C_Q)         0.456    -0.477 f  RBDTST/TEST/R_REGS_reg[cntbusy][4]/Q
                         net (fo=2, routed)           0.873     0.396    RBDTST/TEST/FIFO/RAM/R_REGS_reg[cntbusy][4]
    SLICE_X48Y118        LUT5 (Prop_lut5_I3_O)        0.149     0.545 r  RBDTST/TEST/FIFO/RAM/R_REGS[cntbusy][7]_i_2/O
                         net (fo=7, routed)           0.364     0.909    RBDTST/TEST/FIFO/RAM/R_REGS_reg[cntbusy]_0_sn_1
    SLICE_X49Y119        LUT6 (Prop_lut6_I5_O)        0.332     1.241 f  RBDTST/TEST/FIFO/RAM/R_REGS[raddr][3]_i_6/O
                         net (fo=10, routed)          0.453     1.695    RLINK/CORE/RL/R_REGS_reg[data][0]
    SLICE_X47Y117        LUT6 (Prop_lut6_I3_O)        0.124     1.819 r  RLINK/CORE/RL/R_REGS[waddr][3]_i_1__2/O
                         net (fo=27, routed)          0.688     2.507    RBDTST/TEST/FIFO/RAM/iram_we3_out
    SLICE_X43Y117        LUT3 (Prop_lut3_I1_O)        0.153     2.660 r  RBDTST/TEST/FIFO/RAM/RAM_reg_0_15_0_0_i_4/O
                         net (fo=16, routed)          0.864     3.524    RBDTST/TEST/FIFO/RAM/RAM_reg_0_15_0_0/A3
    SLICE_X42Y115        RAMS32 (Prop_rams32_ADR3_O)
                                                      0.327     3.851 r  RBDTST/TEST/FIFO/RAM/RAM_reg_0_15_0_0/SP/O
                         net (fo=1, routed)           0.596     4.447    RLINK/CORE/RL/DO[0]
    SLICE_X41Y116        LUT6 (Prop_lut6_I2_O)        0.124     4.571 r  RLINK/CORE/RL/R_BREGS[rbdout][0]_i_8/O
                         net (fo=1, routed)           0.473     5.044    RLINK/CORE/RL/R_BREGS[rbdout][0]_i_8_n_0
    SLICE_X41Y116        LUT6 (Prop_lut6_I5_O)        0.124     5.168 f  RLINK/CORE/RL/R_BREGS[rbdout][0]_i_3/O
                         net (fo=1, routed)           0.351     5.519    RBDTST/TEST/R_BREGS_reg[rbdout][0]
    SLICE_X40Y116        LUT6 (Prop_lut6_I0_O)        0.124     5.643 r  RBDTST/TEST/R_BREGS[rbdout][0]_i_2/O
                         net (fo=2, routed)           0.599     6.242    RLINK/CORE/RL/R_BREGS_reg[rbdout][6]_0[0]
    SLICE_X40Y112        LUT4 (Prop_lut4_I3_O)        0.124     6.366 r  RLINK/CORE/RL/R_REGS[rbdata][0]_i_1/O
                         net (fo=1, routed)           0.000     6.366    RBDTST/MON/N_REGS[rbdata][0]
    SLICE_X40Y112        FDRE                                         r  RBDTST/MON/R_REGS_reg[rbdata][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     9.745 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.906    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324     3.583 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639     5.222    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.313 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.498     6.810    RBDTST/MON/CLKFX
    SLICE_X40Y112        FDRE                                         r  RBDTST/MON/R_REGS_reg[rbdata][0]/C
                         clock pessimism              0.560     7.370    
                         clock uncertainty           -0.066     7.305    
    SLICE_X40Y112        FDRE (Setup_fdre_C_D)        0.029     7.334    RBDTST/MON/R_REGS_reg[rbdata][0]
  -------------------------------------------------------------------
                         required time                          7.334    
                         arrival time                          -6.366    
  -------------------------------------------------------------------
                         slack                                  0.968    

Slack (MET) :             1.016ns  (required time - arrival time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[addr][5]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[bcnt][2]/CE
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (USEMMCM.CLKOUT0 rise@8.333ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.923ns  (logic 1.568ns (22.650%)  route 5.355ns (77.350%))
  Logic Levels:           6  (LUT4=2 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.124ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.533ns = ( 6.800 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.920ns
    Clock Pessimism Removal (CPR):    0.488ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.620    -0.920    RLINK/CORE/RL/CLKFX
    SLICE_X40Y111        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[addr][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y111        FDRE (Prop_fdre_C_Q)         0.419    -0.501 r  RLINK/CORE/RL/R_LREGS_reg[addr][5]/Q
                         net (fo=21, routed)          1.283     0.782    RLINK/CORE/RL/R_LREGS_reg[addr][5]_0
    SLICE_X33Y121        LUT4 (Prop_lut4_I2_O)        0.327     1.109 r  RLINK/CORE/RL/SM_i_11/O
                         net (fo=23, routed)          0.524     1.633    RLINK/CORE/RL/RTBUF/R_REGS_reg[rbtout]_6
    SLICE_X32Y121        LUT6 (Prop_lut6_I4_O)        0.326     1.959 f  RLINK/CORE/RL/RTBUF/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           0.940     2.898    RLINK/CORE/RL/RTBUF/R_BREGS_reg[rbre]
    SLICE_X45Y117        LUT5 (Prop_lut5_I2_O)        0.124     3.022 f  RLINK/CORE/RL/RTBUF/R_REGS[rbtout]_i_1/O
                         net (fo=8, routed)           0.679     3.701    RLINK/CORE/RL/RTBUF/R_LREGS_reg[addr][0]_rep
    SLICE_X50Y114        LUT6 (Prop_lut6_I3_O)        0.124     3.825 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_14/O
                         net (fo=4, routed)           0.674     4.499    RLINK/CORE/RL/RTBUF_n_17
    SLICE_X54Y108        LUT4 (Prop_lut4_I3_O)        0.124     4.623 r  RLINK/CORE/RL/R_LREGS[bcnt][11]_i_3/O
                         net (fo=1, routed)           0.606     5.230    RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS_reg[bcnt][0]_1
    SLICE_X54Y108        LUT6 (Prop_lut6_I0_O)        0.124     5.354 r  RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS[bcnt][11]_i_1/O
                         net (fo=12, routed)          0.649     6.003    RLINK/CORE/RL/DOFIFO_n_24
    SLICE_X53Y105        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     9.745 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.906    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324     3.583 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639     5.222    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.313 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.488     6.800    RLINK/CORE/RL/CLKFX
    SLICE_X53Y105        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][2]/C
                         clock pessimism              0.488     7.289    
                         clock uncertainty           -0.066     7.223    
    SLICE_X53Y105        FDRE (Setup_fdre_C_CE)      -0.205     7.018    RLINK/CORE/RL/R_LREGS_reg[bcnt][2]
  -------------------------------------------------------------------
                         required time                          7.018    
                         arrival time                          -6.003    
  -------------------------------------------------------------------
                         slack                                  1.016    

Slack (MET) :             1.016ns  (required time - arrival time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[addr][5]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[bcnt][4]/CE
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (USEMMCM.CLKOUT0 rise@8.333ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.923ns  (logic 1.568ns (22.650%)  route 5.355ns (77.350%))
  Logic Levels:           6  (LUT4=2 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.124ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.533ns = ( 6.800 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.920ns
    Clock Pessimism Removal (CPR):    0.488ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.620    -0.920    RLINK/CORE/RL/CLKFX
    SLICE_X40Y111        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[addr][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y111        FDRE (Prop_fdre_C_Q)         0.419    -0.501 r  RLINK/CORE/RL/R_LREGS_reg[addr][5]/Q
                         net (fo=21, routed)          1.283     0.782    RLINK/CORE/RL/R_LREGS_reg[addr][5]_0
    SLICE_X33Y121        LUT4 (Prop_lut4_I2_O)        0.327     1.109 r  RLINK/CORE/RL/SM_i_11/O
                         net (fo=23, routed)          0.524     1.633    RLINK/CORE/RL/RTBUF/R_REGS_reg[rbtout]_6
    SLICE_X32Y121        LUT6 (Prop_lut6_I4_O)        0.326     1.959 f  RLINK/CORE/RL/RTBUF/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           0.940     2.898    RLINK/CORE/RL/RTBUF/R_BREGS_reg[rbre]
    SLICE_X45Y117        LUT5 (Prop_lut5_I2_O)        0.124     3.022 f  RLINK/CORE/RL/RTBUF/R_REGS[rbtout]_i_1/O
                         net (fo=8, routed)           0.679     3.701    RLINK/CORE/RL/RTBUF/R_LREGS_reg[addr][0]_rep
    SLICE_X50Y114        LUT6 (Prop_lut6_I3_O)        0.124     3.825 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_14/O
                         net (fo=4, routed)           0.674     4.499    RLINK/CORE/RL/RTBUF_n_17
    SLICE_X54Y108        LUT4 (Prop_lut4_I3_O)        0.124     4.623 r  RLINK/CORE/RL/R_LREGS[bcnt][11]_i_3/O
                         net (fo=1, routed)           0.606     5.230    RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS_reg[bcnt][0]_1
    SLICE_X54Y108        LUT6 (Prop_lut6_I0_O)        0.124     5.354 r  RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS[bcnt][11]_i_1/O
                         net (fo=12, routed)          0.649     6.003    RLINK/CORE/RL/DOFIFO_n_24
    SLICE_X53Y105        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][4]/CE
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     9.745 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.906    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324     3.583 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639     5.222    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.313 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.488     6.800    RLINK/CORE/RL/CLKFX
    SLICE_X53Y105        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][4]/C
                         clock pessimism              0.488     7.289    
                         clock uncertainty           -0.066     7.223    
    SLICE_X53Y105        FDRE (Setup_fdre_C_CE)      -0.205     7.018    RLINK/CORE/RL/R_LREGS_reg[bcnt][4]
  -------------------------------------------------------------------
                         required time                          7.018    
                         arrival time                          -6.003    
  -------------------------------------------------------------------
                         slack                                  1.016    

Slack (MET) :             1.059ns  (required time - arrival time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[addr][5]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[rtaddrb][0]/CE
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (USEMMCM.CLKOUT0 rise@8.333ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.921ns  (logic 1.568ns (22.657%)  route 5.353ns (77.343%))
  Logic Levels:           6  (LUT3=1 LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.119ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.528ns = ( 6.805 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.920ns
    Clock Pessimism Removal (CPR):    0.488ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.620    -0.920    RLINK/CORE/RL/CLKFX
    SLICE_X40Y111        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[addr][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y111        FDRE (Prop_fdre_C_Q)         0.419    -0.501 r  RLINK/CORE/RL/R_LREGS_reg[addr][5]/Q
                         net (fo=21, routed)          1.283     0.782    RLINK/CORE/RL/R_LREGS_reg[addr][5]_0
    SLICE_X33Y121        LUT4 (Prop_lut4_I2_O)        0.327     1.109 r  RLINK/CORE/RL/SM_i_11/O
                         net (fo=23, routed)          0.524     1.633    RLINK/CORE/RL/RTBUF/R_REGS_reg[rbtout]_6
    SLICE_X32Y121        LUT6 (Prop_lut6_I4_O)        0.326     1.959 f  RLINK/CORE/RL/RTBUF/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           0.940     2.898    RLINK/CORE/RL/RTBUF/R_BREGS_reg[rbre]
    SLICE_X45Y117        LUT5 (Prop_lut5_I2_O)        0.124     3.022 f  RLINK/CORE/RL/RTBUF/R_REGS[rbtout]_i_1/O
                         net (fo=8, routed)           0.679     3.701    RLINK/CORE/RL/RTBUF/R_LREGS_reg[addr][0]_rep
    SLICE_X50Y114        LUT6 (Prop_lut6_I3_O)        0.124     3.825 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_14/O
                         net (fo=4, routed)           0.664     4.489    RLINK/CORE/RL/RTBUF/FSM_onehot_R_LREGS_reg[state][20]
    SLICE_X54Y108        LUT6 (Prop_lut6_I3_O)        0.124     4.613 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_1/O
                         net (fo=4, routed)           0.660     5.273    RLINK/CORE/RL/ICRC/R_LREGS_reg[rtaddrb][0]_0
    SLICE_X58Y106        LUT3 (Prop_lut3_I2_O)        0.124     5.397 r  RLINK/CORE/RL/ICRC/R_LREGS[rtaddrb][11]_i_2/O
                         net (fo=12, routed)          0.603     6.001    RLINK/CORE/RL/ICRC_n_17
    SLICE_X58Y106        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     9.745 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.906    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324     3.583 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639     5.222    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.313 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.493     6.805    RLINK/CORE/RL/CLKFX
    SLICE_X58Y106        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][0]/C
                         clock pessimism              0.488     7.294    
                         clock uncertainty           -0.066     7.228    
    SLICE_X58Y106        FDRE (Setup_fdre_C_CE)      -0.169     7.059    RLINK/CORE/RL/R_LREGS_reg[rtaddrb][0]
  -------------------------------------------------------------------
                         required time                          7.059    
                         arrival time                          -6.001    
  -------------------------------------------------------------------
                         slack                                  1.059    

Slack (MET) :             1.075ns  (required time - arrival time)
  Source:                 RBDTST/EMON/BRAM/sv_ram_reg/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/EMON/BRAM/sv_ram_reg/DIBDI[15]
                            (rising edge-triggered cell RAMB18E1 clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (USEMMCM.CLKOUT0 rise@8.333ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.724ns  (logic 4.363ns (64.884%)  route 2.361ns (35.116%))
  Logic Levels:           9  (CARRY4=8 LUT2=1)
  Clock Path Skew:        -0.024ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.469ns = ( 6.864 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.868ns
    Clock Pessimism Removal (CPR):    0.578ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.672    -0.868    RBDTST/EMON/BRAM/CLKFX
    RAMB18_X0Y40         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X0Y40         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[1])
                                                      2.454     1.586 r  RBDTST/EMON/BRAM/sv_ram_reg/DOADO[1]
                         net (fo=2, routed)           0.967     2.553    RBDTST/EMON/DOA[1]
    SLICE_X8Y98          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.637     3.190 r  RBDTST/EMON/plusOp_inferred__0/i__carry/CO[3]
                         net (fo=1, routed)           0.000     3.190    RBDTST/EMON/plusOp_inferred__0/i__carry_n_0
    SLICE_X8Y99          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.307 r  RBDTST/EMON/plusOp_inferred__0/i__carry__0/CO[3]
                         net (fo=1, routed)           0.001     3.308    RBDTST/EMON/plusOp_inferred__0/i__carry__0_n_0
    SLICE_X8Y100         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.425 r  RBDTST/EMON/plusOp_inferred__0/i__carry__1/CO[3]
                         net (fo=1, routed)           0.000     3.425    RBDTST/EMON/plusOp_inferred__0/i__carry__1_n_0
    SLICE_X8Y101         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.542 r  RBDTST/EMON/plusOp_inferred__0/i__carry__2/CO[3]
                         net (fo=1, routed)           0.000     3.542    RBDTST/EMON/plusOp_inferred__0/i__carry__2_n_0
    SLICE_X8Y102         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.659 r  RBDTST/EMON/plusOp_inferred__0/i__carry__3/CO[3]
                         net (fo=1, routed)           0.000     3.659    RBDTST/EMON/plusOp_inferred__0/i__carry__3_n_0
    SLICE_X8Y103         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.776 r  RBDTST/EMON/plusOp_inferred__0/i__carry__4/CO[3]
                         net (fo=1, routed)           0.000     3.776    RBDTST/EMON/plusOp_inferred__0/i__carry__4_n_0
    SLICE_X8Y104         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.893 r  RBDTST/EMON/plusOp_inferred__0/i__carry__5/CO[3]
                         net (fo=1, routed)           0.000     3.893    RBDTST/EMON/plusOp_inferred__0/i__carry__5_n_0
    SLICE_X8Y105         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     4.132 r  RBDTST/EMON/plusOp_inferred__0/i__carry__6/O[2]
                         net (fo=1, routed)           0.811     4.943    RBDTST/EMON/BRAM/plusOp[30]
    SLICE_X9Y104         LUT2 (Prop_lut2_I0_O)        0.331     5.274 r  RBDTST/EMON/BRAM/sv_ram_reg_i_18__0/O
                         net (fo=1, routed)           0.583     5.857    RBDTST/EMON/BRAM/BRAM_DIB[31]
    RAMB18_X0Y40         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/DIBDI[15]
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     9.745 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.906    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324     3.583 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639     5.222    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.313 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.551     6.864    RBDTST/EMON/BRAM/CLKFX
    RAMB18_X0Y40         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/CLKBWRCLK
                         clock pessimism              0.578     7.442    
                         clock uncertainty           -0.066     7.376    
    RAMB18_X0Y40         RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_DIBDI[15])
                                                     -0.444     6.932    RBDTST/EMON/BRAM/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          6.932    
                         arrival time                          -5.857    
  -------------------------------------------------------------------
                         slack                                  1.075    

Slack (MET) :             1.104ns  (required time - arrival time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[addr][5]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[rtaddrb][1]/CE
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (USEMMCM.CLKOUT0 rise@8.333ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.839ns  (logic 1.568ns (22.927%)  route 5.271ns (77.073%))
  Logic Levels:           6  (LUT3=1 LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.119ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.528ns = ( 6.805 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.920ns
    Clock Pessimism Removal (CPR):    0.488ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.620    -0.920    RLINK/CORE/RL/CLKFX
    SLICE_X40Y111        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[addr][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y111        FDRE (Prop_fdre_C_Q)         0.419    -0.501 r  RLINK/CORE/RL/R_LREGS_reg[addr][5]/Q
                         net (fo=21, routed)          1.283     0.782    RLINK/CORE/RL/R_LREGS_reg[addr][5]_0
    SLICE_X33Y121        LUT4 (Prop_lut4_I2_O)        0.327     1.109 r  RLINK/CORE/RL/SM_i_11/O
                         net (fo=23, routed)          0.524     1.633    RLINK/CORE/RL/RTBUF/R_REGS_reg[rbtout]_6
    SLICE_X32Y121        LUT6 (Prop_lut6_I4_O)        0.326     1.959 f  RLINK/CORE/RL/RTBUF/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           0.940     2.898    RLINK/CORE/RL/RTBUF/R_BREGS_reg[rbre]
    SLICE_X45Y117        LUT5 (Prop_lut5_I2_O)        0.124     3.022 f  RLINK/CORE/RL/RTBUF/R_REGS[rbtout]_i_1/O
                         net (fo=8, routed)           0.679     3.701    RLINK/CORE/RL/RTBUF/R_LREGS_reg[addr][0]_rep
    SLICE_X50Y114        LUT6 (Prop_lut6_I3_O)        0.124     3.825 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_14/O
                         net (fo=4, routed)           0.664     4.489    RLINK/CORE/RL/RTBUF/FSM_onehot_R_LREGS_reg[state][20]
    SLICE_X54Y108        LUT6 (Prop_lut6_I3_O)        0.124     4.613 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_1/O
                         net (fo=4, routed)           0.660     5.273    RLINK/CORE/RL/ICRC/R_LREGS_reg[rtaddrb][0]_0
    SLICE_X58Y106        LUT3 (Prop_lut3_I2_O)        0.124     5.397 r  RLINK/CORE/RL/ICRC/R_LREGS[rtaddrb][11]_i_2/O
                         net (fo=12, routed)          0.522     5.919    RLINK/CORE/RL/ICRC_n_17
    SLICE_X61Y104        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     9.745 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.906    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324     3.583 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639     5.222    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.313 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.493     6.805    RLINK/CORE/RL/CLKFX
    SLICE_X61Y104        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][1]/C
                         clock pessimism              0.488     7.294    
                         clock uncertainty           -0.066     7.228    
    SLICE_X61Y104        FDRE (Setup_fdre_C_CE)      -0.205     7.023    RLINK/CORE/RL/R_LREGS_reg[rtaddrb][1]
  -------------------------------------------------------------------
                         required time                          7.023    
                         arrival time                          -5.919    
  -------------------------------------------------------------------
                         slack                                  1.104    

Slack (MET) :             1.104ns  (required time - arrival time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[addr][5]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[rtaddrb][2]/CE
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (USEMMCM.CLKOUT0 rise@8.333ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.839ns  (logic 1.568ns (22.927%)  route 5.271ns (77.073%))
  Logic Levels:           6  (LUT3=1 LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.119ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.528ns = ( 6.805 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.920ns
    Clock Pessimism Removal (CPR):    0.488ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.620    -0.920    RLINK/CORE/RL/CLKFX
    SLICE_X40Y111        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[addr][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y111        FDRE (Prop_fdre_C_Q)         0.419    -0.501 r  RLINK/CORE/RL/R_LREGS_reg[addr][5]/Q
                         net (fo=21, routed)          1.283     0.782    RLINK/CORE/RL/R_LREGS_reg[addr][5]_0
    SLICE_X33Y121        LUT4 (Prop_lut4_I2_O)        0.327     1.109 r  RLINK/CORE/RL/SM_i_11/O
                         net (fo=23, routed)          0.524     1.633    RLINK/CORE/RL/RTBUF/R_REGS_reg[rbtout]_6
    SLICE_X32Y121        LUT6 (Prop_lut6_I4_O)        0.326     1.959 f  RLINK/CORE/RL/RTBUF/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           0.940     2.898    RLINK/CORE/RL/RTBUF/R_BREGS_reg[rbre]
    SLICE_X45Y117        LUT5 (Prop_lut5_I2_O)        0.124     3.022 f  RLINK/CORE/RL/RTBUF/R_REGS[rbtout]_i_1/O
                         net (fo=8, routed)           0.679     3.701    RLINK/CORE/RL/RTBUF/R_LREGS_reg[addr][0]_rep
    SLICE_X50Y114        LUT6 (Prop_lut6_I3_O)        0.124     3.825 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_14/O
                         net (fo=4, routed)           0.664     4.489    RLINK/CORE/RL/RTBUF/FSM_onehot_R_LREGS_reg[state][20]
    SLICE_X54Y108        LUT6 (Prop_lut6_I3_O)        0.124     4.613 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_1/O
                         net (fo=4, routed)           0.660     5.273    RLINK/CORE/RL/ICRC/R_LREGS_reg[rtaddrb][0]_0
    SLICE_X58Y106        LUT3 (Prop_lut3_I2_O)        0.124     5.397 r  RLINK/CORE/RL/ICRC/R_LREGS[rtaddrb][11]_i_2/O
                         net (fo=12, routed)          0.522     5.919    RLINK/CORE/RL/ICRC_n_17
    SLICE_X61Y104        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     9.745 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.906    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324     3.583 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639     5.222    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.313 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.493     6.805    RLINK/CORE/RL/CLKFX
    SLICE_X61Y104        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][2]/C
                         clock pessimism              0.488     7.294    
                         clock uncertainty           -0.066     7.228    
    SLICE_X61Y104        FDRE (Setup_fdre_C_CE)      -0.205     7.023    RLINK/CORE/RL/R_LREGS_reg[rtaddrb][2]
  -------------------------------------------------------------------
                         required time                          7.023    
                         arrival time                          -5.919    
  -------------------------------------------------------------------
                         slack                                  1.104    

Slack (MET) :             1.104ns  (required time - arrival time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[addr][5]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[rtaddrb][4]/CE
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (USEMMCM.CLKOUT0 rise@8.333ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.839ns  (logic 1.568ns (22.927%)  route 5.271ns (77.073%))
  Logic Levels:           6  (LUT3=1 LUT4=1 LUT5=1 LUT6=3)
  Clock Path Skew:        -0.119ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.528ns = ( 6.805 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.920ns
    Clock Pessimism Removal (CPR):    0.488ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.620    -0.920    RLINK/CORE/RL/CLKFX
    SLICE_X40Y111        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[addr][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y111        FDRE (Prop_fdre_C_Q)         0.419    -0.501 r  RLINK/CORE/RL/R_LREGS_reg[addr][5]/Q
                         net (fo=21, routed)          1.283     0.782    RLINK/CORE/RL/R_LREGS_reg[addr][5]_0
    SLICE_X33Y121        LUT4 (Prop_lut4_I2_O)        0.327     1.109 r  RLINK/CORE/RL/SM_i_11/O
                         net (fo=23, routed)          0.524     1.633    RLINK/CORE/RL/RTBUF/R_REGS_reg[rbtout]_6
    SLICE_X32Y121        LUT6 (Prop_lut6_I4_O)        0.326     1.959 f  RLINK/CORE/RL/RTBUF/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           0.940     2.898    RLINK/CORE/RL/RTBUF/R_BREGS_reg[rbre]
    SLICE_X45Y117        LUT5 (Prop_lut5_I2_O)        0.124     3.022 f  RLINK/CORE/RL/RTBUF/R_REGS[rbtout]_i_1/O
                         net (fo=8, routed)           0.679     3.701    RLINK/CORE/RL/RTBUF/R_LREGS_reg[addr][0]_rep
    SLICE_X50Y114        LUT6 (Prop_lut6_I3_O)        0.124     3.825 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_14/O
                         net (fo=4, routed)           0.664     4.489    RLINK/CORE/RL/RTBUF/FSM_onehot_R_LREGS_reg[state][20]
    SLICE_X54Y108        LUT6 (Prop_lut6_I3_O)        0.124     4.613 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_1/O
                         net (fo=4, routed)           0.660     5.273    RLINK/CORE/RL/ICRC/R_LREGS_reg[rtaddrb][0]_0
    SLICE_X58Y106        LUT3 (Prop_lut3_I2_O)        0.124     5.397 r  RLINK/CORE/RL/ICRC/R_LREGS[rtaddrb][11]_i_2/O
                         net (fo=12, routed)          0.522     5.919    RLINK/CORE/RL/ICRC_n_17
    SLICE_X61Y104        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][4]/CE
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     9.745 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.906    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324     3.583 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639     5.222    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.313 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.493     6.805    RLINK/CORE/RL/CLKFX
    SLICE_X61Y104        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][4]/C
                         clock pessimism              0.488     7.294    
                         clock uncertainty           -0.066     7.228    
    SLICE_X61Y104        FDRE (Setup_fdre_C_CE)      -0.205     7.023    RLINK/CORE/RL/R_LREGS_reg[rtaddrb][4]
  -------------------------------------------------------------------
                         required time                          7.023    
                         arrival time                          -5.919    
  -------------------------------------------------------------------
                         slack                                  1.104    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.013ns  (arrival time - required time)
  Source:                 HIO/HIO/HIO/DEB.DEB_BTN/R_REGS_reg[dchange][3]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            HIO/HIO/HIO/DEB.DEB_BTN/R_REGS_reg[dout][3]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.CLKOUT0 rise@0.000ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.369ns  (logic 0.186ns (50.412%)  route 0.183ns (49.588%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.264ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.836ns
    Source Clock Delay      (SCD):    -0.591ns
    Clock Pessimism Removal (CPR):    -0.509ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.573    -0.591    HIO/HIO/HIO/DEB.DEB_BTN/CLKFX
    SLICE_X28Y99         FDRE                                         r  HIO/HIO/HIO/DEB.DEB_BTN/R_REGS_reg[dchange][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y99         FDRE (Prop_fdre_C_Q)         0.141    -0.450 r  HIO/HIO/HIO/DEB.DEB_BTN/R_REGS_reg[dchange][3]/Q
                         net (fo=2, routed)           0.183    -0.267    HIO/HIO/HIO/DEB.DEB_BTN/p_3_in
    SLICE_X29Y100        LUT6 (Prop_lut6_I2_O)        0.045    -0.222 r  HIO/HIO/HIO/DEB.DEB_BTN/R_REGS[dout][3]_i_1/O
                         net (fo=1, routed)           0.000    -0.222    HIO/HIO/HIO/DEB.DEB_BTN/R_REGS[dout][3]_i_1_n_0
    SLICE_X29Y100        FDRE                                         r  HIO/HIO/HIO/DEB.DEB_BTN/R_REGS_reg[dout][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.837    -0.836    HIO/HIO/HIO/DEB.DEB_BTN/CLKFX
    SLICE_X29Y100        FDRE                                         r  HIO/HIO/HIO/DEB.DEB_BTN/R_REGS_reg[dout][3]/C
                         clock pessimism              0.509    -0.327    
    SLICE_X29Y100        FDRE (Hold_fdre_C_D)         0.092    -0.235    HIO/HIO/HIO/DEB.DEB_BTN/R_REGS_reg[dout][3]
  -------------------------------------------------------------------
                         required time                          0.235    
                         arrival time                          -0.222    
  -------------------------------------------------------------------
                         slack                                  0.013    

Slack (MET) :             0.031ns  (arrival time - required time)
  Source:                 RBDTST/MON/R_REGS_reg[rbwe]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/MON/BRAM1/sv_ram_reg/DIBDI[7]
                            (rising edge-triggered cell RAMB18E1 clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.CLKOUT0 rise@0.000ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.411ns  (logic 0.141ns (34.265%)  route 0.270ns (65.735%))
  Logic Levels:           0  
  Clock Path Skew:        0.084ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.793ns
    Source Clock Delay      (SCD):    -0.602ns
    Clock Pessimism Removal (CPR):    -0.275ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.562    -0.602    RBDTST/MON/CLKFX
    SLICE_X28Y114        FDRE                                         r  RBDTST/MON/R_REGS_reg[rbwe]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y114        FDRE (Prop_fdre_C_Q)         0.141    -0.461 r  RBDTST/MON/R_REGS_reg[rbwe]/Q
                         net (fo=1, routed)           0.270    -0.191    RBDTST/MON/BRAM1/BRAM1_DI_reg[25]
    RAMB18_X0Y45         RAMB18E1                                     r  RBDTST/MON/BRAM1/sv_ram_reg/DIBDI[7]
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.880    -0.793    RBDTST/MON/BRAM1/CLKFX
    RAMB18_X0Y45         RAMB18E1                                     r  RBDTST/MON/BRAM1/sv_ram_reg/CLKBWRCLK
                         clock pessimism              0.275    -0.518    
    RAMB18_X0Y45         RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_DIBDI[7])
                                                      0.296    -0.222    RBDTST/MON/BRAM1/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.222    
                         arrival time                          -0.191    
  -------------------------------------------------------------------
                         slack                                  0.031    

Slack (MET) :             0.041ns  (arrival time - required time)
  Source:                 RBDTST/MON/R_REGS_reg[rback]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/MON/BRAM1/sv_ram_reg/DIBDI[10]
                            (rising edge-triggered cell RAMB18E1 clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.CLKOUT0 rise@0.000ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.422ns  (logic 0.141ns (33.446%)  route 0.281ns (66.554%))
  Logic Levels:           0  
  Clock Path Skew:        0.084ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.793ns
    Source Clock Delay      (SCD):    -0.602ns
    Clock Pessimism Removal (CPR):    -0.275ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.562    -0.602    RBDTST/MON/CLKFX
    SLICE_X28Y113        FDRE                                         r  RBDTST/MON/R_REGS_reg[rback]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y113        FDRE (Prop_fdre_C_Q)         0.141    -0.461 r  RBDTST/MON/R_REGS_reg[rback]/Q
                         net (fo=2, routed)           0.281    -0.181    RBDTST/MON/BRAM1/BRAM1_DI_reg[28]
    RAMB18_X0Y45         RAMB18E1                                     r  RBDTST/MON/BRAM1/sv_ram_reg/DIBDI[10]
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.880    -0.793    RBDTST/MON/BRAM1/CLKFX
    RAMB18_X0Y45         RAMB18E1                                     r  RBDTST/MON/BRAM1/sv_ram_reg/CLKBWRCLK
                         clock pessimism              0.275    -0.518    
    RAMB18_X0Y45         RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_DIBDI[10])
                                                      0.296    -0.222    RBDTST/MON/BRAM1/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.222    
                         arrival time                          -0.181    
  -------------------------------------------------------------------
                         slack                                  0.041    

Slack (MET) :             0.044ns  (arrival time - required time)
  Source:                 RBDTST/MON/R_REGS_reg[rbaddr][15]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/MON/BRAM0/sv_ram_reg/DIADI[15]
                            (rising edge-triggered cell RAMB18E1 clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.CLKOUT0 rise@0.000ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.420ns  (logic 0.141ns (33.587%)  route 0.279ns (66.413%))
  Logic Levels:           0  
  Clock Path Skew:        0.079ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.796ns
    Source Clock Delay      (SCD):    -0.600ns
    Clock Pessimism Removal (CPR):    -0.275ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.564    -0.600    RBDTST/MON/CLKFX
    SLICE_X28Y111        FDRE                                         r  RBDTST/MON/R_REGS_reg[rbaddr][15]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y111        FDRE (Prop_fdre_C_Q)         0.141    -0.459 r  RBDTST/MON/R_REGS_reg[rbaddr][15]/Q
                         net (fo=2, routed)           0.279    -0.180    RBDTST/MON/BRAM0/BRAM0_DI_reg[3]
    RAMB18_X0Y44         RAMB18E1                                     r  RBDTST/MON/BRAM0/sv_ram_reg/DIADI[15]
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.877    -0.796    RBDTST/MON/BRAM0/CLKFX
    RAMB18_X0Y44         RAMB18E1                                     r  RBDTST/MON/BRAM0/sv_ram_reg/CLKARDCLK
                         clock pessimism              0.275    -0.521    
    RAMB18_X0Y44         RAMB18E1 (Hold_ramb18e1_CLKARDCLK_DIADI[15])
                                                      0.296    -0.225    RBDTST/MON/BRAM0/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.225    
                         arrival time                          -0.180    
  -------------------------------------------------------------------
                         slack                                  0.044    

Slack (MET) :             0.046ns  (arrival time - required time)
  Source:                 RBDTST/MON/R_REGS_reg[rbaddr][2]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/MON/BRAM0/sv_ram_reg/DIADI[2]
                            (rising edge-triggered cell RAMB18E1 clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.CLKOUT0 rise@0.000ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.422ns  (logic 0.141ns (33.446%)  route 0.281ns (66.554%))
  Logic Levels:           0  
  Clock Path Skew:        0.079ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.796ns
    Source Clock Delay      (SCD):    -0.600ns
    Clock Pessimism Removal (CPR):    -0.275ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.564    -0.600    RBDTST/MON/CLKFX
    SLICE_X28Y110        FDRE                                         r  RBDTST/MON/R_REGS_reg[rbaddr][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X28Y110        FDRE (Prop_fdre_C_Q)         0.141    -0.459 r  RBDTST/MON/R_REGS_reg[rbaddr][2]/Q
                         net (fo=2, routed)           0.281    -0.179    RBDTST/MON/BRAM0/BRAM0_DI_reg[2]
    RAMB18_X0Y44         RAMB18E1                                     r  RBDTST/MON/BRAM0/sv_ram_reg/DIADI[2]
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.877    -0.796    RBDTST/MON/BRAM0/CLKFX
    RAMB18_X0Y44         RAMB18E1                                     r  RBDTST/MON/BRAM0/sv_ram_reg/CLKARDCLK
                         clock pessimism              0.275    -0.521    
    RAMB18_X0Y44         RAMB18E1 (Hold_ramb18e1_CLKARDCLK_DIADI[2])
                                                      0.296    -0.225    RBDTST/MON/BRAM0/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.225    
                         arrival time                          -0.179    
  -------------------------------------------------------------------
                         slack                                  0.046    

Slack (MET) :             0.057ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[cnt][7]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_BREGS_reg[cnt][7]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.CLKOUT0 rise@0.000ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.410ns  (logic 0.209ns (50.965%)  route 0.201ns (49.035%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.261ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.850ns
    Source Clock Delay      (SCD):    -0.607ns
    Clock Pessimism Removal (CPR):    -0.504ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.557    -0.607    RLINK/CORE/RL/CLKFX
    SLICE_X50Y111        FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[cnt][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X50Y111        FDRE (Prop_fdre_C_Q)         0.164    -0.443 r  RLINK/CORE/RL/R_LREGS_reg[cnt][7]/Q
                         net (fo=4, routed)           0.201    -0.242    RLINK/CORE/RL/in61[8]
    SLICE_X53Y113        LUT5 (Prop_lut5_I0_O)        0.045    -0.197 r  RLINK/CORE/RL/R_BREGS[cnt][7]_i_1/O
                         net (fo=1, routed)           0.000    -0.197    RLINK/CORE/RL/N_BREGS[cnt][7]
    SLICE_X53Y113        FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[cnt][7]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.822    -0.850    RLINK/CORE/RL/CLKFX
    SLICE_X53Y113        FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[cnt][7]/C
                         clock pessimism              0.504    -0.346    
    SLICE_X53Y113        FDRE (Hold_fdre_C_D)         0.092    -0.254    RLINK/CORE/RL/R_BREGS_reg[cnt][7]
  -------------------------------------------------------------------
                         required time                          0.254    
                         arrival time                          -0.197    
  -------------------------------------------------------------------
                         slack                                  0.057    

Slack (MET) :             0.068ns  (arrival time - required time)
  Source:                 HIO/HIO/HIO/DEB.DEB_SWI/R_REGS_reg[dref][2]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            HIO/HIO/HIO/DEB.DEB_SWI/R_REGS_reg[dchange][2]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.CLKOUT0 rise@0.000ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.453ns  (logic 0.186ns (41.098%)  route 0.267ns (58.902%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.265ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.836ns
    Source Clock Delay      (SCD):    -0.592ns
    Clock Pessimism Removal (CPR):    -0.509ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.572    -0.592    HIO/HIO/HIO/DEB.DEB_SWI/CLKFX
    SLICE_X31Y99         FDRE                                         r  HIO/HIO/HIO/DEB.DEB_SWI/R_REGS_reg[dref][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X31Y99         FDRE (Prop_fdre_C_Q)         0.141    -0.451 r  HIO/HIO/HIO/DEB.DEB_SWI/R_REGS_reg[dref][2]/Q
                         net (fo=2, routed)           0.267    -0.185    HIO/HIO/HIO/DEB.DEB_SWI/p_0_in1_in
    SLICE_X30Y100        LUT3 (Prop_lut3_I1_O)        0.045    -0.140 r  HIO/HIO/HIO/DEB.DEB_SWI/R_REGS[dchange][2]_i_1/O
                         net (fo=1, routed)           0.000    -0.140    HIO/HIO/HIO/DEB.DEB_SWI/R_REGS[dchange][2]_i_1_n_0
    SLICE_X30Y100        FDRE                                         r  HIO/HIO/HIO/DEB.DEB_SWI/R_REGS_reg[dchange][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.837    -0.836    HIO/HIO/HIO/DEB.DEB_SWI/CLKFX
    SLICE_X30Y100        FDRE                                         r  HIO/HIO/HIO/DEB.DEB_SWI/R_REGS_reg[dchange][2]/C
                         clock pessimism              0.509    -0.327    
    SLICE_X30Y100        FDRE (Hold_fdre_C_D)         0.120    -0.207    HIO/HIO/HIO/DEB.DEB_SWI/R_REGS_reg[dchange][2]
  -------------------------------------------------------------------
                         required time                          0.207    
                         arrival time                          -0.140    
  -------------------------------------------------------------------
                         slack                                  0.068    

Slack (MET) :             0.069ns  (arrival time - required time)
  Source:                 RBDTST/EMON/R_REGS_reg[laddr_1][0]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/EMON/BRAM/sv_ram_reg/ADDRBWRADDR[5]
                            (rising edge-triggered cell RAMB18E1 clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.CLKOUT0 rise@0.000ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.311ns  (logic 0.164ns (52.747%)  route 0.147ns (47.253%))
  Logic Levels:           0  
  Clock Path Skew:        0.058ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.790ns
    Source Clock Delay      (SCD):    -0.594ns
    Clock Pessimism Removal (CPR):    -0.254ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.570    -0.594    RBDTST/EMON/CLKFX
    SLICE_X8Y102         FDRE                                         r  RBDTST/EMON/R_REGS_reg[laddr_1][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y102         FDRE (Prop_fdre_C_Q)         0.164    -0.430 r  RBDTST/EMON/R_REGS_reg[laddr_1][0]/Q
                         net (fo=1, routed)           0.147    -0.283    RBDTST/EMON/BRAM/ADDRBWRADDR[0]
    RAMB18_X0Y40         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/ADDRBWRADDR[5]
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.883    -0.790    RBDTST/EMON/BRAM/CLKFX
    RAMB18_X0Y40         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/CLKBWRCLK
                         clock pessimism              0.254    -0.536    
    RAMB18_X0Y40         RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[5])
                                                      0.183    -0.353    RBDTST/EMON/BRAM/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.353    
                         arrival time                          -0.283    
  -------------------------------------------------------------------
                         slack                                  0.069    

Slack (MET) :             0.069ns  (arrival time - required time)
  Source:                 RBDTST/EMON/R_REGS_reg[laddr_1][1]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/EMON/BRAM/sv_ram_reg/ADDRBWRADDR[6]
                            (rising edge-triggered cell RAMB18E1 clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.CLKOUT0 rise@0.000ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.311ns  (logic 0.164ns (52.747%)  route 0.147ns (47.253%))
  Logic Levels:           0  
  Clock Path Skew:        0.058ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.790ns
    Source Clock Delay      (SCD):    -0.594ns
    Clock Pessimism Removal (CPR):    -0.254ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.570    -0.594    RBDTST/EMON/CLKFX
    SLICE_X8Y102         FDRE                                         r  RBDTST/EMON/R_REGS_reg[laddr_1][1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y102         FDRE (Prop_fdre_C_Q)         0.164    -0.430 r  RBDTST/EMON/R_REGS_reg[laddr_1][1]/Q
                         net (fo=1, routed)           0.147    -0.283    RBDTST/EMON/BRAM/ADDRBWRADDR[1]
    RAMB18_X0Y40         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/ADDRBWRADDR[6]
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.883    -0.790    RBDTST/EMON/BRAM/CLKFX
    RAMB18_X0Y40         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/CLKBWRCLK
                         clock pessimism              0.254    -0.536    
    RAMB18_X0Y40         RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[6])
                                                      0.183    -0.353    RBDTST/EMON/BRAM/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.353    
                         arrival time                          -0.283    
  -------------------------------------------------------------------
                         slack                                  0.069    

Slack (MET) :             0.071ns  (arrival time - required time)
  Source:                 RBDTST/EMON/R_REGS_reg[laddr_1][6]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/EMON/BRAM/sv_ram_reg/ADDRBWRADDR[11]
                            (rising edge-triggered cell RAMB18E1 clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             USEMMCM.CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.CLKOUT0 rise@0.000ns - USEMMCM.CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.313ns  (logic 0.164ns (52.410%)  route 0.149ns (47.590%))
  Logic Levels:           0  
  Clock Path Skew:        0.058ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.790ns
    Source Clock Delay      (SCD):    -0.594ns
    Clock Pessimism Removal (CPR):    -0.254ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.570    -0.594    RBDTST/EMON/CLKFX
    SLICE_X8Y102         FDRE                                         r  RBDTST/EMON/R_REGS_reg[laddr_1][6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y102         FDRE (Prop_fdre_C_Q)         0.164    -0.430 r  RBDTST/EMON/R_REGS_reg[laddr_1][6]/Q
                         net (fo=1, routed)           0.149    -0.281    RBDTST/EMON/BRAM/ADDRBWRADDR[6]
    RAMB18_X0Y40         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/ADDRBWRADDR[11]
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.883    -0.790    RBDTST/EMON/BRAM/CLKFX
    RAMB18_X0Y40         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/CLKBWRCLK
                         clock pessimism              0.254    -0.536    
    RAMB18_X0Y40         RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[11])
                                                      0.183    -0.353    RBDTST/EMON/BRAM/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.353    
                         arrival time                          -0.281    
  -------------------------------------------------------------------
                         slack                                  0.071    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         USEMMCM.CLKOUT0
Waveform(ns):       { 0.000 4.167 }
Period(ns):         8.333
Sources:            { GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     XADC/DCLK           n/a            4.000         8.333       4.333      XADC_X0Y0        SMRB.I0/SM/DCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.944         8.333       5.389      RAMB18_X0Y40     RBDTST/EMON/BRAM/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.944         8.333       5.389      RAMB18_X0Y40     RBDTST/EMON/BRAM/sv_ram_reg/CLKBWRCLK
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.944         8.333       5.389      RAMB36_X1Y21     RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.944         8.333       5.389      RAMB36_X1Y21     RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         8.333       5.757      RAMB18_X0Y46     RBDTST/BRAM/BRAM/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         8.333       5.757      RAMB18_X0Y44     RBDTST/MON/BRAM0/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.576         8.333       5.757      RAMB18_X0Y44     RBDTST/MON/BRAM0/sv_ram_reg/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         8.333       5.757      RAMB18_X0Y45     RBDTST/MON/BRAM1/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.576         8.333       5.757      RAMB18_X0Y45     RBDTST/MON/BRAM1/sv_ram_reg/CLKBWRCLK
Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       8.333       205.027    MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB_D1/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X50Y113    DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK



--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  USEMMCM.CLKFBOUT
  To Clock:  

Max Delay             1 Endpoint
Min Delay             1 Endpoint
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT
                            (clock source 'USEMMCM.CLKFBOUT'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            GEN_CLKSYS/USEMMCM.MMCM/CLKFBIN
  Path Group:             (none)
  Path Type:              Max at Fast Process Corner
  Data Path Delay:        1.396ns  (logic 0.029ns (2.077%)  route 1.367ns (97.923%))
  Logic Levels:           1  (BUFG=1)
  Clock Uncertainty:      0.131ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.072ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKFBOUT fall edge)
                                                      5.000     5.000 f  
    E3                                                0.000     5.000 f  I_CLK100 (IN)
                         net (fo=0)                   0.000     5.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     5.438 f  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     5.918    GEN_CLKSYS/CLKIN
  -------------------------------------------------------------------    -------------------
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT)
                                                     -3.163     2.755 f  GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT
                         net (fo=1, routed)           0.544     3.298    GEN_CLKSYS/USEMMCM.CLKFBOUT
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.029     3.327 f  GEN_CLKSYS/USEMMCM.BUFG_CLKFB/O
                         net (fo=1, routed)           0.824     4.151    GEN_CLKSYS/USEMMCM.CLKFBOUT_BUF
    MMCME2_ADV_X1Y2      MMCME2_ADV                                   f  GEN_CLKSYS/USEMMCM.MMCM/CLKFBIN
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT
                            (clock source 'USEMMCM.CLKFBOUT'  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            GEN_CLKSYS/USEMMCM.MMCM/CLKFBIN
  Path Group:             (none)
  Path Type:              Min at Slow Process Corner
  Data Path Delay:        3.236ns  (logic 0.091ns (2.812%)  route 3.145ns (97.188%))
  Logic Levels:           1  (BUFG=1)
  Clock Uncertainty:      0.131ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.072ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKFBOUT rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     1.411 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162     2.573    GEN_CLKSYS/CLKIN
  -------------------------------------------------------------------    -------------------
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT)
                                                     -7.324    -4.751 r  GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT
                         net (fo=1, routed)           1.639    -3.112    GEN_CLKSYS/USEMMCM.CLKFBOUT
    BUFGCTRL_X0Y17       BUFG (Prop_bufg_I_O)         0.091    -3.021 r  GEN_CLKSYS/USEMMCM.BUFG_CLKFB/O
                         net (fo=1, routed)           1.506    -1.515    GEN_CLKSYS/USEMMCM.CLKFBOUT_BUF
    MMCME2_ADV_X1Y2      MMCME2_ADV                                   r  GEN_CLKSYS/USEMMCM.MMCM/CLKFBIN
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  USEMMCM.CLKOUT0
  To Clock:  

Max Delay            40 Endpoints
Min Delay            40 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 HIO/HIO/IOB_SEG_N/R_DO_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_SEG_N[0]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.050ns  (logic 4.049ns (99.975%)  route 0.001ns (0.025%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.732    -0.808    HIO/HIO/IOB_SEG_N/CLKFX
    OLOGIC_X0Y51         FDRE                                         r  HIO/HIO/IOB_SEG_N/R_DO_reg[0]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y51         FDRE (Prop_fdre_C_Q)         0.472    -0.336 r  HIO/HIO/IOB_SEG_N/R_DO_reg[0]/Q
                         net (fo=1, routed)           0.001    -0.335    O_SEG_N_OBUF[0]
    T10                  OBUF (Prop_obuf_I_O)         3.577     3.242 r  O_SEG_N_OBUF[0]_inst/O
                         net (fo=0)                   0.000     3.242    O_SEG_N[0]
    T10                                                               r  O_SEG_N[0] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 HIO/HIO/IOB_ANO_N/R_DO_reg[2]/C
                            (rising edge-triggered cell FDSE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_ANO_N[2]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.047ns  (logic 4.046ns (99.975%)  route 0.001ns (0.025%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.732    -0.808    HIO/HIO/IOB_ANO_N/CLKFX
    OLOGIC_X0Y52         FDSE                                         r  HIO/HIO/IOB_ANO_N/R_DO_reg[2]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y52         FDSE (Prop_fdse_C_Q)         0.472    -0.336 r  HIO/HIO/IOB_ANO_N/R_DO_reg[2]/Q
                         net (fo=1, routed)           0.001    -0.335    O_ANO_N_OBUF[2]
    T9                   OBUF (Prop_obuf_I_O)         3.574     3.239 r  O_ANO_N_OBUF[2]_inst/O
                         net (fo=0)                   0.000     3.239    O_ANO_N[2]
    T9                                                                r  O_ANO_N[2] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 HIO/HIO/HIO/IOB_LED/R_DO_reg[14]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_LED[14]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.043ns  (logic 4.042ns (99.975%)  route 0.001ns (0.025%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.729    -0.811    HIO/HIO/HIO/IOB_LED/CLKFX
    OLOGIC_X0Y59         FDRE                                         r  HIO/HIO/HIO/IOB_LED/R_DO_reg[14]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y59         FDRE (Prop_fdre_C_Q)         0.472    -0.339 r  HIO/HIO/HIO/IOB_LED/R_DO_reg[14]/Q
                         net (fo=1, routed)           0.001    -0.338    O_LED_OBUF[14]
    V12                  OBUF (Prop_obuf_I_O)         3.570     3.232 r  O_LED_OBUF[14]_inst/O
                         net (fo=0)                   0.000     3.232    O_LED[14]
    V12                                                               r  O_LED[14] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 HIO/HIO/HIO/IOB_LED/R_DO_reg[15]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_LED[15]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.042ns  (logic 4.041ns (99.975%)  route 0.001ns (0.025%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.730    -0.810    HIO/HIO/HIO/IOB_LED/CLKFX
    OLOGIC_X0Y57         FDRE                                         r  HIO/HIO/HIO/IOB_LED/R_DO_reg[15]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y57         FDRE (Prop_fdre_C_Q)         0.472    -0.338 r  HIO/HIO/HIO/IOB_LED/R_DO_reg[15]/Q
                         net (fo=1, routed)           0.001    -0.337    O_LED_OBUF[15]
    V11                  OBUF (Prop_obuf_I_O)         3.569     3.232 r  O_LED_OBUF[15]_inst/O
                         net (fo=0)                   0.000     3.232    O_LED[15]
    V11                                                               r  O_LED[15] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 RGB0/RGB/IOB_RGB/R_DO_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_RGBLED0[2]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.040ns  (logic 4.039ns (99.975%)  route 0.001ns (0.025%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.729    -0.811    RGB0/RGB/IOB_RGB/CLKFX
    OLOGIC_X0Y90         FDRE                                         r  RGB0/RGB/IOB_RGB/R_DO_reg[2]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y90         FDRE (Prop_fdre_C_Q)         0.472    -0.339 r  RGB0/RGB/IOB_RGB/R_DO_reg[2]/Q
                         net (fo=1, routed)           0.001    -0.338    O_RGBLED0_OBUF[2]
    R12                  OBUF (Prop_obuf_I_O)         3.567     3.229 r  O_RGBLED0_OBUF[2]_inst/O
                         net (fo=0)                   0.000     3.229    O_RGBLED0[2]
    R12                                                               r  O_RGBLED0[2] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 HIO/HIO/IOB_SEG_N/R_DO_reg[5]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_SEG_N[5]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.034ns  (logic 4.033ns (99.975%)  route 0.001ns (0.025%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.729    -0.811    HIO/HIO/IOB_SEG_N/CLKFX
    OLOGIC_X0Y62         FDRE                                         r  HIO/HIO/IOB_SEG_N/R_DO_reg[5]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y62         FDRE (Prop_fdre_C_Q)         0.472    -0.339 r  HIO/HIO/IOB_SEG_N/R_DO_reg[5]/Q
                         net (fo=1, routed)           0.001    -0.338    O_SEG_N_OBUF[5]
    T11                  OBUF (Prop_obuf_I_O)         3.561     3.222 r  O_SEG_N_OBUF[5]_inst/O
                         net (fo=0)                   0.000     3.222    O_SEG_N[5]
    T11                                                               r  O_SEG_N[5] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 HIO/HIO/IOB_SEG_N/R_DO_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_SEG_N[1]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.028ns  (logic 4.027ns (99.975%)  route 0.001ns (0.025%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.732    -0.808    HIO/HIO/IOB_SEG_N/CLKFX
    OLOGIC_X0Y50         FDRE                                         r  HIO/HIO/IOB_SEG_N/R_DO_reg[1]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y50         FDRE (Prop_fdre_C_Q)         0.472    -0.336 r  HIO/HIO/IOB_SEG_N/R_DO_reg[1]/Q
                         net (fo=1, routed)           0.001    -0.335    O_SEG_N_OBUF[1]
    R10                  OBUF (Prop_obuf_I_O)         3.555     3.220 r  O_SEG_N_OBUF[1]_inst/O
                         net (fo=0)                   0.000     3.220    O_SEG_N[1]
    R10                                                               r  O_SEG_N[1] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 HIO/HIO/IOB_ANO_N/R_DO_reg[7]/C
                            (rising edge-triggered cell FDSE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_ANO_N[7]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.026ns  (logic 4.025ns (99.975%)  route 0.001ns (0.025%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.731    -0.809    HIO/HIO/IOB_ANO_N/CLKFX
    OLOGIC_X0Y53         FDSE                                         r  HIO/HIO/IOB_ANO_N/R_DO_reg[7]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y53         FDSE (Prop_fdse_C_Q)         0.472    -0.337 r  HIO/HIO/IOB_ANO_N/R_DO_reg[7]/Q
                         net (fo=1, routed)           0.001    -0.336    O_ANO_N_OBUF[7]
    U13                  OBUF (Prop_obuf_I_O)         3.553     3.217 r  O_ANO_N_OBUF[7]_inst/O
                         net (fo=0)                   0.000     3.217    O_ANO_N[7]
    U13                                                               r  O_ANO_N[7] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 HIO/HIO/HIO/IOB_LED/R_DO_reg[13]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_LED[13]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.027ns  (logic 4.026ns (99.975%)  route 0.001ns (0.025%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.730    -0.810    HIO/HIO/HIO/IOB_LED/CLKFX
    OLOGIC_X0Y55         FDRE                                         r  HIO/HIO/HIO/IOB_LED/R_DO_reg[13]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y55         FDRE (Prop_fdre_C_Q)         0.472    -0.338 r  HIO/HIO/HIO/IOB_LED/R_DO_reg[13]/Q
                         net (fo=1, routed)           0.001    -0.337    O_LED_OBUF[13]
    V14                  OBUF (Prop_obuf_I_O)         3.554     3.217 r  O_LED_OBUF[13]_inst/O
                         net (fo=0)                   0.000     3.217    O_LED[13]
    V14                                                               r  O_LED[13] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 HIO/HIO/HIO/IOB_LED/R_DO_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_LED[10]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        4.025ns  (logic 4.024ns (99.975%)  route 0.001ns (0.025%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.070    -4.355 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.719    -2.636    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.730    -0.810    HIO/HIO/HIO/IOB_LED/CLKFX
    OLOGIC_X0Y56         FDRE                                         r  HIO/HIO/HIO/IOB_LED/R_DO_reg[10]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y56         FDRE (Prop_fdre_C_Q)         0.472    -0.338 r  HIO/HIO/HIO/IOB_LED/R_DO_reg[10]/Q
                         net (fo=1, routed)           0.001    -0.337    O_LED_OBUF[10]
    U14                  OBUF (Prop_obuf_I_O)         3.552     3.215 r  O_LED_OBUF[10]_inst/O
                         net (fo=0)                   0.000     3.215    O_LED[10]
    U14                                                               r  O_LED[10] (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 HIO/HIO/IOB_SEG_N/R_DO_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_SEG_N[2]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.372ns  (logic 1.371ns (99.927%)  route 0.001ns (0.073%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.592    -0.572    HIO/HIO/IOB_SEG_N/CLKFX
    OLOGIC_X0Y100        FDRE                                         r  HIO/HIO/IOB_SEG_N/R_DO_reg[2]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y100        FDRE (Prop_fdre_C_Q)         0.177    -0.395 r  HIO/HIO/IOB_SEG_N/R_DO_reg[2]/Q
                         net (fo=1, routed)           0.001    -0.394    O_SEG_N_OBUF[2]
    K16                  OBUF (Prop_obuf_I_O)         1.194     0.800 r  O_SEG_N_OBUF[2]_inst/O
                         net (fo=0)                   0.000     0.800    O_SEG_N[2]
    K16                                                               r  O_SEG_N[2] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 RGB0/RGB/IOB_RGB/R_DO_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_RGBLED0[0]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.396ns  (logic 1.395ns (99.928%)  route 0.001ns (0.072%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.590    -0.574    RGB0/RGB/IOB_RGB/CLKFX
    OLOGIC_X0Y78         FDRE                                         r  RGB0/RGB/IOB_RGB/R_DO_reg[0]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y78         FDRE (Prop_fdre_C_Q)         0.177    -0.397 r  RGB0/RGB/IOB_RGB/R_DO_reg[0]/Q
                         net (fo=1, routed)           0.001    -0.396    O_RGBLED0_OBUF[0]
    N15                  OBUF (Prop_obuf_I_O)         1.218     0.822 r  O_RGBLED0_OBUF[0]_inst/O
                         net (fo=0)                   0.000     0.822    O_RGBLED0[0]
    N15                                                               r  O_RGBLED0[0] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 HIO/HIO/HIO/IOB_LED/R_DO_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_LED[0]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.399ns  (logic 1.398ns (99.929%)  route 0.001ns (0.071%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.588    -0.576    HIO/HIO/HIO/IOB_LED/CLKFX
    OLOGIC_X0Y114        FDRE                                         r  HIO/HIO/HIO/IOB_LED/R_DO_reg[0]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y114        FDRE (Prop_fdre_C_Q)         0.177    -0.399 r  HIO/HIO/HIO/IOB_LED/R_DO_reg[0]/Q
                         net (fo=1, routed)           0.001    -0.398    O_LED_OBUF[0]
    H17                  OBUF (Prop_obuf_I_O)         1.221     0.823 r  O_LED_OBUF[0]_inst/O
                         net (fo=0)                   0.000     0.823    O_LED[0]
    H17                                                               r  O_LED[0] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 HIO/HIO/IOB_ANO_N/R_DO_reg[6]/C
                            (rising edge-triggered cell FDSE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_ANO_N[6]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.397ns  (logic 1.396ns (99.928%)  route 0.001ns (0.072%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.593    -0.571    HIO/HIO/IOB_ANO_N/CLKFX
    OLOGIC_X1Y104        FDSE                                         r  HIO/HIO/IOB_ANO_N/R_DO_reg[6]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y104        FDSE (Prop_fdse_C_Q)         0.177    -0.394 r  HIO/HIO/IOB_ANO_N/R_DO_reg[6]/Q
                         net (fo=1, routed)           0.001    -0.393    O_ANO_N_OBUF[6]
    K2                   OBUF (Prop_obuf_I_O)         1.219     0.825 r  O_ANO_N_OBUF[6]_inst/O
                         net (fo=0)                   0.000     0.825    O_ANO_N[6]
    K2                                                                r  O_ANO_N[6] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 RGB0/RGB/IOB_RGB/R_DO_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_RGBLED0[1]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.400ns  (logic 1.399ns (99.929%)  route 0.001ns (0.071%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.591    -0.573    RGB0/RGB/IOB_RGB/CLKFX
    OLOGIC_X0Y80         FDRE                                         r  RGB0/RGB/IOB_RGB/R_DO_reg[1]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y80         FDRE (Prop_fdre_C_Q)         0.177    -0.396 r  RGB0/RGB/IOB_RGB/R_DO_reg[1]/Q
                         net (fo=1, routed)           0.001    -0.395    O_RGBLED0_OBUF[1]
    M16                  OBUF (Prop_obuf_I_O)         1.222     0.827 r  O_RGBLED0_OBUF[1]_inst/O
                         net (fo=0)                   0.000     0.827    O_RGBLED0[1]
    M16                                                               r  O_RGBLED0[1] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 RGB1/RGB/IOB_RGB/R_DO_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_RGBLED1[0]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.403ns  (logic 1.402ns (99.929%)  route 0.001ns (0.071%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.590    -0.574    RGB1/RGB/IOB_RGB/CLKFX
    OLOGIC_X0Y77         FDRE                                         r  RGB1/RGB/IOB_RGB/R_DO_reg[0]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y77         FDRE (Prop_fdre_C_Q)         0.177    -0.397 r  RGB1/RGB/IOB_RGB/R_DO_reg[0]/Q
                         net (fo=1, routed)           0.001    -0.396    O_RGBLED1_OBUF[0]
    N16                  OBUF (Prop_obuf_I_O)         1.225     0.828 r  O_RGBLED1_OBUF[0]_inst/O
                         net (fo=0)                   0.000     0.828    O_RGBLED1[0]
    N16                                                               r  O_RGBLED1[0] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 RGB1/RGB/IOB_RGB/R_DO_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_RGBLED1[2]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.413ns  (logic 1.412ns (99.929%)  route 0.001ns (0.071%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.585    -0.579    RGB1/RGB/IOB_RGB/CLKFX
    OLOGIC_X0Y119        FDRE                                         r  RGB1/RGB/IOB_RGB/R_DO_reg[2]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y119        FDRE (Prop_fdre_C_Q)         0.177    -0.402 r  RGB1/RGB/IOB_RGB/R_DO_reg[2]/Q
                         net (fo=1, routed)           0.001    -0.401    O_RGBLED1_OBUF[2]
    G14                  OBUF (Prop_obuf_I_O)         1.235     0.834 r  O_RGBLED1_OBUF[2]_inst/O
                         net (fo=0)                   0.000     0.834    O_RGBLED1[2]
    G14                                                               r  O_RGBLED1[2] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 IOB_RS232/IOB_RTS/IOB/R_DO_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_RTS_N
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.414ns  (logic 1.413ns (99.929%)  route 0.001ns (0.071%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.585    -0.579    IOB_RS232/IOB_RTS/IOB/CLKFX
    OLOGIC_X1Y125        FDRE                                         r  IOB_RS232/IOB_RTS/IOB/R_DO_reg[0]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X1Y125        FDRE (Prop_fdre_C_Q)         0.177    -0.402 r  IOB_RS232/IOB_RTS/IOB/R_DO_reg[0]/Q
                         net (fo=1, routed)           0.001    -0.401    O_RTS_N_OBUF
    D3                   OBUF (Prop_obuf_I_O)         1.236     0.835 r  O_RTS_N_OBUF_inst/O
                         net (fo=0)                   0.000     0.835    O_RTS_N
    D3                                                                r  O_RTS_N (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 HIO/HIO/HIO/IOB_LED/R_DO_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_LED[11]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.410ns  (logic 1.409ns (99.929%)  route 0.001ns (0.071%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.591    -0.573    HIO/HIO/HIO/IOB_LED/CLKFX
    OLOGIC_X0Y69         FDRE                                         r  HIO/HIO/HIO/IOB_LED/R_DO_reg[11]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y69         FDRE (Prop_fdre_C_Q)         0.177    -0.396 r  HIO/HIO/HIO/IOB_LED/R_DO_reg[11]/Q
                         net (fo=1, routed)           0.001    -0.395    O_LED_OBUF[11]
    T16                  OBUF (Prop_obuf_I_O)         1.232     0.837 r  O_LED_OBUF[11]_inst/O
                         net (fo=0)                   0.000     0.837    O_LED[11]
    T16                                                               r  O_LED[11] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 HIO/HIO/IOB_SEG_N/R_DO_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            O_SEG_N[4]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.412ns  (logic 1.411ns (99.929%)  route 0.001ns (0.071%))
  Logic Levels:           1  (OBUF=1)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.379    -1.689 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.499    -1.190    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.589    -0.575    HIO/HIO/IOB_SEG_N/CLKFX
    OLOGIC_X0Y74         FDRE                                         r  HIO/HIO/IOB_SEG_N/R_DO_reg[4]/C
  -------------------------------------------------------------------    -------------------
    OLOGIC_X0Y74         FDRE (Prop_fdre_C_Q)         0.177    -0.398 r  HIO/HIO/IOB_SEG_N/R_DO_reg[4]/Q
                         net (fo=1, routed)           0.001    -0.397    O_SEG_N_OBUF[4]
    P15                  OBUF (Prop_obuf_I_O)         1.234     0.837 r  O_SEG_N_OBUF[4]_inst/O
                         net (fo=0)                   0.000     0.837    O_SEG_N[4]
    P15                                                               r  O_SEG_N[4] (OUT)
  -------------------------------------------------------------------    -------------------





--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  
  To Clock:  USEMMCM.CLKOUT0

Max Delay            55 Endpoints
Min Delay            55 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 UARB/UA/UA/DATA[3]
                            (internal pin)
  Destination:            RLINK/CORE/RL/R_BREGS_reg[rbdout][3]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.666ns  (logic 0.620ns (10.942%)  route 5.046ns (89.058%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    USR_ACCESS_X0Y0      USR_ACCESSE2                 0.000     0.000 r  UARB/UA/UA/DATA[3]
                         net (fo=1, routed)           2.738     2.738    UARB/UA/DATA[3]
    SLICE_X28Y109        LUT6 (Prop_lut6_I2_O)        0.124     2.862 r  UARB/UA/R_BREGS[rbdout][3]_i_17/O
                         net (fo=1, routed)           0.500     3.362    RBDTST/BRAM/BRAM/R_BREGS[rbdout][3]_i_5_0
    SLICE_X28Y116        LUT6 (Prop_lut6_I1_O)        0.124     3.486 r  RBDTST/BRAM/BRAM/R_BREGS[rbdout][3]_i_10/O
                         net (fo=1, routed)           0.433     3.919    SMRB.I0/SMRB/R_BREGS[rbdout][3]_i_2
    SLICE_X28Y116        LUT5 (Prop_lut5_I0_O)        0.124     4.043 r  SMRB.I0/SMRB/R_BREGS[rbdout][3]_i_5/O
                         net (fo=2, routed)           0.615     4.658    RBDTST/MON/BRAM1/R_BREGS_reg[rbdout][3]
    SLICE_X30Y114        LUT6 (Prop_lut6_I1_O)        0.124     4.782 r  RBDTST/MON/BRAM1/R_BREGS[rbdout][3]_i_2/O
                         net (fo=1, routed)           0.760     5.542    RLINK/CORE/RL/SEL__0/R_BREGS_reg[rbdout][3]_0
    SLICE_X45Y114        LUT6 (Prop_lut6_I0_O)        0.124     5.666 r  RLINK/CORE/RL/SEL__0/R_BREGS[rbdout][3]_i_1/O
                         net (fo=1, routed)           0.000     5.666    RLINK/CORE/RL/RB_SRES_OR[dout][3]
    SLICE_X45Y114        FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     1.411 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162     2.573    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324    -4.751 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639    -3.112    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -3.021 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.494    -1.527    RLINK/CORE/RL/CLKFX
    SLICE_X45Y114        FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][3]/C

Slack:                    inf
  Source:                 UARB/UA/UA/DATA[18]
                            (internal pin)
  Destination:            RLINK/CORE/RL/R_BREGS_reg[rbdout][2]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.595ns  (logic 0.620ns (11.081%)  route 4.975ns (88.919%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    USR_ACCESS_X0Y0      USR_ACCESSE2                 0.000     0.000 r  UARB/UA/UA/DATA[18]
                         net (fo=1, routed)           2.406     2.406    UARB/UA/DATA[18]
    SLICE_X28Y111        LUT6 (Prop_lut6_I4_O)        0.124     2.530 r  UARB/UA/R_BREGS[rbdout][2]_i_21/O
                         net (fo=1, routed)           0.496     3.026    RBDTST/BRAM/BRAM/R_BREGS[rbdout][2]_i_10_0
    SLICE_X28Y116        LUT6 (Prop_lut6_I1_O)        0.124     3.150 r  RBDTST/BRAM/BRAM/R_BREGS[rbdout][2]_i_18/O
                         net (fo=1, routed)           0.416     3.566    SMRB.I0/SMRB/R_BREGS[rbdout][2]_i_3_0
    SLICE_X28Y117        LUT5 (Prop_lut5_I0_O)        0.124     3.690 r  SMRB.I0/SMRB/R_BREGS[rbdout][2]_i_10/O
                         net (fo=1, routed)           0.695     4.385    SMRB.I0/SMRB/R_BREGS[rbdout][2]_i_10_n_0
    SLICE_X29Y114        LUT6 (Prop_lut6_I5_O)        0.124     4.509 r  SMRB.I0/SMRB/R_BREGS[rbdout][2]_i_3/O
                         net (fo=2, routed)           0.962     5.471    RLINK/CORE/RL/SEL__0/R_BREGS_reg[rbdout][2]_0
    SLICE_X45Y113        LUT6 (Prop_lut6_I1_O)        0.124     5.595 r  RLINK/CORE/RL/SEL__0/R_BREGS[rbdout][2]_i_1/O
                         net (fo=1, routed)           0.000     5.595    RLINK/CORE/RL/RB_SRES_OR[dout][2]
    SLICE_X45Y113        FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     1.411 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162     2.573    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324    -4.751 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639    -3.112    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -3.021 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.494    -1.527    RLINK/CORE/RL/CLKFX
    SLICE_X45Y113        FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][2]/C

Slack:                    inf
  Source:                 UARB/UA/UA/DATA[8]
                            (internal pin)
  Destination:            RLINK/CORE/RL/R_BREGS_reg[rbdout][8]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.536ns  (logic 0.620ns (11.199%)  route 4.916ns (88.801%))
  Logic Levels:           5  (LUT5=3 LUT6=2)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    USR_ACCESS_X0Y0      USR_ACCESSE2                 0.000     0.000 r  UARB/UA/UA/DATA[8]
                         net (fo=1, routed)           2.151     2.151    UARB/UA/DATA[8]
    SLICE_X28Y101        LUT5 (Prop_lut5_I2_O)        0.124     2.275 r  UARB/UA/R_BREGS[rbdout][8]_i_17/O
                         net (fo=1, routed)           1.072     3.347    RBDTST/BRAM/BRAM/R_BREGS[rbdout][8]_i_4
    SLICE_X28Y112        LUT6 (Prop_lut6_I0_O)        0.124     3.471 r  RBDTST/BRAM/BRAM/R_BREGS[rbdout][8]_i_10/O
                         net (fo=1, routed)           0.492     3.963    RBDTST/EMON/BRAM/R_BREGS[rbdout][8]_i_2_1
    SLICE_X29Y112        LUT5 (Prop_lut5_I4_O)        0.124     4.087 r  RBDTST/EMON/BRAM/R_BREGS[rbdout][8]_i_4/O
                         net (fo=1, routed)           0.766     4.854    RLINK/CORE/RL/R_BREGS_reg[rbdout][8]_0
    SLICE_X41Y112        LUT6 (Prop_lut6_I3_O)        0.124     4.978 r  RLINK/CORE/RL/R_BREGS[rbdout][8]_i_2/O
                         net (fo=2, routed)           0.435     5.412    RLINK/CORE/RL/SEL__0/RB_SRES[dout][0]
    SLICE_X44Y112        LUT5 (Prop_lut5_I4_O)        0.124     5.536 r  RLINK/CORE/RL/SEL__0/R_BREGS[rbdout][8]_i_1/O
                         net (fo=1, routed)           0.000     5.536    RLINK/CORE/RL/RB_SRES_OR[dout][8]
    SLICE_X44Y112        FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][8]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     1.411 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162     2.573    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324    -4.751 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639    -3.112    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -3.021 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.495    -1.526    RLINK/CORE/RL/CLKFX
    SLICE_X44Y112        FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][8]/C

Slack:                    inf
  Source:                 UARB/UA/UA/DATA[8]
                            (internal pin)
  Destination:            RBDTST/MON/R_REGS_reg[rbdata][8]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.461ns  (logic 0.620ns (11.353%)  route 4.841ns (88.647%))
  Logic Levels:           5  (LUT4=1 LUT5=2 LUT6=2)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    USR_ACCESS_X0Y0      USR_ACCESSE2                 0.000     0.000 r  UARB/UA/UA/DATA[8]
                         net (fo=1, routed)           2.151     2.151    UARB/UA/DATA[8]
    SLICE_X28Y101        LUT5 (Prop_lut5_I2_O)        0.124     2.275 r  UARB/UA/R_BREGS[rbdout][8]_i_17/O
                         net (fo=1, routed)           1.072     3.347    RBDTST/BRAM/BRAM/R_BREGS[rbdout][8]_i_4
    SLICE_X28Y112        LUT6 (Prop_lut6_I0_O)        0.124     3.471 r  RBDTST/BRAM/BRAM/R_BREGS[rbdout][8]_i_10/O
                         net (fo=1, routed)           0.492     3.963    RBDTST/EMON/BRAM/R_BREGS[rbdout][8]_i_2_1
    SLICE_X29Y112        LUT5 (Prop_lut5_I4_O)        0.124     4.087 r  RBDTST/EMON/BRAM/R_BREGS[rbdout][8]_i_4/O
                         net (fo=1, routed)           0.766     4.854    RLINK/CORE/RL/R_BREGS_reg[rbdout][8]_0
    SLICE_X41Y112        LUT6 (Prop_lut6_I3_O)        0.124     4.978 r  RLINK/CORE/RL/R_BREGS[rbdout][8]_i_2/O
                         net (fo=2, routed)           0.360     5.337    RLINK/CORE/RL/RB_SRES[dout][8]
    SLICE_X40Y112        LUT4 (Prop_lut4_I3_O)        0.124     5.461 r  RLINK/CORE/RL/R_REGS[rbdata][8]_i_1/O
                         net (fo=1, routed)           0.000     5.461    RBDTST/MON/N_REGS[rbdata][8]
    SLICE_X40Y112        FDRE                                         r  RBDTST/MON/R_REGS_reg[rbdata][8]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     1.411 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162     2.573    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324    -4.751 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639    -3.112    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -3.021 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.498    -1.523    RBDTST/MON/CLKFX
    SLICE_X40Y112        FDRE                                         r  RBDTST/MON/R_REGS_reg[rbdata][8]/C

Slack:                    inf
  Source:                 UARB/UA/UA/DATA[6]
                            (internal pin)
  Destination:            RLINK/CORE/RL/R_BREGS_reg[rbdout][6]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.441ns  (logic 0.620ns (11.396%)  route 4.821ns (88.604%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    USR_ACCESS_X0Y0      USR_ACCESSE2                 0.000     0.000 r  UARB/UA/UA/DATA[6]
                         net (fo=1, routed)           2.457     2.457    UARB/UA/DATA[6]
    SLICE_X28Y113        LUT6 (Prop_lut6_I2_O)        0.124     2.581 r  UARB/UA/R_BREGS[rbdout][6]_i_18/O
                         net (fo=1, routed)           0.823     3.404    RBDTST/BRAM/BRAM/R_BREGS[rbdout][6]_i_5
    SLICE_X15Y116        LUT5 (Prop_lut5_I4_O)        0.124     3.528 r  RBDTST/BRAM/BRAM/R_BREGS[rbdout][6]_i_12/O
                         net (fo=1, routed)           0.460     3.988    RBDTST/EMON/BRAM/R_BREGS[rbdout][6]_i_2_0
    SLICE_X32Y116        LUT6 (Prop_lut6_I3_O)        0.124     4.112 r  RBDTST/EMON/BRAM/R_BREGS[rbdout][6]_i_5/O
                         net (fo=1, routed)           0.579     4.691    RBDTST/TEST/R_BREGS_reg[rbdout][6]_1
    SLICE_X40Y116        LUT6 (Prop_lut6_I4_O)        0.124     4.815 r  RBDTST/TEST/R_BREGS[rbdout][6]_i_2/O
                         net (fo=2, routed)           0.501     5.317    RLINK/CORE/RL/SEL__0/R_BREGS_reg[rbdout][6][1]
    SLICE_X45Y116        LUT6 (Prop_lut6_I0_O)        0.124     5.441 r  RLINK/CORE/RL/SEL__0/R_BREGS[rbdout][6]_i_1/O
                         net (fo=1, routed)           0.000     5.441    RLINK/CORE/RL/RB_SRES_OR[dout][6]
    SLICE_X45Y116        FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][6]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     1.411 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162     2.573    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324    -4.751 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639    -3.112    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -3.021 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.492    -1.529    RLINK/CORE/RL/CLKFX
    SLICE_X45Y116        FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][6]/C

Slack:                    inf
  Source:                 UARB/UA/UA/DATA[6]
                            (internal pin)
  Destination:            RBDTST/MON/R_REGS_reg[rbdata][6]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.385ns  (logic 0.620ns (11.514%)  route 4.765ns (88.486%))
  Logic Levels:           5  (LUT4=1 LUT5=1 LUT6=3)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    USR_ACCESS_X0Y0      USR_ACCESSE2                 0.000     0.000 r  UARB/UA/UA/DATA[6]
                         net (fo=1, routed)           2.457     2.457    UARB/UA/DATA[6]
    SLICE_X28Y113        LUT6 (Prop_lut6_I2_O)        0.124     2.581 r  UARB/UA/R_BREGS[rbdout][6]_i_18/O
                         net (fo=1, routed)           0.823     3.404    RBDTST/BRAM/BRAM/R_BREGS[rbdout][6]_i_5
    SLICE_X15Y116        LUT5 (Prop_lut5_I4_O)        0.124     3.528 r  RBDTST/BRAM/BRAM/R_BREGS[rbdout][6]_i_12/O
                         net (fo=1, routed)           0.460     3.988    RBDTST/EMON/BRAM/R_BREGS[rbdout][6]_i_2_0
    SLICE_X32Y116        LUT6 (Prop_lut6_I3_O)        0.124     4.112 r  RBDTST/EMON/BRAM/R_BREGS[rbdout][6]_i_5/O
                         net (fo=1, routed)           0.579     4.691    RBDTST/TEST/R_BREGS_reg[rbdout][6]_1
    SLICE_X40Y116        LUT6 (Prop_lut6_I4_O)        0.124     4.815 r  RBDTST/TEST/R_BREGS[rbdout][6]_i_2/O
                         net (fo=2, routed)           0.446     5.261    RLINK/CORE/RL/R_BREGS_reg[rbdout][6]_0[1]
    SLICE_X39Y115        LUT4 (Prop_lut4_I3_O)        0.124     5.385 r  RLINK/CORE/RL/R_REGS[rbdata][6]_i_1/O
                         net (fo=1, routed)           0.000     5.385    RBDTST/MON/N_REGS[rbdata][6]
    SLICE_X39Y115        FDRE                                         r  RBDTST/MON/R_REGS_reg[rbdata][6]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     1.411 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162     2.573    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324    -4.751 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639    -3.112    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -3.021 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.496    -1.525    RBDTST/MON/CLKFX
    SLICE_X39Y115        FDRE                                         r  RBDTST/MON/R_REGS_reg[rbdata][6]/C

Slack:                    inf
  Source:                 UARB/UA/UA/DATA[3]
                            (internal pin)
  Destination:            RBDTST/MON/R_REGS_reg[rbdata][3]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.333ns  (logic 0.620ns (11.626%)  route 4.713ns (88.374%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    USR_ACCESS_X0Y0      USR_ACCESSE2                 0.000     0.000 r  UARB/UA/UA/DATA[3]
                         net (fo=1, routed)           2.738     2.738    UARB/UA/DATA[3]
    SLICE_X28Y109        LUT6 (Prop_lut6_I2_O)        0.124     2.862 r  UARB/UA/R_BREGS[rbdout][3]_i_17/O
                         net (fo=1, routed)           0.500     3.362    RBDTST/BRAM/BRAM/R_BREGS[rbdout][3]_i_5_0
    SLICE_X28Y116        LUT6 (Prop_lut6_I1_O)        0.124     3.486 r  RBDTST/BRAM/BRAM/R_BREGS[rbdout][3]_i_10/O
                         net (fo=1, routed)           0.433     3.919    SMRB.I0/SMRB/R_BREGS[rbdout][3]_i_2
    SLICE_X28Y116        LUT5 (Prop_lut5_I0_O)        0.124     4.043 r  SMRB.I0/SMRB/R_BREGS[rbdout][3]_i_5/O
                         net (fo=2, routed)           0.612     4.655    RLINK/CORE/RL/R_REGS_reg[rbdata][3]_2
    SLICE_X30Y114        LUT6 (Prop_lut6_I5_O)        0.124     4.779 r  RLINK/CORE/RL/R_REGS[rbdata][3]_i_2/O
                         net (fo=1, routed)           0.430     5.209    RLINK/CORE/RL/R_REGS[rbdata][3]_i_2_n_0
    SLICE_X37Y114        LUT6 (Prop_lut6_I4_O)        0.124     5.333 r  RLINK/CORE/RL/R_REGS[rbdata][3]_i_1/O
                         net (fo=1, routed)           0.000     5.333    RBDTST/MON/N_REGS[rbdata][3]
    SLICE_X37Y114        FDRE                                         r  RBDTST/MON/R_REGS_reg[rbdata][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     1.411 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162     2.573    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324    -4.751 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639    -3.112    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -3.021 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.498    -1.523    RBDTST/MON/CLKFX
    SLICE_X37Y114        FDRE                                         r  RBDTST/MON/R_REGS_reg[rbdata][3]/C

Slack:                    inf
  Source:                 UARB/UA/UA/DATA[31]
                            (internal pin)
  Destination:            RLINK/CORE/RL/R_BREGS_reg[rbdout][15]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.274ns  (logic 0.496ns (9.405%)  route 4.778ns (90.595%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    USR_ACCESS_X0Y0      USR_ACCESSE2                 0.000     0.000 r  UARB/UA/UA/DATA[31]
                         net (fo=1, routed)           2.177     2.177    UARB/UA/DATA[31]
    SLICE_X28Y101        LUT5 (Prop_lut5_I0_O)        0.124     2.301 r  UARB/UA/R_BREGS[rbdout][15]_i_13/O
                         net (fo=1, routed)           1.239     3.541    SMRB.I0/SMRB/R_BREGS[rbdout][15]_i_3_0
    SLICE_X29Y113        LUT6 (Prop_lut6_I4_O)        0.124     3.665 r  SMRB.I0/SMRB/R_BREGS[rbdout][15]_i_9/O
                         net (fo=1, routed)           0.449     4.114    RLINK/CORE/RL/R_BREGS_reg[rbdout][15]_2
    SLICE_X31Y113        LUT5 (Prop_lut5_I2_O)        0.124     4.238 r  RLINK/CORE/RL/R_BREGS[rbdout][15]_i_3/O
                         net (fo=2, routed)           0.912     5.150    RLINK/CORE/RL/SEL__0/R_BREGS_reg[rbdout][15]_0
    SLICE_X43Y116        LUT6 (Prop_lut6_I2_O)        0.124     5.274 r  RLINK/CORE/RL/SEL__0/R_BREGS[rbdout][15]_i_1/O
                         net (fo=1, routed)           0.000     5.274    RLINK/CORE/RL/RB_SRES_OR[dout][15]
    SLICE_X43Y116        FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][15]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     1.411 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162     2.573    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324    -4.751 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639    -3.112    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -3.021 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.492    -1.529    RLINK/CORE/RL/CLKFX
    SLICE_X43Y116        FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][15]/C

Slack:                    inf
  Source:                 UARB/UA/UA/DATA[31]
                            (internal pin)
  Destination:            RBDTST/MON/R_REGS_reg[rbdata][15]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.260ns  (logic 0.496ns (9.429%)  route 4.764ns (90.571%))
  Logic Levels:           4  (LUT5=2 LUT6=2)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    USR_ACCESS_X0Y0      USR_ACCESSE2                 0.000     0.000 r  UARB/UA/UA/DATA[31]
                         net (fo=1, routed)           2.177     2.177    UARB/UA/DATA[31]
    SLICE_X28Y101        LUT5 (Prop_lut5_I0_O)        0.124     2.301 r  UARB/UA/R_BREGS[rbdout][15]_i_13/O
                         net (fo=1, routed)           1.239     3.541    SMRB.I0/SMRB/R_BREGS[rbdout][15]_i_3_0
    SLICE_X29Y113        LUT6 (Prop_lut6_I4_O)        0.124     3.665 r  SMRB.I0/SMRB/R_BREGS[rbdout][15]_i_9/O
                         net (fo=1, routed)           0.449     4.114    RLINK/CORE/RL/R_BREGS_reg[rbdout][15]_2
    SLICE_X31Y113        LUT5 (Prop_lut5_I2_O)        0.124     4.238 r  RLINK/CORE/RL/R_BREGS[rbdout][15]_i_3/O
                         net (fo=2, routed)           0.899     5.136    RLINK/CORE/RL/R_BREGS[rbdout][15]_i_3_n_0
    SLICE_X41Y117        LUT6 (Prop_lut6_I4_O)        0.124     5.260 r  RLINK/CORE/RL/R_REGS[rbdata][15]_i_2/O
                         net (fo=1, routed)           0.000     5.260    RBDTST/MON/N_REGS[rbdata][15]
    SLICE_X41Y117        FDRE                                         r  RBDTST/MON/R_REGS_reg[rbdata][15]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     1.411 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162     2.573    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324    -4.751 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639    -3.112    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -3.021 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.494    -1.527    RBDTST/MON/CLKFX
    SLICE_X41Y117        FDRE                                         r  RBDTST/MON/R_REGS_reg[rbdata][15]/C

Slack:                    inf
  Source:                 UARB/UA/UA/DATA[18]
                            (internal pin)
  Destination:            RBDTST/MON/R_REGS_reg[rbdata][2]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Setup (Max at Slow Process Corner)
  Data Path Delay:        5.153ns  (logic 0.620ns (12.032%)  route 4.533ns (87.968%))
  Logic Levels:           5  (LUT5=1 LUT6=4)
  Clock Uncertainty:      0.148ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.087ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    USR_ACCESS_X0Y0      USR_ACCESSE2                 0.000     0.000 r  UARB/UA/UA/DATA[18]
                         net (fo=1, routed)           2.406     2.406    UARB/UA/DATA[18]
    SLICE_X28Y111        LUT6 (Prop_lut6_I4_O)        0.124     2.530 r  UARB/UA/R_BREGS[rbdout][2]_i_21/O
                         net (fo=1, routed)           0.496     3.026    RBDTST/BRAM/BRAM/R_BREGS[rbdout][2]_i_10_0
    SLICE_X28Y116        LUT6 (Prop_lut6_I1_O)        0.124     3.150 r  RBDTST/BRAM/BRAM/R_BREGS[rbdout][2]_i_18/O
                         net (fo=1, routed)           0.416     3.566    SMRB.I0/SMRB/R_BREGS[rbdout][2]_i_3_0
    SLICE_X28Y117        LUT5 (Prop_lut5_I0_O)        0.124     3.690 r  SMRB.I0/SMRB/R_BREGS[rbdout][2]_i_10/O
                         net (fo=1, routed)           0.695     4.385    SMRB.I0/SMRB/R_BREGS[rbdout][2]_i_10_n_0
    SLICE_X29Y114        LUT6 (Prop_lut6_I5_O)        0.124     4.509 r  SMRB.I0/SMRB/R_BREGS[rbdout][2]_i_3/O
                         net (fo=2, routed)           0.520     5.029    RLINK/CORE/RL/R_BREGS_reg[rbdout][2]_1
    SLICE_X38Y113        LUT6 (Prop_lut6_I3_O)        0.124     5.153 r  RLINK/CORE/RL/R_REGS[rbdata][2]_i_1/O
                         net (fo=1, routed)           0.000     5.153    RBDTST/MON/N_REGS[rbdata][2]
    SLICE_X38Y113        FDRE                                         r  RBDTST/MON/R_REGS_reg[rbdata][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411     1.411 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162     2.573    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.324    -4.751 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.639    -3.112    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091    -3.021 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        1.497    -1.524    RBDTST/MON/CLKFX
    SLICE_X38Y113        FDRE                                         r  RBDTST/MON/R_REGS_reg[rbdata][2]/C





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 I_SWI[9]
                            (input port)
  Destination:            HIO/HIO/HIO/IOB_SWI/R_DI_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.196ns  (logic 0.196ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Clock Path Skew:        -0.798ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.798ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    U8                                                0.000     0.000 r  I_SWI[9] (IN)
                         net (fo=0)                   0.000     0.000    I_SWI[9]
    U8                   IBUF (Prop_ibuf_I_O)         0.196     0.196 r  I_SWI_IBUF[9]_inst/O
                         net (fo=1, routed)           0.000     0.196    HIO/HIO/HIO/IOB_SWI/R_DI_reg[15]_0[9]
    ILOGIC_X1Y50         FDRE                                         r  HIO/HIO/HIO/IOB_SWI/R_DI_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.875    -0.798    HIO/HIO/HIO/IOB_SWI/CLKFX
    ILOGIC_X1Y50         FDRE                                         r  HIO/HIO/HIO/IOB_SWI/R_DI_reg[9]/C

Slack:                    inf
  Source:                 I_SWI[8]
                            (input port)
  Destination:            HIO/HIO/HIO/IOB_SWI/R_DI_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.211ns  (logic 0.211ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Clock Path Skew:        -0.798ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.798ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    T8                                                0.000     0.000 r  I_SWI[8] (IN)
                         net (fo=0)                   0.000     0.000    I_SWI[8]
    T8                   IBUF (Prop_ibuf_I_O)         0.211     0.211 r  I_SWI_IBUF[8]_inst/O
                         net (fo=1, routed)           0.000     0.211    HIO/HIO/HIO/IOB_SWI/R_DI_reg[15]_0[8]
    ILOGIC_X1Y51         FDRE                                         r  HIO/HIO/HIO/IOB_SWI/R_DI_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.875    -0.798    HIO/HIO/HIO/IOB_SWI/CLKFX
    ILOGIC_X1Y51         FDRE                                         r  HIO/HIO/HIO/IOB_SWI/R_DI_reg[8]/C

Slack:                    inf
  Source:                 I_CTS_N
                            (input port)
  Destination:            IOB_RS232/IOB_CTS/IOB/R_DI_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.233ns  (logic 0.233ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Clock Path Skew:        -0.806ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.806ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    E5                                                0.000     0.000 r  I_CTS_N (IN)
                         net (fo=0)                   0.000     0.000    I_CTS_N
    E5                   IBUF (Prop_ibuf_I_O)         0.233     0.233 r  I_CTS_N_IBUF_inst/O
                         net (fo=1, routed)           0.000     0.233    IOB_RS232/IOB_CTS/IOB/I_CTS_N_IBUF
    ILOGIC_X1Y139        FDRE                                         r  IOB_RS232/IOB_CTS/IOB/R_DI_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.867    -0.806    IOB_RS232/IOB_CTS/IOB/CLKFX
    ILOGIC_X1Y139        FDRE                                         r  IOB_RS232/IOB_CTS/IOB/R_DI_reg[0]/C

Slack:                    inf
  Source:                 I_SWI[12]
                            (input port)
  Destination:            HIO/HIO/HIO/IOB_SWI/R_DI_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.235ns  (logic 0.235ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Clock Path Skew:        -0.804ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.804ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    H6                                                0.000     0.000 r  I_SWI[12] (IN)
                         net (fo=0)                   0.000     0.000    I_SWI[12]
    H6                   IBUF (Prop_ibuf_I_O)         0.235     0.235 r  I_SWI_IBUF[12]_inst/O
                         net (fo=1, routed)           0.000     0.235    HIO/HIO/HIO/IOB_SWI/R_DI_reg[15]_0[12]
    ILOGIC_X1Y102        FDRE                                         r  HIO/HIO/HIO/IOB_SWI/R_DI_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.869    -0.804    HIO/HIO/HIO/IOB_SWI/CLKFX
    ILOGIC_X1Y102        FDRE                                         r  HIO/HIO/HIO/IOB_SWI/R_DI_reg[12]/C

Slack:                    inf
  Source:                 I_BTN[1]
                            (input port)
  Destination:            HIO/HIO/HIO/IOB_BTN/R_DI_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.235ns  (logic 0.235ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Clock Path Skew:        -0.810ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.810ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    M17                                               0.000     0.000 r  I_BTN[1] (IN)
                         net (fo=0)                   0.000     0.000    I_BTN[1]
    M17                  IBUF (Prop_ibuf_I_O)         0.235     0.235 r  I_BTN_IBUF[1]_inst/O
                         net (fo=1, routed)           0.000     0.235    HIO/HIO/HIO/IOB_BTN/R_DI_reg[4]_0[1]
    ILOGIC_X0Y79         FDRE                                         r  HIO/HIO/HIO/IOB_BTN/R_DI_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.863    -0.810    HIO/HIO/HIO/IOB_BTN/CLKFX
    ILOGIC_X0Y79         FDRE                                         r  HIO/HIO/HIO/IOB_BTN/R_DI_reg[1]/C

Slack:                    inf
  Source:                 I_BTN[4]
                            (input port)
  Destination:            HIO/HIO/HIO/IOB_BTN/R_DI_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.244ns  (logic 0.244ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Clock Path Skew:        -0.808ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.808ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    N17                                               0.000     0.000 r  I_BTN[4] (IN)
                         net (fo=0)                   0.000     0.000    I_BTN[4]
    N17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_BTN_IBUF[4]_inst/O
                         net (fo=1, routed)           0.000     0.244    HIO/HIO/HIO/IOB_BTN/R_DI_reg[4]_0[4]
    ILOGIC_X0Y82         FDRE                                         r  HIO/HIO/HIO/IOB_BTN/R_DI_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.865    -0.808    HIO/HIO/HIO/IOB_BTN/CLKFX
    ILOGIC_X0Y82         FDRE                                         r  HIO/HIO/HIO/IOB_BTN/R_DI_reg[4]/C

Slack:                    inf
  Source:                 I_SWI[3]
                            (input port)
  Destination:            HIO/HIO/HIO/IOB_SWI/R_DI_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.245ns  (logic 0.245ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Clock Path Skew:        -0.813ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.813ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    R15                                               0.000     0.000 r  I_SWI[3] (IN)
                         net (fo=0)                   0.000     0.000    I_SWI[3]
    R15                  IBUF (Prop_ibuf_I_O)         0.245     0.245 r  I_SWI_IBUF[3]_inst/O
                         net (fo=1, routed)           0.000     0.245    HIO/HIO/HIO/IOB_SWI/R_DI_reg[15]_0[3]
    ILOGIC_X0Y73         FDRE                                         r  HIO/HIO/HIO/IOB_SWI/R_DI_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.860    -0.813    HIO/HIO/HIO/IOB_SWI/CLKFX
    ILOGIC_X0Y73         FDRE                                         r  HIO/HIO/HIO/IOB_SWI/R_DI_reg[3]/C

Slack:                    inf
  Source:                 I_SWI[0]
                            (input port)
  Destination:            HIO/HIO/HIO/IOB_SWI/R_DI_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.245ns  (logic 0.245ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Clock Path Skew:        -0.808ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.808ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    J15                                               0.000     0.000 r  I_SWI[0] (IN)
                         net (fo=0)                   0.000     0.000    I_SWI[0]
    J15                  IBUF (Prop_ibuf_I_O)         0.245     0.245 r  I_SWI_IBUF[0]_inst/O
                         net (fo=1, routed)           0.000     0.245    HIO/HIO/HIO/IOB_SWI/R_DI_reg[15]_0[0]
    ILOGIC_X0Y101        FDRE                                         r  HIO/HIO/HIO/IOB_SWI/R_DI_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.865    -0.808    HIO/HIO/HIO/IOB_SWI/CLKFX
    ILOGIC_X0Y101        FDRE                                         r  HIO/HIO/HIO/IOB_SWI/R_DI_reg[0]/C

Slack:                    inf
  Source:                 I_SWI[1]
                            (input port)
  Destination:            HIO/HIO/HIO/IOB_SWI/R_DI_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.247ns  (logic 0.247ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Clock Path Skew:        -0.804ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.804ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    L16                                               0.000     0.000 r  I_SWI[1] (IN)
                         net (fo=0)                   0.000     0.000    I_SWI[1]
    L16                  IBUF (Prop_ibuf_I_O)         0.247     0.247 r  I_SWI_IBUF[1]_inst/O
                         net (fo=1, routed)           0.000     0.247    HIO/HIO/HIO/IOB_SWI/R_DI_reg[15]_0[1]
    ILOGIC_X0Y93         FDRE                                         r  HIO/HIO/HIO/IOB_SWI/R_DI_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.869    -0.804    HIO/HIO/HIO/IOB_SWI/CLKFX
    ILOGIC_X0Y93         FDRE                                         r  HIO/HIO/HIO/IOB_SWI/R_DI_reg[1]/C

Slack:                    inf
  Source:                 I_BTN[2]
                            (input port)
  Destination:            HIO/HIO/HIO/IOB_BTN/R_DI_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             (none)
  Path Type:              Hold (Min at Fast Process Corner)
  Data Path Delay:        0.248ns  (logic 0.248ns (100.000%)  route 0.000ns (0.000%))
  Logic Levels:           1  (IBUF=1)
  Clock Path Skew:        -0.808ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.808ns
    Source Clock Delay      (SCD):    0.000ns
    Clock Pessimism Removal (CPR):    -0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    P18                                               0.000     0.000 r  I_BTN[2] (IN)
                         net (fo=0)                   0.000     0.000    I_BTN[2]
    P18                  IBUF (Prop_ibuf_I_O)         0.248     0.248 r  I_BTN_IBUF[2]_inst/O
                         net (fo=1, routed)           0.000     0.248    HIO/HIO/HIO/IOB_BTN/R_DI_reg[4]_0[2]
    ILOGIC_X0Y81         FDRE                                         r  HIO/HIO/HIO/IOB_BTN/R_DI_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.CLKOUT0 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.163    -2.245 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.544    -1.702    GEN_CLKSYS/USEMMCM.CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1306, routed)        0.865    -0.808    HIO/HIO/HIO/IOB_BTN/CLKFX
    ILOGIC_X0Y81         FDRE                                         r  HIO/HIO/HIO/IOB_BTN/R_DI_reg[2]/C





