
*** Running vivado
    with args -log sys_tst_rlink_n4d.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source sys_tst_rlink_n4d.tcl


****** Vivado v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source sys_tst_rlink_n4d.tcl -notrace
Command: synth_design -top sys_tst_rlink_n4d -part xc7a100tcsg324-1 -directive PerformanceOptimized -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5 -assert
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 647528
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Starting RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2608.312 ; gain = 0.000 ; free physical = 3449 ; free virtual = 22005
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'sys_tst_rlink_n4d' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd:107]
	Parameter VCO_DIVIDE bound to: 1 - type: integer 
	Parameter VCO_MULTIPLY bound to: 12 - type: integer 
	Parameter OUT_DIVIDE bound to: 10 - type: integer 
	Parameter CLKIN_PERIOD bound to: 10.000000 - type: double 
	Parameter CLKIN_JITTER bound to: 0.010000 - type: double 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
	Parameter GEN_TYPE bound to: MMCM - type: string 
INFO: [Synth 8-3491] module 's7_cmt_sfs' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:28' bound to instance 'GEN_CLKSYS' of component 's7_cmt_sfs' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd:162]
INFO: [Synth 8-638] synthesizing module 's7_cmt_sfs' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:45]
	Parameter VCO_DIVIDE bound to: 1 - type: integer 
	Parameter VCO_MULTIPLY bound to: 12 - type: integer 
	Parameter OUT_DIVIDE bound to: 10 - type: integer 
	Parameter CLKIN_PERIOD bound to: 10.000000 - type: double 
	Parameter CLKIN_JITTER bound to: 0.010000 - type: double 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
	Parameter GEN_TYPE bound to: MMCM - type: string 
	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
	Parameter CLKFBOUT_MULT_F bound to: 12.000000 - type: double 
	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double 
	Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double 
	Parameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: double 
	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double 
	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double 
	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
	Parameter REF_JITTER1 bound to: 0.010000 - type: double 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
INFO: [Synth 8-113] binding component instance 'MMCM' to cell 'MMCME2_BASE' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:143]
INFO: [Synth 8-113] binding component instance 'BUFG_CLKFB' to cell 'BUFG' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:175]
INFO: [Synth 8-113] binding component instance 'BUFG_CLKOUT' to cell 'BUFG' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:181]
INFO: [Synth 8-256] done synthesizing module 's7_cmt_sfs' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:45]
	Parameter CDUWIDTH bound to: 7 - type: integer 
	Parameter USECDIV bound to: 120 - type: integer 
	Parameter MSECDIV bound to: 1000 - type: integer 
INFO: [Synth 8-3491] module 'clkdivce' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/genlib/clkdivce.vhd:30' bound to instance 'CLKDIV' of component 'clkdivce' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd:177]
INFO: [Synth 8-638] synthesizing module 'clkdivce' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/genlib/clkdivce.vhd:43]
	Parameter CDUWIDTH bound to: 7 - type: integer 
	Parameter USECDIV bound to: 120 - type: integer 
	Parameter MSECDIV bound to: 1000 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'clkdivce' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/genlib/clkdivce.vhd:43]
INFO: [Synth 8-3491] module 'bp_rs232_4line_iob' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd:32' bound to instance 'IOB_RS232' of component 'bp_rs232_4line_iob' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd:188]
INFO: [Synth 8-638] synthesizing module 'bp_rs232_4line_iob' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd:46]
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-3491] module 'iob_reg_i' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i.vhd:25' bound to instance 'IOB_RXD' of component 'iob_reg_i' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd:49]
INFO: [Synth 8-638] synthesizing module 'iob_reg_i' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i.vhd:37]
	Parameter INIT bound to: 1'b1 
	Parameter DWIDTH bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-3491] module 'iob_reg_i_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:25' bound to instance 'IOB' of component 'iob_reg_i_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i.vhd:41]
INFO: [Synth 8-638] synthesizing module 'iob_reg_i_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:38]
	Parameter DWIDTH bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-256] done synthesizing module 'iob_reg_i_gen' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:38]
INFO: [Synth 8-256] done synthesizing module 'iob_reg_i' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i.vhd:37]
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-3491] module 'iob_reg_o' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o.vhd:25' bound to instance 'IOB_TXD' of component 'iob_reg_o' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd:53]
INFO: [Synth 8-638] synthesizing module 'iob_reg_o' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o.vhd:37]
	Parameter INIT bound to: 1'b1 
	Parameter DWIDTH bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-3491] module 'iob_reg_o_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:25' bound to instance 'IOB' of component 'iob_reg_o_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o.vhd:41]
INFO: [Synth 8-638] synthesizing module 'iob_reg_o_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:38]
	Parameter DWIDTH bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-256] done synthesizing module 'iob_reg_o_gen' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:38]
INFO: [Synth 8-256] done synthesizing module 'iob_reg_o' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o.vhd:37]
INFO: [Synth 8-3491] module 'iob_reg_i' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i.vhd:25' bound to instance 'IOB_CTS' of component 'iob_reg_i' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd:57]
INFO: [Synth 8-638] synthesizing module 'iob_reg_i__parameterized1' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i.vhd:37]
	Parameter INIT bound to: 1'b0 
	Parameter DWIDTH bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'iob_reg_i_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:25' bound to instance 'IOB' of component 'iob_reg_i_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i.vhd:41]
INFO: [Synth 8-638] synthesizing module 'iob_reg_i_gen__parameterized1' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:38]
	Parameter DWIDTH bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'iob_reg_i_gen__parameterized1' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:38]
INFO: [Synth 8-256] done synthesizing module 'iob_reg_i__parameterized1' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i.vhd:37]
INFO: [Synth 8-3491] module 'iob_reg_o' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o.vhd:25' bound to instance 'IOB_RTS' of component 'iob_reg_o' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd:60]
INFO: [Synth 8-638] synthesizing module 'iob_reg_o__parameterized1' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o.vhd:37]
	Parameter INIT bound to: 1'b0 
	Parameter DWIDTH bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'iob_reg_o_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:25' bound to instance 'IOB' of component 'iob_reg_o_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o.vhd:41]
INFO: [Synth 8-638] synthesizing module 'iob_reg_o_gen__parameterized1' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:38]
	Parameter DWIDTH bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'iob_reg_o_gen__parameterized1' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:38]
INFO: [Synth 8-256] done synthesizing module 'iob_reg_o__parameterized1' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o.vhd:37]
INFO: [Synth 8-256] done synthesizing module 'bp_rs232_4line_iob' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd:46]
	Parameter SWIDTH bound to: 16 - type: integer 
	Parameter BWIDTH bound to: 5 - type: integer 
	Parameter LWIDTH bound to: 16 - type: integer 
	Parameter DCWIDTH bound to: 3 - type: integer 
	Parameter DEBOUNCE bound to: 1 - type: bool 
	Parameter RB_ADDR bound to: 16'b1111111011110000 
INFO: [Synth 8-3491] module 'sn_humanio_rbus' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/sn_humanio_rbus.vhd:85' bound to instance 'HIO' of component 'sn_humanio_rbus' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd:201]
INFO: [Synth 8-638] synthesizing module 'sn_humanio_rbus' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/sn_humanio_rbus.vhd:112]
	Parameter SWIDTH bound to: 16 - type: integer 
	Parameter BWIDTH bound to: 5 - type: integer 
	Parameter LWIDTH bound to: 16 - type: integer 
	Parameter DCWIDTH bound to: 3 - type: integer 
	Parameter DEBOUNCE bound to: 1 - type: bool 
	Parameter RB_ADDR bound to: 16'b1111111011110000 
	Parameter SWIDTH bound to: 16 - type: integer 
	Parameter BWIDTH bound to: 5 - type: integer 
	Parameter LWIDTH bound to: 16 - type: integer 
	Parameter DCWIDTH bound to: 3 - type: integer 
	Parameter DEBOUNCE bound to: 1 - type: bool 
INFO: [Synth 8-3491] module 'sn_humanio' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/sn_humanio.vhd:48' bound to instance 'HIO' of component 'sn_humanio' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/sn_humanio_rbus.vhd:205]
INFO: [Synth 8-638] synthesizing module 'sn_humanio' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/sn_humanio.vhd:72]
	Parameter SWIDTH bound to: 16 - type: integer 
	Parameter BWIDTH bound to: 5 - type: integer 
	Parameter LWIDTH bound to: 16 - type: integer 
	Parameter DCWIDTH bound to: 3 - type: integer 
	Parameter DEBOUNCE bound to: 1 - type: bool 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'iob_reg_o_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:25' bound to instance 'IOB_ANO_N' of component 'iob_reg_o_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/sn_humanio.vhd:79]
INFO: [Synth 8-638] synthesizing module 'iob_reg_o_gen__parameterized3' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:38]
	Parameter DWIDTH bound to: 8 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'iob_reg_o_gen__parameterized3' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:38]
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'iob_reg_o_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:25' bound to instance 'IOB_SEG_N' of component 'iob_reg_o_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/sn_humanio.vhd:83]
	Parameter SWIDTH bound to: 16 - type: integer 
	Parameter BWIDTH bound to: 5 - type: integer 
	Parameter LWIDTH bound to: 16 - type: integer 
	Parameter DEBOUNCE bound to: 1 - type: bool 
INFO: [Synth 8-3491] module 'bp_swibtnled' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/bp_swibtnled.vhd:34' bound to instance 'HIO' of component 'bp_swibtnled' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/sn_humanio.vhd:87]
INFO: [Synth 8-638] synthesizing module 'bp_swibtnled' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/bp_swibtnled.vhd:53]
	Parameter SWIDTH bound to: 16 - type: integer 
	Parameter BWIDTH bound to: 5 - type: integer 
	Parameter LWIDTH bound to: 16 - type: integer 
	Parameter DEBOUNCE bound to: 1 - type: bool 
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-3491] module 'iob_reg_i_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:25' bound to instance 'IOB_SWI' of component 'iob_reg_i_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/bp_swibtnled.vhd:60]
INFO: [Synth 8-638] synthesizing module 'iob_reg_i_gen__parameterized3' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:38]
	Parameter DWIDTH bound to: 16 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'iob_reg_i_gen__parameterized3' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:38]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'iob_reg_i_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:25' bound to instance 'IOB_BTN' of component 'iob_reg_i_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/bp_swibtnled.vhd:64]
INFO: [Synth 8-638] synthesizing module 'iob_reg_i_gen__parameterized5' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:38]
	Parameter DWIDTH bound to: 5 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'iob_reg_i_gen__parameterized5' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:38]
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-3491] module 'iob_reg_o_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:25' bound to instance 'IOB_LED' of component 'iob_reg_o_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/bp_swibtnled.vhd:68]
INFO: [Synth 8-638] synthesizing module 'iob_reg_o_gen__parameterized5' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:38]
	Parameter DWIDTH bound to: 16 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'iob_reg_o_gen__parameterized5' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:38]
	Parameter CWIDTH bound to: 2 - type: integer 
	Parameter CEDIV bound to: 3 - type: integer 
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-3491] module 'debounce_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/genlib/debounce_gen.vhd:27' bound to instance 'DEB_SWI' of component 'debounce_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/bp_swibtnled.vhd:74]
INFO: [Synth 8-638] synthesizing module 'debounce_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/genlib/debounce_gen.vhd:42]
	Parameter CWIDTH bound to: 2 - type: integer 
	Parameter CEDIV bound to: 3 - type: integer 
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'debounce_gen' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/genlib/debounce_gen.vhd:42]
	Parameter CWIDTH bound to: 2 - type: integer 
	Parameter CEDIV bound to: 3 - type: integer 
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'debounce_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/genlib/debounce_gen.vhd:27' bound to instance 'DEB_BTN' of component 'debounce_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/bp_swibtnled.vhd:87]
INFO: [Synth 8-638] synthesizing module 'debounce_gen__parameterized1' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/genlib/debounce_gen.vhd:42]
	Parameter CWIDTH bound to: 2 - type: integer 
	Parameter CEDIV bound to: 3 - type: integer 
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'debounce_gen__parameterized1' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/genlib/debounce_gen.vhd:42]
INFO: [Synth 8-256] done synthesizing module 'bp_swibtnled' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/bp_swibtnled.vhd:53]
	Parameter DCWIDTH bound to: 3 - type: integer 
	Parameter CDWIDTH bound to: 7 - type: integer 
INFO: [Synth 8-3491] module 'sn_7segctl' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/sn_7segctl.vhd:40' bound to instance 'DRV' of component 'sn_7segctl' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/sn_humanio.vhd:105]
INFO: [Synth 8-638] synthesizing module 'sn_7segctl' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/sn_7segctl.vhd:53]
	Parameter DCWIDTH bound to: 3 - type: integer 
	Parameter CDWIDTH bound to: 7 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'sn_7segctl' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/sn_7segctl.vhd:53]
INFO: [Synth 8-256] done synthesizing module 'sn_humanio' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/sn_humanio.vhd:72]
INFO: [Synth 8-226] default block is never used [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/sn_humanio_rbus.vhd:280]
INFO: [Synth 8-256] done synthesizing module 'sn_humanio_rbus' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/sn_humanio_rbus.vhd:112]
	Parameter BTOWIDTH bound to: 6 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 32'b00000001000000010000100000000000 
	Parameter IFAWIDTH bound to: 5 - type: integer 
	Parameter OFAWIDTH bound to: 5 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
	Parameter RBMON_AWIDTH bound to: 0 - type: integer 
	Parameter RBMON_RBADDR bound to: 16'b0000000000000000 
INFO: [Synth 8-3491] module 'rlink_sp1c' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_sp1c.vhd:43' bound to instance 'RLINK' of component 'rlink_sp1c' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd:227]
INFO: [Synth 8-638] synthesizing module 'rlink_sp1c' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_sp1c.vhd:79]
	Parameter BTOWIDTH bound to: 6 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 16844800 - type: integer 
	Parameter IFAWIDTH bound to: 5 - type: integer 
	Parameter OFAWIDTH bound to: 5 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RLBMON bound to: -1 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
	Parameter RBMON_AWIDTH bound to: 0 - type: integer 
	Parameter RBMON_RBADDR bound to: 16'b0000000000000000 
	Parameter BTOWIDTH bound to: 6 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 16844800 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RLBMON bound to: -1 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
INFO: [Synth 8-3491] module 'rlink_core8' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core8.vhd:40' bound to instance 'CORE' of component 'rlink_core8' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_sp1c.vhd:94]
INFO: [Synth 8-638] synthesizing module 'rlink_core8' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core8.vhd:69]
	Parameter BTOWIDTH bound to: 6 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 16844800 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RLBMON bound to: -1 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
	Parameter BTOWIDTH bound to: 6 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 16844800 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
INFO: [Synth 8-3491] module 'rlink_core' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core.vhd:156' bound to instance 'RL' of component 'rlink_core' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core8.vhd:83]
INFO: [Synth 8-638] synthesizing module 'rlink_core' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core.vhd:185]
	Parameter BTOWIDTH bound to: 6 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 16844800 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_2swsr_rfirst_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:33' bound to instance 'RTBUF' of component 'ram_2swsr_rfirst_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core.vhd:438]
INFO: [Synth 8-638] synthesizing module 'ram_2swsr_rfirst_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:54]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ram_2swsr_rfirst_gen' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:54]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'fifo_1c_dram' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/fifo_1c_dram.vhd:34' bound to instance 'DOFIFO' of component 'fifo_1c_dram' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core.vhd:457]
INFO: [Synth 8-638] synthesizing module 'fifo_1c_dram' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/fifo_1c_dram.vhd:52]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'fifo_1c_dram_raw' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:29' bound to instance 'FIFO' of component 'fifo_1c_dram_raw' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/fifo_1c_dram.vhd:62]
INFO: [Synth 8-638] synthesizing module 'fifo_1c_dram_raw' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:47]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_1ar_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:41' bound to instance 'RAM' of component 'ram_1swar_1ar_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:70]
INFO: [Synth 8-638] synthesizing module 'ram_1swar_1ar_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:57]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ram_1swar_1ar_gen' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:57]
INFO: [Synth 8-256] done synthesizing module 'fifo_1c_dram_raw' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'fifo_1c_dram' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/fifo_1c_dram.vhd:52]
INFO: [Synth 8-3491] module 'crc16' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/comlib/crc16.vhd:31' bound to instance 'ICRC' of component 'crc16' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core.vhd:473]
INFO: [Synth 8-638] synthesizing module 'crc16' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/comlib/crc16.vhd:44]
	Parameter INIT bound to: 16'b0000000000000000 
INFO: [Synth 8-256] done synthesizing module 'crc16' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/comlib/crc16.vhd:44]
INFO: [Synth 8-3491] module 'crc16' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/comlib/crc16.vhd:31' bound to instance 'OCRC' of component 'crc16' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core.vhd:482]
	Parameter RB_ADDR bound to: 16'b1111111111111100 
	Parameter SAWIDTH bound to: 2 - type: integer 
INFO: [Synth 8-3491] module 'rb_sel' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sel.vhd:29' bound to instance 'SEL' of component 'rb_sel' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core.vhd:491]
INFO: [Synth 8-638] synthesizing module 'rb_sel' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sel.vhd:40]
	Parameter RB_ADDR bound to: 16'b1111111111111100 
	Parameter SAWIDTH bound to: 2 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'rb_sel' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sel.vhd:40]
INFO: [Synth 8-3491] module 'rb_sres_or_2' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sres_or_2.vhd:30' bound to instance 'RB_SRES_OR' of component 'rb_sres_or_2' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core.vhd:501]
INFO: [Synth 8-638] synthesizing module 'rb_sres_or_2' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sres_or_2.vhd:38]
INFO: [Synth 8-256] done synthesizing module 'rb_sres_or_2' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sres_or_2.vhd:38]
INFO: [Synth 8-226] default block is never used [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core.vhd:1393]
INFO: [Synth 8-226] default block is never used [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core.vhd:1614]
INFO: [Synth 8-256] done synthesizing module 'rlink_core' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core.vhd:185]
INFO: [Synth 8-3491] module 'byte2cdata' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/comlib/byte2cdata.vhd:29' bound to instance 'B2CD' of component 'byte2cdata' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core8.vhd:108]
INFO: [Synth 8-638] synthesizing module 'byte2cdata' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/comlib/byte2cdata.vhd:44]
INFO: [Synth 8-256] done synthesizing module 'byte2cdata' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/comlib/byte2cdata.vhd:44]
INFO: [Synth 8-3491] module 'cdata2byte' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/comlib/cdata2byte.vhd:29' bound to instance 'CD2B' of component 'cdata2byte' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core8.vhd:122]
INFO: [Synth 8-638] synthesizing module 'cdata2byte' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/comlib/cdata2byte.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'cdata2byte' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/comlib/cdata2byte.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'rlink_core8' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_core8.vhd:69]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
	Parameter RXFAWIDTH bound to: 5 - type: integer 
	Parameter TXFAWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'serport_1clock' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_1clock.vhd:40' bound to instance 'SERPORT' of component 'serport_1clock' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_sp1c.vhd:121]
INFO: [Synth 8-638] synthesizing module 'serport_1clock' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_1clock.vhd:67]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
	Parameter RXFAWIDTH bound to: 5 - type: integer 
	Parameter TXFAWIDTH bound to: 5 - type: integer 
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
INFO: [Synth 8-3491] module 'serport_uart_rxtx_ab' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_rxtx_ab.vhd:38' bound to instance 'UART' of component 'serport_uart_rxtx_ab' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_1clock.vhd:107]
INFO: [Synth 8-638] synthesizing module 'serport_uart_rxtx_ab' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_rxtx_ab.vhd:62]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
INFO: [Synth 8-3491] module 'serport_uart_autobaud' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:33' bound to instance 'AB' of component 'serport_uart_autobaud' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_rxtx_ab.vhd:71]
INFO: [Synth 8-638] synthesizing module 'serport_uart_autobaud' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:50]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
INFO: [Synth 8-226] default block is never used [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:124]
INFO: [Synth 8-256] done synthesizing module 'serport_uart_autobaud' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:50]
	Parameter CDWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-3491] module 'serport_uart_rxtx' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_rxtx.vhd:29' bound to instance 'RXTX' of component 'serport_uart_rxtx' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_rxtx_ab.vhd:91]
INFO: [Synth 8-638] synthesizing module 'serport_uart_rxtx' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_rxtx.vhd:48]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-3491] module 'serport_uart_rx' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_rx.vhd:46' bound to instance 'RX' of component 'serport_uart_rx' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_rxtx.vhd:52]
INFO: [Synth 8-638] synthesizing module 'serport_uart_rx' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_rx.vhd:62]
	Parameter CDWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'serport_uart_rx' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_rx.vhd:62]
	Parameter CDWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-3491] module 'serport_uart_tx' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_tx.vhd:31' bound to instance 'TX' of component 'serport_uart_tx' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_rxtx.vhd:66]
INFO: [Synth 8-638] synthesizing module 'serport_uart_tx' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_tx.vhd:46]
	Parameter CDWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'serport_uart_tx' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_tx.vhd:46]
INFO: [Synth 8-256] done synthesizing module 'serport_uart_rxtx' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_rxtx.vhd:48]
INFO: [Synth 8-256] done synthesizing module 'serport_uart_rxtx_ab' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_uart_rxtx_ab.vhd:62]
INFO: [Synth 8-3491] module 'serport_xonrx' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_xonrx.vhd:28' bound to instance 'XONRX' of component 'serport_xonrx' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_1clock.vhd:132]
INFO: [Synth 8-638] synthesizing module 'serport_xonrx' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_xonrx.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'serport_xonrx' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_xonrx.vhd:45]
INFO: [Synth 8-3491] module 'serport_xontx' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_xontx.vhd:29' bound to instance 'XONTX' of component 'serport_xontx' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_1clock.vhd:147]
INFO: [Synth 8-638] synthesizing module 'serport_xontx' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_xontx.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'serport_xontx' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_xontx.vhd:47]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'fifo_1c_dram' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/fifo_1c_dram.vhd:34' bound to instance 'RXFIFO' of component 'fifo_1c_dram' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_1clock.vhd:163]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'fifo_1c_dram' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/fifo_1c_dram.vhd:34' bound to instance 'TXFIFO' of component 'fifo_1c_dram' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_1clock.vhd:179]
INFO: [Synth 8-256] done synthesizing module 'serport_1clock' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/serport/serport_1clock.vhd:67]
INFO: [Synth 8-3491] module 'rb_sres_or_2' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sres_or_2.vhd:30' bound to instance 'RB_SRES_OR' of component 'rb_sres_or_2' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_sp1c.vhd:161]
INFO: [Synth 8-256] done synthesizing module 'rlink_sp1c' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rlink/rlink_sp1c.vhd:79]
INFO: [Synth 8-638] synthesizing module 'rbd_tst_rlink' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/rbd_tst_rlink.vhd:60]
	Parameter RB_ADDR bound to: 16'b1111111111100000 
INFO: [Synth 8-3491] module 'rbd_tester' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_tester.vhd:60' bound to instance 'TEST' of component 'rbd_tester' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/rbd_tst_rlink.vhd:86]
INFO: [Synth 8-638] synthesizing module 'rbd_tester' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_tester.vhd:75]
	Parameter RB_ADDR bound to: 16'b1111111111100000 
	Parameter AWIDTH bound to: 4 - type: integer 
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-3491] module 'fifo_simple_dram' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/fifo_simple_dram.vhd:29' bound to instance 'FIFO' of component 'fifo_simple_dram' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_tester.vhd:133]
INFO: [Synth 8-638] synthesizing module 'fifo_simple_dram' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/fifo_simple_dram.vhd:47]
	Parameter AWIDTH bound to: 4 - type: integer 
	Parameter DWIDTH bound to: 16 - type: integer 
	Parameter AWIDTH bound to: 4 - type: integer 
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:37' bound to instance 'RAM' of component 'ram_1swar_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/fifo_simple_dram.vhd:71]
INFO: [Synth 8-638] synthesizing module 'ram_1swar_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:51]
	Parameter AWIDTH bound to: 4 - type: integer 
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ram_1swar_gen' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:51]
INFO: [Synth 8-256] done synthesizing module 'fifo_simple_dram' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/fifo_simple_dram.vhd:47]
INFO: [Synth 8-226] default block is never used [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_tester.vhd:222]
INFO: [Synth 8-226] default block is never used [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_tester.vhd:301]
INFO: [Synth 8-256] done synthesizing module 'rbd_tester' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_tester.vhd:75]
	Parameter RB_ADDR bound to: 16'b1111111000000000 
INFO: [Synth 8-3491] module 'rbd_bram' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_bram.vhd:47' bound to instance 'BRAM' of component 'rbd_bram' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/rbd_tst_rlink.vhd:98]
INFO: [Synth 8-638] synthesizing module 'rbd_bram' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_bram.vhd:60]
	Parameter RB_ADDR bound to: 16'b1111111000000000 
	Parameter AWIDTH bound to: 10 - type: integer 
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:37' bound to instance 'BRAM' of component 'ram_1swsr_wfirst_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_bram.vhd:91]
INFO: [Synth 8-638] synthesizing module 'ram_1swsr_wfirst_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:52]
	Parameter AWIDTH bound to: 10 - type: integer 
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ram_1swsr_wfirst_gen' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:52]
INFO: [Synth 8-226] default block is never used [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_bram.vhd:168]
INFO: [Synth 8-226] default block is never used [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_bram.vhd:193]
INFO: [Synth 8-256] done synthesizing module 'rbd_bram' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_bram.vhd:60]
	Parameter RB_ADDR bound to: 16'b1111111111101000 
	Parameter AWIDTH bound to: 9 - type: integer 
INFO: [Synth 8-3491] module 'rbd_rbmon' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_rbmon.vhd:92' bound to instance 'MON' of component 'rbd_rbmon' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/rbd_tst_rlink.vhd:108]
INFO: [Synth 8-638] synthesizing module 'rbd_rbmon' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_rbmon.vhd:106]
	Parameter RB_ADDR bound to: 16'b1111111111101000 
	Parameter AWIDTH bound to: 9 - type: integer 
	Parameter AWIDTH bound to: 9 - type: integer 
	Parameter DWIDTH bound to: 32 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:37' bound to instance 'BRAM1' of component 'ram_1swsr_wfirst_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_rbmon.vhd:223]
INFO: [Synth 8-638] synthesizing module 'ram_1swsr_wfirst_gen__parameterized1' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:52]
	Parameter AWIDTH bound to: 9 - type: integer 
	Parameter DWIDTH bound to: 32 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ram_1swsr_wfirst_gen__parameterized1' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:52]
	Parameter AWIDTH bound to: 9 - type: integer 
	Parameter DWIDTH bound to: 32 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:37' bound to instance 'BRAM0' of component 'ram_1swsr_wfirst_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_rbmon.vhd:236]
INFO: [Synth 8-226] default block is never used [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_rbmon.vhd:397]
INFO: [Synth 8-256] done synthesizing module 'rbd_rbmon' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_rbmon.vhd:106]
	Parameter RB_ADDR bound to: 16'b1111111111010000 
	Parameter RDIV bound to: 8'b00000000 
INFO: [Synth 8-3491] module 'rbd_eyemon' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_eyemon.vhd:60' bound to instance 'EMON' of component 'rbd_eyemon' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/rbd_tst_rlink.vhd:120]
INFO: [Synth 8-638] synthesizing module 'rbd_eyemon' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_eyemon.vhd:75]
	Parameter RB_ADDR bound to: 16'b1111111111010000 
	Parameter RDIV bound to: 8'b00000000 
	Parameter AWIDTH bound to: 9 - type: integer 
	Parameter DWIDTH bound to: 32 - type: integer 
INFO: [Synth 8-3491] module 'ram_2swsr_wfirst_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd:32' bound to instance 'BRAM' of component 'ram_2swsr_wfirst_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_eyemon.vhd:137]
INFO: [Synth 8-638] synthesizing module 'ram_2swsr_wfirst_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd:53]
	Parameter AWIDTH bound to: 9 - type: integer 
	Parameter DWIDTH bound to: 32 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ram_2swsr_wfirst_gen' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd:53]
INFO: [Synth 8-226] default block is never used [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_eyemon.vhd:210]
INFO: [Synth 8-226] default block is never used [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_eyemon.vhd:254]
INFO: [Synth 8-226] default block is never used [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_eyemon.vhd:266]
INFO: [Synth 8-256] done synthesizing module 'rbd_eyemon' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_eyemon.vhd:75]
	Parameter RB_ADDR bound to: 16'b1111111000010000 
INFO: [Synth 8-3491] module 'rbd_timer' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_timer.vhd:41' bound to instance 'TIM0' of component 'rbd_timer' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/rbd_tst_rlink.vhd:133]
INFO: [Synth 8-638] synthesizing module 'rbd_timer' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_timer.vhd:56]
	Parameter RB_ADDR bound to: 16'b1111111000010000 
INFO: [Synth 8-256] done synthesizing module 'rbd_timer' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_timer.vhd:56]
	Parameter RB_ADDR bound to: 16'b1111111000010001 
INFO: [Synth 8-3491] module 'rbd_timer' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_timer.vhd:41' bound to instance 'TIM1' of component 'rbd_timer' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/rbd_tst_rlink.vhd:146]
INFO: [Synth 8-638] synthesizing module 'rbd_timer__parameterized1' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_timer.vhd:56]
	Parameter RB_ADDR bound to: 16'b1111111000010001 
INFO: [Synth 8-256] done synthesizing module 'rbd_timer__parameterized1' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_timer.vhd:56]
INFO: [Synth 8-3491] module 'rb_sres_or_3' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sres_or_3.vhd:30' bound to instance 'RB_SRES_OR1' of component 'rb_sres_or_3' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/rbd_tst_rlink.vhd:159]
INFO: [Synth 8-638] synthesizing module 'rb_sres_or_3' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sres_or_3.vhd:39]
INFO: [Synth 8-256] done synthesizing module 'rb_sres_or_3' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sres_or_3.vhd:39]
INFO: [Synth 8-3491] module 'rb_sres_or_4' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sres_or_4.vhd:30' bound to instance 'RB_SRES_OR' of component 'rb_sres_or_4' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/rbd_tst_rlink.vhd:167]
INFO: [Synth 8-638] synthesizing module 'rb_sres_or_4' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sres_or_4.vhd:40]
INFO: [Synth 8-256] done synthesizing module 'rb_sres_or_4' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sres_or_4.vhd:40]
INFO: [Synth 8-256] done synthesizing module 'rbd_tst_rlink' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/rbd_tst_rlink.vhd:60]
	Parameter DWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-3491] module 'rgbdrv_master' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/rgbdrv_master.vhd:25' bound to instance 'RGBMSTR' of component 'rgbdrv_master' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd:275]
INFO: [Synth 8-638] synthesizing module 'rgbdrv_master' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/rgbdrv_master.vhd:37]
	Parameter DWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'rgbdrv_master' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/rgbdrv_master.vhd:37]
	Parameter DWIDTH bound to: 12 - type: integer 
	Parameter RB_ADDR bound to: 16'b1111110000000000 
INFO: [Synth 8-3491] module 'rgbdrv_analog_rbus' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd:40' bound to instance 'RGB0' of component 'rgbdrv_analog_rbus' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd:286]
INFO: [Synth 8-638] synthesizing module 'rgbdrv_analog_rbus' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd:56]
	Parameter DWIDTH bound to: 12 - type: integer 
	Parameter ACTLOW bound to: 1'b0 
	Parameter RB_ADDR bound to: 16'b1111110000000000 
	Parameter DWIDTH bound to: 12 - type: integer 
	Parameter ACTLOW bound to: 1'b0 
INFO: [Synth 8-3491] module 'rgbdrv_analog' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/rgbdrv_analog.vhd:27' bound to instance 'RGB' of component 'rgbdrv_analog' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd:89]
INFO: [Synth 8-638] synthesizing module 'rgbdrv_analog' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/rgbdrv_analog.vhd:43]
	Parameter DWIDTH bound to: 12 - type: integer 
	Parameter ACTLOW bound to: 1'b0 
	Parameter DWIDTH bound to: 3 - type: integer 
INFO: [Synth 8-3491] module 'iob_reg_o_gen' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:25' bound to instance 'IOB_RGB' of component 'iob_reg_o_gen' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/rgbdrv_analog.vhd:50]
INFO: [Synth 8-638] synthesizing module 'iob_reg_o_gen__parameterized7' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:38]
	Parameter DWIDTH bound to: 3 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'iob_reg_o_gen__parameterized7' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:38]
INFO: [Synth 8-256] done synthesizing module 'rgbdrv_analog' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/rgbdrv_analog.vhd:43]
INFO: [Synth 8-256] done synthesizing module 'rgbdrv_analog_rbus' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd:56]
	Parameter DWIDTH bound to: 12 - type: integer 
	Parameter RB_ADDR bound to: 16'b1111110000000100 
INFO: [Synth 8-3491] module 'rgbdrv_analog_rbus' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd:40' bound to instance 'RGB1' of component 'rgbdrv_analog_rbus' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd:300]
INFO: [Synth 8-638] synthesizing module 'rgbdrv_analog_rbus__parameterized1' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd:56]
	Parameter DWIDTH bound to: 12 - type: integer 
	Parameter ACTLOW bound to: 1'b0 
	Parameter RB_ADDR bound to: 16'b1111110000000100 
	Parameter DWIDTH bound to: 12 - type: integer 
	Parameter ACTLOW bound to: 1'b0 
INFO: [Synth 8-3491] module 'rgbdrv_analog' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/rgbdrv_analog.vhd:27' bound to instance 'RGB' of component 'rgbdrv_analog' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd:89]
INFO: [Synth 8-256] done synthesizing module 'rgbdrv_analog_rbus__parameterized1' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/bpgen/rgbdrv_analog_rbus.vhd:56]
	Parameter CLK_MHZ bound to: 120 - type: integer 
	Parameter RB_ADDR bound to: 16'b1111101100000000 
INFO: [Synth 8-3491] module 'sysmonx_rbus_base' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/sysmon/sysmonx_rbus_base.vhd:41' bound to instance 'I0' of component 'sysmonx_rbus_base' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd:316]
INFO: [Synth 8-638] synthesizing module 'sysmonx_rbus_base' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/sysmon/sysmonx_rbus_base.vhd:64]
	Parameter INIT_TEMP_UP bound to: 85.000000 - type: double 
	Parameter INIT_TEMP_LOW bound to: 60.000000 - type: double 
	Parameter INIT_VCCINT_UP bound to: 1.050000 - type: double 
	Parameter INIT_VCCINT_LOW bound to: 0.950000 - type: double 
	Parameter INIT_VCCAUX_UP bound to: 1.890000 - type: double 
	Parameter INIT_VCCAUX_LOW bound to: 1.710000 - type: double 
	Parameter INIT_VCCBRAM_UP bound to: 1.050000 - type: double 
	Parameter INIT_VCCBRAM_LOW bound to: 0.950000 - type: double 
	Parameter CLK_MHZ bound to: 120 - type: integer 
	Parameter RB_ADDR bound to: 16'b1111101100000000 
	Parameter INIT_40 bound to: 16'b1001000000000000 
	Parameter INIT_41 bound to: 16'b0010111011110000 
	Parameter INIT_42 bound to: 16'b0000010100000000 
	Parameter INIT_43 bound to: 16'b0000000000000000 
	Parameter INIT_44 bound to: 16'b0000000000000000 
	Parameter INIT_45 bound to: 16'b0000000000000000 
	Parameter INIT_46 bound to: 16'b0000000000000000 
	Parameter INIT_47 bound to: 16'b0000000000000000 
	Parameter INIT_48 bound to: 16'b0100011100000001 
	Parameter INIT_49 bound to: 16'b0000000000000000 
	Parameter INIT_4A bound to: 16'b0000000000000000 
	Parameter INIT_4B bound to: 16'b0000000000000000 
	Parameter INIT_4C bound to: 16'b0000000000000000 
	Parameter INIT_4D bound to: 16'b0000000000000000 
	Parameter INIT_4E bound to: 16'b0000000000000000 
	Parameter INIT_4F bound to: 16'b0000000000000000 
	Parameter INIT_50 bound to: 16'b1011010111101100 
	Parameter INIT_51 bound to: 16'b0101100110011010 
	Parameter INIT_52 bound to: 16'b1010000101001000 
	Parameter INIT_53 bound to: 16'b1100101000110011 
	Parameter INIT_54 bound to: 16'b1010100100111001 
	Parameter INIT_55 bound to: 16'b0101000100010001 
	Parameter INIT_56 bound to: 16'b1001000111101100 
	Parameter INIT_57 bound to: 16'b1010111001000000 
	Parameter INIT_58 bound to: 16'b0101100110011010 
	Parameter INIT_59 bound to: 16'b0000000000000000 
	Parameter INIT_5A bound to: 16'b0000000000000000 
	Parameter INIT_5B bound to: 16'b0000000000000000 
	Parameter INIT_5C bound to: 16'b0101000100010001 
	Parameter INIT_5D bound to: 16'b0000000000000000 
	Parameter INIT_5E bound to: 16'b0000000000000000 
	Parameter INIT_5F bound to: 16'b0000000000000000 
	Parameter SIM_DEVICE bound to: 7SERIES - type: string 
	Parameter SIM_MONITOR_FILE bound to: sysmon_stim - type: string 
INFO: [Synth 8-113] binding component instance 'SM' to cell 'XADC' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/sysmon/sysmonx_rbus_base.vhd:87]
	Parameter DAWIDTH bound to: 7 - type: integer 
	Parameter ALWIDTH bound to: 8 - type: integer 
	Parameter TEWIDTH bound to: 12 - type: integer 
	Parameter IBASE bound to: 8'b01111000 
	Parameter RB_ADDR bound to: 16'b1111101100000000 
INFO: [Synth 8-3491] module 'sysmon_rbus_core' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/sysmon/sysmon_rbus_core.vhd:58' bound to instance 'SMRB' of component 'sysmon_rbus_core' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/sysmon/sysmonx_rbus_base.vhd:152]
INFO: [Synth 8-638] synthesizing module 'sysmon_rbus_core' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/sysmon/sysmon_rbus_core.vhd:87]
	Parameter DAWIDTH bound to: 7 - type: integer 
	Parameter ALWIDTH bound to: 8 - type: integer 
	Parameter TEWIDTH bound to: 12 - type: integer 
	Parameter IBASE bound to: 8'b01111000 
	Parameter RB_ADDR bound to: 16'b1111101100000000 
INFO: [Synth 8-226] default block is never used [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/sysmon/sysmon_rbus_core.vhd:231]
INFO: [Synth 8-256] done synthesizing module 'sysmon_rbus_core' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/sysmon/sysmon_rbus_core.vhd:87]
INFO: [Synth 8-256] done synthesizing module 'sysmonx_rbus_base' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/sysmon/sysmonx_rbus_base.vhd:64]
INFO: [Synth 8-3491] module 'rbd_usracc' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_usracc.vhd:36' bound to instance 'UARB' of component 'rbd_usracc' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd:331]
INFO: [Synth 8-638] synthesizing module 'rbd_usracc' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_usracc.vhd:47]
	Parameter RB_ADDR bound to: 16'b1111111111111010 
	Parameter RB_ADDR bound to: 16'b1111111111111010 
	Parameter SAWIDTH bound to: 1 - type: integer 
INFO: [Synth 8-3491] module 'rb_sel' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sel.vhd:29' bound to instance 'RBSEL' of component 'rb_sel' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_usracc.vhd:54]
INFO: [Synth 8-638] synthesizing module 'rb_sel__parameterized1' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sel.vhd:40]
	Parameter RB_ADDR bound to: 16'b1111111111111010 
	Parameter SAWIDTH bound to: 1 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'rb_sel__parameterized1' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sel.vhd:40]
INFO: [Synth 8-3491] module 'usr_access_unisim' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/usr_access_unisim.vhd:27' bound to instance 'UA' of component 'usr_access_unisim' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_usracc.vhd:64]
INFO: [Synth 8-638] synthesizing module 'usr_access_unisim' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/usr_access_unisim.vhd:34]
INFO: [Synth 8-113] binding component instance 'UA' to cell 'USR_ACCESSE2' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/usr_access_unisim.vhd:40]
INFO: [Synth 8-256] done synthesizing module 'usr_access_unisim' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/xlib/usr_access_unisim.vhd:34]
INFO: [Synth 8-226] default block is never used [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_usracc.vhd:84]
INFO: [Synth 8-256] done synthesizing module 'rbd_usracc' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rbd_usracc.vhd:47]
INFO: [Synth 8-3491] module 'rb_sres_or_2' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sres_or_2.vhd:30' bound to instance 'RB_SRES_ORRGB' of component 'rb_sres_or_2' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd:338]
INFO: [Synth 8-3491] module 'rb_sres_or_6' declared at '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sres_or_6.vhd:28' bound to instance 'RB_SRES_OR1' of component 'rb_sres_or_6' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd:345]
INFO: [Synth 8-638] synthesizing module 'rb_sres_or_6' [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sres_or_6.vhd:40]
INFO: [Synth 8-256] done synthesizing module 'rb_sres_or_6' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/vlib/rbus/rb_sres_or_6.vhd:40]
INFO: [Synth 8-256] done synthesizing module 'sys_tst_rlink_n4d' (0#1) [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd:107]
WARNING: [Synth 8-7129] Port RB_MREQ[re] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[we] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[init] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[addr][0] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][15] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][14] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][13] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][12] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][11] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][10] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][9] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][8] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][7] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][6] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][5] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][4] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][3] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][2] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][1] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][0] in module rb_sel__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[init] in module sysmon_rbus_core is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[init] in module rgbdrv_analog_rbus__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][15] in module rgbdrv_analog_rbus__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][14] in module rgbdrv_analog_rbus__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][13] in module rgbdrv_analog_rbus__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][12] in module rgbdrv_analog_rbus__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[init] in module rgbdrv_analog_rbus is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][15] in module rgbdrv_analog_rbus is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][14] in module rgbdrv_analog_rbus is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][13] in module rgbdrv_analog_rbus is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][12] in module rgbdrv_analog_rbus is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[init] in module rbd_timer__parameterized1 is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[init] in module rbd_timer is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[init] in module rbd_eyemon is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][15] in module rbd_eyemon is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][14] in module rbd_eyemon is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][13] in module rbd_eyemon is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][12] in module rbd_eyemon is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][11] in module rbd_eyemon is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][10] in module rbd_eyemon is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[init] in module rbd_bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[re] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[we] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[init] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[addr][1] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[addr][0] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][15] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][14] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][13] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][12] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][11] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][10] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][9] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][8] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][7] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][6] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][5] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][4] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][3] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][2] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][1] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][0] in module rb_sel is either unconnected or has no load
WARNING: [Synth 8-7129] Port CE_USEC in module rlink_sp1c is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[init] in module sn_humanio_rbus is either unconnected or has no load
WARNING: [Synth 8-7129] Port I_BTNRST_N in module sys_tst_rlink_n4d is either unconnected or has no load
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2608.312 ; gain = 0.000 ; free physical = 4621 ; free virtual = 23181
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2608.312 ; gain = 0.000 ; free physical = 4647 ; free virtual = 23208
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2608.312 ; gain = 0.000 ; free physical = 4647 ; free virtual = 23208
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2608.312 ; gain = 0.000 ; free physical = 4646 ; free virtual = 23207
INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/nexys4d/nexys4d_pclk.xdc]
Finished Parsing XDC File [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/nexys4d/nexys4d_pclk.xdc]
Parsing XDC File [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/nexys4d/nexys4d_pins.xdc]
Finished Parsing XDC File [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/nexys4d/nexys4d_pins.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/nexys4d/nexys4d_pins.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/sys_tst_rlink_n4d_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/sys_tst_rlink_n4d_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
INFO: [Timing 38-2] Deriving generated clocks
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2672.344 ; gain = 0.000 ; free physical = 4406 ; free virtual = 22967
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 1 instances were transformed.
  MMCME2_BASE => MMCME2_ADV: 1 instance 

Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2672.344 ; gain = 0.000 ; free physical = 4405 ; free virtual = 22966
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 4606 ; free virtual = 23180
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 4606 ; free virtual = 23180
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 4596 ; free virtual = 23171
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'R_LREGS_reg[state]' in module 'rlink_core'
INFO: [Synth 8-802] inferred FSM for state register 'R_BREGS_reg[state]' in module 'rlink_core'
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'serport_uart_autobaud'
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'serport_uart_rx'
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'rbd_eyemon'
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'sysmon_rbus_core'
INFO: [Synth 8-3971] The signal "ram_2swsr_rfirst_gen:/sv_ram_reg" was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 sb_idle |                    0000000000001 |                             0000
               sb_rstart |                    0000000000010 |                             0001
                sb_rreg0 |                    0000000000100 |                             0010
                sb_rreg1 |                    0000000001000 |                             0011
                sb_rwait |                    0000000010000 |                             0100
                sb_rabo1 |                    0000000100000 |                             0111
                sb_rabo0 |                    0000001000000 |                             0110
                 sb_rend |                    0000010000000 |                             0101
               sb_wstart |                    0000100000000 |                             1000
                sb_wreg0 |                    0001000000000 |                             1001
                sb_wreg1 |                    0010000000000 |                             1010
                sb_wabo0 |                    0100000000000 |                             1011
                sb_wabo1 |                    1000000000000 |                             1100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_BREGS_reg[state]' using encoding 'one-hot' in module 'rlink_core'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 sl_idle | 0000000000000000000000000000000000000001 |                           000000
               sl_txanot | 0000000000000000000000000000000000000010 |                           000001
                sl_txsop | 0000000000000000000000000000000000000100 |                           000010
              sl_txrtbuf | 0000000000000000000000000000000000001000 |                           000101
                sl_rxcmd | 0000000000000000000000000000000000010000 |                           001000
              sl_rxaddrl | 0000000000000000000000000000000000100000 |                           001001
              sl_rxaddrh | 0000000000000000000000000000000001000000 |                           001010
               sl_rxdatl | 0000000000000000000000000000000010000000 |                           001011
               sl_rxdath | 0000000000000000000000000000000100000000 |                           001100
               sl_rxcntl | 0000000000000000000000000000001000000000 |                           001101
               sl_rxcnth | 0000000000000000000000000000010000000000 |                           001110
              sl_rxccrcl | 0000000000000000000000000000100000000000 |                           001111
              sl_rxccrch | 0000000000000000000000000001000000000000 |                           010000
                sl_txcmd | 0000000000000000000000000010000000000000 |                           010001
                 sl_wblk | 0000000000000000000000000100000000000000 |                           010110
               sl_rxwblk | 0000000000000000000000001000000000000000 |                           010111
              sl_rxdcrcl | 0000000000000000000000010000000000000000 |                           011000
              sl_rxdcrch | 0000000000000000000000100000000000000000 |                           011001
                sl_wblk0 | 0000000000000000000001000000000000000000 |                           011010
                sl_wblk1 | 0000000000000000000010000000000000000000 |                           011011
                sl_wblk2 | 0000000000000000000100000000000000000000 |                           011100
                sl_wblkl | 0000000000000000001000000000000000000000 |                           011101
                sl_wblkh | 0000000000000000010000000000000000000000 |                           011110
               sl_wwait0 | 0000000000000000100000000000000000000000 |                           011111
               sl_wwait1 | 0000000000000001000000000000000000000000 |                           100000
               sl_txlabo | 0000000000000010000000000000000000000000 |                           100011
                 sl_attn | 0000000000000100000000000000000000000000 |                           100100
               sl_txcntl | 0000000000001000000000000000000000000000 |                           010010
               sl_txcnth | 0000000000010000000000000000000000000000 |                           010011
               sl_rstart | 0000000000100000000000000000000000000000 |                           010100
                sl_txdat | 0000000001000000000000000000000000000000 |                           010101
              sl_txdcntl | 0000000010000000000000000000000000000000 |                           100001
              sl_txdcnth | 0000000100000000000000000000000000000000 |                           100010
               sl_txstat | 0000001000000000000000000000000000000000 |                           100101
               sl_txcrcl | 0000010000000000000000000000000000000000 |                           100110
               sl_txcrch | 0000100000000000000000000000000000000000 |                           100111
                sl_txnak | 0001000000000000000000000000000000000000 |                           000011
            sl_txnakcode | 0010000000000000000000000000000000000000 |                           000100
                sl_rxeop | 0100000000000000000000000000000000000000 |                           000111
                sl_txeop | 1000000000000000000000000000000000000000 |                           000110
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_LREGS_reg[state]' using encoding 'one-hot' in module 'rlink_core'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_idle |                             0001 |                               00
                 s_break |                             0010 |                               01
                  s_wait |                             0100 |                               10
                  s_sync |                             1000 |                               11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'serport_uart_autobaud'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_idle |                          0000001 |                              000
                 s_colb0 |                          0000010 |                              001
                 s_endb0 |                          0000100 |                              010
                 s_colbx |                          0001000 |                              011
                 s_endbx |                          0010000 |                              100
                 s_colb9 |                          0100000 |                              101
                 s_endb9 |                          1000000 |                              110
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'serport_uart_rx'
INFO: [Synth 8-3971] The signal "ram_2swsr_wfirst_gen:/sv_ram_reg" was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_idle |                              001 |                               00
                   s_clr |                              010 |                               10
                  s_char |                              100 |                               01
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'rbd_eyemon'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_init |                             0001 |                               00
                  s_idle |                             0010 |                               01
                 s_twait |                             0100 |                               11
                  s_wait |                             1000 |                               10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'sysmon_rbus_core'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 4686 ; free virtual = 23270
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input   32 Bit       Adders := 1     
	   2 Input   16 Bit       Adders := 4     
	   2 Input   15 Bit       Adders := 1     
	   2 Input   14 Bit       Adders := 1     
	   2 Input   13 Bit       Adders := 1     
	   2 Input   12 Bit       Adders := 6     
	   2 Input   11 Bit       Adders := 2     
	   2 Input   10 Bit       Adders := 5     
	   2 Input    9 Bit       Adders := 2     
	   3 Input    9 Bit       Adders := 1     
	   2 Input    8 Bit       Adders := 2     
	   2 Input    7 Bit       Adders := 3     
	   2 Input    6 Bit       Adders := 2     
	   2 Input    5 Bit       Adders := 6     
	   3 Input    5 Bit       Adders := 3     
	   2 Input    4 Bit       Adders := 4     
	   3 Input    4 Bit       Adders := 1     
	   2 Input    3 Bit       Adders := 1     
	   2 Input    2 Bit       Adders := 3     
+---XORs : 
	   2 Input      8 Bit         XORs := 2     
	   2 Input      1 Bit         XORs := 28    
	   3 Input      1 Bit         XORs := 2     
+---Registers : 
	               32 Bit    Registers := 6     
	               16 Bit    Registers := 26    
	               15 Bit    Registers := 1     
	               14 Bit    Registers := 1     
	               13 Bit    Registers := 1     
	               12 Bit    Registers := 13    
	               11 Bit    Registers := 2     
	               10 Bit    Registers := 7     
	                9 Bit    Registers := 5     
	                8 Bit    Registers := 19    
	                7 Bit    Registers := 3     
	                6 Bit    Registers := 3     
	                5 Bit    Registers := 12    
	                4 Bit    Registers := 6     
	                3 Bit    Registers := 8     
	                2 Bit    Registers := 3     
	                1 Bit    Registers := 115   
+---RAMs : 
	              32K Bit	(4096 X 8 bit)          RAMs := 1     
	              16K Bit	(1024 X 16 bit)          RAMs := 1     
	              16K Bit	(512 X 32 bit)          RAMs := 3     
+---Muxes : 
	  40 Input   40 Bit        Muxes := 1     
	   2 Input   40 Bit        Muxes := 39    
	   4 Input   40 Bit        Muxes := 1     
	   3 Input   40 Bit        Muxes := 2     
	   8 Input   40 Bit        Muxes := 1     
	   2 Input   32 Bit        Muxes := 2     
	   8 Input   32 Bit        Muxes := 1     
	   2 Input   16 Bit        Muxes := 39    
	  40 Input   16 Bit        Muxes := 6     
	   4 Input   16 Bit        Muxes := 5     
	   8 Input   16 Bit        Muxes := 2     
	   4 Input   15 Bit        Muxes := 1     
	  13 Input   13 Bit        Muxes := 1     
	   4 Input   13 Bit        Muxes := 1     
	   2 Input   13 Bit        Muxes := 8     
	   2 Input   12 Bit        Muxes := 4     
	  40 Input   12 Bit        Muxes := 1     
	   2 Input   11 Bit        Muxes := 1     
	   2 Input   10 Bit        Muxes := 7     
	  40 Input    9 Bit        Muxes := 1     
	   2 Input    9 Bit        Muxes := 8     
	   4 Input    9 Bit        Muxes := 1     
	   7 Input    9 Bit        Muxes := 1     
	   2 Input    8 Bit        Muxes := 18    
	  13 Input    8 Bit        Muxes := 1     
	   6 Input    8 Bit        Muxes := 1     
	   3 Input    8 Bit        Muxes := 1     
	   7 Input    8 Bit        Muxes := 1     
	   4 Input    8 Bit        Muxes := 1     
	   2 Input    7 Bit        Muxes := 13    
	   7 Input    7 Bit        Muxes := 1     
	   4 Input    7 Bit        Muxes := 1     
	   2 Input    6 Bit        Muxes := 3     
	   2 Input    5 Bit        Muxes := 8     
	   8 Input    5 Bit        Muxes := 1     
	   5 Input    5 Bit        Muxes := 1     
	   2 Input    4 Bit        Muxes := 4     
	   4 Input    4 Bit        Muxes := 1     
	   4 Input    3 Bit        Muxes := 1     
	   2 Input    3 Bit        Muxes := 10    
	  40 Input    3 Bit        Muxes := 1     
	   5 Input    3 Bit        Muxes := 2     
	   3 Input    3 Bit        Muxes := 1     
	   2 Input    2 Bit        Muxes := 3     
	   9 Input    2 Bit        Muxes := 1     
	  40 Input    2 Bit        Muxes := 1     
	   7 Input    2 Bit        Muxes := 1     
	   2 Input    1 Bit        Muxes := 205   
	   8 Input    1 Bit        Muxes := 17    
	   4 Input    1 Bit        Muxes := 42    
	  13 Input    1 Bit        Muxes := 22    
	   5 Input    1 Bit        Muxes := 4     
	   3 Input    1 Bit        Muxes := 9     
	  40 Input    1 Bit        Muxes := 31    
	   7 Input    1 Bit        Muxes := 22    
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
WARNING: [Synth 8-7129] Port RB_MREQ[init] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][15] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][14] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][13] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][12] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][11] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][10] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][9] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][8] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][7] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][6] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][5] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][4] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][3] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][2] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][1] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][0] in module rbd_usracc is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[init] in module sysmonx_rbus_base is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[init] in module rbd_eyemon is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][15] in module rbd_eyemon is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][14] in module rbd_eyemon is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][13] in module rbd_eyemon is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][12] in module rbd_eyemon is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][11] in module rbd_eyemon is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[din][10] in module rbd_eyemon is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[init] in module rbd_bram is either unconnected or has no load
WARNING: [Synth 8-7129] Port CE_USEC in module rlink_sp1c is either unconnected or has no load
WARNING: [Synth 8-7129] Port RB_MREQ[init] in module sn_humanio_rbus is either unconnected or has no load
WARNING: [Synth 8-7129] Port I_BTNRST_N in module sys_tst_rlink_n4d is either unconnected or has no load
INFO: [Synth 8-3971] The signal "RLINK/\CORE/RL /RTBUF/sv_ram_reg" was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 5586 ; free virtual = 24201
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Block RAM: Preliminary Mapping Report (see note below)
+------------------+-----------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name       | RTL Object                  | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | 
+------------------+-----------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|RLINK/\CORE/RL    | RTBUF/sv_ram_reg            | 4 K x 8(READ_FIRST)    | W | R | 4 K x 8(READ_FIRST)    | W |   | Port A and B     | 0      | 1      | 
|sys_tst_rlink_n4d | RBDTST/BRAM/BRAM/sv_ram_reg | 1 K x 16(WRITE_FIRST)  | W | R |                        |   |   | Port A           | 1      | 0      | 
|sys_tst_rlink_n4d | RBDTST/MON/BRAM1/sv_ram_reg | 512 x 32(WRITE_FIRST)  | W | R |                        |   |   | Port A           | 1      | 0      | 
|sys_tst_rlink_n4d | RBDTST/MON/BRAM0/sv_ram_reg | 512 x 32(WRITE_FIRST)  | W | R |                        |   |   | Port A           | 1      | 0      | 
|sys_tst_rlink_n4d | RBDTST/EMON/BRAM/sv_ram_reg | 512 x 32(READ_FIRST)   | W |   | 512 x 32(WRITE_FIRST)  |   | R | Port A and B     | 1      | 0      | 
+------------------+-----------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+

Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. 

Distributed RAM: Preliminary Mapping Report (see note below)
+------------------+---------------------------------+----------------+----------------------+----------------+
|Module Name       | RTL Object                      | Inference      | Size (Depth x Width) | Primitives     | 
+------------------+---------------------------------+----------------+----------------------+----------------+
|RLINK/\CORE/RL    | DOFIFO/FIFO/RAM/RAM_reg         | User Attribute | 32 x 8               | RAM32M x 2     | 
|RLINK             | SERPORT/RXFIFO/FIFO/RAM/RAM_reg | User Attribute | 32 x 8               | RAM32M x 2     | 
|RLINK             | SERPORT/TXFIFO/FIFO/RAM/RAM_reg | User Attribute | 32 x 8               | RAM32M x 2     | 
|sys_tst_rlink_n4d | RBDTST/TEST/FIFO/RAM/RAM_reg    | User Attribute | 16 x 16              | RAM16X1S x 16  | 
+------------------+---------------------------------+----------------+----------------------+----------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:30 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 5208 ; free virtual = 23873
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:00:32 ; elapsed = 00:00:33 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 4971 ; free virtual = 23671
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Block RAM: Final Mapping Report
+------------------+-----------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name       | RTL Object                  | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | 
+------------------+-----------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|RLINK/\CORE/RL    | RTBUF/sv_ram_reg            | 4 K x 8(READ_FIRST)    | W | R | 4 K x 8(READ_FIRST)    | W |   | Port A and B     | 0      | 1      | 
|sys_tst_rlink_n4d | RBDTST/BRAM/BRAM/sv_ram_reg | 1 K x 16(WRITE_FIRST)  | W | R |                        |   |   | Port A           | 1      | 0      | 
|sys_tst_rlink_n4d | RBDTST/MON/BRAM1/sv_ram_reg | 512 x 32(WRITE_FIRST)  | W | R |                        |   |   | Port A           | 1      | 0      | 
|sys_tst_rlink_n4d | RBDTST/MON/BRAM0/sv_ram_reg | 512 x 32(WRITE_FIRST)  | W | R |                        |   |   | Port A           | 1      | 0      | 
|sys_tst_rlink_n4d | RBDTST/EMON/BRAM/sv_ram_reg | 512 x 32(READ_FIRST)   | W |   | 512 x 32(WRITE_FIRST)  |   | R | Port A and B     | 1      | 0      | 
+------------------+-----------------------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+


Distributed RAM: Final Mapping Report
+------------------+---------------------------------+----------------+----------------------+----------------+
|Module Name       | RTL Object                      | Inference      | Size (Depth x Width) | Primitives     | 
+------------------+---------------------------------+----------------+----------------------+----------------+
|RLINK/\CORE/RL    | DOFIFO/FIFO/RAM/RAM_reg         | User Attribute | 32 x 8               | RAM32M x 2     | 
|RLINK             | SERPORT/RXFIFO/FIFO/RAM/RAM_reg | User Attribute | 32 x 8               | RAM32M x 2     | 
|RLINK             | SERPORT/TXFIFO/FIFO/RAM/RAM_reg | User Attribute | 32 x 8               | RAM32M x 2     | 
|sys_tst_rlink_n4d | RBDTST/TEST/FIFO/RAM/RAM_reg    | User Attribute | 16 x 16              | RAM16X1S x 16  | 
+------------------+---------------------------------+----------------+----------------------+----------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-7052] The timing for the instance RLINK/CORE/RL/RTBUF/sv_ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance RBDTST/BRAM/BRAM/sv_ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance RBDTST/MON/BRAM1/sv_ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance RBDTST/MON/BRAM1/sv_ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance RBDTST/MON/BRAM0/sv_ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance RBDTST/MON/BRAM0/sv_ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
INFO: [Synth 8-7052] The timing for the instance RBDTST/EMON/BRAM/sv_ram_reg (implemented as a Block RAM) might be sub-optimal as no optional output register could be merged into the ram block. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:00:33 ; elapsed = 00:00:34 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 4938 ; free virtual = 23638
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
INFO: [Synth 8-4163] Replicating register \IOB_RS232/IOB_CTS/IOB/R_DI_reg[0]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_BTN/R_DI_reg[0]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_BTN/R_DI_reg[1]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_BTN/R_DI_reg[2]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_BTN/R_DI_reg[3]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_BTN/R_DI_reg[4]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[0]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[1]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[2]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[3]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[4]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[5]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[6]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[7]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[8]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[9]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[10]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[11]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[12]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[13]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[14]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[15]  to handle IOB=TRUE attribute
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 4669 ; free virtual = 23370
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 4667 ; free virtual = 23369
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 4664 ; free virtual = 23365
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 4671 ; free virtual = 23372
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 4668 ; free virtual = 23370
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 4659 ; free virtual = 23361
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+-------------+------+
|      |Cell         |Count |
+------+-------------+------+
|1     |BUFG         |     2|
|2     |CARRY4       |    75|
|3     |LUT1         |    98|
|4     |LUT2         |   171|
|5     |LUT3         |   257|
|6     |LUT4         |   349|
|7     |LUT5         |   357|
|8     |LUT6         |   595|
|9     |MMCME2_BASE  |     1|
|10    |MUXF7        |     8|
|11    |RAM16X1S     |    16|
|12    |RAM32M       |     3|
|13    |RAM32X1D     |     6|
|14    |RAMB18E1     |     4|
|17    |RAMB36E1     |     1|
|18    |USR_ACCESSE2 |     1|
|19    |XADC         |     1|
|20    |FDRE         |  1227|
|21    |FDSE         |    17|
|22    |IBUF         |    24|
|23    |OBUF         |    40|
+------+-------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 4661 ; free virtual = 23362
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 30 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:00:34 ; elapsed = 00:00:36 . Memory (MB): peak = 2672.344 ; gain = 0.000 ; free physical = 4765 ; free virtual = 23466
Synthesis Optimization Complete : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 4770 ; free virtual = 23472
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2672.344 ; gain = 0.000 ; free physical = 5028 ; free virtual = 23733
INFO: [Netlist 29-17] Analyzing 115 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2672.344 ; gain = 0.000 ; free physical = 4868 ; free virtual = 23559
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 26 instances were transformed.
  MMCME2_BASE => MMCME2_ADV: 1 instance 
  RAM16X1S => RAM32X1S (RAMS32): 16 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 3 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 6 instances

Synth Design complete, checksum: dd1c1e3b
INFO: [Common 17-83] Releasing license: Synthesis
289 Infos, 95 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:00:45 ; elapsed = 00:00:42 . Memory (MB): peak = 2672.344 ; gain = 64.031 ; free physical = 5095 ; free virtual = 23786
INFO: [Common 17-1381] The checkpoint '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/project_mflow/project_mflow.runs/synth_1/sys_tst_rlink_n4d.dcp' has been generated.
INFO: [runtcl-4] Executing : report_utilization -file sys_tst_rlink_n4d_utilization_synth.rpt -pb sys_tst_rlink_n4d_utilization_synth.pb
INFO: [Common 17-206] Exiting Vivado at Thu Feb  9 12:12:09 2023...
