
*** Running vivado
    with args -log sys_tst_rlink_n4d.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source sys_tst_rlink_n4d.tcl -notrace


****** Vivado v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source sys_tst_rlink_n4d.tcl -notrace
Command: link_design -top sys_tst_rlink_n4d -part xc7a100tcsg324-1
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2611.316 ; gain = 0.000 ; free physical = 4908 ; free virtual = 23610
INFO: [Netlist 29-17] Analyzing 115 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2022.1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/nexys4d/nexys4d_pclk.xdc]
Finished Parsing XDC File [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/nexys4d/nexys4d_pclk.xdc]
Parsing XDC File [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/nexys4d/nexys4d_pins.xdc]
Finished Parsing XDC File [/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/bplib/nexys4d/nexys4d_pins.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2611.316 ; gain = 0.000 ; free physical = 4695 ; free virtual = 23402
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 25 instances were transformed.
  RAM16X1S => RAM32X1S (RAMS32): 16 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 3 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 6 instances

7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
link_design completed successfully
link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 2611.316 ; gain = 0.000 ; free physical = 4695 ; free virtual = 23402
Command: opt_design -directive Explore
INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.76 . Memory (MB): peak = 2675.348 ; gain = 64.031 ; free physical = 4651 ; free virtual = 23355

Starting Logic Optimization Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-2] Deriving generated clocks

Phase 1 Retarget
INFO: [Opt 31-1287] Pulled Inverter RLINK/CORE/RL/OCRC/sv_ram_reg_i_5 into driver instance RLINK/CORE/RL/OCRC/sv_ram_reg_i_20, which resulted in an inversion of 10 pins
INFO: [Opt 31-1287] Pulled Inverter RLINK/CORE/RL/OCRC/sv_ram_reg_i_6 into driver instance RLINK/CORE/RL/OCRC/sv_ram_reg_i_21, which resulted in an inversion of 11 pins
INFO: [Opt 31-1287] Pulled Inverter RLINK/CORE/RL/OCRC/sv_ram_reg_i_7 into driver instance RLINK/CORE/RL/OCRC/sv_ram_reg_i_22, which resulted in an inversion of 11 pins
INFO: [Opt 31-1287] Pulled Inverter RLINK/CORE/RL/RTBUF/sv_ram_reg_i_10 into driver instance RLINK/CORE/RL/RTBUF/sv_ram_reg_i_25, which resulted in an inversion of 14 pins
INFO: [Opt 31-1287] Pulled Inverter RLINK/CORE/RL/RTBUF/sv_ram_reg_i_3 into driver instance RLINK/CORE/RL/RTBUF/sv_ram_reg_i_18, which resulted in an inversion of 14 pins
INFO: [Opt 31-1287] Pulled Inverter RLINK/CORE/RL/RTBUF/sv_ram_reg_i_4 into driver instance RLINK/CORE/RL/RTBUF/sv_ram_reg_i_19, which resulted in an inversion of 14 pins
INFO: [Opt 31-1287] Pulled Inverter RLINK/CORE/RL/RTBUF/sv_ram_reg_i_8 into driver instance RLINK/CORE/RL/RTBUF/sv_ram_reg_i_23, which resulted in an inversion of 16 pins
INFO: [Opt 31-1287] Pulled Inverter RLINK/CORE/RL/RTBUF/sv_ram_reg_i_9 into driver instance RLINK/CORE/RL/RTBUF/sv_ram_reg_i_24, which resulted in an inversion of 9 pins
INFO: [Opt 31-1287] Pulled Inverter RLINK/CORE/RL/R_REGS[data][8]_i_1 into driver instance RLINK/CORE/RL/R_REGS[raddr][4]_i_3, which resulted in an inversion of 2 pins
INFO: [Opt 31-1287] Pulled Inverter RLINK/CORE/RL/R_REGS[rbnak]_i_1 into driver instance RLINK/CORE/RL/R_REGS[rback]_i_2, which resulted in an inversion of 3 pins
INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s).
In IDDR TRANSFORM
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 164784835

Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2869.129 ; gain = 193.781 ; free physical = 3303 ; free virtual = 22011
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 11 cells
INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail. 

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 164784835

Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2869.129 ; gain = 193.781 ; free physical = 3302 ; free virtual = 22011
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 1a36161ac

Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2869.129 ; gain = 193.781 ; free physical = 3309 ; free virtual = 22016
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 1a36161ac

Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2901.145 ; gain = 225.797 ; free physical = 3309 ; free virtual = 22016
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 5 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 5 Shift Register Optimization | Checksum: 1a36161ac

Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2901.145 ; gain = 225.797 ; free physical = 3309 ; free virtual = 22016
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 6 Post Processing Netlist
Phase 6 Post Processing Netlist | Checksum: 1a36161ac

Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2901.145 ; gain = 225.797 ; free physical = 3309 ; free virtual = 22016
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |              11  |                                              1  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |               0  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------



Starting Connectivity Check Task

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2901.145 ; gain = 0.000 ; free physical = 3308 ; free virtual = 22015
Ending Logic Optimization Task | Checksum: 9c765afb

Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2901.145 ; gain = 225.797 ; free physical = 3308 ; free virtual = 22015

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2901.145 ; gain = 0.000 ; free physical = 3308 ; free virtual = 22015
Ending Netlist Obfuscation Task | Checksum: 9c765afb

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2901.145 ; gain = 0.000 ; free physical = 3308 ; free virtual = 22015
INFO: [Common 17-83] Releasing license: Implementation
36 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 2901.145 ; gain = 289.828 ; free physical = 3308 ; free virtual = 22015
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2909.148 ; gain = 0.000 ; free physical = 3301 ; free virtual = 22009
INFO: [Common 17-1381] The checkpoint '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_n4d_opt.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file sys_tst_rlink_n4d_drc_opted.rpt -pb sys_tst_rlink_n4d_drc_opted.pb -rpx sys_tst_rlink_n4d_drc_opted.rpx
Command: report_drc -file sys_tst_rlink_n4d_drc_opted.rpt -pb sys_tst_rlink_n4d_drc_opted.pb -rpx sys_tst_rlink_n4d_drc_opted.rpx
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2022.1/data/ip'.
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_n4d_drc_opted.rpt.
report_drc completed successfully
Command: place_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 46-5] The placer was invoked with the 'Explore' directive.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 3203 ; free virtual = 21908
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 2b1e01c7

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 3203 ; free virtual = 21908
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 3203 ; free virtual = 21908

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1cfa67c08

Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.28 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 3264 ; free virtual = 21972

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 244ec67f4

Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.96 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 3295 ; free virtual = 22002

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 244ec67f4

Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.97 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 3295 ; free virtual = 22002
Phase 1 Placer Initialization | Checksum: 244ec67f4

Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.98 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 3295 ; free virtual = 22002

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 232a03d38

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 3248 ; free virtual = 21956

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 2919f5721

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 3246 ; free virtual = 21951

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 2919f5721

Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 3246 ; free virtual = 21951

Phase 2.4 Global Placement Core

Phase 2.4.1 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 357 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 146 nets or LUTs. Breaked 0 LUT, combined 146 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4372 ; free virtual = 23083

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            0  |            146  |                   146  |           0  |           1  |  00:00:00  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            0  |            146  |                   146  |           0  |           4  |  00:00:00  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.1 Physical Synthesis In Placer | Checksum: 206973044

Time (s): cpu = 00:00:44 ; elapsed = 00:00:15 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4337 ; free virtual = 23047
Phase 2.4 Global Placement Core | Checksum: 28a307c12

Time (s): cpu = 00:01:03 ; elapsed = 00:00:20 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4200 ; free virtual = 22913
Phase 2 Global Placement | Checksum: 28a307c12

Time (s): cpu = 00:01:03 ; elapsed = 00:00:20 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4200 ; free virtual = 22913

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1fa163968

Time (s): cpu = 00:01:04 ; elapsed = 00:00:21 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4198 ; free virtual = 22906

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 179f2c38e

Time (s): cpu = 00:01:04 ; elapsed = 00:00:21 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4189 ; free virtual = 22897

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1462ebe05

Time (s): cpu = 00:01:05 ; elapsed = 00:00:22 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4185 ; free virtual = 22894

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 19a157530

Time (s): cpu = 00:01:05 ; elapsed = 00:00:22 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4185 ; free virtual = 22894

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 1b026484a

Time (s): cpu = 00:01:07 ; elapsed = 00:00:22 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4162 ; free virtual = 22871

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 18d198637

Time (s): cpu = 00:01:07 ; elapsed = 00:00:23 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4161 ; free virtual = 22870

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 2691f516c

Time (s): cpu = 00:01:07 ; elapsed = 00:00:23 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4161 ; free virtual = 22870
Phase 3 Detail Placement | Checksum: 2691f516c

Time (s): cpu = 00:01:07 ; elapsed = 00:00:23 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4160 ; free virtual = 22870

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 27f5fb812

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=0.243 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 24554cd46

Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4149 ; free virtual = 22859
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
Ending Physical Synthesis Task | Checksum: 1fd553af5

Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.11 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4149 ; free virtual = 22859
Phase 4.1.1.1 BUFG Insertion | Checksum: 27f5fb812

Time (s): cpu = 00:01:08 ; elapsed = 00:00:23 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4149 ; free virtual = 22858

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.557. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 14b6b7888

Time (s): cpu = 00:01:08 ; elapsed = 00:00:24 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4146 ; free virtual = 22854

Time (s): cpu = 00:01:08 ; elapsed = 00:00:24 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4146 ; free virtual = 22854
Phase 4.1 Post Commit Optimization | Checksum: 14b6b7888

Time (s): cpu = 00:01:08 ; elapsed = 00:00:24 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4146 ; free virtual = 22854

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 14b6b7888

Time (s): cpu = 00:01:09 ; elapsed = 00:00:24 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4146 ; free virtual = 22854

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                1x1|
|___________|___________________|___________________|
|      South|                1x1|                1x1|
|___________|___________________|___________________|
|       East|                1x1|                1x1|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 14b6b7888

Time (s): cpu = 00:01:09 ; elapsed = 00:00:24 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4146 ; free virtual = 22854
Phase 4.3 Placer Reporting | Checksum: 14b6b7888

Time (s): cpu = 00:01:09 ; elapsed = 00:00:24 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4146 ; free virtual = 22854

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4146 ; free virtual = 22854

Time (s): cpu = 00:01:09 ; elapsed = 00:00:24 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4146 ; free virtual = 22854
Phase 4 Post Placement Optimization and Clean-Up | Checksum: ec2708a1

Time (s): cpu = 00:01:09 ; elapsed = 00:00:24 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4146 ; free virtual = 22854
Ending Placer Task | Checksum: c6e6be1b

Time (s): cpu = 00:01:09 ; elapsed = 00:00:24 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4146 ; free virtual = 22854
INFO: [Common 17-83] Releasing license: Implementation
74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:10 ; elapsed = 00:00:24 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4165 ; free virtual = 22873
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.19 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4155 ; free virtual = 22867
INFO: [Common 17-1381] The checkpoint '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_n4d_placed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_io -file sys_tst_rlink_n4d_io_placed.rpt
report_io: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.13 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4145 ; free virtual = 22855
INFO: [runtcl-4] Executing : report_utilization -file sys_tst_rlink_n4d_utilization_placed.rpt -pb sys_tst_rlink_n4d_utilization_placed.pb
INFO: [runtcl-4] Executing : report_control_sets -verbose -file sys_tst_rlink_n4d_control_sets_placed.rpt
report_control_sets: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.08 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4141 ; free virtual = 22853
Command: phys_opt_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
INFO: [Common 17-83] Releasing license: Implementation
84 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.18 . Memory (MB): peak = 3143.727 ; gain = 0.000 ; free physical = 4221 ; free virtual = 22937
INFO: [Common 17-1381] The checkpoint '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_n4d_physopt.dcp' has been generated.
Command: route_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-270] Using Router directive 'Explore'.
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: 45919041 ConstDB: 0 ShapeSum: 81552dda RouteDB: 0
Post Restoration Checksum: NetGraph: bd66dce3 NumContArr: fe844934 Constraints: 0 Timing: 0
Phase 1 Build RT Design | Checksum: 1bbeb2617

Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 3195.957 ; gain = 52.230 ; free physical = 3457 ; free virtual = 22139

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 1bbeb2617

Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 3220.953 ; gain = 77.227 ; free physical = 3425 ; free virtual = 22107

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 1bbeb2617

Time (s): cpu = 00:00:23 ; elapsed = 00:00:19 . Memory (MB): peak = 3220.953 ; gain = 77.227 ; free physical = 3425 ; free virtual = 22107
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 2946156bf

Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 3246.250 ; gain = 102.523 ; free physical = 3320 ; free virtual = 22002
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.598  | TNS=0.000  | WHS=-0.357 | THS=-65.911|


Router Utilization Summary
  Global Vertical Routing Utilization    = 0 %
  Global Horizontal Routing Utilization  = 0 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 2593
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 2593
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 2 Router Initialization | Checksum: 24be17101

Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 3246.250 ; gain = 102.523 ; free physical = 3231 ; free virtual = 21913

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 24be17101

Time (s): cpu = 00:00:25 ; elapsed = 00:00:20 . Memory (MB): peak = 3246.250 ; gain = 102.523 ; free physical = 3230 ; free virtual = 21912
Phase 3 Initial Routing | Checksum: 11570da76

Time (s): cpu = 00:00:26 ; elapsed = 00:00:21 . Memory (MB): peak = 3246.250 ; gain = 102.523 ; free physical = 3073 ; free virtual = 21759

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 459
 Number of Nodes with overlaps = 99
 Number of Nodes with overlaps = 37
 Number of Nodes with overlaps = 14
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.465  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 13e9b2734

Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 3246.250 ; gain = 102.523 ; free physical = 2847 ; free virtual = 21532

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.465  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 22d956569

Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 3246.250 ; gain = 102.523 ; free physical = 2845 ; free virtual = 21530
Phase 4 Rip-up And Reroute | Checksum: 22d956569

Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 3246.250 ; gain = 102.523 ; free physical = 2845 ; free virtual = 21530

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 22d956569

Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 3246.250 ; gain = 102.523 ; free physical = 2845 ; free virtual = 21530

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 22d956569

Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 3246.250 ; gain = 102.523 ; free physical = 2845 ; free virtual = 21530
Phase 5 Delay and Skew Optimization | Checksum: 22d956569

Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 3246.250 ; gain = 102.523 ; free physical = 2845 ; free virtual = 21530

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 1d73154d4

Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 3246.250 ; gain = 102.523 ; free physical = 2845 ; free virtual = 21530
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.545  | TNS=0.000  | WHS=0.013  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 18afe7e74

Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 3246.250 ; gain = 102.523 ; free physical = 2845 ; free virtual = 21530
Phase 6 Post Hold Fix | Checksum: 18afe7e74

Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 3246.250 ; gain = 102.523 ; free physical = 2845 ; free virtual = 21530

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.543761 %
  Global Horizontal Routing Utilization  = 0.661481 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 18afe7e74

Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 3246.250 ; gain = 102.523 ; free physical = 2845 ; free virtual = 21530

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 18afe7e74

Time (s): cpu = 00:00:30 ; elapsed = 00:00:23 . Memory (MB): peak = 3246.250 ; gain = 102.523 ; free physical = 2845 ; free virtual = 21530

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: ba3e92a7

Time (s): cpu = 00:00:30 ; elapsed = 00:00:24 . Memory (MB): peak = 3262.258 ; gain = 118.531 ; free physical = 2845 ; free virtual = 21530

Phase 10 Post Router Timing
INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.543  | TNS=0.000  | WHS=0.013  | THS=0.000  |

Phase 10 Post Router Timing | Checksum: 138363aec

Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 3262.258 ; gain = 118.531 ; free physical = 2845 ; free virtual = 21530
INFO: [Route 35-61] The design met the timing requirement.
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:31 ; elapsed = 00:00:24 . Memory (MB): peak = 3262.258 ; gain = 118.531 ; free physical = 2970 ; free virtual = 21655

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
100 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:25 . Memory (MB): peak = 3262.258 ; gain = 118.531 ; free physical = 2970 ; free virtual = 21655
INFO: [Timing 38-480] Writing timing data to binary archive.
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.15 . Memory (MB): peak = 3262.258 ; gain = 0.000 ; free physical = 2961 ; free virtual = 21650
INFO: [Common 17-1381] The checkpoint '/opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_n4d_routed.dcp' has been generated.
INFO: [runtcl-4] Executing : report_drc -file sys_tst_rlink_n4d_drc_routed.rpt -pb sys_tst_rlink_n4d_drc_routed.pb -rpx sys_tst_rlink_n4d_drc_routed.rpx
Command: report_drc -file sys_tst_rlink_n4d_drc_routed.rpt -pb sys_tst_rlink_n4d_drc_routed.pb -rpx sys_tst_rlink_n4d_drc_routed.rpx
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_n4d_drc_routed.rpt.
report_drc completed successfully
INFO: [runtcl-4] Executing : report_methodology -file sys_tst_rlink_n4d_methodology_drc_routed.rpt -pb sys_tst_rlink_n4d_methodology_drc_routed.pb -rpx sys_tst_rlink_n4d_methodology_drc_routed.rpx
Command: report_methodology -file sys_tst_rlink_n4d_methodology_drc_routed.rpt -pb sys_tst_rlink_n4d_methodology_drc_routed.pb -rpx sys_tst_rlink_n4d_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 8 threads
INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /opt/walter/tmp/tmp/w11-test/v0.794/w11/rtl/sys_gen/tst_rlink/nexys4d/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_n4d_methodology_drc_routed.rpt.
report_methodology completed successfully
INFO: [runtcl-4] Executing : report_power -file sys_tst_rlink_n4d_power_routed.rpt -pb sys_tst_rlink_n4d_power_summary_routed.pb -rpx sys_tst_rlink_n4d_power_routed.rpx
Command: report_power -file sys_tst_rlink_n4d_power_routed.rpt -pb sys_tst_rlink_n4d_power_summary_routed.pb -rpx sys_tst_rlink_n4d_power_routed.rpx
INFO: [Power 33-23] Power model is not available for UA
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
113 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [runtcl-4] Executing : report_route_status -file sys_tst_rlink_n4d_route_status.rpt -pb sys_tst_rlink_n4d_route_status.pb
INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file sys_tst_rlink_n4d_timing_summary_routed.rpt -pb sys_tst_rlink_n4d_timing_summary_routed.pb -rpx sys_tst_rlink_n4d_timing_summary_routed.rpx -warn_on_violation 
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [runtcl-4] Executing : report_incremental_reuse -file sys_tst_rlink_n4d_incremental_reuse_routed.rpt
INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
INFO: [runtcl-4] Executing : report_clock_utilization -file sys_tst_rlink_n4d_clock_utilization_routed.rpt
INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file sys_tst_rlink_n4d_bus_skew_routed.rpt -pb sys_tst_rlink_n4d_bus_skew_routed.pb -rpx sys_tst_rlink_n4d_bus_skew_routed.rpx
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
INFO: [Common 17-206] Exiting Vivado at Thu Feb  9 12:13:32 2023...

*** Running vivado
    with args -log sys_tst_rlink_n4d.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source sys_tst_rlink_n4d.tcl -notrace


****** Vivado v2022.1 (64-bit)
  **** SW Build 3526262 on Mon Apr 18 15:47:01 MDT 2022
  **** IP Build 3524634 on Mon Apr 18 20:55:01 MDT 2022
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

source sys_tst_rlink_n4d.tcl -notrace
Command: open_checkpoint sys_tst_rlink_n4d_routed.dcp
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2604.250 ; gain = 0.000 ; free physical = 3235 ; free virtual = 21938
INFO: [Netlist 29-17] Analyzing 115 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2022.1
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF Files: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2668.281 ; gain = 0.000 ; free physical = 2054 ; free virtual = 20755
Restored from archive | CPU: 0.260000 secs | Memory: 4.493965 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2668.281 ; gain = 0.000 ; free physical = 2054 ; free virtual = 20755
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2668.281 ; gain = 0.000 ; free physical = 2043 ; free virtual = 20744
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 25 instances were transformed.
  RAM16X1S => RAM32X1S (RAMS32): 16 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 3 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 6 instances

INFO: [Project 1-604] Checkpoint was created with Vivado v2022.1 (64-bit) build 3526262
open_checkpoint: Time (s): cpu = 00:00:16 ; elapsed = 00:00:15 . Memory (MB): peak = 2668.281 ; gain = 75.930 ; free physical = 2040 ; free virtual = 20741
Command: write_bitstream -force sys_tst_rlink_n4d.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2022.1/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado 12-3199] DRC finished with 0 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Overwriting "TIMESTAMP" with "492EC397" for option USR_ACCESS
TIMESTAMP = Thu Feb  9 12:14:23 2023

Creating bitmap...
Creating bitstream...
Writing bitstream ./sys_tst_rlink_n4d.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
22 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:16 ; elapsed = 00:00:11 . Memory (MB): peak = 3131.227 ; gain = 462.945 ; free physical = 4231 ; free virtual = 22960
INFO: [Common 17-206] Exiting Vivado at Thu Feb  9 12:14:25 2023...
