Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
| Date         : Thu Feb  9 12:13:03 2023
| Host         : athome2 running 64-bit Ubuntu 20.04.5 LTS
| Command      : report_control_sets -verbose -file sys_tst_rlink_n4d_control_sets_placed.rpt
| Design       : sys_tst_rlink_n4d
| Device       : xc7a100t
----------------------------------------------------------------------------------------------

Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |    97 |
|    Minimum number of control sets                        |    97 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   251 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |    97 |
| >= 0 to < 4        |     1 |
| >= 4 to < 6        |    21 |
| >= 6 to < 8        |     6 |
| >= 8 to < 10       |    19 |
| >= 10 to < 12      |    10 |
| >= 12 to < 14      |    17 |
| >= 14 to < 16      |     2 |
| >= 16              |    21 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |             259 |          123 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |              54 |           23 |
| Yes          | No                    | No                     |             661 |          248 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |             207 |           79 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+-------------------+----------------------------------------------------------------+-------------------------------------------------------+------------------+----------------+--------------+
|    Clock Signal   |                          Enable Signal                         |                    Set/Reset Signal                   | Slice Load Count | Bel Load Count | Bels / Slice |
+-------------------+----------------------------------------------------------------+-------------------------------------------------------+------------------+----------------+--------------+
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_BREGS_reg[rbwe]_3                              |                                                       |                1 |              3 |         3.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/E[0]                                             | RLINK/CORE/RL/SR[0]                                   |                2 |              4 |         2.00 |
|  GEN_CLKSYS/CLKFX | CLKDIV/CE_MSEC                                                 |                                                       |                1 |              4 |         4.00 |
|  GEN_CLKSYS/CLKFX | SMRB.I0/SMRB/FSM_onehot_R_REGS[state][3]_i_1__1_n_0            |                                                       |                2 |              4 |         2.00 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/AB/FSM_onehot_R_REGS[state][3]_i_1_n_0      |                                                       |                2 |              4 |         2.00 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/TX/E[0]                                | RLINK/SERPORT/UART/RXTX/TX/R_REGS[bcnt][3]_i_1__0_n_0 |                2 |              4 |         2.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[rbsel]__0_1[0]                        | RLINK/CORE/RL/R_LREGS_reg[din][0]_1[0]                |                2 |              4 |         2.00 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/RX/ce_bcnt                             | RLINK/SERPORT/UART/RXTX/RX/R_REGS[bcnt][3]_i_1_n_0    |                1 |              4 |         4.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[stat]                                          |                                                       |                1 |              4 |         4.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/iram_we3_out                                     | RLINK/CORE/RL/SR[0]                                   |                3 |              4 |         1.33 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[swi_en]                                        |                                                       |                2 |              5 |         2.50 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/XONRX/E[0]                                       | RLINK/SERPORT/UART/AB/SR[0]                           |                2 |              5 |         2.50 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/XONTX/n[oval]12_out                              | RLINK/SERPORT/XONTX/R_REGS[obuf][7]_i_1_n_0           |                1 |              5 |         5.00 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/AB/n[mcnt]                                  | RLINK/SERPORT/UART/AB/R_REGS[mcnt][6]_i_1_n_0         |                3 |              5 |         1.67 |
|  GEN_CLKSYS/CLKFX | HIO/HIO/HIO/DEB.DEB_BTN/n[dref]                                |                                                       |                2 |              5 |         2.50 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/N_REGS[empty]                        |                                                       |                2 |              5 |         2.50 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/CD2B/R_REGS_reg[dataval]_0[0]                       | RLINK/SERPORT/UART/AB/SR[0]                           |                3 |              5 |         1.67 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_BREGS_reg[rbwe]_3                              | RLINK/CORE/RL/R_BREGS_reg[rbwe]_2                     |                3 |              5 |         1.67 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/N_REGS[empty]                                    | RLINK/SERPORT/UART/AB/SR[0]                           |                2 |              5 |         2.50 |
|  GEN_CLKSYS/CLKFX |                                                                | HIO/R_REGS[ledeff][6]_i_1_n_0                         |                2 |              5 |         2.50 |
|  GEN_CLKSYS/CLKFX |                                                                | HIO/HIO/HIO/DEB.DEB_BTN/n[dref]                       |                2 |              5 |         2.50 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_BREGS_reg[rbaval]_4                            |                                                       |                2 |              5 |         2.50 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[nbusy]                                         |                                                       |                1 |              6 |         6.00 |
|  GEN_CLKSYS/CLKFX |                                                                | RLINK/CORE/RL/R_BREGS[btocnt][5]_i_1_n_0              |                2 |              6 |         3.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/N_REGS[rbtake_1]                                 |                                                       |                2 |              6 |         3.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_BREGS_reg[rbre]_4                              |                                                       |                3 |              6 |         2.00 |
|  GEN_CLKSYS/CLKFX |                                                                | RLINK/SERPORT/UART/AB/SR[0]                           |                3 |              6 |         2.00 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_1_n_0 | RLINK/SERPORT/UART/AB/SR[0]                           |                3 |              7 |         2.33 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[din][7]_i_1_n_0                          |                                                       |                3 |              8 |         2.67 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[dsp_dp]                                        |                                                       |                3 |              8 |         2.67 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/RTBUF/n[lcmd]                                    |                                                       |                2 |              8 |         4.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/RTBUF/n[dinl]                                    |                                                       |                1 |              8 |         8.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[rcmd]                                          |                                                       |                4 |              8 |         2.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[rdiv]                                          |                                                       |                2 |              8 |         4.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[atocnt][7]_i_1_n_0                       |                                                       |                5 |              8 |         1.60 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/RX/E[0]                                | RLINK/SERPORT/UART/AB/SR[0]                           |                2 |              8 |         4.00 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/TX/R_REGS[sreg][7]_i_1_n_0             |                                                       |                3 |              8 |         2.67 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/RX/n[sreg]                             |                                                       |                2 |              8 |         4.00 |
|  GEN_CLKSYS/CLKFX | RBDTST/EMON/n[rdivcnt]                                         |                                                       |                4 |              8 |         2.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[cnt][15]_i_1_n_0                         |                                                       |                3 |              8 |         2.67 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[din][15]_i_1_n_0                         |                                                       |                2 |              8 |         4.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state_n_0_][6]            |                                                       |                1 |              8 |         8.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[cnt][7]_i_1_n_0                          |                                                       |                3 |              8 |         2.67 |
|  GEN_CLKSYS/CLKFX | RBDTST/EMON/R_REGS[laddr][8]_i_1_n_0                           |                                                       |                4 |              9 |         2.25 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/R_REGS_reg[full]_0[0]                |                                                       |                6 |              9 |         1.50 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[swi]                                           |                                                       |                2 |              9 |         4.50 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[rbsel]_2                              |                                                       |                6 |              9 |         1.50 |
|  GEN_CLKSYS/CLKFX | RBDTST/MON/R_REGS[rbnbusy][9]_i_2_n_0                          | RBDTST/MON/R_REGS[rbnbusy][9]_i_1_n_0                 |                3 |             10 |         3.33 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state][1]_0[0]            |                                                       |                5 |             10 |         2.00 |
|  GEN_CLKSYS/CLKFX | RBDTST/BRAM/n[addr]                                            |                                                       |                7 |             10 |         1.43 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/SEL__0/n[anena]                                  |                                                       |                3 |             10 |         3.33 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS_reg[addr][0]_rep_6[0]                    | RLINK/CORE/RL/R_LREGS_reg[din][0]_1[0]                |                4 |             10 |         2.50 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[ncyc]0                                |                                                       |                3 |             10 |         3.33 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_BREGS_reg[rbwe]_4                              |                                                       |                4 |             10 |         2.50 |
|  GEN_CLKSYS/CLKFX | CLKDIV/n[mcnt]                                                 |                                                       |                4 |             10 |         2.50 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/dcnt_inc                                         | RLINK/CORE/RL/dcnt_clear                              |                4 |             11 |         2.75 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_BREGS[cnt][10]_i_1_n_0                         |                                                       |                4 |             11 |         2.75 |
|  GEN_CLKSYS/CLKFX | IOB_RS232/IOB_RXD/IOB/RXD                                      | RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][12]_i_1_n_0   |                3 |             12 |         4.00 |
|  GEN_CLKSYS/CLKFX | CLKDIV/CE_USEC                                                 |                                                       |                4 |             12 |         3.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][21]    |                                                       |                6 |             12 |         2.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[dimg]                                          |                                                       |                3 |             12 |         4.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/ICRC/E[0]                                        | RLINK/CORE/RL/ICRC/R_REGS_reg[dataval][0]             |                5 |             12 |         2.40 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[dimb]                                          |                                                       |                4 |             12 |         3.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[dimr]                                          |                                                       |                4 |             12 |         3.00 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/AB/iram_we_0                                |                                                       |                2 |             12 |         6.00 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/AB/iram_we                                  |                                                       |                2 |             12 |         6.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[rbsel]_4                              |                                                       |                4 |             12 |         3.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/E[0]                                 | RLINK/CORE/B2CD/SR[0]                                 |                4 |             12 |         3.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[rbsel]_7                              |                                                       |                4 |             12 |         3.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[rbsel]_8                              |                                                       |                3 |             12 |         4.00 |
|  GEN_CLKSYS/CLKFX | SMRB.I0/SMRB/n[temp]                                           |                                                       |                6 |             12 |         2.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state_n_0_][5]            |                                                       |                3 |             12 |         4.00 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/XONTX/E[0]                                       | RLINK/SERPORT/UART/AB/SR[0]                           |                4 |             13 |         3.25 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/FSM_onehot_R_BREGS[state][12]_i_1_n_0            |                                                       |                5 |             13 |         2.60 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_BREGS_reg[rbaval]_3[0]                         | RLINK/CORE/RL/R_BREGS_reg[rbaval]_1                   |                5 |             14 |         2.80 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/AB/n[ccnt]                                  |                                                       |                4 |             15 |         3.75 |
|  GEN_CLKSYS/CLKFX |                                                                | HIO/HIO/HIO/DEB.DEB_SWI/n[dref]                       |                8 |             16 |         2.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][13][0] | RLINK/CORE/RL/crcreset                                |                6 |             16 |         2.67 |
|  GEN_CLKSYS/CLKFX |                                                                | HIO/R_REGS[dateff][15]_i_1_n_0                        |                6 |             16 |         2.67 |
|  GEN_CLKSYS/CLKFX | RBDTST/TIM0/R_REGS[timer][15]_i_1_n_0                          |                                                       |                6 |             16 |         2.67 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[rbsel]__0_2[0]                        | RLINK/CORE/RL/R_LREGS_reg[din][1]_4[0]                |                5 |             16 |         3.20 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/ICRC/icrcena                                     | RLINK/CORE/RL/crcreset                                |                7 |             16 |         2.29 |
|  GEN_CLKSYS/CLKFX | SMRB.I0/SM_EOS                                                 |                                                       |                5 |             16 |         3.20 |
|  GEN_CLKSYS/CLKFX | HIO/HIO/HIO/DEB.DEB_SWI/n[dref]                                |                                                       |                7 |             16 |         2.29 |
|  GEN_CLKSYS/CLKFX | RBDTST/TIM1/R_REGS[timer][15]_i_1__0_n_0                       |                                                       |                7 |             16 |         2.29 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[rbdata]0                              |                                                       |                9 |             16 |         1.78 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[rbsel]_5                              |                                                       |                3 |             16 |         5.33 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[rbsel]_9                              |                                                       |                2 |             16 |         8.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[rbdout]                                        |                                                       |                8 |             16 |         2.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/iram_we3_out                                     |                                                       |                4 |             16 |         4.00 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[lolim]                                         |                                                       |                5 |             16 |         3.20 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[led]                                           |                                                       |                7 |             16 |         2.29 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[hilim]                                         |                                                       |                5 |             16 |         3.20 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_BREGS_reg[state][6]     |                                                       |                4 |             17 |         4.25 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[addrsame]0                            |                                                       |                5 |             17 |         3.40 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/R_REGS_reg[dataval]                  |                                                       |               20 |             39 |         1.95 |
|  GEN_CLKSYS/CLKFX |                                                                |                                                       |              123 |            259 |         2.11 |
+-------------------+----------------------------------------------------------------+-------------------------------------------------------+------------------+----------------+--------------+


