Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017
| Date         : Sun Feb 10 12:40:06 2019
| Host         : athome running 64-bit Ubuntu 16.04.5 LTS
| Command      : report_timing_summary -warn_on_violation -max_paths 10 -file sys_w11a_b3_timing_summary_routed.rpt -rpx sys_w11a_b3_timing_summary_routed.rpx
| Design       : sys_w11a_b3
| Device       : 7a35t-cpg236
| Speed File   : -1  PRODUCTION 1.17 2017-05-11
---------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  false

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
--------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock
--------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
--------------------------
 There are 22 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
 There are 29 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
--------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops
------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.290        0.000                      0                 8715        0.055        0.000                      0                 8666        2.917        0.000                       0                  3028  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock         Waveform(ns)         Period(ns)      Frequency(MHz)
-----         ------------         ----------      --------------
I_CLK100      {0.000 5.000}        10.000          100.000         
  CLKFBOUT    {0.000 5.000}        10.000          100.000         
  CLKFBOUT_1  {0.000 5.000}        10.000          100.000         
  CLKOUT0     {0.000 6.250}        12.500          80.000          
  CLKOUT0_1   {0.000 4.167}        8.333           120.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
I_CLK100                                                                                                                                                        3.000        0.000                       0                     2  
  CLKFBOUT                                                                                                                                                      7.845        0.000                       0                     3  
  CLKFBOUT_1                                                                                                                                                    7.845        0.000                       0                     3  
  CLKOUT0           0.290        0.000                      0                 8190        0.055        0.000                      0                 8190        5.000        0.000                       0                  2805  
  CLKOUT0_1         1.110        0.000                      0                  476        0.119        0.000                      0                  476        2.917        0.000                       0                   215  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
CLKOUT0_1     CLKOUT0             2.548        0.000                      0                   45                                                                        
CLKOUT0       CLKOUT0_1           4.628        0.000                      0                   23                                                                        


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  I_CLK100
  To Clock:  I_CLK100

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        3.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         I_CLK100
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { I_CLK100 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     MMCME2_ADV/CLKIN1  n/a            1.249         10.000      8.751      MMCME2_ADV_X1Y0  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKIN1
Min Period        n/a     PLLE2_ADV/CLKIN1   n/a            1.249         10.000      8.751      PLLE2_ADV_X1Y0   GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKIN1
Max Period        n/a     PLLE2_ADV/CLKIN1   n/a            52.633        10.000      42.633     PLLE2_ADV_X1Y0   GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKIN1
Max Period        n/a     MMCME2_ADV/CLKIN1  n/a            100.000       10.000      90.000     MMCME2_ADV_X1Y0  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKIN1
Low Pulse Width   Fast    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y0  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKIN1
Low Pulse Width   Fast    PLLE2_ADV/CLKIN1   n/a            2.000         5.000       3.000      PLLE2_ADV_X1Y0   GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKIN1
Low Pulse Width   Slow    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y0  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKIN1
Low Pulse Width   Slow    PLLE2_ADV/CLKIN1   n/a            2.000         5.000       3.000      PLLE2_ADV_X1Y0   GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKIN1
High Pulse Width  Slow    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y0  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKIN1
High Pulse Width  Slow    PLLE2_ADV/CLKIN1   n/a            2.000         5.000       3.000      PLLE2_ADV_X1Y0   GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKIN1
High Pulse Width  Fast    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y0  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKIN1
High Pulse Width  Fast    PLLE2_ADV/CLKIN1   n/a            2.000         5.000       3.000      PLLE2_ADV_X1Y0   GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  CLKFBOUT
  To Clock:  CLKFBOUT

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        7.845ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         CLKFBOUT
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFG/I               n/a            2.155         10.000      7.845      BUFGCTRL_X0Y2    GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKFB/I
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         10.000      8.751      MMCME2_ADV_X1Y0  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKFBOUT
Min Period  n/a     MMCME2_ADV/CLKFBIN   n/a            1.249         10.000      8.751      MMCME2_ADV_X1Y0  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKFBIN
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       10.000      90.000     MMCME2_ADV_X1Y0  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKFBIN
Max Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            213.360       10.000      203.360    MMCME2_ADV_X1Y0  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKFBOUT



---------------------------------------------------------------------------------------------------
From Clock:  CLKFBOUT_1
  To Clock:  CLKFBOUT_1

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        7.845ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         CLKFBOUT_1
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKFBOUT }

Check Type  Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period  n/a     BUFG/I              n/a            2.155         10.000      7.845      BUFGCTRL_X0Y3   GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKFB/I
Min Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            1.249         10.000      8.751      PLLE2_ADV_X1Y0  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKFBOUT
Min Period  n/a     PLLE2_ADV/CLKFBIN   n/a            1.249         10.000      8.751      PLLE2_ADV_X1Y0  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKFBIN
Max Period  n/a     PLLE2_ADV/CLKFBIN   n/a            52.633        10.000      42.633     PLLE2_ADV_X1Y0  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKFBIN
Max Period  n/a     PLLE2_ADV/CLKFBOUT  n/a            160.000       10.000      150.000    PLLE2_ADV_X1Y0  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKFBOUT



---------------------------------------------------------------------------------------------------
From Clock:  CLKOUT0
  To Clock:  CLKOUT0

Setup :            0  Failing Endpoints,  Worst Slack        0.290ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.055ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        5.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.290ns  (required time - arrival time)
  Source:                 SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/RAM_reg_0_63_1_1/SP/I
                            (rising edge-triggered cell RAMS64E clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (CLKOUT0 rise@12.500ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        11.772ns  (logic 2.848ns (24.194%)  route 8.924ns (75.806%))
  Logic Levels:           16  (CARRY4=1 LUT3=3 LUT4=3 LUT5=3 LUT6=5 RAMS64E=1)
  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.545ns = ( 10.955 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.953ns
    Clock Pessimism Removal (CPR):    0.564ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.691    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.961    -4.269 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.608    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.512 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.559    -0.953    SYS70/W11A/SEQ/CLK0
    SLICE_X45Y33         FDRE                                         r  SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y33         FDRE (Prop_fdre_C_Q)         0.456    -0.497 r  SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[25]/Q
                         net (fo=11, routed)          1.037     0.541    SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg_n_0_[25]
    SLICE_X45Y30         LUT5 (Prop_lut5_I0_O)        0.124     0.665 r  SYS70/W11A/SEQ/FSM_onehot_R_STATE[28]_i_2/O
                         net (fo=8, routed)           0.339     1.004    SYS70/W11A/SEQ/FSM_onehot_R_STATE[28]_i_2_n_0
    SLICE_X45Y29         LUT3 (Prop_lut3_I1_O)        0.124     1.128 r  SYS70/W11A/SEQ/FSM_onehot_R_STATE[85]_i_2/O
                         net (fo=9, routed)           0.358     1.486    SYS70/W11A/SEQ/FSM_onehot_R_STATE[85]_i_2_n_0
    SLICE_X46Y30         LUT6 (Prop_lut6_I0_O)        0.124     1.610 r  SYS70/W11A/SEQ/FSM_onehot_R_STATE[95]_i_2/O
                         net (fo=8, routed)           0.335     1.945    SYS70/W11A/SEQ/FSM_onehot_R_STATE[95]_i_2_n_0
    SLICE_X46Y31         LUT5 (Prop_lut5_I0_O)        0.124     2.069 r  SYS70/W11A/SEQ/RAM_reg_0_15_0_0_i_59/O
                         net (fo=3, routed)           0.655     2.724    SYS70/W11A/SEQ/RAM_reg_0_15_0_0_i_59_n_0
    SLICE_X47Y31         LUT4 (Prop_lut4_I0_O)        0.124     2.848 r  SYS70/W11A/SEQ/FSM_onehot_R_STATE[63]_i_2/O
                         net (fo=10, routed)          0.653     3.501    SYS70/W11A/SEQ/FSM_onehot_R_STATE[63]_i_2_n_0
    SLICE_X48Y31         LUT6 (Prop_lut6_I5_O)        0.124     3.625 r  SYS70/W11A/SEQ/R_SSR0[seg_mode][1]_i_8/O
                         net (fo=6, routed)           0.468     4.093    SYS70/W11A/SEQ/R_SSR0[seg_mode][1]_i_8_n_0
    SLICE_X49Y33         LUT4 (Prop_lut4_I0_O)        0.124     4.217 r  SYS70/W11A/SEQ/R_SSR0[seg_mode][1]_i_5/O
                         net (fo=9, routed)           0.349     4.566    SYS70/W11A/SEQ/R_SSR0[seg_mode][1]_i_5_n_0
    SLICE_X48Y35         LUT6 (Prop_lut6_I5_O)        0.124     4.690 r  SYS70/W11A/SEQ/R_SSR0[seg_mode][1]_i_1/O
                         net (fo=5, routed)           0.456     5.146    SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][1][1]
    SLICE_X50Y35         LUT6 (Prop_lut6_I1_O)        0.124     5.270 r  SYS70/W11A/SEQ/RAM_reg_0_63_0_0_i_8/O
                         net (fo=2, routed)           0.314     5.584    SYS70/W11A/VMBOX/MMU/SADR/SAR_HIGH/iasn_reg[0]
    SLICE_X49Y35         LUT6 (Prop_lut6_I5_O)        0.124     5.708 r  SYS70/W11A/VMBOX/MMU/SADR/SAR_HIGH/RAM_reg_0_63_0_0_i_5/O
                         net (fo=29, routed)          1.005     6.713    SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/RAM_reg_0_63_0_0/A3
    SLICE_X52Y38         RAMS64E (Prop_rams64e_ADR3_O)
                                                      0.124     6.837 r  SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/RAM_reg_0_63_0_0/SP/O
                         net (fo=5, routed)           0.828     7.665    SYS70/W11A/DPATH/GPR/DO[0]
    SLICE_X53Y39         LUT4 (Prop_lut4_I1_O)        0.124     7.789 r  SYS70/W11A/DPATH/GPR/abo_length0_carry_i_8/O
                         net (fo=1, routed)           0.000     7.789    SYS70/W11A/VMBOX/MMU/R_DSRC_reg[12][0]
    SLICE_X53Y39         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     8.321 f  SYS70/W11A/VMBOX/MMU/abo_length0_carry/CO[3]
                         net (fo=2, routed)           0.906     9.227    SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/CO[0]
    SLICE_X54Y39         LUT3 (Prop_lut3_I0_O)        0.124     9.351 f  SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/RAM_reg_0_63_0_0_i_6__0/O
                         net (fo=1, routed)           0.312     9.663    SYS70/W11A/VMBOX/MMU/SADR/SDR_LOW/R_REGS_reg[mdin][3]
    SLICE_X54Y40         LUT5 (Prop_lut5_I0_O)        0.124     9.787 r  SYS70/W11A/VMBOX/MMU/SADR/SDR_LOW/RAM_reg_0_63_0_0_i_5__0/O
                         net (fo=4, routed)           0.426    10.213    SYS70/W11A/VMBOX/MMU/SADR/SDR_LOW/R_REGS_reg[trap_mmu]
    SLICE_X55Y39         LUT3 (Prop_lut3_I1_O)        0.124    10.337 r  SYS70/W11A/VMBOX/MMU/SADR/SDR_LOW/RAM_reg_0_63_1_1_i_1/O
                         net (fo=1, routed)           0.482    10.819    SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/RAM_reg_0_63_1_1/D
    SLICE_X52Y40         RAMS64E                                      r  SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/RAM_reg_0_63_1_1/SP/I
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)   12.500    12.500 r  
    W5                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    13.888 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.162    15.050    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.217     7.832 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     9.414    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     9.505 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.450    10.955    SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/RAM_reg_0_63_1_1/WCLK
    SLICE_X52Y40         RAMS64E                                      r  SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/RAM_reg_0_63_1_1/SP/CLK
                         clock pessimism              0.564    11.518    
                         clock uncertainty           -0.082    11.436    
    SLICE_X52Y40         RAMS64E (Setup_rams64e_CLK_I)
                                                     -0.327    11.109    SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/RAM_reg_0_63_1_1/SP
  -------------------------------------------------------------------
                         required time                         11.109    
                         arrival time                         -10.819    
  -------------------------------------------------------------------
                         slack                                  0.290    

Slack (MET) :             0.362ns  (required time - arrival time)
  Source:                 SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/CACHE/CMEM_DAT1/sv_ram_reg/DIADI[4]
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (CLKOUT0 rise@12.500ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        11.786ns  (logic 4.747ns (40.276%)  route 7.039ns (59.724%))
  Logic Levels:           13  (CARRY4=2 LUT2=1 LUT3=2 LUT4=1 LUT5=1 LUT6=6)
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.505ns = ( 10.995 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.899ns
    Clock Pessimism Removal (CPR):    0.578ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.691    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.961    -4.269 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.608    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.512 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.613    -0.899    SYS70/CACHE/CMEM_DAT3/CLK0
    RAMB18_X1Y16         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X1Y16         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[0])
                                                      2.454     1.555 r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/DOADO[0]
                         net (fo=2, routed)           1.172     2.727    SYS70/CACHE/CMEM_DAT3/CMEM_DOA_3[0]
    SLICE_X48Y37         LUT6 (Prop_lut6_I0_O)        0.124     2.851 r  SYS70/CACHE/CMEM_DAT3/R_IREG[8]_i_2/O
                         net (fo=1, routed)           0.715     3.565    SYS70/W11A/VMBOX/EM_SRES[dout][8]
    SLICE_X46Y34         LUT4 (Prop_lut4_I2_O)        0.124     3.689 r  SYS70/W11A/VMBOX/R_IREG[8]_i_1/O
                         net (fo=6, routed)           0.201     3.891    SYS70/W11A/VMBOX/VM_DOUT[8]
    SLICE_X46Y34         LUT6 (Prop_lut6_I5_O)        0.124     4.015 r  SYS70/W11A/VMBOX/R_IREG[0]_i_1/O
                         net (fo=3, routed)           0.424     4.438    SYS70/W11A/SEQ/VM_DOUT[0]
    SLICE_X47Y35         LUT6 (Prop_lut6_I2_O)        0.124     4.562 r  SYS70/W11A/SEQ/i__carry_i_4__0/O
                         net (fo=3, routed)           0.420     4.983    SYS70/W11A/SEQ/mb[0]
    SLICE_X47Y36         LUT2 (Prop_lut2_I1_O)        0.124     5.107 r  SYS70/W11A/SEQ/sum0_carry_i_8/O
                         net (fo=1, routed)           0.000     5.107    SYS70/W11A/DPATH/OUNIT/S[0]
    SLICE_X47Y36         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     5.639 r  SYS70/W11A/DPATH/OUNIT/sum0_carry/CO[3]
                         net (fo=1, routed)           0.000     5.639    SYS70/W11A/DPATH/OUNIT/sum0_carry_n_0
    SLICE_X47Y37         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.222     5.861 r  SYS70/W11A/DPATH/OUNIT/sum0_carry__0/O[0]
                         net (fo=2, routed)           0.871     6.732    SYS70/W11A/DPATH/OUNIT/sum00_out[4]
    SLICE_X50Y36         LUT3 (Prop_lut3_I0_O)        0.299     7.031 r  SYS70/W11A/DPATH/OUNIT/R_REGS[mdin][4]_i_7/O
                         net (fo=1, routed)           0.303     7.334    SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[106]_12
    SLICE_X49Y36         LUT5 (Prop_lut5_I4_O)        0.124     7.458 r  SYS70/W11A/SEQ/R_REGS[mdin][4]_i_3/O
                         net (fo=1, routed)           0.313     7.771    SYS70/W11A/SEQ/R_REGS[mdin][4]_i_3_n_0
    SLICE_X51Y35         LUT6 (Prop_lut6_I0_O)        0.124     7.895 r  SYS70/W11A/SEQ/R_REGS[mdin][4]_i_2/O
                         net (fo=16, routed)          1.122     9.017    SYS70/W11A/SEQ/R_CPDOUT_reg[4][4]
    SLICE_X54Y43         LUT6 (Prop_lut6_I0_O)        0.124     9.141 r  SYS70/W11A/SEQ/R_REGS[mdin][12]_i_4/O
                         net (fo=1, routed)           0.493     9.634    SYS70/W11A/SEQ/R_REGS[mdin][12]_i_4_n_0
    SLICE_X54Y43         LUT6 (Prop_lut6_I5_O)        0.124     9.758 r  SYS70/W11A/SEQ/R_REGS[mdin][12]_i_3/O
                         net (fo=2, routed)           0.172     9.930    SYS70/W11A/SEQ/R_REGS[mdin][12]_i_3_n_0
    SLICE_X54Y43         LUT3 (Prop_lut3_I2_O)        0.124    10.054 r  SYS70/W11A/SEQ/sv_ram_reg_i_4__0/O
                         net (fo=3, routed)           0.833    10.887    SYS70/CACHE/CMEM_DAT1/D[4]
    RAMB18_X1Y15         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT1/sv_ram_reg/DIADI[4]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)   12.500    12.500 r  
    W5                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    13.888 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.162    15.050    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.217     7.832 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     9.414    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     9.505 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.491    10.995    SYS70/CACHE/CMEM_DAT1/CLK0
    RAMB18_X1Y15         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT1/sv_ram_reg/CLKARDCLK
                         clock pessimism              0.578    11.573    
                         clock uncertainty           -0.082    11.491    
    RAMB18_X1Y15         RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[4])
                                                     -0.241    11.250    SYS70/CACHE/CMEM_DAT1/sv_ram_reg
  -------------------------------------------------------------------
                         required time                         11.250    
                         arrival time                         -10.887    
  -------------------------------------------------------------------
                         slack                                  0.362    

Slack (MET) :             0.545ns  (required time - arrival time)
  Source:                 SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/CACHE/CMEM_DAT3/sv_ram_reg/DIADI[7]
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (CLKOUT0 rise@12.500ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        11.631ns  (logic 5.103ns (43.873%)  route 6.528ns (56.127%))
  Logic Levels:           13  (CARRY4=2 LUT2=1 LUT3=2 LUT4=2 LUT6=5 MUXF7=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.502ns = ( 10.998 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.899ns
    Clock Pessimism Removal (CPR):    0.603ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.691    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.961    -4.269 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.608    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.512 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.613    -0.899    SYS70/CACHE/CMEM_DAT3/CLK0
    RAMB18_X1Y16         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X1Y16         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[0])
                                                      2.454     1.555 r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/DOADO[0]
                         net (fo=2, routed)           1.172     2.727    SYS70/CACHE/CMEM_DAT3/CMEM_DOA_3[0]
    SLICE_X48Y37         LUT6 (Prop_lut6_I0_O)        0.124     2.851 r  SYS70/CACHE/CMEM_DAT3/R_IREG[8]_i_2/O
                         net (fo=1, routed)           0.715     3.565    SYS70/W11A/VMBOX/EM_SRES[dout][8]
    SLICE_X46Y34         LUT4 (Prop_lut4_I2_O)        0.124     3.689 r  SYS70/W11A/VMBOX/R_IREG[8]_i_1/O
                         net (fo=6, routed)           0.201     3.891    SYS70/W11A/VMBOX/VM_DOUT[8]
    SLICE_X46Y34         LUT6 (Prop_lut6_I5_O)        0.124     4.015 r  SYS70/W11A/VMBOX/R_IREG[0]_i_1/O
                         net (fo=3, routed)           0.424     4.438    SYS70/W11A/SEQ/VM_DOUT[0]
    SLICE_X47Y35         LUT6 (Prop_lut6_I2_O)        0.124     4.562 r  SYS70/W11A/SEQ/i__carry_i_4__0/O
                         net (fo=3, routed)           0.420     4.983    SYS70/W11A/SEQ/mb[0]
    SLICE_X47Y36         LUT2 (Prop_lut2_I1_O)        0.124     5.107 r  SYS70/W11A/SEQ/sum0_carry_i_8/O
                         net (fo=1, routed)           0.000     5.107    SYS70/W11A/DPATH/OUNIT/S[0]
    SLICE_X47Y36         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     5.639 r  SYS70/W11A/DPATH/OUNIT/sum0_carry/CO[3]
                         net (fo=1, routed)           0.000     5.639    SYS70/W11A/DPATH/OUNIT/sum0_carry_n_0
    SLICE_X47Y37         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.313     5.952 r  SYS70/W11A/DPATH/OUNIT/sum0_carry__0/O[3]
                         net (fo=2, routed)           0.807     6.758    SYS70/W11A/DPATH/OUNIT/sum00_out[7]
    SLICE_X51Y38         LUT3 (Prop_lut3_I0_O)        0.306     7.064 r  SYS70/W11A/DPATH/OUNIT/RAM_reg_0_15_7_7_i_6__0/O
                         net (fo=1, routed)           0.580     7.644    SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[106]_4
    SLICE_X54Y39         LUT6 (Prop_lut6_I5_O)        0.124     7.768 r  SYS70/W11A/SEQ/RAM_reg_0_15_7_7_i_2/O
                         net (fo=1, routed)           0.000     7.768    SYS70/W11A/SEQ/RAM_reg_0_15_7_7_i_2_n_0
    SLICE_X54Y39         MUXF7 (Prop_muxf7_I0_O)      0.209     7.977 r  SYS70/W11A/SEQ/RAM_reg_0_15_7_7_i_1/O
                         net (fo=15, routed)          0.859     8.836    SYS70/W11A/SEQ/R_CPDOUT_reg[7]
    SLICE_X55Y42         LUT4 (Prop_lut4_I0_O)        0.297     9.133 r  SYS70/W11A/SEQ/R_REGS[mdin][15]_i_3/O
                         net (fo=3, routed)           0.285     9.418    SYS70/W11A/VMBOX/R_DSRC_reg[0]_6
    SLICE_X55Y42         LUT6 (Prop_lut6_I4_O)        0.124     9.542 r  SYS70/W11A/VMBOX/R_REGS[mdin][15]_i_4/O
                         net (fo=2, routed)           0.373     9.915    SYS70/W11A/VMBOX/R_REGS[mdin][15]_i_4_n_0
    SLICE_X54Y42         LUT3 (Prop_lut3_I2_O)        0.124    10.039 r  SYS70/W11A/VMBOX/sv_ram_reg_i_1__0/O
                         net (fo=3, routed)           0.694    10.732    SYS70/CACHE/CMEM_DAT3/D[7]
    RAMB18_X1Y16         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/DIADI[7]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)   12.500    12.500 r  
    W5                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    13.888 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.162    15.050    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.217     7.832 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     9.414    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     9.505 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.494    10.998    SYS70/CACHE/CMEM_DAT3/CLK0
    RAMB18_X1Y16         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
                         clock pessimism              0.603    11.601    
                         clock uncertainty           -0.082    11.519    
    RAMB18_X1Y16         RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7])
                                                     -0.241    11.278    SYS70/CACHE/CMEM_DAT3/sv_ram_reg
  -------------------------------------------------------------------
                         required time                         11.278    
                         arrival time                         -10.732    
  -------------------------------------------------------------------
                         slack                                  0.545    

Slack (MET) :             0.551ns  (required time - arrival time)
  Source:                 SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/CACHE/CMEM_DAT1/sv_ram_reg/DIADI[7]
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (CLKOUT0 rise@12.500ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        11.597ns  (logic 5.103ns (44.002%)  route 6.494ns (55.998%))
  Logic Levels:           13  (CARRY4=2 LUT2=1 LUT3=2 LUT4=2 LUT6=5 MUXF7=1)
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.505ns = ( 10.995 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.899ns
    Clock Pessimism Removal (CPR):    0.578ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.691    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.961    -4.269 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.608    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.512 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.613    -0.899    SYS70/CACHE/CMEM_DAT3/CLK0
    RAMB18_X1Y16         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X1Y16         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[0])
                                                      2.454     1.555 r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/DOADO[0]
                         net (fo=2, routed)           1.172     2.727    SYS70/CACHE/CMEM_DAT3/CMEM_DOA_3[0]
    SLICE_X48Y37         LUT6 (Prop_lut6_I0_O)        0.124     2.851 r  SYS70/CACHE/CMEM_DAT3/R_IREG[8]_i_2/O
                         net (fo=1, routed)           0.715     3.565    SYS70/W11A/VMBOX/EM_SRES[dout][8]
    SLICE_X46Y34         LUT4 (Prop_lut4_I2_O)        0.124     3.689 r  SYS70/W11A/VMBOX/R_IREG[8]_i_1/O
                         net (fo=6, routed)           0.201     3.891    SYS70/W11A/VMBOX/VM_DOUT[8]
    SLICE_X46Y34         LUT6 (Prop_lut6_I5_O)        0.124     4.015 r  SYS70/W11A/VMBOX/R_IREG[0]_i_1/O
                         net (fo=3, routed)           0.424     4.438    SYS70/W11A/SEQ/VM_DOUT[0]
    SLICE_X47Y35         LUT6 (Prop_lut6_I2_O)        0.124     4.562 r  SYS70/W11A/SEQ/i__carry_i_4__0/O
                         net (fo=3, routed)           0.420     4.983    SYS70/W11A/SEQ/mb[0]
    SLICE_X47Y36         LUT2 (Prop_lut2_I1_O)        0.124     5.107 r  SYS70/W11A/SEQ/sum0_carry_i_8/O
                         net (fo=1, routed)           0.000     5.107    SYS70/W11A/DPATH/OUNIT/S[0]
    SLICE_X47Y36         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     5.639 r  SYS70/W11A/DPATH/OUNIT/sum0_carry/CO[3]
                         net (fo=1, routed)           0.000     5.639    SYS70/W11A/DPATH/OUNIT/sum0_carry_n_0
    SLICE_X47Y37         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.313     5.952 r  SYS70/W11A/DPATH/OUNIT/sum0_carry__0/O[3]
                         net (fo=2, routed)           0.807     6.758    SYS70/W11A/DPATH/OUNIT/sum00_out[7]
    SLICE_X51Y38         LUT3 (Prop_lut3_I0_O)        0.306     7.064 r  SYS70/W11A/DPATH/OUNIT/RAM_reg_0_15_7_7_i_6__0/O
                         net (fo=1, routed)           0.580     7.644    SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[106]_4
    SLICE_X54Y39         LUT6 (Prop_lut6_I5_O)        0.124     7.768 r  SYS70/W11A/SEQ/RAM_reg_0_15_7_7_i_2/O
                         net (fo=1, routed)           0.000     7.768    SYS70/W11A/SEQ/RAM_reg_0_15_7_7_i_2_n_0
    SLICE_X54Y39         MUXF7 (Prop_muxf7_I0_O)      0.209     7.977 r  SYS70/W11A/SEQ/RAM_reg_0_15_7_7_i_1/O
                         net (fo=15, routed)          0.859     8.836    SYS70/W11A/SEQ/R_CPDOUT_reg[7]
    SLICE_X55Y42         LUT4 (Prop_lut4_I0_O)        0.297     9.133 r  SYS70/W11A/SEQ/R_REGS[mdin][15]_i_3/O
                         net (fo=3, routed)           0.285     9.418    SYS70/W11A/VMBOX/R_DSRC_reg[0]_6
    SLICE_X55Y42         LUT6 (Prop_lut6_I4_O)        0.124     9.542 r  SYS70/W11A/VMBOX/R_REGS[mdin][15]_i_4/O
                         net (fo=2, routed)           0.373     9.915    SYS70/W11A/VMBOX/R_REGS[mdin][15]_i_4_n_0
    SLICE_X54Y42         LUT3 (Prop_lut3_I2_O)        0.124    10.039 r  SYS70/W11A/VMBOX/sv_ram_reg_i_1__0/O
                         net (fo=3, routed)           0.660    10.698    SYS70/CACHE/CMEM_DAT1/D[7]
    RAMB18_X1Y15         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT1/sv_ram_reg/DIADI[7]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)   12.500    12.500 r  
    W5                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    13.888 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.162    15.050    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.217     7.832 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     9.414    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     9.505 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.491    10.995    SYS70/CACHE/CMEM_DAT1/CLK0
    RAMB18_X1Y15         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT1/sv_ram_reg/CLKARDCLK
                         clock pessimism              0.578    11.573    
                         clock uncertainty           -0.082    11.491    
    RAMB18_X1Y15         RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[7])
                                                     -0.241    11.250    SYS70/CACHE/CMEM_DAT1/sv_ram_reg
  -------------------------------------------------------------------
                         required time                         11.250    
                         arrival time                         -10.698    
  -------------------------------------------------------------------
                         slack                                  0.551    

Slack (MET) :             0.555ns  (required time - arrival time)
  Source:                 SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[25]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/RAM_reg_0_63_0_0/SP/I
                            (rising edge-triggered cell RAMS64E clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (CLKOUT0 rise@12.500ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        11.650ns  (logic 2.848ns (24.447%)  route 8.802ns (75.553%))
  Logic Levels:           16  (CARRY4=1 LUT3=2 LUT4=4 LUT5=3 LUT6=5 RAMS64E=1)
  Clock Path Skew:        -0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.545ns = ( 10.955 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.953ns
    Clock Pessimism Removal (CPR):    0.564ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.691    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.961    -4.269 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.608    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.512 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.559    -0.953    SYS70/W11A/SEQ/CLK0
    SLICE_X45Y33         FDRE                                         r  SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[25]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X45Y33         FDRE (Prop_fdre_C_Q)         0.456    -0.497 r  SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[25]/Q
                         net (fo=11, routed)          1.037     0.541    SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg_n_0_[25]
    SLICE_X45Y30         LUT5 (Prop_lut5_I0_O)        0.124     0.665 r  SYS70/W11A/SEQ/FSM_onehot_R_STATE[28]_i_2/O
                         net (fo=8, routed)           0.339     1.004    SYS70/W11A/SEQ/FSM_onehot_R_STATE[28]_i_2_n_0
    SLICE_X45Y29         LUT3 (Prop_lut3_I1_O)        0.124     1.128 r  SYS70/W11A/SEQ/FSM_onehot_R_STATE[85]_i_2/O
                         net (fo=9, routed)           0.358     1.486    SYS70/W11A/SEQ/FSM_onehot_R_STATE[85]_i_2_n_0
    SLICE_X46Y30         LUT6 (Prop_lut6_I0_O)        0.124     1.610 r  SYS70/W11A/SEQ/FSM_onehot_R_STATE[95]_i_2/O
                         net (fo=8, routed)           0.335     1.945    SYS70/W11A/SEQ/FSM_onehot_R_STATE[95]_i_2_n_0
    SLICE_X46Y31         LUT5 (Prop_lut5_I0_O)        0.124     2.069 r  SYS70/W11A/SEQ/RAM_reg_0_15_0_0_i_59/O
                         net (fo=3, routed)           0.655     2.724    SYS70/W11A/SEQ/RAM_reg_0_15_0_0_i_59_n_0
    SLICE_X47Y31         LUT4 (Prop_lut4_I0_O)        0.124     2.848 r  SYS70/W11A/SEQ/FSM_onehot_R_STATE[63]_i_2/O
                         net (fo=10, routed)          0.653     3.501    SYS70/W11A/SEQ/FSM_onehot_R_STATE[63]_i_2_n_0
    SLICE_X48Y31         LUT6 (Prop_lut6_I5_O)        0.124     3.625 r  SYS70/W11A/SEQ/R_SSR0[seg_mode][1]_i_8/O
                         net (fo=6, routed)           0.468     4.093    SYS70/W11A/SEQ/R_SSR0[seg_mode][1]_i_8_n_0
    SLICE_X49Y33         LUT4 (Prop_lut4_I0_O)        0.124     4.217 r  SYS70/W11A/SEQ/R_SSR0[seg_mode][1]_i_5/O
                         net (fo=9, routed)           0.349     4.566    SYS70/W11A/SEQ/R_SSR0[seg_mode][1]_i_5_n_0
    SLICE_X48Y35         LUT6 (Prop_lut6_I5_O)        0.124     4.690 r  SYS70/W11A/SEQ/R_SSR0[seg_mode][1]_i_1/O
                         net (fo=5, routed)           0.456     5.146    SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][1][1]
    SLICE_X50Y35         LUT6 (Prop_lut6_I1_O)        0.124     5.270 r  SYS70/W11A/SEQ/RAM_reg_0_63_0_0_i_8/O
                         net (fo=2, routed)           0.314     5.584    SYS70/W11A/VMBOX/MMU/SADR/SAR_HIGH/iasn_reg[0]
    SLICE_X49Y35         LUT6 (Prop_lut6_I5_O)        0.124     5.708 r  SYS70/W11A/VMBOX/MMU/SADR/SAR_HIGH/RAM_reg_0_63_0_0_i_5/O
                         net (fo=29, routed)          1.005     6.713    SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/RAM_reg_0_63_0_0/A3
    SLICE_X52Y38         RAMS64E (Prop_rams64e_ADR3_O)
                                                      0.124     6.837 r  SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/RAM_reg_0_63_0_0/SP/O
                         net (fo=5, routed)           0.828     7.665    SYS70/W11A/DPATH/GPR/DO[0]
    SLICE_X53Y39         LUT4 (Prop_lut4_I1_O)        0.124     7.789 r  SYS70/W11A/DPATH/GPR/abo_length0_carry_i_8/O
                         net (fo=1, routed)           0.000     7.789    SYS70/W11A/VMBOX/MMU/R_DSRC_reg[12][0]
    SLICE_X53Y39         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     8.321 f  SYS70/W11A/VMBOX/MMU/abo_length0_carry/CO[3]
                         net (fo=2, routed)           0.906     9.227    SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/CO[0]
    SLICE_X54Y39         LUT3 (Prop_lut3_I0_O)        0.124     9.351 f  SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/RAM_reg_0_63_0_0_i_6__0/O
                         net (fo=1, routed)           0.312     9.663    SYS70/W11A/VMBOX/MMU/SADR/SDR_LOW/R_REGS_reg[mdin][3]
    SLICE_X54Y40         LUT5 (Prop_lut5_I0_O)        0.124     9.787 r  SYS70/W11A/VMBOX/MMU/SADR/SDR_LOW/RAM_reg_0_63_0_0_i_5__0/O
                         net (fo=4, routed)           0.306    10.093    SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/R_REGS_reg[mdin][2]
    SLICE_X54Y40         LUT4 (Prop_lut4_I3_O)        0.124    10.217 r  SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/RAM_reg_0_63_0_0_i_1/O
                         net (fo=1, routed)           0.480    10.697    SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/RAM_reg_0_63_0_0/D
    SLICE_X52Y40         RAMS64E                                      r  SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/RAM_reg_0_63_0_0/SP/I
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)   12.500    12.500 r  
    W5                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    13.888 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.162    15.050    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.217     7.832 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     9.414    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     9.505 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.450    10.955    SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/RAM_reg_0_63_0_0/WCLK
    SLICE_X52Y40         RAMS64E                                      r  SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/RAM_reg_0_63_0_0/SP/CLK
                         clock pessimism              0.564    11.518    
                         clock uncertainty           -0.082    11.436    
    SLICE_X52Y40         RAMS64E (Setup_rams64e_CLK_I)
                                                     -0.184    11.252    SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/RAM_reg_0_63_0_0/SP
  -------------------------------------------------------------------
                         required time                         11.252    
                         arrival time                         -10.697    
  -------------------------------------------------------------------
                         slack                                  0.555    

Slack (MET) :             0.561ns  (required time - arrival time)
  Source:                 SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/CACHE/CMEM_DAT3/sv_ram_reg/DIADI[4]
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (CLKOUT0 rise@12.500ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        11.616ns  (logic 4.747ns (40.865%)  route 6.869ns (59.134%))
  Logic Levels:           13  (CARRY4=2 LUT2=1 LUT3=2 LUT4=1 LUT5=1 LUT6=6)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.502ns = ( 10.998 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.899ns
    Clock Pessimism Removal (CPR):    0.603ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.691    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.961    -4.269 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.608    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.512 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.613    -0.899    SYS70/CACHE/CMEM_DAT3/CLK0
    RAMB18_X1Y16         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X1Y16         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[0])
                                                      2.454     1.555 r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/DOADO[0]
                         net (fo=2, routed)           1.172     2.727    SYS70/CACHE/CMEM_DAT3/CMEM_DOA_3[0]
    SLICE_X48Y37         LUT6 (Prop_lut6_I0_O)        0.124     2.851 r  SYS70/CACHE/CMEM_DAT3/R_IREG[8]_i_2/O
                         net (fo=1, routed)           0.715     3.565    SYS70/W11A/VMBOX/EM_SRES[dout][8]
    SLICE_X46Y34         LUT4 (Prop_lut4_I2_O)        0.124     3.689 r  SYS70/W11A/VMBOX/R_IREG[8]_i_1/O
                         net (fo=6, routed)           0.201     3.891    SYS70/W11A/VMBOX/VM_DOUT[8]
    SLICE_X46Y34         LUT6 (Prop_lut6_I5_O)        0.124     4.015 r  SYS70/W11A/VMBOX/R_IREG[0]_i_1/O
                         net (fo=3, routed)           0.424     4.438    SYS70/W11A/SEQ/VM_DOUT[0]
    SLICE_X47Y35         LUT6 (Prop_lut6_I2_O)        0.124     4.562 r  SYS70/W11A/SEQ/i__carry_i_4__0/O
                         net (fo=3, routed)           0.420     4.983    SYS70/W11A/SEQ/mb[0]
    SLICE_X47Y36         LUT2 (Prop_lut2_I1_O)        0.124     5.107 r  SYS70/W11A/SEQ/sum0_carry_i_8/O
                         net (fo=1, routed)           0.000     5.107    SYS70/W11A/DPATH/OUNIT/S[0]
    SLICE_X47Y36         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     5.639 r  SYS70/W11A/DPATH/OUNIT/sum0_carry/CO[3]
                         net (fo=1, routed)           0.000     5.639    SYS70/W11A/DPATH/OUNIT/sum0_carry_n_0
    SLICE_X47Y37         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.222     5.861 r  SYS70/W11A/DPATH/OUNIT/sum0_carry__0/O[0]
                         net (fo=2, routed)           0.871     6.732    SYS70/W11A/DPATH/OUNIT/sum00_out[4]
    SLICE_X50Y36         LUT3 (Prop_lut3_I0_O)        0.299     7.031 r  SYS70/W11A/DPATH/OUNIT/R_REGS[mdin][4]_i_7/O
                         net (fo=1, routed)           0.303     7.334    SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[106]_12
    SLICE_X49Y36         LUT5 (Prop_lut5_I4_O)        0.124     7.458 r  SYS70/W11A/SEQ/R_REGS[mdin][4]_i_3/O
                         net (fo=1, routed)           0.313     7.771    SYS70/W11A/SEQ/R_REGS[mdin][4]_i_3_n_0
    SLICE_X51Y35         LUT6 (Prop_lut6_I0_O)        0.124     7.895 r  SYS70/W11A/SEQ/R_REGS[mdin][4]_i_2/O
                         net (fo=16, routed)          1.122     9.017    SYS70/W11A/SEQ/R_CPDOUT_reg[4][4]
    SLICE_X54Y43         LUT6 (Prop_lut6_I0_O)        0.124     9.141 r  SYS70/W11A/SEQ/R_REGS[mdin][12]_i_4/O
                         net (fo=1, routed)           0.493     9.634    SYS70/W11A/SEQ/R_REGS[mdin][12]_i_4_n_0
    SLICE_X54Y43         LUT6 (Prop_lut6_I5_O)        0.124     9.758 r  SYS70/W11A/SEQ/R_REGS[mdin][12]_i_3/O
                         net (fo=2, routed)           0.172     9.930    SYS70/W11A/SEQ/R_REGS[mdin][12]_i_3_n_0
    SLICE_X54Y43         LUT3 (Prop_lut3_I2_O)        0.124    10.054 r  SYS70/W11A/SEQ/sv_ram_reg_i_4__0/O
                         net (fo=3, routed)           0.663    10.717    SYS70/CACHE/CMEM_DAT3/D[4]
    RAMB18_X1Y16         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/DIADI[4]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)   12.500    12.500 r  
    W5                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    13.888 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.162    15.050    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.217     7.832 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     9.414    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     9.505 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.494    10.998    SYS70/CACHE/CMEM_DAT3/CLK0
    RAMB18_X1Y16         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
                         clock pessimism              0.603    11.601    
                         clock uncertainty           -0.082    11.519    
    RAMB18_X1Y16         RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[4])
                                                     -0.241    11.278    SYS70/CACHE/CMEM_DAT3/sv_ram_reg
  -------------------------------------------------------------------
                         required time                         11.278    
                         arrival time                         -10.717    
  -------------------------------------------------------------------
                         slack                                  0.561    

Slack (MET) :             0.569ns  (required time - arrival time)
  Source:                 SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/CACHE/CMEM_DAT1/sv_ram_reg/DIADI[1]
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (CLKOUT0 rise@12.500ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        11.580ns  (logic 5.240ns (45.251%)  route 6.340ns (54.749%))
  Logic Levels:           14  (CARRY4=3 LUT2=1 LUT3=2 LUT4=2 LUT6=5 MUXF7=1)
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.505ns = ( 10.995 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.899ns
    Clock Pessimism Removal (CPR):    0.578ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.691    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.961    -4.269 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.608    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.512 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.613    -0.899    SYS70/CACHE/CMEM_DAT3/CLK0
    RAMB18_X1Y16         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X1Y16         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[0])
                                                      2.454     1.555 r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/DOADO[0]
                         net (fo=2, routed)           1.172     2.727    SYS70/CACHE/CMEM_DAT3/CMEM_DOA_3[0]
    SLICE_X48Y37         LUT6 (Prop_lut6_I0_O)        0.124     2.851 r  SYS70/CACHE/CMEM_DAT3/R_IREG[8]_i_2/O
                         net (fo=1, routed)           0.715     3.565    SYS70/W11A/VMBOX/EM_SRES[dout][8]
    SLICE_X46Y34         LUT4 (Prop_lut4_I2_O)        0.124     3.689 r  SYS70/W11A/VMBOX/R_IREG[8]_i_1/O
                         net (fo=6, routed)           0.201     3.891    SYS70/W11A/VMBOX/VM_DOUT[8]
    SLICE_X46Y34         LUT6 (Prop_lut6_I5_O)        0.124     4.015 r  SYS70/W11A/VMBOX/R_IREG[0]_i_1/O
                         net (fo=3, routed)           0.424     4.438    SYS70/W11A/SEQ/VM_DOUT[0]
    SLICE_X47Y35         LUT6 (Prop_lut6_I2_O)        0.124     4.562 r  SYS70/W11A/SEQ/i__carry_i_4__0/O
                         net (fo=3, routed)           0.420     4.983    SYS70/W11A/SEQ/mb[0]
    SLICE_X47Y36         LUT2 (Prop_lut2_I1_O)        0.124     5.107 r  SYS70/W11A/SEQ/sum0_carry_i_8/O
                         net (fo=1, routed)           0.000     5.107    SYS70/W11A/DPATH/OUNIT/S[0]
    SLICE_X47Y36         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     5.639 r  SYS70/W11A/DPATH/OUNIT/sum0_carry/CO[3]
                         net (fo=1, routed)           0.000     5.639    SYS70/W11A/DPATH/OUNIT/sum0_carry_n_0
    SLICE_X47Y37         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     5.753 r  SYS70/W11A/DPATH/OUNIT/sum0_carry__0/CO[3]
                         net (fo=1, routed)           0.000     5.753    SYS70/W11A/DPATH/OUNIT/sum0_carry__0_n_0
    SLICE_X47Y38         CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334     6.087 r  SYS70/W11A/DPATH/OUNIT/sum0_carry__1/O[1]
                         net (fo=2, routed)           0.665     6.752    SYS70/W11A/DPATH/OUNIT/sum00_out[9]
    SLICE_X48Y39         LUT3 (Prop_lut3_I0_O)        0.303     7.055 r  SYS70/W11A/DPATH/OUNIT/RAM_reg_0_15_1_1_i_6__0/O
                         net (fo=1, routed)           0.318     7.372    SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[106]_5
    SLICE_X51Y40         LUT6 (Prop_lut6_I3_O)        0.124     7.496 r  SYS70/W11A/SEQ/RAM_reg_0_15_1_1_i_2/O
                         net (fo=1, routed)           0.000     7.496    SYS70/W11A/SEQ/RAM_reg_0_15_1_1_i_2_n_0
    SLICE_X51Y40         MUXF7 (Prop_muxf7_I0_O)      0.212     7.708 r  SYS70/W11A/SEQ/RAM_reg_0_15_1_1_i_1__0/O
                         net (fo=9, routed)           0.611     8.319    SYS70/W11A/SEQ/R_CPDOUT_reg[9]
    SLICE_X49Y42         LUT4 (Prop_lut4_I3_O)        0.299     8.618 r  SYS70/W11A/SEQ/R_REGS[mdin][9]_i_2/O
                         net (fo=3, routed)           0.517     9.135    SYS70/W11A/VMBOX/R_DSRC_reg[0]_1
    SLICE_X47Y42         LUT6 (Prop_lut6_I4_O)        0.124     9.259 r  SYS70/W11A/VMBOX/R_REGS[mdin][9]_i_3/O
                         net (fo=2, routed)           0.445     9.704    SYS70/W11A/VMBOX/R_REGS[mdin][9]_i_3_n_0
    SLICE_X47Y42         LUT3 (Prop_lut3_I2_O)        0.124     9.828 r  SYS70/W11A/VMBOX/sv_ram_reg_i_7__0/O
                         net (fo=3, routed)           0.853    10.681    SYS70/CACHE/CMEM_DAT1/D[1]
    RAMB18_X1Y15         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT1/sv_ram_reg/DIADI[1]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)   12.500    12.500 r  
    W5                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    13.888 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.162    15.050    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.217     7.832 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     9.414    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     9.505 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.491    10.995    SYS70/CACHE/CMEM_DAT1/CLK0
    RAMB18_X1Y15         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT1/sv_ram_reg/CLKARDCLK
                         clock pessimism              0.578    11.573    
                         clock uncertainty           -0.082    11.491    
    RAMB18_X1Y15         RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[1])
                                                     -0.241    11.250    SYS70/CACHE/CMEM_DAT1/sv_ram_reg
  -------------------------------------------------------------------
                         required time                         11.250    
                         arrival time                         -10.681    
  -------------------------------------------------------------------
                         slack                                  0.569    

Slack (MET) :             0.610ns  (required time - arrival time)
  Source:                 SYS70/CACHE/CMEM_DAT1/sv_ram_reg/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/CACHE/CMEM_DAT1/sv_ram_reg/DIADI[6]
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (CLKOUT0 rise@12.500ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        11.567ns  (logic 5.010ns (43.313%)  route 6.557ns (56.687%))
  Logic Levels:           13  (CARRY4=3 LUT3=2 LUT4=2 LUT5=1 LUT6=4 MUXF7=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.505ns = ( 10.995 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.902ns
    Clock Pessimism Removal (CPR):    0.603ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.691    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.961    -4.269 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.608    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.512 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.610    -0.902    SYS70/CACHE/CMEM_DAT1/CLK0
    RAMB18_X1Y15         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT1/sv_ram_reg/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X1Y15         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[5])
                                                      2.454     1.552 r  SYS70/CACHE/CMEM_DAT1/sv_ram_reg/DOADO[5]
                         net (fo=2, routed)           1.370     2.922    SYS70/CACHE/CMEM_DAT3/DOADO[5]
    SLICE_X48Y42         LUT6 (Prop_lut6_I1_O)        0.124     3.046 r  SYS70/CACHE/CMEM_DAT3/R_IREG[13]_i_2/O
                         net (fo=1, routed)           0.407     3.453    SYS70/W11A/VMBOX/EM_SRES[dout][13]
    SLICE_X49Y42         LUT4 (Prop_lut4_I2_O)        0.124     3.577 r  SYS70/W11A/VMBOX/R_IREG[13]_i_1/O
                         net (fo=6, routed)           0.544     4.121    SYS70/W11A/VMBOX/VM_DOUT[13]
    SLICE_X48Y37         LUT6 (Prop_lut6_I5_O)        0.124     4.245 r  SYS70/W11A/VMBOX/R_IREG[5]_i_1/O
                         net (fo=5, routed)           0.303     4.548    SYS70/W11A/SEQ/VM_DOUT[5]
    SLICE_X48Y37         LUT5 (Prop_lut5_I0_O)        0.124     4.672 r  SYS70/W11A/SEQ/i__carry__0_i_3/O
                         net (fo=1, routed)           0.612     5.284    SYS70/W11A/DPATH/OUNIT/mb[5]
    SLICE_X46Y37         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520     5.804 r  SYS70/W11A/DPATH/OUNIT/sum0_inferred__0/i__carry__0/CO[3]
                         net (fo=1, routed)           0.000     5.804    SYS70/W11A/DPATH/OUNIT/sum0_inferred__0/i__carry__0_n_0
    SLICE_X46Y38         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     5.921 r  SYS70/W11A/DPATH/OUNIT/sum0_inferred__0/i__carry__1/CO[3]
                         net (fo=1, routed)           0.000     5.921    SYS70/W11A/DPATH/OUNIT/sum0_inferred__0/i__carry__1_n_0
    SLICE_X46Y39         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     6.160 r  SYS70/W11A/DPATH/OUNIT/sum0_inferred__0/i__carry__2/O[2]
                         net (fo=2, routed)           0.883     7.044    SYS70/W11A/DPATH/OUNIT/sum01_out[14]
    SLICE_X54Y40         LUT3 (Prop_lut3_I2_O)        0.301     7.345 r  SYS70/W11A/DPATH/OUNIT/RAM_reg_0_15_6_6_i_6/O
                         net (fo=1, routed)           0.410     7.755    SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[106]_9
    SLICE_X55Y38         LUT6 (Prop_lut6_I5_O)        0.124     7.879 r  SYS70/W11A/SEQ/RAM_reg_0_15_6_6_i_2__0/O
                         net (fo=1, routed)           0.000     7.879    SYS70/W11A/SEQ/RAM_reg_0_15_6_6_i_2__0_n_0
    SLICE_X55Y38         MUXF7 (Prop_muxf7_I0_O)      0.212     8.091 r  SYS70/W11A/SEQ/RAM_reg_0_15_6_6_i_1__0/O
                         net (fo=11, routed)          0.689     8.779    SYS70/W11A/SEQ/R_CPDOUT_reg[14]
    SLICE_X53Y41         LUT4 (Prop_lut4_I3_O)        0.299     9.078 r  SYS70/W11A/SEQ/R_REGS[mdin][14]_i_2/O
                         net (fo=3, routed)           0.497     9.575    SYS70/W11A/VMBOX/R_DSRC_reg[0]_5
    SLICE_X53Y41         LUT6 (Prop_lut6_I4_O)        0.124     9.699 r  SYS70/W11A/VMBOX/R_REGS[mdin][14]_i_3/O
                         net (fo=2, routed)           0.166     9.865    SYS70/W11A/VMBOX/R_REGS[mdin][14]_i_3_n_0
    SLICE_X53Y41         LUT3 (Prop_lut3_I2_O)        0.124     9.989 r  SYS70/W11A/VMBOX/sv_ram_reg_i_2__0/O
                         net (fo=3, routed)           0.676    10.665    SYS70/CACHE/CMEM_DAT1/D[6]
    RAMB18_X1Y15         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT1/sv_ram_reg/DIADI[6]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)   12.500    12.500 r  
    W5                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    13.888 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.162    15.050    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.217     7.832 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     9.414    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     9.505 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.491    10.995    SYS70/CACHE/CMEM_DAT1/CLK0
    RAMB18_X1Y15         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT1/sv_ram_reg/CLKARDCLK
                         clock pessimism              0.603    11.598    
                         clock uncertainty           -0.082    11.516    
    RAMB18_X1Y15         RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[6])
                                                     -0.241    11.275    SYS70/CACHE/CMEM_DAT1/sv_ram_reg
  -------------------------------------------------------------------
                         required time                         11.275    
                         arrival time                         -10.665    
  -------------------------------------------------------------------
                         slack                                  0.610    

Slack (MET) :             0.628ns  (required time - arrival time)
  Source:                 SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/CACHE/CMEM_DAT1/sv_ram_reg/DIADI[5]
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (CLKOUT0 rise@12.500ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        11.520ns  (logic 5.379ns (46.691%)  route 6.141ns (53.309%))
  Logic Levels:           15  (CARRY4=4 LUT2=1 LUT3=2 LUT4=2 LUT6=5 MUXF7=1)
  Clock Path Skew:        -0.028ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.505ns = ( 10.995 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.899ns
    Clock Pessimism Removal (CPR):    0.578ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.691    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.961    -4.269 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.608    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.512 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.613    -0.899    SYS70/CACHE/CMEM_DAT3/CLK0
    RAMB18_X1Y16         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X1Y16         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[0])
                                                      2.454     1.555 r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/DOADO[0]
                         net (fo=2, routed)           1.172     2.727    SYS70/CACHE/CMEM_DAT3/CMEM_DOA_3[0]
    SLICE_X48Y37         LUT6 (Prop_lut6_I0_O)        0.124     2.851 r  SYS70/CACHE/CMEM_DAT3/R_IREG[8]_i_2/O
                         net (fo=1, routed)           0.715     3.565    SYS70/W11A/VMBOX/EM_SRES[dout][8]
    SLICE_X46Y34         LUT4 (Prop_lut4_I2_O)        0.124     3.689 r  SYS70/W11A/VMBOX/R_IREG[8]_i_1/O
                         net (fo=6, routed)           0.201     3.891    SYS70/W11A/VMBOX/VM_DOUT[8]
    SLICE_X46Y34         LUT6 (Prop_lut6_I5_O)        0.124     4.015 r  SYS70/W11A/VMBOX/R_IREG[0]_i_1/O
                         net (fo=3, routed)           0.424     4.438    SYS70/W11A/SEQ/VM_DOUT[0]
    SLICE_X47Y35         LUT6 (Prop_lut6_I2_O)        0.124     4.562 r  SYS70/W11A/SEQ/i__carry_i_4__0/O
                         net (fo=3, routed)           0.420     4.983    SYS70/W11A/SEQ/mb[0]
    SLICE_X47Y36         LUT2 (Prop_lut2_I1_O)        0.124     5.107 r  SYS70/W11A/SEQ/sum0_carry_i_8/O
                         net (fo=1, routed)           0.000     5.107    SYS70/W11A/DPATH/OUNIT/S[0]
    SLICE_X47Y36         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     5.639 r  SYS70/W11A/DPATH/OUNIT/sum0_carry/CO[3]
                         net (fo=1, routed)           0.000     5.639    SYS70/W11A/DPATH/OUNIT/sum0_carry_n_0
    SLICE_X47Y37         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     5.753 r  SYS70/W11A/DPATH/OUNIT/sum0_carry__0/CO[3]
                         net (fo=1, routed)           0.000     5.753    SYS70/W11A/DPATH/OUNIT/sum0_carry__0_n_0
    SLICE_X47Y38         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     5.867 r  SYS70/W11A/DPATH/OUNIT/sum0_carry__1/CO[3]
                         net (fo=1, routed)           0.000     5.867    SYS70/W11A/DPATH/OUNIT/sum0_carry__1_n_0
    SLICE_X47Y39         CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334     6.201 r  SYS70/W11A/DPATH/OUNIT/sum0_carry__2/O[1]
                         net (fo=2, routed)           0.821     7.022    SYS70/W11A/DPATH/OUNIT/sum00_out[13]
    SLICE_X51Y39         LUT3 (Prop_lut3_I0_O)        0.303     7.325 r  SYS70/W11A/DPATH/OUNIT/RAM_reg_0_15_5_5_i_6__0/O
                         net (fo=1, routed)           0.294     7.620    SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[106]_8
    SLICE_X51Y40         LUT6 (Prop_lut6_I3_O)        0.124     7.744 r  SYS70/W11A/SEQ/RAM_reg_0_15_5_5_i_2__0/O
                         net (fo=1, routed)           0.000     7.744    SYS70/W11A/SEQ/RAM_reg_0_15_5_5_i_2__0_n_0
    SLICE_X51Y40         MUXF7 (Prop_muxf7_I0_O)      0.238     7.982 r  SYS70/W11A/SEQ/RAM_reg_0_15_5_5_i_1__0/O
                         net (fo=10, routed)          0.542     8.523    SYS70/W11A/SEQ/R_CPDOUT_reg[13]
    SLICE_X54Y40         LUT4 (Prop_lut4_I3_O)        0.298     8.821 r  SYS70/W11A/SEQ/R_REGS[mdin][13]_i_2/O
                         net (fo=3, routed)           0.425     9.246    SYS70/W11A/VMBOX/R_DSRC_reg[0]_4
    SLICE_X55Y39         LUT6 (Prop_lut6_I4_O)        0.124     9.370 r  SYS70/W11A/VMBOX/R_REGS[mdin][13]_i_3/O
                         net (fo=2, routed)           0.324     9.694    SYS70/W11A/VMBOX/R_REGS[mdin][13]_i_3_n_0
    SLICE_X54Y41         LUT3 (Prop_lut3_I2_O)        0.124     9.818 r  SYS70/W11A/VMBOX/sv_ram_reg_i_3__0/O
                         net (fo=3, routed)           0.803    10.621    SYS70/CACHE/CMEM_DAT1/D[5]
    RAMB18_X1Y15         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT1/sv_ram_reg/DIADI[5]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)   12.500    12.500 r  
    W5                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    13.888 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.162    15.050    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.217     7.832 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     9.414    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     9.505 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.491    10.995    SYS70/CACHE/CMEM_DAT1/CLK0
    RAMB18_X1Y15         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT1/sv_ram_reg/CLKARDCLK
                         clock pessimism              0.578    11.573    
                         clock uncertainty           -0.082    11.491    
    RAMB18_X1Y15         RAMB18E1 (Setup_ramb18e1_CLKARDCLK_DIADI[5])
                                                     -0.241    11.250    SYS70/CACHE/CMEM_DAT1/sv_ram_reg
  -------------------------------------------------------------------
                         required time                         11.250    
                         arrival time                         -10.621    
  -------------------------------------------------------------------
                         slack                                  0.628    

Slack (MET) :             0.643ns  (required time - arrival time)
  Source:                 SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[0]/D
                            (rising edge-triggered cell FDSE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (CLKOUT0 rise@12.500ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        11.716ns  (logic 5.105ns (43.574%)  route 6.611ns (56.426%))
  Logic Levels:           16  (CARRY4=1 LUT2=1 LUT4=1 LUT5=1 LUT6=12)
  Clock Path Skew:        -0.088ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.551ns = ( 10.949 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.899ns
    Clock Pessimism Removal (CPR):    0.564ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.691    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.961    -4.269 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.608    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.512 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.613    -0.899    SYS70/CACHE/CMEM_DAT3/CLK0
    RAMB18_X1Y16         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X1Y16         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[0])
                                                      2.454     1.555 r  SYS70/CACHE/CMEM_DAT3/sv_ram_reg/DOADO[0]
                         net (fo=2, routed)           1.172     2.727    SYS70/CACHE/CMEM_DAT3/CMEM_DOA_3[0]
    SLICE_X48Y37         LUT6 (Prop_lut6_I0_O)        0.124     2.851 r  SYS70/CACHE/CMEM_DAT3/R_IREG[8]_i_2/O
                         net (fo=1, routed)           0.715     3.565    SYS70/W11A/VMBOX/EM_SRES[dout][8]
    SLICE_X46Y34         LUT4 (Prop_lut4_I2_O)        0.124     3.689 r  SYS70/W11A/VMBOX/R_IREG[8]_i_1/O
                         net (fo=6, routed)           0.201     3.891    SYS70/W11A/VMBOX/VM_DOUT[8]
    SLICE_X46Y34         LUT6 (Prop_lut6_I5_O)        0.124     4.015 r  SYS70/W11A/VMBOX/R_IREG[0]_i_1/O
                         net (fo=3, routed)           0.424     4.438    SYS70/W11A/SEQ/VM_DOUT[0]
    SLICE_X47Y35         LUT6 (Prop_lut6_I2_O)        0.124     4.562 r  SYS70/W11A/SEQ/i__carry_i_4__0/O
                         net (fo=3, routed)           0.434     4.997    SYS70/W11A/SEQ/mb[0]
    SLICE_X46Y36         LUT2 (Prop_lut2_I1_O)        0.124     5.121 r  SYS70/W11A/SEQ/i__carry_i_8__0/O
                         net (fo=1, routed)           0.000     5.121    SYS70/W11A/DPATH/OUNIT/R_IREG_reg[2][0]
    SLICE_X46Y36         CARRY4 (Prop_carry4_S[0]_O[3])
                                                      0.608     5.729 f  SYS70/W11A/DPATH/OUNIT/sum0_inferred__0/i__carry/O[3]
                         net (fo=2, routed)           0.733     6.461    SYS70/W11A/DPATH/OUNIT/sum01_out[3]
    SLICE_X43Y36         LUT5 (Prop_lut5_I0_O)        0.307     6.768 f  SYS70/W11A/DPATH/OUNIT/R_PSW[cc][2]_i_23/O
                         net (fo=1, routed)           0.607     7.376    SYS70/W11A/DPATH/OUNIT/R_PSW[cc][2]_i_23_n_0
    SLICE_X42Y37         LUT6 (Prop_lut6_I5_O)        0.124     7.500 f  SYS70/W11A/DPATH/OUNIT/R_PSW[cc][2]_i_17/O
                         net (fo=1, routed)           0.495     7.995    SYS70/W11A/DPATH/OUNIT/R_PSW[cc][2]_i_17_n_0
    SLICE_X43Y37         LUT6 (Prop_lut6_I5_O)        0.124     8.119 f  SYS70/W11A/DPATH/OUNIT/R_PSW[cc][2]_i_8/O
                         net (fo=1, routed)           0.303     8.422    SYS70/W11A/DPATH/OUNIT/R_PSW[cc][2]_i_8_n_0
    SLICE_X42Y38         LUT6 (Prop_lut6_I0_O)        0.124     8.546 r  SYS70/W11A/DPATH/OUNIT/R_PSW[cc][2]_i_4/O
                         net (fo=1, routed)           0.161     8.707    SYS70/W11A/SEQ/R_IDSTAT_reg[res_sel][1]_0
    SLICE_X42Y38         LUT6 (Prop_lut6_I0_O)        0.124     8.831 r  SYS70/W11A/SEQ/R_PSW[cc][2]_i_2/O
                         net (fo=3, routed)           0.177     9.008    SYS70/W11A/SEQ/STAT[ccout_z]
    SLICE_X42Y38         LUT6 (Prop_lut6_I0_O)        0.124     9.132 r  SYS70/W11A/SEQ/FSM_onehot_R_STATE[6]_i_18/O
                         net (fo=2, routed)           0.441     9.573    SYS70/W11A/SEQ/FSM_onehot_R_STATE[6]_i_18_n_0
    SLICE_X42Y39         LUT6 (Prop_lut6_I1_O)        0.124     9.697 r  SYS70/W11A/SEQ/FSM_onehot_R_STATE[111]_i_21/O
                         net (fo=2, routed)           0.445    10.141    SYS70/W11A/SEQ/FSM_onehot_R_STATE[111]_i_21_n_0
    SLICE_X41Y38         LUT6 (Prop_lut6_I0_O)        0.124    10.265 r  SYS70/W11A/SEQ/FSM_onehot_R_STATE[0]_i_27/O
                         net (fo=1, routed)           0.149    10.414    SYS70/W11A/SEQ/FSM_onehot_R_STATE[0]_i_27_n_0
    SLICE_X41Y38         LUT6 (Prop_lut6_I5_O)        0.124    10.538 r  SYS70/W11A/SEQ/FSM_onehot_R_STATE[0]_i_7/O
                         net (fo=1, routed)           0.154    10.693    SYS70/W11A/SEQ/FSM_onehot_R_STATE[0]_i_7_n_0
    SLICE_X41Y38         LUT6 (Prop_lut6_I5_O)        0.124    10.817 r  SYS70/W11A/SEQ/FSM_onehot_R_STATE[0]_i_1/O
                         net (fo=1, routed)           0.000    10.817    SYS70/W11A/SEQ/FSM_onehot_R_STATE[0]_i_1_n_0
    SLICE_X41Y38         FDSE                                         r  SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)   12.500    12.500 r  
    W5                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    13.888 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.162    15.050    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.217     7.832 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     9.414    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     9.505 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.444    10.949    SYS70/W11A/SEQ/CLK0
    SLICE_X41Y38         FDSE                                         r  SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[0]/C
                         clock pessimism              0.564    11.512    
                         clock uncertainty           -0.082    11.430    
    SLICE_X41Y38         FDSE (Setup_fdse_C_D)        0.029    11.459    SYS70/W11A/SEQ/FSM_onehot_R_STATE_reg[0]
  -------------------------------------------------------------------
                         required time                         11.459    
                         arrival time                         -10.817    
  -------------------------------------------------------------------
                         slack                                  0.643    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.055ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/R_BREGS_reg[rbdout][10]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/I
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.462ns  (logic 0.186ns (40.228%)  route 0.276ns (59.772%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.262ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.873ns
    Source Clock Delay      (SCD):    -0.631ns
    Clock Pessimism Removal (CPR):    -0.503ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.360    -1.693 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.207    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.181 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.550    -0.631    RLINK/CORE/RL/CLK0
    SLICE_X35Y71         FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y71         FDRE (Prop_fdre_C_Q)         0.141    -0.490 r  RLINK/CORE/RL/R_BREGS_reg[rbdout][10]/Q
                         net (fo=1, routed)           0.112    -0.378    RLINK/CORE/RL/DOFIFO/FIFO/RAM/R_BREGS_reg[rbdout][10]
    SLICE_X35Y71         LUT5 (Prop_lut5_I4_O)        0.045    -0.333 r  RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5_i_5/O
                         net (fo=1, routed)           0.164    -0.169    RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/DIB0
    SLICE_X38Y72         RAMD32                                       r  RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/I
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.894    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.142    -2.248 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.718    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.689 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.816    -0.873    RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X38Y72         RAMD32                                       r  RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
                         clock pessimism              0.503    -0.369    
    SLICE_X38Y72         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.146    -0.223    RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB
  -------------------------------------------------------------------
                         required time                          0.223    
                         arrival time                          -0.169    
  -------------------------------------------------------------------
                         slack                                  0.055    

Slack (MET) :             0.069ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[lcmd][4]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/CORE/RL/R_BREGS_reg[rbdout][12]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.455ns  (logic 0.186ns (40.881%)  route 0.269ns (59.119%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.266ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.871ns
    Source Clock Delay      (SCD):    -0.633ns
    Clock Pessimism Removal (CPR):    -0.503ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.360    -1.693 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.207    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.181 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.548    -0.633    RLINK/CORE/RL/CLK0
    SLICE_X37Y75         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[lcmd][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y75         FDRE (Prop_fdre_C_Q)         0.141    -0.492 r  RLINK/CORE/RL/R_LREGS_reg[lcmd][4]/Q
                         net (fo=1, routed)           0.269    -0.223    RLINK/CORE/RL/SEL/R_LREGS_reg[lcmd][4]
    SLICE_X34Y69         LUT6 (Prop_lut6_I3_O)        0.045    -0.178 r  RLINK/CORE/RL/SEL/R_BREGS[rbdout][12]_i_1/O
                         net (fo=1, routed)           0.000    -0.178    RLINK/CORE/RL/RB_SRES_OR[dout]_1[12]
    SLICE_X34Y69         FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][12]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.894    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.142    -2.248 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.718    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.689 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.818    -0.871    RLINK/CORE/RL/CLK0
    SLICE_X34Y69         FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][12]/C
                         clock pessimism              0.503    -0.367    
    SLICE_X34Y69         FDRE (Hold_fdre_C_D)         0.120    -0.247    RLINK/CORE/RL/R_BREGS_reg[rbdout][12]
  -------------------------------------------------------------------
                         required time                          0.247    
                         arrival time                          -0.178    
  -------------------------------------------------------------------
                         slack                                  0.069    

Slack (MET) :             0.071ns  (arrival time - required time)
  Source:                 BRAM_CTL/R_REGS_reg[celladdr][5]_rep__1/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            BRAM_CTL/MARRAY[5].MROW[0].MCELL/sv_ram_reg/ADDRARDADDR[8]
                            (rising edge-triggered cell RAMB36E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.312ns  (logic 0.141ns (45.156%)  route 0.171ns (54.844%))
  Logic Levels:           0  
  Clock Path Skew:        0.058ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.817ns
    Source Clock Delay      (SCD):    -0.620ns
    Clock Pessimism Removal (CPR):    -0.255ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.360    -1.693 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.207    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.181 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.561    -0.620    BRAM_CTL/CLKFX
    SLICE_X57Y31         FDRE                                         r  BRAM_CTL/R_REGS_reg[celladdr][5]_rep__1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y31         FDRE (Prop_fdre_C_Q)         0.141    -0.479 r  BRAM_CTL/R_REGS_reg[celladdr][5]_rep__1/Q
                         net (fo=11, routed)          0.171    -0.308    BRAM_CTL/MARRAY[5].MROW[0].MCELL/ADDRARDADDR[5]
    RAMB36_X2Y6          RAMB36E1                                     r  BRAM_CTL/MARRAY[5].MROW[0].MCELL/sv_ram_reg/ADDRARDADDR[8]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.894    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.142    -2.248 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.718    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.689 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.872    -0.817    BRAM_CTL/MARRAY[5].MROW[0].MCELL/CLKFX
    RAMB36_X2Y6          RAMB36E1                                     r  BRAM_CTL/MARRAY[5].MROW[0].MCELL/sv_ram_reg/CLKARDCLK
                         clock pessimism              0.255    -0.562    
    RAMB36_X2Y6          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[8])
                                                      0.183    -0.379    BRAM_CTL/MARRAY[5].MROW[0].MCELL/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.379    
                         arrival time                          -0.308    
  -------------------------------------------------------------------
                         slack                                  0.071    

Slack (MET) :             0.071ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/R_BREGS_reg[rbdout][7]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA_D1/I
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.453ns  (logic 0.209ns (46.108%)  route 0.244ns (53.892%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.262ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.872ns
    Source Clock Delay      (SCD):    -0.630ns
    Clock Pessimism Removal (CPR):    -0.503ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.360    -1.693 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.207    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.181 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.551    -0.630    RLINK/CORE/RL/CLK0
    SLICE_X34Y70         FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y70         FDRE (Prop_fdre_C_Q)         0.164    -0.466 r  RLINK/CORE/RL/R_BREGS_reg[rbdout][7]/Q
                         net (fo=1, routed)           0.083    -0.383    RLINK/CORE/RL/DOFIFO/FIFO/RAM/R_BREGS_reg[rbdout][7]
    SLICE_X35Y70         LUT5 (Prop_lut5_I0_O)        0.045    -0.338 r  RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_6_7_i_1/O
                         net (fo=1, routed)           0.161    -0.177    RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_6_7/DIA1
    SLICE_X38Y71         RAMD32                                       r  RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.894    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.142    -2.248 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.718    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.689 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.817    -0.872    RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_6_7/WCLK
    SLICE_X38Y71         RAMD32                                       r  RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA_D1/CLK
                         clock pessimism              0.503    -0.368    
    SLICE_X38Y71         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.120    -0.248    RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA_D1
  -------------------------------------------------------------------
                         required time                          0.248    
                         arrival time                          -0.177    
  -------------------------------------------------------------------
                         slack                                  0.071    

Slack (MET) :             0.084ns  (arrival time - required time)
  Source:                 BRAM_CTL/R_REGS_reg[celladdr][2]_rep__1/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            BRAM_CTL/MARRAY[4].MROW[0].MCELL/sv_ram_reg/ADDRARDADDR[5]
                            (rising edge-triggered cell RAMB36E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.323ns  (logic 0.141ns (43.708%)  route 0.182ns (56.292%))
  Logic Levels:           0  
  Clock Path Skew:        0.055ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.823ns
    Source Clock Delay      (SCD):    -0.624ns
    Clock Pessimism Removal (CPR):    -0.254ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.360    -1.693 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.207    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.181 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.557    -0.624    BRAM_CTL/CLKFX
    SLICE_X49Y29         FDRE                                         r  BRAM_CTL/R_REGS_reg[celladdr][2]_rep__1/C
  -------------------------------------------------------------------    -------------------
    SLICE_X49Y29         FDRE (Prop_fdre_C_Q)         0.141    -0.483 r  BRAM_CTL/R_REGS_reg[celladdr][2]_rep__1/Q
                         net (fo=11, routed)          0.182    -0.302    BRAM_CTL/MARRAY[4].MROW[0].MCELL/ADDRARDADDR[2]
    RAMB36_X1Y5          RAMB36E1                                     r  BRAM_CTL/MARRAY[4].MROW[0].MCELL/sv_ram_reg/ADDRARDADDR[5]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.894    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.142    -2.248 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.718    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.689 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.866    -0.823    BRAM_CTL/MARRAY[4].MROW[0].MCELL/CLKFX
    RAMB36_X1Y5          RAMB36E1                                     r  BRAM_CTL/MARRAY[4].MROW[0].MCELL/sv_ram_reg/CLKARDCLK
                         clock pessimism              0.254    -0.569    
    RAMB36_X1Y5          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[5])
                                                      0.183    -0.386    BRAM_CTL/MARRAY[4].MROW[0].MCELL/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.386    
                         arrival time                          -0.302    
  -------------------------------------------------------------------
                         slack                                  0.084    

Slack (MET) :             0.086ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[rtaddrb][11]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/CORE/RL/RTBUF/sv_ram_reg/ADDRBWRADDR[14]
                            (rising edge-triggered cell RAMB36E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.321ns  (logic 0.141ns (43.900%)  route 0.180ns (56.100%))
  Logic Levels:           0  
  Clock Path Skew:        0.052ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.828ns
    Source Clock Delay      (SCD):    -0.626ns
    Clock Pessimism Removal (CPR):    -0.255ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.360    -1.693 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.207    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.181 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.555    -0.626    RLINK/CORE/RL/CLK0
    SLICE_X48Y79         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y79         FDRE (Prop_fdre_C_Q)         0.141    -0.485 r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][11]/Q
                         net (fo=3, routed)           0.180    -0.305    RLINK/CORE/RL/RTBUF/ADDRBWRADDR[11]
    RAMB36_X1Y15         RAMB36E1                                     r  RLINK/CORE/RL/RTBUF/sv_ram_reg/ADDRBWRADDR[14]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.894    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.142    -2.248 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.718    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.689 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.861    -0.828    RLINK/CORE/RL/RTBUF/CLK0
    RAMB36_X1Y15         RAMB36E1                                     r  RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKBWRCLK
                         clock pessimism              0.255    -0.574    
    RAMB36_X1Y15         RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_ADDRBWRADDR[14])
                                                      0.183    -0.391    RLINK/CORE/RL/RTBUF/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.391    
                         arrival time                          -0.305    
  -------------------------------------------------------------------
                         slack                                  0.086    

Slack (MET) :             0.087ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[rtaddrb][3]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/CORE/RL/RTBUF/sv_ram_reg/ADDRBWRADDR[6]
                            (rising edge-triggered cell RAMB36E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.324ns  (logic 0.141ns (43.552%)  route 0.183ns (56.448%))
  Logic Levels:           0  
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.828ns
    Source Clock Delay      (SCD):    -0.627ns
    Clock Pessimism Removal (CPR):    -0.255ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.360    -1.693 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.207    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.181 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.554    -0.627    RLINK/CORE/RL/CLK0
    SLICE_X48Y77         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y77         FDRE (Prop_fdre_C_Q)         0.141    -0.486 r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][3]/Q
                         net (fo=3, routed)           0.183    -0.304    RLINK/CORE/RL/RTBUF/ADDRBWRADDR[3]
    RAMB36_X1Y15         RAMB36E1                                     r  RLINK/CORE/RL/RTBUF/sv_ram_reg/ADDRBWRADDR[6]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.894    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.142    -2.248 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.718    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.689 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.861    -0.828    RLINK/CORE/RL/RTBUF/CLK0
    RAMB36_X1Y15         RAMB36E1                                     r  RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKBWRCLK
                         clock pessimism              0.255    -0.574    
    RAMB36_X1Y15         RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_ADDRBWRADDR[6])
                                                      0.183    -0.391    RLINK/CORE/RL/RTBUF/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.391    
                         arrival time                          -0.304    
  -------------------------------------------------------------------
                         slack                                  0.087    

Slack (MET) :             0.087ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[rtaddrb][6]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/CORE/RL/RTBUF/sv_ram_reg/ADDRBWRADDR[9]
                            (rising edge-triggered cell RAMB36E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.324ns  (logic 0.141ns (43.545%)  route 0.183ns (56.455%))
  Logic Levels:           0  
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.828ns
    Source Clock Delay      (SCD):    -0.627ns
    Clock Pessimism Removal (CPR):    -0.255ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.360    -1.693 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.207    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.181 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.554    -0.627    RLINK/CORE/RL/CLK0
    SLICE_X48Y78         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y78         FDRE (Prop_fdre_C_Q)         0.141    -0.486 r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][6]/Q
                         net (fo=3, routed)           0.183    -0.303    RLINK/CORE/RL/RTBUF/ADDRBWRADDR[6]
    RAMB36_X1Y15         RAMB36E1                                     r  RLINK/CORE/RL/RTBUF/sv_ram_reg/ADDRBWRADDR[9]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.894    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.142    -2.248 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.718    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.689 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.861    -0.828    RLINK/CORE/RL/RTBUF/CLK0
    RAMB36_X1Y15         RAMB36E1                                     r  RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKBWRCLK
                         clock pessimism              0.255    -0.574    
    RAMB36_X1Y15         RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_ADDRBWRADDR[9])
                                                      0.183    -0.391    RLINK/CORE/RL/RTBUF/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.391    
                         arrival time                          -0.303    
  -------------------------------------------------------------------
                         slack                                  0.087    

Slack (MET) :             0.088ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[rtaddrb][2]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/CORE/RL/RTBUF/sv_ram_reg/ADDRBWRADDR[5]
                            (rising edge-triggered cell RAMB36E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.324ns  (logic 0.141ns (43.521%)  route 0.183ns (56.479%))
  Logic Levels:           0  
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.828ns
    Source Clock Delay      (SCD):    -0.627ns
    Clock Pessimism Removal (CPR):    -0.255ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.360    -1.693 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.207    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.181 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.554    -0.627    RLINK/CORE/RL/CLK0
    SLICE_X48Y77         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y77         FDRE (Prop_fdre_C_Q)         0.141    -0.486 r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][2]/Q
                         net (fo=3, routed)           0.183    -0.303    RLINK/CORE/RL/RTBUF/ADDRBWRADDR[2]
    RAMB36_X1Y15         RAMB36E1                                     r  RLINK/CORE/RL/RTBUF/sv_ram_reg/ADDRBWRADDR[5]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.894    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.142    -2.248 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.718    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.689 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.861    -0.828    RLINK/CORE/RL/RTBUF/CLK0
    RAMB36_X1Y15         RAMB36E1                                     r  RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKBWRCLK
                         clock pessimism              0.255    -0.574    
    RAMB36_X1Y15         RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_ADDRBWRADDR[5])
                                                      0.183    -0.391    RLINK/CORE/RL/RTBUF/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.391    
                         arrival time                          -0.303    
  -------------------------------------------------------------------
                         slack                                  0.088    

Slack (MET) :             0.088ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[rtaddrb][4]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/CORE/RL/RTBUF/sv_ram_reg/ADDRBWRADDR[7]
                            (rising edge-triggered cell RAMB36E1 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.324ns  (logic 0.141ns (43.452%)  route 0.183ns (56.548%))
  Logic Levels:           0  
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.828ns
    Source Clock Delay      (SCD):    -0.627ns
    Clock Pessimism Removal (CPR):    -0.255ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.360    -1.693 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.207    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.181 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.554    -0.627    RLINK/CORE/RL/CLK0
    SLICE_X48Y78         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y78         FDRE (Prop_fdre_C_Q)         0.141    -0.486 r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][4]/Q
                         net (fo=3, routed)           0.183    -0.303    RLINK/CORE/RL/RTBUF/ADDRBWRADDR[4]
    RAMB36_X1Y15         RAMB36E1                                     r  RLINK/CORE/RL/RTBUF/sv_ram_reg/ADDRBWRADDR[7]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.894    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.142    -2.248 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.718    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.689 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        0.861    -0.828    RLINK/CORE/RL/RTBUF/CLK0
    RAMB36_X1Y15         RAMB36E1                                     r  RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKBWRCLK
                         clock pessimism              0.255    -0.574    
    RAMB36_X1Y15         RAMB36E1 (Hold_ramb36e1_CLKBWRCLK_ADDRBWRADDR[7])
                                                      0.183    -0.391    RLINK/CORE/RL/RTBUF/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.391    
                         arrival time                          -0.303    
  -------------------------------------------------------------------
                         slack                                  0.088    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         CLKOUT0
Waveform(ns):       { 0.000 6.250 }
Period(ns):         12.500
Sources:            { GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     XADC/DCLK           n/a            4.000         12.500      8.500      XADC_X0Y0        SMRB.I0/SM/DCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.944         12.500      9.556      RAMB18_X1Y14     SYS70/CACHE/CMEM_DAT0/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.944         12.500      9.556      RAMB18_X1Y14     SYS70/CACHE/CMEM_DAT0/sv_ram_reg/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.944         12.500      9.556      RAMB18_X1Y15     SYS70/CACHE/CMEM_DAT1/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.944         12.500      9.556      RAMB18_X1Y15     SYS70/CACHE/CMEM_DAT1/sv_ram_reg/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.944         12.500      9.556      RAMB18_X1Y17     SYS70/CACHE/CMEM_DAT2/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.944         12.500      9.556      RAMB18_X1Y17     SYS70/CACHE/CMEM_DAT2/sv_ram_reg/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.944         12.500      9.556      RAMB18_X1Y16     SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.944         12.500      9.556      RAMB18_X1Y16     SYS70/CACHE/CMEM_DAT3/sv_ram_reg/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.944         12.500      9.556      RAMB18_X1Y18     SYS70/CACHE/CMEM_TAG/sv_ram_reg/CLKARDCLK
Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       12.500      200.860    MMCME2_ADV_X1Y0  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
Low Pulse Width   Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X46Y69     IBDR_SYS/RHRP.RPA/MEM_1/RAM_reg_0_31_1_1/SP/CLK
Low Pulse Width   Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X46Y69     IBDR_SYS/RHRP.RPA/MEM_1/RAM_reg_0_31_2_2/SP/CLK
Low Pulse Width   Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X46Y69     IBDR_SYS/RHRP.RPA/MEM_1/RAM_reg_0_31_3_3/SP/CLK
Low Pulse Width   Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X46Y47     SYS70/W11A/VMBOX/UBMAP/MAP_2/RAM_reg_0_31_4_4/SP/CLK
Low Pulse Width   Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X46Y47     SYS70/W11A/VMBOX/UBMAP/MAP_2/RAM_reg_0_31_5_5/SP/CLK
Low Pulse Width   Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X30Y50     DMPCNT.I0/MEM/RAM_reg_0_31_13_13/SP/CLK
Low Pulse Width   Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X30Y50     DMPCNT.I0/MEM/RAM_reg_0_31_14_14/SP/CLK
Low Pulse Width   Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X30Y50     DMPCNT.I0/MEM/RAM_reg_0_31_15_15/SP/CLK
Low Pulse Width   Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X30Y50     DMPCNT.I0/MEM/RAM_reg_0_31_16_16/SP/CLK
Low Pulse Width   Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X30Y51     DMPCNT.I0/MEM/RAM_reg_0_31_20_20/SP/CLK
High Pulse Width  Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X42Y44     SYS70/W11A/VMBOX/UBMAP/MAP_0/RAM_reg_0_31_0_0/SP/CLK
High Pulse Width  Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X42Y44     SYS70/W11A/VMBOX/UBMAP/MAP_0/RAM_reg_0_31_1_1/SP/CLK
High Pulse Width  Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X42Y44     SYS70/W11A/VMBOX/UBMAP/MAP_0/RAM_reg_0_31_2_2/SP/CLK
High Pulse Width  Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X42Y44     SYS70/W11A/VMBOX/UBMAP/MAP_0/RAM_reg_0_31_3_3/SP/CLK
High Pulse Width  Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X42Y45     SYS70/W11A/VMBOX/UBMAP/MAP_0/RAM_reg_0_31_4_4/SP/CLK
High Pulse Width  Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X42Y45     SYS70/W11A/VMBOX/UBMAP/MAP_0/RAM_reg_0_31_5_5/SP/CLK
High Pulse Width  Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X42Y45     SYS70/W11A/VMBOX/UBMAP/MAP_0/RAM_reg_0_31_6_6/SP/CLK
High Pulse Width  Slow    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X52Y61     IBDR_SYS/RK11.RKA/MEM_0/RAM_reg_0_15_4_4/SP/CLK
High Pulse Width  Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X52Y61     IBDR_SYS/RK11.RKA/MEM_0/RAM_reg_0_15_4_4/SP/CLK
High Pulse Width  Slow    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X52Y61     IBDR_SYS/RK11.RKA/MEM_0/RAM_reg_0_15_5_5/SP/CLK



---------------------------------------------------------------------------------------------------
From Clock:  CLKOUT0_1
  To Clock:  CLKOUT0_1

Setup :            0  Failing Endpoints,  Worst Slack        1.110ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.119ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.917ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.110ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][9]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0_1 rise@8.333ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        6.857ns  (logic 1.918ns (27.972%)  route 4.939ns (72.028%))
  Logic Levels:           6  (CARRY4=3 LUT3=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.410ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.082ns = ( 6.252 - 8.333 ) 
    Source Clock Delay      (SCD):    -2.170ns
    Clock Pessimism Removal (CPR):    -0.498ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.253     2.711    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.770 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.655    -4.115    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -4.019 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.849    -2.170    IOB_RS232/IOB_RXD/IOB/CLK1
    ILOGIC_X0Y112        FDRE                                         r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517    -1.653 f  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=17, routed)          3.622     1.969    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X30Y64         LUT4 (Prop_lut4_I2_O)        0.180     2.149 f  RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_6/O
                         net (fo=3, routed)           0.638     2.787    RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_6_n_0
    SLICE_X30Y64         LUT6 (Prop_lut6_I2_O)        0.124     2.911 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=23, routed)          0.678     3.590    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_2__0_n_0
    SLICE_X30Y59         LUT3 (Prop_lut3_I2_O)        0.124     3.714 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_8__0/O
                         net (fo=1, routed)           0.000     3.714    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_8__0_n_0
    SLICE_X30Y59         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.533     4.247 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.247    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1_n_0
    SLICE_X30Y60         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.364 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.364    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1_n_0
    SLICE_X30Y61         CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323     4.687 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1/O[1]
                         net (fo=1, routed)           0.000     4.687    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1_n_6
    SLICE_X30Y61         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][9]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      8.333     8.333 r  
    W5                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388     9.721 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.181    10.902    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750     3.153 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.576     4.729    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     4.820 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.432     6.252    RLINK/SERPORT/UART/RXTX/RX/CLK1
    SLICE_X30Y61         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][9]/C
                         clock pessimism             -0.498     5.753    
                         clock uncertainty           -0.066     5.688    
    SLICE_X30Y61         FDRE (Setup_fdre_C_D)        0.109     5.797    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][9]
  -------------------------------------------------------------------
                         required time                          5.797    
                         arrival time                          -4.687    
  -------------------------------------------------------------------
                         slack                                  1.110    

Slack (MET) :             1.118ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][11]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0_1 rise@8.333ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        6.849ns  (logic 1.910ns (27.888%)  route 4.939ns (72.112%))
  Logic Levels:           6  (CARRY4=3 LUT3=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.410ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.082ns = ( 6.252 - 8.333 ) 
    Source Clock Delay      (SCD):    -2.170ns
    Clock Pessimism Removal (CPR):    -0.498ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.253     2.711    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.770 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.655    -4.115    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -4.019 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.849    -2.170    IOB_RS232/IOB_RXD/IOB/CLK1
    ILOGIC_X0Y112        FDRE                                         r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517    -1.653 f  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=17, routed)          3.622     1.969    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X30Y64         LUT4 (Prop_lut4_I2_O)        0.180     2.149 f  RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_6/O
                         net (fo=3, routed)           0.638     2.787    RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_6_n_0
    SLICE_X30Y64         LUT6 (Prop_lut6_I2_O)        0.124     2.911 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=23, routed)          0.678     3.590    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_2__0_n_0
    SLICE_X30Y59         LUT3 (Prop_lut3_I2_O)        0.124     3.714 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_8__0/O
                         net (fo=1, routed)           0.000     3.714    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_8__0_n_0
    SLICE_X30Y59         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.533     4.247 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.247    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1_n_0
    SLICE_X30Y60         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.364 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.364    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1_n_0
    SLICE_X30Y61         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.315     4.679 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1/O[3]
                         net (fo=1, routed)           0.000     4.679    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1_n_4
    SLICE_X30Y61         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][11]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      8.333     8.333 r  
    W5                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388     9.721 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.181    10.902    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750     3.153 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.576     4.729    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     4.820 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.432     6.252    RLINK/SERPORT/UART/RXTX/RX/CLK1
    SLICE_X30Y61         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][11]/C
                         clock pessimism             -0.498     5.753    
                         clock uncertainty           -0.066     5.688    
    SLICE_X30Y61         FDRE (Setup_fdre_C_D)        0.109     5.797    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][11]
  -------------------------------------------------------------------
                         required time                          5.797    
                         arrival time                          -4.679    
  -------------------------------------------------------------------
                         slack                                  1.118    

Slack (MET) :             1.194ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][10]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0_1 rise@8.333ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        6.773ns  (logic 1.834ns (27.078%)  route 4.939ns (72.922%))
  Logic Levels:           6  (CARRY4=3 LUT3=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.410ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.082ns = ( 6.252 - 8.333 ) 
    Source Clock Delay      (SCD):    -2.170ns
    Clock Pessimism Removal (CPR):    -0.498ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.253     2.711    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.770 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.655    -4.115    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -4.019 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.849    -2.170    IOB_RS232/IOB_RXD/IOB/CLK1
    ILOGIC_X0Y112        FDRE                                         r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517    -1.653 f  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=17, routed)          3.622     1.969    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X30Y64         LUT4 (Prop_lut4_I2_O)        0.180     2.149 f  RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_6/O
                         net (fo=3, routed)           0.638     2.787    RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_6_n_0
    SLICE_X30Y64         LUT6 (Prop_lut6_I2_O)        0.124     2.911 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=23, routed)          0.678     3.590    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_2__0_n_0
    SLICE_X30Y59         LUT3 (Prop_lut3_I2_O)        0.124     3.714 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_8__0/O
                         net (fo=1, routed)           0.000     3.714    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_8__0_n_0
    SLICE_X30Y59         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.533     4.247 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.247    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1_n_0
    SLICE_X30Y60         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.364 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.364    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1_n_0
    SLICE_X30Y61         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     4.603 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1/O[2]
                         net (fo=1, routed)           0.000     4.603    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1_n_5
    SLICE_X30Y61         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][10]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      8.333     8.333 r  
    W5                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388     9.721 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.181    10.902    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750     3.153 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.576     4.729    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     4.820 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.432     6.252    RLINK/SERPORT/UART/RXTX/RX/CLK1
    SLICE_X30Y61         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][10]/C
                         clock pessimism             -0.498     5.753    
                         clock uncertainty           -0.066     5.688    
    SLICE_X30Y61         FDRE (Setup_fdre_C_D)        0.109     5.797    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][10]
  -------------------------------------------------------------------
                         required time                          5.797    
                         arrival time                          -4.603    
  -------------------------------------------------------------------
                         slack                                  1.194    

Slack (MET) :             1.214ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0_1 rise@8.333ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        6.753ns  (logic 1.814ns (26.862%)  route 4.939ns (73.138%))
  Logic Levels:           6  (CARRY4=3 LUT3=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.410ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.082ns = ( 6.252 - 8.333 ) 
    Source Clock Delay      (SCD):    -2.170ns
    Clock Pessimism Removal (CPR):    -0.498ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.253     2.711    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.770 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.655    -4.115    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -4.019 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.849    -2.170    IOB_RS232/IOB_RXD/IOB/CLK1
    ILOGIC_X0Y112        FDRE                                         r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517    -1.653 f  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=17, routed)          3.622     1.969    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X30Y64         LUT4 (Prop_lut4_I2_O)        0.180     2.149 f  RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_6/O
                         net (fo=3, routed)           0.638     2.787    RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_6_n_0
    SLICE_X30Y64         LUT6 (Prop_lut6_I2_O)        0.124     2.911 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=23, routed)          0.678     3.590    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_2__0_n_0
    SLICE_X30Y59         LUT3 (Prop_lut3_I2_O)        0.124     3.714 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_8__0/O
                         net (fo=1, routed)           0.000     3.714    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_8__0_n_0
    SLICE_X30Y59         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.533     4.247 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.247    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1_n_0
    SLICE_X30Y60         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     4.364 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.364    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1_n_0
    SLICE_X30Y61         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.219     4.583 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1/O[0]
                         net (fo=1, routed)           0.000     4.583    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1_n_7
    SLICE_X30Y61         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      8.333     8.333 r  
    W5                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388     9.721 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.181    10.902    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750     3.153 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.576     4.729    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     4.820 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.432     6.252    RLINK/SERPORT/UART/RXTX/RX/CLK1
    SLICE_X30Y61         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]/C
                         clock pessimism             -0.498     5.753    
                         clock uncertainty           -0.066     5.688    
    SLICE_X30Y61         FDRE (Setup_fdre_C_D)        0.109     5.797    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]
  -------------------------------------------------------------------
                         required time                          5.797    
                         arrival time                          -4.583    
  -------------------------------------------------------------------
                         slack                                  1.214    

Slack (MET) :             1.228ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][5]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0_1 rise@8.333ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        6.740ns  (logic 1.801ns (26.721%)  route 4.939ns (73.279%))
  Logic Levels:           5  (CARRY4=2 LUT3=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.409ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.081ns = ( 6.253 - 8.333 ) 
    Source Clock Delay      (SCD):    -2.170ns
    Clock Pessimism Removal (CPR):    -0.498ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.253     2.711    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.770 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.655    -4.115    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -4.019 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.849    -2.170    IOB_RS232/IOB_RXD/IOB/CLK1
    ILOGIC_X0Y112        FDRE                                         r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517    -1.653 f  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=17, routed)          3.622     1.969    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X30Y64         LUT4 (Prop_lut4_I2_O)        0.180     2.149 f  RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_6/O
                         net (fo=3, routed)           0.638     2.787    RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_6_n_0
    SLICE_X30Y64         LUT6 (Prop_lut6_I2_O)        0.124     2.911 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=23, routed)          0.678     3.590    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_2__0_n_0
    SLICE_X30Y59         LUT3 (Prop_lut3_I2_O)        0.124     3.714 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_8__0/O
                         net (fo=1, routed)           0.000     3.714    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_8__0_n_0
    SLICE_X30Y59         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.533     4.247 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.247    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1_n_0
    SLICE_X30Y60         CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323     4.570 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1/O[1]
                         net (fo=1, routed)           0.000     4.570    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1_n_6
    SLICE_X30Y60         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][5]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      8.333     8.333 r  
    W5                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388     9.721 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.181    10.902    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750     3.153 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.576     4.729    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     4.820 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.433     6.253    RLINK/SERPORT/UART/RXTX/RX/CLK1
    SLICE_X30Y60         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][5]/C
                         clock pessimism             -0.498     5.754    
                         clock uncertainty           -0.066     5.689    
    SLICE_X30Y60         FDRE (Setup_fdre_C_D)        0.109     5.798    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][5]
  -------------------------------------------------------------------
                         required time                          5.798    
                         arrival time                          -4.570    
  -------------------------------------------------------------------
                         slack                                  1.228    

Slack (MET) :             1.236ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][7]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0_1 rise@8.333ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        6.732ns  (logic 1.793ns (26.634%)  route 4.939ns (73.366%))
  Logic Levels:           5  (CARRY4=2 LUT3=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.409ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.081ns = ( 6.253 - 8.333 ) 
    Source Clock Delay      (SCD):    -2.170ns
    Clock Pessimism Removal (CPR):    -0.498ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.253     2.711    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.770 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.655    -4.115    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -4.019 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.849    -2.170    IOB_RS232/IOB_RXD/IOB/CLK1
    ILOGIC_X0Y112        FDRE                                         r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517    -1.653 f  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=17, routed)          3.622     1.969    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X30Y64         LUT4 (Prop_lut4_I2_O)        0.180     2.149 f  RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_6/O
                         net (fo=3, routed)           0.638     2.787    RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_6_n_0
    SLICE_X30Y64         LUT6 (Prop_lut6_I2_O)        0.124     2.911 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=23, routed)          0.678     3.590    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_2__0_n_0
    SLICE_X30Y59         LUT3 (Prop_lut3_I2_O)        0.124     3.714 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_8__0/O
                         net (fo=1, routed)           0.000     3.714    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_8__0_n_0
    SLICE_X30Y59         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.533     4.247 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.247    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1_n_0
    SLICE_X30Y60         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.315     4.562 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1/O[3]
                         net (fo=1, routed)           0.000     4.562    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1_n_4
    SLICE_X30Y60         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][7]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      8.333     8.333 r  
    W5                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388     9.721 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.181    10.902    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750     3.153 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.576     4.729    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     4.820 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.433     6.253    RLINK/SERPORT/UART/RXTX/RX/CLK1
    SLICE_X30Y60         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][7]/C
                         clock pessimism             -0.498     5.754    
                         clock uncertainty           -0.066     5.689    
    SLICE_X30Y60         FDRE (Setup_fdre_C_D)        0.109     5.798    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][7]
  -------------------------------------------------------------------
                         required time                          5.798    
                         arrival time                          -4.562    
  -------------------------------------------------------------------
                         slack                                  1.236    

Slack (MET) :             1.312ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][6]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0_1 rise@8.333ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        6.656ns  (logic 1.717ns (25.797%)  route 4.939ns (74.203%))
  Logic Levels:           5  (CARRY4=2 LUT3=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.409ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.081ns = ( 6.253 - 8.333 ) 
    Source Clock Delay      (SCD):    -2.170ns
    Clock Pessimism Removal (CPR):    -0.498ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.253     2.711    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.770 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.655    -4.115    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -4.019 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.849    -2.170    IOB_RS232/IOB_RXD/IOB/CLK1
    ILOGIC_X0Y112        FDRE                                         r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517    -1.653 f  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=17, routed)          3.622     1.969    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X30Y64         LUT4 (Prop_lut4_I2_O)        0.180     2.149 f  RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_6/O
                         net (fo=3, routed)           0.638     2.787    RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_6_n_0
    SLICE_X30Y64         LUT6 (Prop_lut6_I2_O)        0.124     2.911 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=23, routed)          0.678     3.590    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_2__0_n_0
    SLICE_X30Y59         LUT3 (Prop_lut3_I2_O)        0.124     3.714 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_8__0/O
                         net (fo=1, routed)           0.000     3.714    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_8__0_n_0
    SLICE_X30Y59         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.533     4.247 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.247    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1_n_0
    SLICE_X30Y60         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     4.486 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1/O[2]
                         net (fo=1, routed)           0.000     4.486    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1_n_5
    SLICE_X30Y60         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][6]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      8.333     8.333 r  
    W5                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388     9.721 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.181    10.902    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750     3.153 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.576     4.729    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     4.820 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.433     6.253    RLINK/SERPORT/UART/RXTX/RX/CLK1
    SLICE_X30Y60         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][6]/C
                         clock pessimism             -0.498     5.754    
                         clock uncertainty           -0.066     5.689    
    SLICE_X30Y60         FDRE (Setup_fdre_C_D)        0.109     5.798    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][6]
  -------------------------------------------------------------------
                         required time                          5.798    
                         arrival time                          -4.486    
  -------------------------------------------------------------------
                         slack                                  1.312    

Slack (MET) :             1.332ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0_1 rise@8.333ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        6.636ns  (logic 1.697ns (25.573%)  route 4.939ns (74.427%))
  Logic Levels:           5  (CARRY4=2 LUT3=1 LUT4=1 LUT6=1)
  Clock Path Skew:        -0.409ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.081ns = ( 6.253 - 8.333 ) 
    Source Clock Delay      (SCD):    -2.170ns
    Clock Pessimism Removal (CPR):    -0.498ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.253     2.711    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.770 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.655    -4.115    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -4.019 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.849    -2.170    IOB_RS232/IOB_RXD/IOB/CLK1
    ILOGIC_X0Y112        FDRE                                         r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517    -1.653 f  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=17, routed)          3.622     1.969    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X30Y64         LUT4 (Prop_lut4_I2_O)        0.180     2.149 f  RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_6/O
                         net (fo=3, routed)           0.638     2.787    RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_6_n_0
    SLICE_X30Y64         LUT6 (Prop_lut6_I2_O)        0.124     2.911 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=23, routed)          0.678     3.590    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_2__0_n_0
    SLICE_X30Y59         LUT3 (Prop_lut3_I2_O)        0.124     3.714 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_8__0/O
                         net (fo=1, routed)           0.000     3.714    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_8__0_n_0
    SLICE_X30Y59         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.533     4.247 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.247    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1_n_0
    SLICE_X30Y60         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.219     4.466 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1/O[0]
                         net (fo=1, routed)           0.000     4.466    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1_n_7
    SLICE_X30Y60         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      8.333     8.333 r  
    W5                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388     9.721 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.181    10.902    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750     3.153 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.576     4.729    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     4.820 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.433     6.253    RLINK/SERPORT/UART/RXTX/RX/CLK1
    SLICE_X30Y60         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]/C
                         clock pessimism             -0.498     5.754    
                         clock uncertainty           -0.066     5.689    
    SLICE_X30Y60         FDRE (Setup_fdre_C_D)        0.109     5.798    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]
  -------------------------------------------------------------------
                         required time                          5.798    
                         arrival time                          -4.466    
  -------------------------------------------------------------------
                         slack                                  1.332    

Slack (MET) :             1.379ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][0]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0_1 rise@8.333ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        6.271ns  (logic 0.821ns (13.091%)  route 5.450ns (86.909%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.412ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.084ns = ( 6.250 - 8.333 ) 
    Source Clock Delay      (SCD):    -2.170ns
    Clock Pessimism Removal (CPR):    -0.498ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.253     2.711    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.770 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.655    -4.115    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -4.019 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.849    -2.170    IOB_RS232/IOB_RXD/IOB/CLK1
    ILOGIC_X0Y112        FDRE                                         r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517    -1.653 r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=17, routed)          3.785     2.132    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X31Y65         LUT5 (Prop_lut5_I1_O)        0.180     2.312 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[txok]_i_2/O
                         net (fo=3, routed)           1.158     3.470    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[rxval]_0
    SLICE_X40Y85         LUT4 (Prop_lut4_I1_O)        0.124     3.594 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[rxdata][7]_i_1/O
                         net (fo=9, routed)           0.507     4.101    RLINK/SERPORT/XONRX/E[0]
    SLICE_X39Y85         FDRE                                         r  RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      8.333     8.333 r  
    W5                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388     9.721 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.181    10.902    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750     3.153 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.576     4.729    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     4.820 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.430     6.250    RLINK/SERPORT/XONRX/CLK1
    SLICE_X39Y85         FDRE                                         r  RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][0]/C
                         clock pessimism             -0.498     5.751    
                         clock uncertainty           -0.066     5.686    
    SLICE_X39Y85         FDRE (Setup_fdre_C_CE)      -0.205     5.481    RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][0]
  -------------------------------------------------------------------
                         required time                          5.481    
                         arrival time                          -4.101    
  -------------------------------------------------------------------
                         slack                                  1.379    

Slack (MET) :             1.379ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][1]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0_1 rise@8.333ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        6.271ns  (logic 0.821ns (13.091%)  route 5.450ns (86.909%))
  Logic Levels:           2  (LUT4=1 LUT5=1)
  Clock Path Skew:        -0.412ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.084ns = ( 6.250 - 8.333 ) 
    Source Clock Delay      (SCD):    -2.170ns
    Clock Pessimism Removal (CPR):    -0.498ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.253     2.711    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -8.482    -5.770 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.655    -4.115    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.096    -4.019 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.849    -2.170    IOB_RS232/IOB_RXD/IOB/CLK1
    ILOGIC_X0Y112        FDRE                                         r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517    -1.653 r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=17, routed)          3.785     2.132    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X31Y65         LUT5 (Prop_lut5_I1_O)        0.180     2.312 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[txok]_i_2/O
                         net (fo=3, routed)           1.158     3.470    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[rxval]_0
    SLICE_X40Y85         LUT4 (Prop_lut4_I1_O)        0.124     3.594 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[rxdata][7]_i_1/O
                         net (fo=9, routed)           0.507     4.101    RLINK/SERPORT/XONRX/E[0]
    SLICE_X39Y85         FDRE                                         r  RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      8.333     8.333 r  
    W5                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388     9.721 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.181    10.902    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750     3.153 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.576     4.729    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     4.820 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.430     6.250    RLINK/SERPORT/XONRX/CLK1
    SLICE_X39Y85         FDRE                                         r  RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][1]/C
                         clock pessimism             -0.498     5.751    
                         clock uncertainty           -0.066     5.686    
    SLICE_X39Y85         FDRE (Setup_fdre_C_CE)      -0.205     5.481    RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][1]
  -------------------------------------------------------------------
                         required time                          5.481    
                         arrival time                          -4.101    
  -------------------------------------------------------------------
                         slack                                  1.379    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.341ns
    Source Clock Delay      (SCD):    -0.570ns
    Clock Pessimism Removal (CPR):    0.229ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.656 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.501    -1.155    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.129 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.559    -0.570    RLINK/SERPORT/RXFIFO/CLKW
    SLICE_X39Y88         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y88         FDRE (Prop_fdre_C_Q)         0.141    -0.429 r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[4]/Q
                         net (fo=1, routed)           0.056    -0.373    RLINK/SERPORT/RXFIFO/RW_RADDR_S0[4]
    SLICE_X39Y88         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.481     0.895    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.743 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.546    -1.197    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.168 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.827    -0.341    RLINK/SERPORT/RXFIFO/CLKW
    SLICE_X39Y88         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[4]/C
                         clock pessimism             -0.229    -0.570    
    SLICE_X39Y88         FDRE (Hold_fdre_C_D)         0.078    -0.492    RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[4]
  -------------------------------------------------------------------
                         required time                          0.492    
                         arrival time                          -0.373    
  -------------------------------------------------------------------
                         slack                                  0.119    

Slack (MET) :             0.121ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.341ns
    Source Clock Delay      (SCD):    -0.570ns
    Clock Pessimism Removal (CPR):    0.229ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.656 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.501    -1.155    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.129 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.559    -0.570    RLINK/SERPORT/RXFIFO/CLKW
    SLICE_X39Y88         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y88         FDRE (Prop_fdre_C_Q)         0.141    -0.429 r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[3]/Q
                         net (fo=1, routed)           0.056    -0.373    RLINK/SERPORT/RXFIFO/RW_RADDR_S0[3]
    SLICE_X39Y88         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.481     0.895    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.743 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.546    -1.197    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.168 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.827    -0.341    RLINK/SERPORT/RXFIFO/CLKW
    SLICE_X39Y88         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[3]/C
                         clock pessimism             -0.229    -0.570    
    SLICE_X39Y88         FDRE (Hold_fdre_C_D)         0.076    -0.494    RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[3]
  -------------------------------------------------------------------
                         required time                          0.494    
                         arrival time                          -0.373    
  -------------------------------------------------------------------
                         slack                                  0.121    

Slack (MET) :             0.121ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.344ns
    Source Clock Delay      (SCD):    -0.572ns
    Clock Pessimism Removal (CPR):    0.228ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.656 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.501    -1.155    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.129 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.557    -0.572    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X33Y85         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y85         FDRE (Prop_fdre_C_Q)         0.141    -0.431 r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[4]/Q
                         net (fo=1, routed)           0.056    -0.375    RLINK/SERPORT/TXFIFO/RR_WADDR_S0[4]
    SLICE_X33Y85         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.481     0.895    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.743 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.546    -1.197    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.168 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.824    -0.344    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X33Y85         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[4]/C
                         clock pessimism             -0.228    -0.572    
    SLICE_X33Y85         FDRE (Hold_fdre_C_D)         0.076    -0.496    RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[4]
  -------------------------------------------------------------------
                         required time                          0.496    
                         arrival time                          -0.375    
  -------------------------------------------------------------------
                         slack                                  0.121    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.341ns
    Source Clock Delay      (SCD):    -0.570ns
    Clock Pessimism Removal (CPR):    0.229ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.656 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.501    -1.155    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.129 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.559    -0.570    RLINK/SERPORT/RXFIFO/CLKW
    SLICE_X39Y88         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y88         FDRE (Prop_fdre_C_Q)         0.141    -0.429 r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[1]/Q
                         net (fo=1, routed)           0.056    -0.373    RLINK/SERPORT/RXFIFO/RW_RADDR_S0[1]
    SLICE_X39Y88         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.481     0.895    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.743 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.546    -1.197    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.168 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.827    -0.341    RLINK/SERPORT/RXFIFO/CLKW
    SLICE_X39Y88         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[1]/C
                         clock pessimism             -0.229    -0.570    
    SLICE_X39Y88         FDRE (Hold_fdre_C_D)         0.075    -0.495    RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[1]
  -------------------------------------------------------------------
                         required time                          0.495    
                         arrival time                          -0.373    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.346ns
    Source Clock Delay      (SCD):    -0.573ns
    Clock Pessimism Removal (CPR):    0.227ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.656 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.501    -1.155    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.129 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.556    -0.573    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X35Y84         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y84         FDRE (Prop_fdre_C_Q)         0.141    -0.432 r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[0]/Q
                         net (fo=1, routed)           0.056    -0.376    RLINK/SERPORT/TXFIFO/RR_WADDR_S0[0]
    SLICE_X35Y84         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.481     0.895    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.743 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.546    -1.197    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.168 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.822    -0.346    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X35Y84         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[0]/C
                         clock pessimism             -0.227    -0.573    
    SLICE_X35Y84         FDRE (Hold_fdre_C_D)         0.075    -0.498    RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[0]
  -------------------------------------------------------------------
                         required time                          0.498    
                         arrival time                          -0.376    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.345ns
    Source Clock Delay      (SCD):    -0.572ns
    Clock Pessimism Removal (CPR):    0.227ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.656 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.501    -1.155    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.129 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.557    -0.572    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X31Y84         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X31Y84         FDRE (Prop_fdre_C_Q)         0.141    -0.431 r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[1]/Q
                         net (fo=1, routed)           0.056    -0.375    RLINK/SERPORT/TXFIFO/RR_WADDR_S0[1]
    SLICE_X31Y84         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.481     0.895    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.743 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.546    -1.197    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.168 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.823    -0.345    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X31Y84         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[1]/C
                         clock pessimism             -0.227    -0.572    
    SLICE_X31Y84         FDRE (Hold_fdre_C_D)         0.075    -0.497    RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[1]
  -------------------------------------------------------------------
                         required time                          0.497    
                         arrival time                          -0.375    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.344ns
    Source Clock Delay      (SCD):    -0.572ns
    Clock Pessimism Removal (CPR):    0.228ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.656 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.501    -1.155    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.129 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.557    -0.572    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X33Y85         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y85         FDRE (Prop_fdre_C_Q)         0.141    -0.431 r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[2]/Q
                         net (fo=1, routed)           0.056    -0.375    RLINK/SERPORT/TXFIFO/RR_WADDR_S0[2]
    SLICE_X33Y85         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.481     0.895    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.743 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.546    -1.197    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.168 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.824    -0.344    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X33Y85         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[2]/C
                         clock pessimism             -0.228    -0.572    
    SLICE_X33Y85         FDRE (Hold_fdre_C_D)         0.075    -0.497    RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[2]
  -------------------------------------------------------------------
                         required time                          0.497    
                         arrival time                          -0.375    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/CDC_ENAXON/R_DO_S0_reg/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_ENAXON/R_DO_S1_reg/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.347ns
    Source Clock Delay      (SCD):    -0.574ns
    Clock Pessimism Removal (CPR):    0.227ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.656 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.501    -1.155    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.129 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.555    -0.574    RLINK/SERPORT/CDC_ENAXON/CLKO
    SLICE_X33Y82         FDRE                                         r  RLINK/SERPORT/CDC_ENAXON/R_DO_S0_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y82         FDRE (Prop_fdre_C_Q)         0.141    -0.433 r  RLINK/SERPORT/CDC_ENAXON/R_DO_S0_reg/Q
                         net (fo=1, routed)           0.056    -0.377    RLINK/SERPORT/CDC_ENAXON/R_DO_S0
    SLICE_X33Y82         FDRE                                         r  RLINK/SERPORT/CDC_ENAXON/R_DO_S1_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.481     0.895    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.743 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.546    -1.197    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.168 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.821    -0.347    RLINK/SERPORT/CDC_ENAXON/CLKO
    SLICE_X33Y82         FDRE                                         r  RLINK/SERPORT/CDC_ENAXON/R_DO_S1_reg/C
                         clock pessimism             -0.227    -0.574    
    SLICE_X33Y82         FDRE (Hold_fdre_C_D)         0.075    -0.499    RLINK/SERPORT/CDC_ENAXON/R_DO_S1_reg
  -------------------------------------------------------------------
                         required time                          0.499    
                         arrival time                          -0.377    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.126ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.341ns
    Source Clock Delay      (SCD):    -0.570ns
    Clock Pessimism Removal (CPR):    0.229ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.656 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.501    -1.155    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.129 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.559    -0.570    RLINK/SERPORT/RXFIFO/CLKW
    SLICE_X39Y88         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y88         FDRE (Prop_fdre_C_Q)         0.141    -0.429 r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[2]/Q
                         net (fo=1, routed)           0.056    -0.373    RLINK/SERPORT/RXFIFO/RW_RADDR_S0[2]
    SLICE_X39Y88         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.481     0.895    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.743 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.546    -1.197    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.168 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.827    -0.341    RLINK/SERPORT/RXFIFO/CLKW
    SLICE_X39Y88         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[2]/C
                         clock pessimism             -0.229    -0.570    
    SLICE_X39Y88         FDRE (Hold_fdre_C_D)         0.071    -0.499    RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[2]
  -------------------------------------------------------------------
                         required time                          0.499    
                         arrival time                          -0.373    
  -------------------------------------------------------------------
                         slack                                  0.126    

Slack (MET) :             0.126ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.344ns
    Source Clock Delay      (SCD):    -0.572ns
    Clock Pessimism Removal (CPR):    0.228ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.667    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.322    -1.656 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.501    -1.155    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.026    -1.129 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.557    -0.572    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X33Y85         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y85         FDRE (Prop_fdre_C_Q)         0.141    -0.431 r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[3]/Q
                         net (fo=1, routed)           0.056    -0.375    RLINK/SERPORT/TXFIFO/RR_WADDR_S0[3]
    SLICE_X33Y85         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           0.481     0.895    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -2.638    -1.743 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           0.546    -1.197    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.029    -1.168 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.824    -0.344    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X33Y85         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[3]/C
                         clock pessimism             -0.228    -0.572    
    SLICE_X33Y85         FDRE (Hold_fdre_C_D)         0.071    -0.501    RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[3]
  -------------------------------------------------------------------
                         required time                          0.501    
                         arrival time                          -0.375    
  -------------------------------------------------------------------
                         slack                                  0.126    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         CLKOUT0_1
Waveform(ns):       { 0.000 4.167 }
Period(ns):         8.333
Sources:            { GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location        Pin
Min Period        n/a     BUFG/I             n/a            2.155         8.333       6.178      BUFGCTRL_X0Y1   GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/I
Min Period        n/a     FDRE/C             n/a            1.474         8.333       6.859      ILOGIC_X0Y112   IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
Min Period        n/a     FDRE/C             n/a            1.474         8.333       6.859      OLOGIC_X0Y111   IOB_RS232/IOB_TXD/IOB/R_DO_reg[0]/C
Min Period        n/a     PLLE2_ADV/CLKOUT0  n/a            1.249         8.333       7.084      PLLE2_ADV_X1Y0  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
Min Period        n/a     FDRE/C             n/a            1.000         8.333       7.333      SLICE_X33Y82    RLINK/SERPORT/CDC_ENAXON/R_DO_S0_reg/C
Min Period        n/a     FDRE/C             n/a            1.000         8.333       7.333      SLICE_X33Y82    RLINK/SERPORT/CDC_ENAXON/R_DO_S1_reg/C
Min Period        n/a     FDRE/C             n/a            1.000         8.333       7.333      SLICE_X28Y81    RLINK/SERPORT/CDC_RESET/RS_REQ_S0_reg/C
Min Period        n/a     FDRE/C             n/a            1.000         8.333       7.333      SLICE_X28Y81    RLINK/SERPORT/CDC_RESET/RS_REQ_S1_reg/C
Min Period        n/a     FDRE/C             n/a            1.000         8.333       7.333      SLICE_X38Y85    RLINK/SERPORT/RXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[0]/C
Min Period        n/a     FDRE/C             n/a            1.000         8.333       7.333      SLICE_X38Y85    RLINK/SERPORT/RXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[1]/C
Max Period        n/a     PLLE2_ADV/CLKOUT0  n/a            160.000       8.333       151.667    PLLE2_ADV_X1Y0  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
Low Pulse Width   Fast    RAMD32/CLK         n/a            1.250         4.167       2.917      SLICE_X42Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK         n/a            1.250         4.167       2.917      SLICE_X42Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK         n/a            1.250         4.167       2.917      SLICE_X42Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
Low Pulse Width   Fast    RAMD32/CLK         n/a            1.250         4.167       2.917      SLICE_X42Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK         n/a            1.250         4.167       2.917      SLICE_X42Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK         n/a            1.250         4.167       2.917      SLICE_X42Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMC_D1/CLK
Low Pulse Width   Fast    RAMS32/CLK         n/a            1.250         4.167       2.917      SLICE_X42Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMD/CLK
Low Pulse Width   Fast    RAMS32/CLK         n/a            1.250         4.167       2.917      SLICE_X42Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMD_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK         n/a            1.250         4.167       2.917      SLICE_X38Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK         n/a            1.250         4.167       2.917      SLICE_X38Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMA_D1/CLK
High Pulse Width  Slow    RAMD32/CLK         n/a            1.250         4.167       2.917      SLICE_X42Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK         n/a            1.250         4.167       2.917      SLICE_X42Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1/CLK
High Pulse Width  Slow    RAMD32/CLK         n/a            1.250         4.167       2.917      SLICE_X42Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
High Pulse Width  Slow    RAMD32/CLK         n/a            1.250         4.167       2.917      SLICE_X42Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMB_D1/CLK
High Pulse Width  Slow    RAMD32/CLK         n/a            1.250         4.167       2.917      SLICE_X42Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
High Pulse Width  Slow    RAMD32/CLK         n/a            1.250         4.167       2.917      SLICE_X42Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMC_D1/CLK
High Pulse Width  Slow    RAMS32/CLK         n/a            1.250         4.167       2.917      SLICE_X42Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMD/CLK
High Pulse Width  Slow    RAMS32/CLK         n/a            1.250         4.167       2.917      SLICE_X42Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMD_D1/CLK
High Pulse Width  Slow    RAMD32/CLK         n/a            1.250         4.167       2.917      SLICE_X38Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMA/CLK
High Pulse Width  Slow    RAMD32/CLK         n/a            1.250         4.167       2.917      SLICE_X38Y86    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMA_D1/CLK



---------------------------------------------------------------------------------------------------
From Clock:  CLKOUT0_1
  To Clock:  CLKOUT0

Setup :            0  Failing Endpoints,  Worst Slack        2.548ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.548ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIVF/R_DO_S0_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.167ns  (MaxDelay Path 4.167ns)
  Data Path Delay:        1.591ns  (logic 0.518ns (32.558%)  route 1.073ns (67.442%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 4.167ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y60                                      0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][0]/C
    SLICE_X34Y60         FDRE (Prop_fdre_C_Q)         0.518     0.518 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][0]/Q
                         net (fo=3, routed)           1.073     1.591    RLINK/SERPORT/CDC_CDIVF/DI[0]
    SLICE_X34Y56         FDRE                                         r  RLINK/SERPORT/CDC_CDIVF/R_DO_S0_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    4.167     4.167    
    SLICE_X34Y56         FDRE (Setup_fdre_C_D)       -0.028     4.139    RLINK/SERPORT/CDC_CDIVF/R_DO_S0_reg[0]
  -------------------------------------------------------------------
                         required time                          4.139    
                         arrival time                          -1.591    
  -------------------------------------------------------------------
                         slack                                  2.548    

Slack (MET) :             2.556ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][4]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.167ns  (MaxDelay Path 4.167ns)
  Data Path Delay:        1.544ns  (logic 0.456ns (29.531%)  route 1.088ns (70.469%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 4.167ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y59                                      0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][4]/C
    SLICE_X32Y59         FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][4]/Q
                         net (fo=6, routed)           1.088     1.544    RLINK/SERPORT/CDC_CDIV/DI[1]
    SLICE_X35Y56         FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    4.167     4.167    
    SLICE_X35Y56         FDRE (Setup_fdre_C_D)       -0.067     4.100    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[1]
  -------------------------------------------------------------------
                         required time                          4.100    
                         arrival time                          -1.544    
  -------------------------------------------------------------------
                         slack                                  2.556    

Slack (MET) :             2.841ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][11]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.167ns  (MaxDelay Path 4.167ns)
  Data Path Delay:        1.298ns  (logic 0.456ns (35.136%)  route 0.842ns (64.864%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 4.167ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y60                                      0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][11]/C
    SLICE_X32Y60         FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][11]/Q
                         net (fo=7, routed)           0.842     1.298    RLINK/SERPORT/CDC_CDIV/DI[8]
    SLICE_X34Y53         FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    4.167     4.167    
    SLICE_X34Y53         FDRE (Setup_fdre_C_D)       -0.028     4.139    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[8]
  -------------------------------------------------------------------
                         required time                          4.139    
                         arrival time                          -1.298    
  -------------------------------------------------------------------
                         slack                                  2.841    

Slack (MET) :             2.880ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][9]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.167ns  (MaxDelay Path 4.167ns)
  Data Path Delay:        1.271ns  (logic 0.456ns (35.874%)  route 0.815ns (64.126%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 4.167ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y60                                      0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][9]/C
    SLICE_X32Y60         FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][9]/Q
                         net (fo=7, routed)           0.815     1.271    RLINK/SERPORT/CDC_CDIV/DI[6]
    SLICE_X34Y56         FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    4.167     4.167    
    SLICE_X34Y56         FDRE (Setup_fdre_C_D)       -0.016     4.151    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[6]
  -------------------------------------------------------------------
                         required time                          4.151    
                         arrival time                          -1.271    
  -------------------------------------------------------------------
                         slack                                  2.880    

Slack (MET) :             2.881ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][8]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.167ns  (MaxDelay Path 4.167ns)
  Data Path Delay:        1.241ns  (logic 0.456ns (36.738%)  route 0.785ns (63.262%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 4.167ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y60                                      0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][8]/C
    SLICE_X32Y60         FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][8]/Q
                         net (fo=7, routed)           0.785     1.241    RLINK/SERPORT/CDC_CDIV/DI[5]
    SLICE_X34Y53         FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    4.167     4.167    
    SLICE_X34Y53         FDRE (Setup_fdre_C_D)       -0.045     4.122    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[5]
  -------------------------------------------------------------------
                         required time                          4.122    
                         arrival time                          -1.241    
  -------------------------------------------------------------------
                         slack                                  2.881    

Slack (MET) :             2.927ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][10]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.167ns  (MaxDelay Path 4.167ns)
  Data Path Delay:        1.135ns  (logic 0.456ns (40.169%)  route 0.679ns (59.831%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 4.167ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y60                                      0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][10]/C
    SLICE_X32Y60         FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][10]/Q
                         net (fo=7, routed)           0.679     1.135    RLINK/SERPORT/CDC_CDIV/DI[7]
    SLICE_X33Y59         FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    4.167     4.167    
    SLICE_X33Y59         FDRE (Setup_fdre_C_D)       -0.105     4.062    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[7]
  -------------------------------------------------------------------
                         required time                          4.062    
                         arrival time                          -1.135    
  -------------------------------------------------------------------
                         slack                                  2.927    

Slack (MET) :             2.939ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][6]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.167ns  (MaxDelay Path 4.167ns)
  Data Path Delay:        1.167ns  (logic 0.518ns (44.374%)  route 0.649ns (55.626%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 4.167ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y60                                      0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][6]/C
    SLICE_X34Y60         FDRE (Prop_fdre_C_Q)         0.518     0.518 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][6]/Q
                         net (fo=6, routed)           0.649     1.167    RLINK/SERPORT/CDC_CDIV/DI[3]
    SLICE_X35Y56         FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    4.167     4.167    
    SLICE_X35Y56         FDRE (Setup_fdre_C_D)       -0.061     4.106    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[3]
  -------------------------------------------------------------------
                         required time                          4.106    
                         arrival time                          -1.167    
  -------------------------------------------------------------------
                         slack                                  2.939    

Slack (MET) :             2.939ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.167ns  (MaxDelay Path 4.167ns)
  Data Path Delay:        1.147ns  (logic 0.518ns (45.157%)  route 0.629ns (54.843%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 4.167ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y60                                      0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
    SLICE_X34Y60         FDRE (Prop_fdre_C_Q)         0.518     0.518 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/Q
                         net (fo=6, routed)           0.629     1.147    RLINK/SERPORT/CDC_CDIV/DI[2]
    SLICE_X35Y56         FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    4.167     4.167    
    SLICE_X35Y56         FDRE (Setup_fdre_C_D)       -0.081     4.086    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[2]
  -------------------------------------------------------------------
                         required time                          4.086    
                         arrival time                          -1.147    
  -------------------------------------------------------------------
                         slack                                  2.939    

Slack (MET) :             2.945ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][7]/C
                            (rising edge-triggered cell FDSE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.167ns  (MaxDelay Path 4.167ns)
  Data Path Delay:        1.164ns  (logic 0.518ns (44.491%)  route 0.646ns (55.509%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 4.167ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y60                                      0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][7]/C
    SLICE_X34Y60         FDSE (Prop_fdse_C_Q)         0.518     0.518 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][7]/Q
                         net (fo=7, routed)           0.646     1.164    RLINK/SERPORT/CDC_CDIV/DI[4]
    SLICE_X35Y56         FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    4.167     4.167    
    SLICE_X35Y56         FDRE (Setup_fdre_C_D)       -0.058     4.109    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[4]
  -------------------------------------------------------------------
                         required time                          4.109    
                         arrival time                          -1.164    
  -------------------------------------------------------------------
                         slack                                  2.945    

Slack (MET) :             2.957ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][12]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            4.167ns  (MaxDelay Path 4.167ns)
  Data Path Delay:        1.165ns  (logic 0.456ns (39.153%)  route 0.709ns (60.847%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 4.167ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y63                                      0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][12]/C
    SLICE_X33Y63         FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][12]/Q
                         net (fo=7, routed)           0.709     1.165    RLINK/SERPORT/CDC_CDIV/DI[9]
    SLICE_X34Y56         FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    4.167     4.167    
    SLICE_X34Y56         FDRE (Setup_fdre_C_D)       -0.045     4.122    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[9]
  -------------------------------------------------------------------
                         required time                          4.122    
                         arrival time                          -1.165    
  -------------------------------------------------------------------
                         slack                                  2.957    





---------------------------------------------------------------------------------------------------
From Clock:  CLKOUT0
  To Clock:  CLKOUT0_1

Setup :            0  Failing Endpoints,  Worst Slack        4.628ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             4.628ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.943ns  (logic 0.456ns (23.467%)  route 1.487ns (76.533%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y83                                      0.000     0.000 r  RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[1]/C
    SLICE_X37Y83         FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[1]/Q
                         net (fo=25, routed)          1.487     1.943    RLINK/SERPORT/TXFIFO/WADDR[1]
    SLICE_X31Y84         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X31Y84         FDRE (Setup_fdre_C_D)       -0.095     6.571    RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[1]
  -------------------------------------------------------------------
                         required time                          6.571    
                         arrival time                          -1.943    
  -------------------------------------------------------------------
                         slack                                  4.628    

Slack (MET) :             4.703ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.870ns  (logic 0.456ns (24.380%)  route 1.414ns (75.620%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y83                                      0.000     0.000 r  RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[4]/C
    SLICE_X37Y83         FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[4]/Q
                         net (fo=27, routed)          1.414     1.870    RLINK/SERPORT/TXFIFO/WADDR[4]
    SLICE_X33Y85         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X33Y85         FDRE (Setup_fdre_C_D)       -0.093     6.573    RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[4]
  -------------------------------------------------------------------
                         required time                          6.573    
                         arrival time                          -1.870    
  -------------------------------------------------------------------
                         slack                                  4.703    

Slack (MET) :             4.856ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][2]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (MaxDelay Path 8.333ns)
  Data Path Delay:        1.835ns  (logic 1.343ns (73.190%)  route 0.492ns (26.810%))
  Logic Levels:           0  
  Clock Path Skew:        -1.048ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.086ns
    Source Clock Delay      (SCD):    -0.968ns
    Clock Pessimism Removal (CPR):    0.070ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.259ns
    Phase Error              (PE):    0.144ns
  Timing Exception:       MaxDelay Path 8.333ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.691    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.961    -4.269 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.608    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.512 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.544    -0.968    RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X34Y83         RAMD32                                       r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y83         RAMD32 (Prop_ramd32_CLK_O)
                                                      1.343     0.375 r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMB/O
                         net (fo=1, routed)           0.492     0.867    RLINK/SERPORT/XONTX/D[2]
    SLICE_X33Y83         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    8.333     8.333    
    W5                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388     9.721 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.181    10.902    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750     3.152 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.576     4.729    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     4.820 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.428     6.247    RLINK/SERPORT/XONTX/CLK1
    SLICE_X33Y83         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][2]/C
                         clock pessimism              0.070     6.318    
                         clock uncertainty           -0.278     6.040    
    SLICE_X33Y83         FDRE (Setup_fdre_C_D)       -0.317     5.723    RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][2]
  -------------------------------------------------------------------
                         required time                          5.723    
                         arrival time                          -0.867    
  -------------------------------------------------------------------
                         slack                                  4.856    

Slack (MET) :             4.869ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][0]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (MaxDelay Path 8.333ns)
  Data Path Delay:        1.839ns  (logic 1.344ns (73.070%)  route 0.495ns (26.930%))
  Logic Levels:           0  
  Clock Path Skew:        -1.048ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.086ns
    Source Clock Delay      (SCD):    -0.968ns
    Clock Pessimism Removal (CPR):    0.070ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.259ns
    Phase Error              (PE):    0.144ns
  Timing Exception:       MaxDelay Path 8.333ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.691    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.961    -4.269 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.608    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.512 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.544    -0.968    RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X34Y83         RAMD32                                       r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y83         RAMD32 (Prop_ramd32_CLK_O)
                                                      1.344     0.376 r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMA/O
                         net (fo=1, routed)           0.495     0.871    RLINK/SERPORT/XONTX/D[0]
    SLICE_X33Y83         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    8.333     8.333    
    W5                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388     9.721 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.181    10.902    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750     3.152 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.576     4.729    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     4.820 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.428     6.247    RLINK/SERPORT/XONTX/CLK1
    SLICE_X33Y83         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][0]/C
                         clock pessimism              0.070     6.318    
                         clock uncertainty           -0.278     6.040    
    SLICE_X33Y83         FDRE (Setup_fdre_C_D)       -0.299     5.741    RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][0]
  -------------------------------------------------------------------
                         required time                          5.741    
                         arrival time                          -0.871    
  -------------------------------------------------------------------
                         slack                                  4.869    

Slack (MET) :             4.875ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.696ns  (logic 0.456ns (26.881%)  route 1.240ns (73.119%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y84                                      0.000     0.000 r  RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[2]/C
    SLICE_X37Y84         FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[2]/Q
                         net (fo=26, routed)          1.240     1.696    RLINK/SERPORT/TXFIFO/WADDR[2]
    SLICE_X33Y85         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X33Y85         FDRE (Setup_fdre_C_D)       -0.095     6.571    RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[2]
  -------------------------------------------------------------------
                         required time                          6.571    
                         arrival time                          -1.696    
  -------------------------------------------------------------------
                         slack                                  4.875    

Slack (MET) :             4.921ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][4]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (MaxDelay Path 8.333ns)
  Data Path Delay:        1.833ns  (logic 1.336ns (72.905%)  route 0.497ns (27.095%))
  Logic Levels:           0  
  Clock Path Skew:        -1.048ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.086ns
    Source Clock Delay      (SCD):    -0.968ns
    Clock Pessimism Removal (CPR):    0.070ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.259ns
    Phase Error              (PE):    0.144ns
  Timing Exception:       MaxDelay Path 8.333ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.691    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.961    -4.269 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.608    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.512 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.544    -0.968    RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X34Y83         RAMD32                                       r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y83         RAMD32 (Prop_ramd32_CLK_O)
                                                      1.336     0.368 r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMC/O
                         net (fo=1, routed)           0.497     0.865    RLINK/SERPORT/XONTX/D[4]
    SLICE_X33Y83         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][4]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    8.333     8.333    
    W5                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388     9.721 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.181    10.902    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750     3.152 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.576     4.729    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     4.820 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.428     6.247    RLINK/SERPORT/XONTX/CLK1
    SLICE_X33Y83         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][4]/C
                         clock pessimism              0.070     6.318    
                         clock uncertainty           -0.278     6.040    
    SLICE_X33Y83         FDRE (Setup_fdre_C_D)       -0.254     5.786    RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][4]
  -------------------------------------------------------------------
                         required time                          5.786    
                         arrival time                          -0.865    
  -------------------------------------------------------------------
                         slack                                  4.921    

Slack (MET) :             5.059ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_6_7/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][6]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (MaxDelay Path 8.333ns)
  Data Path Delay:        1.701ns  (logic 1.344ns (79.034%)  route 0.357ns (20.966%))
  Logic Levels:           0  
  Clock Path Skew:        -1.049ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.086ns
    Source Clock Delay      (SCD):    -0.967ns
    Clock Pessimism Removal (CPR):    0.070ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.259ns
    Phase Error              (PE):    0.144ns
  Timing Exception:       MaxDelay Path 8.333ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.691    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.961    -4.269 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.608    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.512 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.545    -0.967    RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_6_7/WCLK
    SLICE_X34Y84         RAMD32                                       r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_6_7/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y84         RAMD32 (Prop_ramd32_CLK_O)
                                                      1.344     0.377 r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_6_7/RAMA/O
                         net (fo=1, routed)           0.357     0.734    RLINK/SERPORT/XONTX/D[6]
    SLICE_X33Y83         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][6]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    8.333     8.333    
    W5                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388     9.721 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.181    10.902    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750     3.152 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.576     4.729    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     4.820 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.428     6.247    RLINK/SERPORT/XONTX/CLK1
    SLICE_X33Y83         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][6]/C
                         clock pessimism              0.070     6.318    
                         clock uncertainty           -0.278     6.040    
    SLICE_X33Y83         FDRE (Setup_fdre_C_D)       -0.247     5.793    RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][6]
  -------------------------------------------------------------------
                         required time                          5.793    
                         arrival time                          -0.734    
  -------------------------------------------------------------------
                         slack                                  5.059    

Slack (MET) :             5.146ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMB_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][3]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (MaxDelay Path 8.333ns)
  Data Path Delay:        1.769ns  (logic 1.317ns (74.446%)  route 0.452ns (25.554%))
  Logic Levels:           0  
  Clock Path Skew:        -1.048ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.086ns
    Source Clock Delay      (SCD):    -0.968ns
    Clock Pessimism Removal (CPR):    0.070ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.259ns
    Phase Error              (PE):    0.144ns
  Timing Exception:       MaxDelay Path 8.333ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.691    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.961    -4.269 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.608    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.512 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.544    -0.968    RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X34Y83         RAMD32                                       r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMB_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y83         RAMD32 (Prop_ramd32_CLK_O)
                                                      1.317     0.349 r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMB_D1/O
                         net (fo=1, routed)           0.452     0.801    RLINK/SERPORT/XONTX/D[3]
    SLICE_X33Y83         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    8.333     8.333    
    W5                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388     9.721 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.181    10.902    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750     3.152 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.576     4.729    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     4.820 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.428     6.247    RLINK/SERPORT/XONTX/CLK1
    SLICE_X33Y83         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][3]/C
                         clock pessimism              0.070     6.318    
                         clock uncertainty           -0.278     6.040    
    SLICE_X33Y83         FDRE (Setup_fdre_C_D)       -0.092     5.948    RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][3]
  -------------------------------------------------------------------
                         required time                          5.948    
                         arrival time                          -0.801    
  -------------------------------------------------------------------
                         slack                                  5.146    

Slack (MET) :             5.163ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/R_DATA_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.408ns  (logic 0.456ns (32.385%)  route 0.952ns (67.615%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y87                                      0.000     0.000 r  RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/R_DATA_reg[1]/C
    SLICE_X40Y87         FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/R_DATA_reg[1]/Q
                         net (fo=20, routed)          0.952     1.408    RLINK/SERPORT/RXFIFO/RADDR[1]
    SLICE_X39Y88         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X39Y88         FDRE (Setup_fdre_C_D)       -0.095     6.571    RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[1]
  -------------------------------------------------------------------
                         required time                          6.571    
                         arrival time                          -1.408    
  -------------------------------------------------------------------
                         slack                                  5.163    

Slack (MET) :             5.164ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1/CLK
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][1]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (MaxDelay Path 8.333ns)
  Data Path Delay:        1.751ns  (logic 1.309ns (74.763%)  route 0.442ns (25.237%))
  Logic Levels:           0  
  Clock Path Skew:        -1.048ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -2.086ns
    Source Clock Delay      (SCD):    -0.968ns
    Clock Pessimism Removal (CPR):    0.070ns
  Clock Uncertainty:      0.278ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.259ns
    Phase Error              (PE):    0.144ns
  Timing Exception:       MaxDelay Path 8.333ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.691    GEN_CLKALL/GEN_CLK0/CLKIN
    MMCME2_ADV_X1Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.961    -4.269 r  GEN_CLKALL/GEN_CLK0/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.608    GEN_CLKALL/GEN_CLK0/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.512 r  GEN_CLKALL/GEN_CLK0/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2804, routed)        1.544    -0.968    RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X34Y83         RAMD32                                       r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X34Y83         RAMD32 (Prop_ramd32_CLK_O)
                                                      1.309     0.341 r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1/O
                         net (fo=1, routed)           0.442     0.783    RLINK/SERPORT/XONTX/D[1]
    SLICE_X33Y83         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    8.333     8.333    
    W5                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388     9.721 r  I_CLK100_IBUF_inst/O
                         net (fo=2, routed)           1.181    10.902    GEN_CLKALL/GEN_CLK1/CLKIN
    PLLE2_ADV_X1Y0       PLLE2_ADV (Prop_plle2_adv_CLKIN1_CLKOUT0)
                                                     -7.750     3.152 r  GEN_CLKALL/GEN_CLK1/USEPLL.PLL/CLKOUT0
                         net (fo=1, routed)           1.576     4.729    GEN_CLKALL/GEN_CLK1/CLKOUT0
    BUFGCTRL_X0Y1        BUFG (Prop_bufg_I_O)         0.091     4.820 r  GEN_CLKALL/GEN_CLK1/USEPLL.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.428     6.247    RLINK/SERPORT/XONTX/CLK1
    SLICE_X33Y83         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][1]/C
                         clock pessimism              0.070     6.318    
                         clock uncertainty           -0.278     6.040    
    SLICE_X33Y83         FDRE (Setup_fdre_C_D)       -0.093     5.947    RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][1]
  -------------------------------------------------------------------
                         required time                          5.947    
                         arrival time                          -0.783    
  -------------------------------------------------------------------
                         slack                                  5.164    





