
*** Running vivado
    with args -log sys_w11a_b3.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source sys_w11a_b3.tcl -notrace


****** Vivado v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source sys_w11a_b3.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 338 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.2
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/basys3/basys3_pclk.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/basys3/basys3_pclk.xdc]
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/basys3/basys3_pins.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/basys3/basys3_pins.xdc]
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_ABDONE'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc:13]
INFO: [Timing 38-2] Deriving generated clocks [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc:13]
get_clocks: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1780.125 ; gain = 456.438 ; free physical = 740 ; free virtual = 8785
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_ABDONE'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RESET'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RESET'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXERR'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXERR'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXOVR'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXOVR'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ABACT'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ABACT'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAESC'
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAESC'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAXON'
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAXON'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXACT'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXACT'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXOK'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXOK'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXACT'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXACT'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXOK'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXOK'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIV'
WARNING: [Vivado 12-2489] -delay contains time 4.166500 which will be rounded to 4.167 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc:34]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIV'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIVF'
WARNING: [Vivado 12-2489] -delay contains time 4.166500 which will be rounded to 4.167 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc:34]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIVF'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/RXFIFO'
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:23]
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:28]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/RXFIFO'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/TXFIFO'
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:35]
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:40]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/TXFIFO'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 152 instances were transformed.
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 16 instances
  RAM16X1S => RAM32X1S (RAMS32): 32 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 6 instances
  RAM32X1S => RAM32X1S (RAMS32): 69 instances
  RAM64X1S => RAM64X1S (RAMS64E): 29 instances

link_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 1780.125 ; gain = 701.066 ; free physical = 760 ; free virtual = 8791
Command: opt_design -directive Explore
INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
Running DRC as a precondition to command opt_design

Starting DRC Task
Command: report_drc (run_mandatory_drcs) for: opt_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1784.133 ; gain = 4.008 ; free physical = 753 ; free virtual = 8785
INFO: [Timing 38-35] Done setting XDC timing constraints.

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 11fd1bde4

Time (s): cpu = 00:00:00.91 ; elapsed = 00:00:00.71 . Memory (MB): peak = 1784.133 ; gain = 0.000 ; free physical = 753 ; free virtual = 8785
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 135 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 19485841d

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1784.133 ; gain = 0.000 ; free physical = 751 ; free virtual = 8783
INFO: [Opt 31-389] Phase Constant propagation created 11 cells and removed 26 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: d1fd601a

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1784.133 ; gain = 0.000 ; free physical = 751 ; free virtual = 8783
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 59 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: d1fd601a

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1784.133 ; gain = 0.000 ; free physical = 751 ; free virtual = 8783
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: d1fd601a

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1784.133 ; gain = 0.000 ; free physical = 751 ; free virtual = 8783
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1784.133 ; gain = 0.000 ; free physical = 751 ; free virtual = 8783
Ending Logic Optimization Task | Checksum: d1fd601a

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1784.133 ; gain = 0.000 ; free physical = 751 ; free virtual = 8783

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Power 33-23] Power model is not available for UA
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...

Finished Running Vector-less Activity Propagation


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 50 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 5 newly gated: 0 Total Ports: 100
Ending PowerOpt Patch Enables Task | Checksum: 1e6b0b0b6

Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.05 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 723 ; free virtual = 8755
Ending Power Optimization Task | Checksum: 1e6b0b0b6

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1983.352 ; gain = 199.219 ; free physical = 732 ; free virtual = 8764
30 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 1983.352 ; gain = 203.227 ; free physical = 732 ; free virtual = 8764
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 733 ; free virtual = 8766
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/impl_1/sys_w11a_b3_opt.dcp' has been generated.
Command: report_drc -file sys_w11a_b3_drc_opted.rpt
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/impl_1/sys_w11a_b3_drc_opted.rpt.
report_drc completed successfully
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
Command: report_drc (run_mandatory_drcs) for: incr_eco_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
Command: report_drc (run_mandatory_drcs) for: placer_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 46-5] The placer was invoked with the 'Explore' directive.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 726 ; free virtual = 8761
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 11e522e87

Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 726 ; free virtual = 8761
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 727 ; free virtual = 8761

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 142548df2

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 721 ; free virtual = 8755

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1b7b70873

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 707 ; free virtual = 8741

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1b7b70873

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 707 ; free virtual = 8741
Phase 1 Placer Initialization | Checksum: 1b7b70873

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 707 ; free virtual = 8741

Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 172ace2e9

Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 697 ; free virtual = 8730

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 172ace2e9

Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 697 ; free virtual = 8730

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 158e98e2a

Time (s): cpu = 00:00:22 ; elapsed = 00:00:17 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 694 ; free virtual = 8728

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 154e71a51

Time (s): cpu = 00:00:22 ; elapsed = 00:00:17 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 694 ; free virtual = 8728

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 154e71a51

Time (s): cpu = 00:00:22 ; elapsed = 00:00:17 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 694 ; free virtual = 8728

Phase 3.5 Timing Path Optimizer
Phase 3.5 Timing Path Optimizer | Checksum: 1a602cb04

Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 694 ; free virtual = 8728

Phase 3.6 Fast Optimization
Phase 3.6 Fast Optimization | Checksum: 12a8d8b4c

Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 694 ; free virtual = 8728

Phase 3.7 Small Shape Detail Placement
Phase 3.7 Small Shape Detail Placement | Checksum: 174924a82

Time (s): cpu = 00:00:27 ; elapsed = 00:00:21 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 688 ; free virtual = 8722

Phase 3.8 Re-assign LUT pins
Phase 3.8 Re-assign LUT pins | Checksum: 18eb67428

Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 688 ; free virtual = 8722

Phase 3.9 Pipeline Register Optimization
Phase 3.9 Pipeline Register Optimization | Checksum: 18eb67428

Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 688 ; free virtual = 8722

Phase 3.10 Fast Optimization
Phase 3.10 Fast Optimization | Checksum: 170291095

Time (s): cpu = 00:00:29 ; elapsed = 00:00:24 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 689 ; free virtual = 8723
Phase 3 Detail Placement | Checksum: 170291095

Time (s): cpu = 00:00:29 ; elapsed = 00:00:24 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 689 ; free virtual = 8723

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1ab7038d7

Phase 4.1.1.1 BUFG Insertion
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
INFO: [Place 46-41] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
Phase 4.1.1.1 BUFG Insertion | Checksum: 1ab7038d7

Time (s): cpu = 00:00:33 ; elapsed = 00:00:26 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 688 ; free virtual = 8722
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.552. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: d69df244

Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 688 ; free virtual = 8722
Phase 4.1 Post Commit Optimization | Checksum: d69df244

Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 688 ; free virtual = 8722

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: d69df244

Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 689 ; free virtual = 8724

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: d69df244

Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 689 ; free virtual = 8724

Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: dcc2917b

Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 689 ; free virtual = 8724
Phase 4 Post Placement Optimization and Clean-Up | Checksum: dcc2917b

Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 689 ; free virtual = 8724
Ending Placer Task | Checksum: 9a0146a1

Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 695 ; free virtual = 8729
50 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:41 ; elapsed = 00:00:33 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 695 ; free virtual = 8729
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 686 ; free virtual = 8731
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/impl_1/sys_w11a_b3_placed.dcp' has been generated.
report_io: Time (s): cpu = 00:00:00.23 ; elapsed = 00:00:00.34 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 689 ; free virtual = 8726
report_utilization: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 693 ; free virtual = 8730
report_control_sets: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 693 ; free virtual = 8730
Command: phys_opt_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.500 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
55 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.96 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 680 ; free virtual = 8727
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/impl_1/sys_w11a_b3_physopt.dcp' has been generated.
Command: route_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
Running DRC as a precondition to command route_design
Command: report_drc (run_mandatory_drcs) for: router_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-270] Using Router directive 'Explore'.
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 1dcadcc4 ConstDB: 0 ShapeSum: 7c3669dd RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 18cb4fa29

Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 659 ; free virtual = 8740

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 18cb4fa29

Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 662 ; free virtual = 8742

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 18cb4fa29

Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 649 ; free virtual = 8735

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 18cb4fa29

Time (s): cpu = 00:00:24 ; elapsed = 00:00:21 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 649 ; free virtual = 8735
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 1905ab2e7

Time (s): cpu = 00:00:30 ; elapsed = 00:00:27 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 661 ; free virtual = 8747
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.602  | TNS=0.000  | WHS=-0.320 | THS=-125.530|

Phase 2 Router Initialization | Checksum: 25206115d

Time (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 666 ; free virtual = 8752

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 166a3cff5

Time (s): cpu = 00:00:35 ; elapsed = 00:00:30 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 687 ; free virtual = 8773

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 1614
 Number of Nodes with overlaps = 242
 Number of Nodes with overlaps = 40
 Number of Nodes with overlaps = 9
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.199  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 1acc65f8c

Time (s): cpu = 00:00:56 ; elapsed = 00:00:47 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 691 ; free virtual = 8786
Phase 4 Rip-up And Reroute | Checksum: 1acc65f8c

Time (s): cpu = 00:00:56 ; elapsed = 00:00:47 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 691 ; free virtual = 8786

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 1f2eed957

Time (s): cpu = 00:00:57 ; elapsed = 00:00:47 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 691 ; free virtual = 8786
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.278  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 5.1 Delay CleanUp | Checksum: 1f2eed957

Time (s): cpu = 00:00:57 ; elapsed = 00:00:47 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 691 ; free virtual = 8786

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1f2eed957

Time (s): cpu = 00:00:57 ; elapsed = 00:00:47 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 691 ; free virtual = 8786
Phase 5 Delay and Skew Optimization | Checksum: 1f2eed957

Time (s): cpu = 00:00:57 ; elapsed = 00:00:47 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 691 ; free virtual = 8786

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 18e644a5a

Time (s): cpu = 00:00:59 ; elapsed = 00:00:48 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 691 ; free virtual = 8786
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.278  | TNS=0.000  | WHS=0.052  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 20413601a

Time (s): cpu = 00:00:59 ; elapsed = 00:00:48 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 691 ; free virtual = 8786
Phase 6 Post Hold Fix | Checksum: 20413601a

Time (s): cpu = 00:00:59 ; elapsed = 00:00:48 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 691 ; free virtual = 8786

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 3.79678 %
  Global Horizontal Routing Utilization  = 4.11465 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 1928e845a

Time (s): cpu = 00:00:59 ; elapsed = 00:00:49 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 690 ; free virtual = 8785

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1928e845a

Time (s): cpu = 00:00:59 ; elapsed = 00:00:49 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 690 ; free virtual = 8785

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 197fa11a1

Time (s): cpu = 00:01:00 ; elapsed = 00:00:50 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 690 ; free virtual = 8785

Phase 10 Post Router Timing
INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.290  | TNS=0.000  | WHS=0.055  | THS=0.000  |

INFO: [Route 35-61] The design met the timing requirement.
Phase 10 Post Router Timing | Checksum: 195fce93c

Time (s): cpu = 00:01:06 ; elapsed = 00:00:53 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 687 ; free virtual = 8782
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:01:06 ; elapsed = 00:00:53 . Memory (MB): peak = 1983.352 ; gain = 0.000 ; free physical = 750 ; free virtual = 8845

Routing Is Done.
69 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:10 ; elapsed = 00:00:55 . Memory (MB): peak = 2017.305 ; gain = 33.953 ; free physical = 750 ; free virtual = 8845
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2017.305 ; gain = 0.000 ; free physical = 737 ; free virtual = 8844
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/impl_1/sys_w11a_b3_routed.dcp' has been generated.
Command: report_drc -file sys_w11a_b3_drc_routed.rpt -pb sys_w11a_b3_drc_routed.pb -rpx sys_w11a_b3_drc_routed.rpx
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/impl_1/sys_w11a_b3_drc_routed.rpt.
report_drc completed successfully
Command: report_methodology -file sys_w11a_b3_methodology_drc_routed.rpt -rpx sys_w11a_b3_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/impl_1/sys_w11a_b3_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:00:16 ; elapsed = 00:00:09 . Memory (MB): peak = 2029.180 ; gain = 0.000 ; free physical = 721 ; free virtual = 8826
Command: report_power -file sys_w11a_b3_power_routed.rpt -pb sys_w11a_b3_power_summary_routed.pb -rpx sys_w11a_b3_power_routed.rpx
INFO: [Power 33-23] Power model is not available for UA
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
77 Infos, 8 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 2029.180 ; gain = 0.000 ; free physical = 712 ; free virtual = 8819
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Sun Feb 10 12:40:06 2019...

*** Running vivado
    with args -log sys_w11a_b3.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source sys_w11a_b3.tcl -notrace


****** Vivado v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source sys_w11a_b3.tcl -notrace
Command: open_checkpoint sys_w11a_b3_routed.dcp

Starting open_checkpoint Task

Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1077.039 ; gain = 0.000 ; free physical = 859 ; free virtual = 8968
INFO: [Netlist 29-17] Analyzing 338 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.2
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/impl_1/.Xil/Vivado-1663-athome/dcp3/sys_w11a_b3_early.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/impl_1/.Xil/Vivado-1663-athome/dcp3/sys_w11a_b3_early.xdc]
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/impl_1/.Xil/Vivado-1663-athome/dcp3/sys_w11a_b3.xdc]
INFO: [Timing 38-35] Done setting XDC timing constraints. [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
INFO: [Timing 38-2] Deriving generated clocks [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
get_clocks: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 1775.387 ; gain = 456.438 ; free physical = 186 ; free virtual = 8310
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/impl_1/.Xil/Vivado-1663-athome/dcp3/sys_w11a_b3.xdc]
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:01 . Memory (MB): peak = 1775.387 ; gain = 0.000 ; free physical = 175 ; free virtual = 8299
Restored from archive | CPU: 1.010000 secs | Memory: 10.012253 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:01 . Memory (MB): peak = 1775.387 ; gain = 0.000 ; free physical = 175 ; free virtual = 8299
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 152 instances were transformed.
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 16 instances
  RAM16X1S => RAM32X1S (RAMS32): 32 instances
  RAM32M => RAM32M (RAMS32, RAMS32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32): 6 instances
  RAM32X1S => RAM32X1S (RAMS32): 69 instances
  RAM64X1S => RAM64X1S (RAMS64E): 29 instances

INFO: [Project 1-604] Checkpoint was created with Vivado v2017.2 (64-bit) build 1909853
open_checkpoint: Time (s): cpu = 00:00:20 ; elapsed = 00:00:20 . Memory (MB): peak = 1775.387 ; gain = 698.348 ; free physical = 190 ; free virtual = 8300
Command: write_bitstream -force sys_w11a_b3.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
Running DRC as a precondition to command write_bitstream
Command: report_drc (run_mandatory_drcs) for: bitstream_checks
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC DPOP-1] PREG Output pipelining: DSP SYS70/W11A/DPATH/MUNIT/DOUT0 output SYS70/W11A/DPATH/MUNIT/DOUT0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
WARNING: [DRC DPOP-2] MREG Output pipelining: DSP SYS70/W11A/DPATH/MUNIT/DOUT0 multiplier stage SYS70/W11A/DPATH/MUNIT/DOUT0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 2 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Project 1-821] Please set project.enableDesignId to be 'true'.
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Overwriting "TIMESTAMP" with "5126CA59" for option USR_ACCESS
Creating bitmap...
Creating bitstream...
Writing bitstream ./sys_w11a_b3.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
16 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:28 ; elapsed = 00:00:26 . Memory (MB): peak = 2182.977 ; gain = 407.590 ; free physical = 437 ; free virtual = 8260
INFO: [Common 17-206] Exiting Vivado at Sun Feb 10 12:41:38 2019...
