
*** Running vivado
    with args -log sys_w11a_b3.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source sys_w11a_b3.tcl


****** Vivado v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source sys_w11a_b3.tcl -notrace
Command: synth_design -top sys_w11a_b3 -part xc7a35tcpg236-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5 -assert
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t-cpg236'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 32701 
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Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1131.637 ; gain = 39.891 ; free physical = 1353 ; free virtual = 9363
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'sys_w11a_b3' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd:146]
	Parameter CLKIN_PERIOD bound to: 10.000000 - type: float 
	Parameter CLKIN_JITTER bound to: 0.010000 - type: float 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
	Parameter CLK0_VCODIV bound to: 1 - type: integer 
	Parameter CLK0_VCOMUL bound to: 8 - type: integer 
	Parameter CLK0_OUTDIV bound to: 10 - type: integer 
	Parameter CLK0_GENTYPE bound to: MMCM - type: string 
	Parameter CLK0_CDUWIDTH bound to: 7 - type: integer 
	Parameter CLK0_USECDIV bound to: 80 - type: integer 
	Parameter CLK0_MSECDIV bound to: 1000 - type: integer 
	Parameter CLK1_VCODIV bound to: 1 - type: integer 
	Parameter CLK1_VCOMUL bound to: 12 - type: integer 
	Parameter CLK1_OUTDIV bound to: 10 - type: integer 
	Parameter CLK1_GENTYPE bound to: PLL - type: string 
	Parameter CLK1_CDUWIDTH bound to: 7 - type: integer 
	Parameter CLK1_USECDIV bound to: 120 - type: integer 
	Parameter CLK1_MSECDIV bound to: 1000 - type: integer 
INFO: [Synth 8-3491] module 's7_cmt_1ce1ce' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/s7_cmt_1ce1ce.vhd:36' bound to instance 'GEN_CLKALL' of component 's7_cmt_1ce1ce' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd:220]
INFO: [Synth 8-638] synthesizing module 's7_cmt_1ce1ce' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/s7_cmt_1ce1ce.vhd:67]
	Parameter CLKIN_PERIOD bound to: 10.000000 - type: float 
	Parameter CLKIN_JITTER bound to: 0.010000 - type: float 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
	Parameter CLK0_VCODIV bound to: 1 - type: integer 
	Parameter CLK0_VCOMUL bound to: 8 - type: integer 
	Parameter CLK0_OUTDIV bound to: 10 - type: integer 
	Parameter CLK0_GENTYPE bound to: MMCM - type: string 
	Parameter CLK0_CDUWIDTH bound to: 7 - type: integer 
	Parameter CLK0_USECDIV bound to: 80 - type: integer 
	Parameter CLK0_MSECDIV bound to: 1000 - type: integer 
	Parameter CLK1_VCODIV bound to: 1 - type: integer 
	Parameter CLK1_VCOMUL bound to: 12 - type: integer 
	Parameter CLK1_OUTDIV bound to: 10 - type: integer 
	Parameter CLK1_GENTYPE bound to: PLL - type: string 
	Parameter CLK1_CDUWIDTH bound to: 7 - type: integer 
	Parameter CLK1_USECDIV bound to: 120 - type: integer 
	Parameter CLK1_MSECDIV bound to: 1000 - type: integer 
	Parameter VCO_DIVIDE bound to: 1 - type: integer 
	Parameter VCO_MULTIPLY bound to: 8 - type: integer 
	Parameter OUT_DIVIDE bound to: 10 - type: integer 
	Parameter CLKIN_PERIOD bound to: 10.000000 - type: float 
	Parameter CLKIN_JITTER bound to: 0.010000 - type: float 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
	Parameter GEN_TYPE bound to: MMCM - type: string 
INFO: [Synth 8-3491] module 's7_cmt_sfs' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:37' bound to instance 'GEN_CLK0' of component 's7_cmt_sfs' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/s7_cmt_1ce1ce.vhd:76]
INFO: [Synth 8-638] synthesizing module 's7_cmt_sfs' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:54]
	Parameter VCO_DIVIDE bound to: 1 - type: integer 
	Parameter VCO_MULTIPLY bound to: 8 - type: integer 
	Parameter OUT_DIVIDE bound to: 10 - type: integer 
	Parameter CLKIN_PERIOD bound to: 10.000000 - type: float 
	Parameter CLKIN_JITTER bound to: 0.010000 - type: float 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
	Parameter GEN_TYPE bound to: MMCM - type: string 
	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
	Parameter CLKFBOUT_MULT_F bound to: 8.000000 - type: float 
	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 
	Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float 
	Parameter CLKOUT0_DIVIDE_F bound to: 10.000000 - type: float 
	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT4_CASCADE bound to: 0 - type: bool 
	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float 
	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
	Parameter REF_JITTER1 bound to: 0.010000 - type: float 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
INFO: [Synth 8-113] binding component instance 'MMCM' to cell 'MMCME2_BASE' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:152]
INFO: [Synth 8-113] binding component instance 'BUFG_CLKFB' to cell 'BUFG' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:184]
INFO: [Synth 8-113] binding component instance 'BUFG_CLKOUT' to cell 'BUFG' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:190]
INFO: [Synth 8-256] done synthesizing module 's7_cmt_sfs' (1#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:54]
	Parameter CDUWIDTH bound to: 7 - type: integer 
	Parameter USECDIV bound to: 80 - type: integer 
	Parameter MSECDIV bound to: 1000 - type: integer 
INFO: [Synth 8-3491] module 'clkdivce' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:39' bound to instance 'DIV_CLK0' of component 'clkdivce' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/s7_cmt_1ce1ce.vhd:91]
INFO: [Synth 8-638] synthesizing module 'clkdivce' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:52]
	Parameter CDUWIDTH bound to: 7 - type: integer 
	Parameter USECDIV bound to: 80 - type: integer 
	Parameter MSECDIV bound to: 1000 - type: integer 
WARNING: [Synth 8-6014] Unused sequential element r_reg[ucnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element r_reg[mcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element r_reg[usec] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element r_reg[msec] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element n_reg[ucnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:94]
WARNING: [Synth 8-6014] Unused sequential element n_reg[mcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:94]
WARNING: [Synth 8-6014] Unused sequential element n_reg[usec] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:94]
WARNING: [Synth 8-6014] Unused sequential element n_reg[msec] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:94]
INFO: [Synth 8-256] done synthesizing module 'clkdivce' (2#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:52]
	Parameter VCO_DIVIDE bound to: 1 - type: integer 
	Parameter VCO_MULTIPLY bound to: 12 - type: integer 
	Parameter OUT_DIVIDE bound to: 10 - type: integer 
	Parameter CLKIN_PERIOD bound to: 10.000000 - type: float 
	Parameter CLKIN_JITTER bound to: 0.010000 - type: float 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
	Parameter GEN_TYPE bound to: PLL - type: string 
INFO: [Synth 8-3491] module 's7_cmt_sfs' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:37' bound to instance 'GEN_CLK1' of component 's7_cmt_sfs' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/s7_cmt_1ce1ce.vhd:102]
INFO: [Synth 8-638] synthesizing module 's7_cmt_sfs__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:54]
	Parameter VCO_DIVIDE bound to: 1 - type: integer 
	Parameter VCO_MULTIPLY bound to: 12 - type: integer 
	Parameter OUT_DIVIDE bound to: 10 - type: integer 
	Parameter CLKIN_PERIOD bound to: 10.000000 - type: float 
	Parameter CLKIN_JITTER bound to: 0.010000 - type: float 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
	Parameter GEN_TYPE bound to: PLL - type: string 
	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
	Parameter CLKFBOUT_MULT bound to: 12 - type: integer 
	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 
	Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float 
	Parameter CLKOUT0_DIVIDE bound to: 10 - type: integer 
	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 
	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
	Parameter REF_JITTER1 bound to: 0.010000 - type: float 
	Parameter STARTUP_WAIT bound to: FALSE - type: string 
INFO: [Synth 8-113] binding component instance 'PLL' to cell 'PLLE2_BASE' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:91]
INFO: [Synth 8-113] binding component instance 'BUFG_CLKFB' to cell 'BUFG' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:118]
INFO: [Synth 8-113] binding component instance 'BUFG_CLKOUT' to cell 'BUFG' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:124]
INFO: [Synth 8-256] done synthesizing module 's7_cmt_sfs__parameterized1' (2#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:54]
	Parameter CDUWIDTH bound to: 7 - type: integer 
	Parameter USECDIV bound to: 120 - type: integer 
	Parameter MSECDIV bound to: 1000 - type: integer 
INFO: [Synth 8-3491] module 'clkdivce' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:39' bound to instance 'DIV_CLK1' of component 'clkdivce' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/s7_cmt_1ce1ce.vhd:117]
INFO: [Synth 8-638] synthesizing module 'clkdivce__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:52]
	Parameter CDUWIDTH bound to: 7 - type: integer 
	Parameter USECDIV bound to: 120 - type: integer 
	Parameter MSECDIV bound to: 1000 - type: integer 
WARNING: [Synth 8-6014] Unused sequential element r_reg[ucnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element r_reg[mcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element r_reg[usec] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element r_reg[msec] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element n_reg[ucnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:94]
WARNING: [Synth 8-6014] Unused sequential element n_reg[mcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:94]
WARNING: [Synth 8-6014] Unused sequential element n_reg[usec] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:94]
WARNING: [Synth 8-6014] Unused sequential element n_reg[msec] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:94]
INFO: [Synth 8-256] done synthesizing module 'clkdivce__parameterized1' (2#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/clkdivce.vhd:52]
INFO: [Synth 8-256] done synthesizing module 's7_cmt_1ce1ce' (3#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/s7_cmt_1ce1ce.vhd:67]
INFO: [Synth 8-3491] module 'bp_rs232_2line_iob' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd:41' bound to instance 'IOB_RS232' of component 'bp_rs232_2line_iob' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd:250]
INFO: [Synth 8-638] synthesizing module 'bp_rs232_2line_iob' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd:51]
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-3491] module 'iob_reg_i' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_i.vhd:34' bound to instance 'IOB_RXD' of component 'iob_reg_i' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd:54]
INFO: [Synth 8-638] synthesizing module 'iob_reg_i' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_i.vhd:46]
	Parameter INIT bound to: 1'b1 
	Parameter DWIDTH bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-3491] module 'iob_reg_i_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:34' bound to instance 'IOB' of component 'iob_reg_i_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_i.vhd:50]
INFO: [Synth 8-638] synthesizing module 'iob_reg_i_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:47]
	Parameter DWIDTH bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'iob_reg_i_gen' (4#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'iob_reg_i' (5#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_i.vhd:46]
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-3491] module 'iob_reg_o' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o.vhd:34' bound to instance 'IOB_TXD' of component 'iob_reg_o' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd:58]
INFO: [Synth 8-638] synthesizing module 'iob_reg_o' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o.vhd:46]
	Parameter INIT bound to: 1'b1 
	Parameter DWIDTH bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-3491] module 'iob_reg_o_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:34' bound to instance 'IOB' of component 'iob_reg_o_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o.vhd:50]
INFO: [Synth 8-638] synthesizing module 'iob_reg_o_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:47]
	Parameter DWIDTH bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'iob_reg_o_gen' (6#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'iob_reg_o' (7#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o.vhd:46]
INFO: [Synth 8-256] done synthesizing module 'bp_rs232_2line_iob' (8#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd:51]
	Parameter BTOWIDTH bound to: 7 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 32'b00000010000000010000011000000000 
	Parameter IFAWIDTH bound to: 5 - type: integer 
	Parameter OFAWIDTH bound to: 5 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RLBMON bound to: -1 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
	Parameter RBMON_AWIDTH bound to: 0 - type: integer 
	Parameter RBMON_RBADDR bound to: 16'b1111111111101000 
INFO: [Synth 8-3491] module 'rlink_sp2c' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_sp2c.vhd:43' bound to instance 'RLINK' of component 'rlink_sp2c' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd:259]
INFO: [Synth 8-638] synthesizing module 'rlink_sp2c' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_sp2c.vhd:81]
	Parameter BTOWIDTH bound to: 7 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 33621504 - type: integer 
	Parameter IFAWIDTH bound to: 5 - type: integer 
	Parameter OFAWIDTH bound to: 5 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RLBMON bound to: -1 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
	Parameter RBMON_AWIDTH bound to: 0 - type: integer 
	Parameter RBMON_RBADDR bound to: 16'b1111111111101000 
	Parameter BTOWIDTH bound to: 7 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 33621504 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RLBMON bound to: -1 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
INFO: [Synth 8-3491] module 'rlink_core8' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core8.vhd:49' bound to instance 'CORE' of component 'rlink_core8' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_sp2c.vhd:96]
INFO: [Synth 8-638] synthesizing module 'rlink_core8' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core8.vhd:78]
	Parameter BTOWIDTH bound to: 7 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 33621504 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RLBMON bound to: -1 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
	Parameter BTOWIDTH bound to: 7 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 33621504 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
INFO: [Synth 8-3491] module 'rlink_core' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:165' bound to instance 'RL' of component 'rlink_core' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core8.vhd:92]
INFO: [Synth 8-638] synthesizing module 'rlink_core' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:194]
	Parameter BTOWIDTH bound to: 7 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 33621504 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_2swsr_rfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:42' bound to instance 'RTBUF' of component 'ram_2swsr_rfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:447]
INFO: [Synth 8-638] synthesizing module 'ram_2swsr_rfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:63]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* ram_style = "block" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:67]
INFO: [Synth 8-256] done synthesizing module 'ram_2swsr_rfirst_gen' (9#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:63]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'fifo_1c_dram' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram.vhd:43' bound to instance 'DOFIFO' of component 'fifo_1c_dram' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:466]
INFO: [Synth 8-638] synthesizing module 'fifo_1c_dram' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram.vhd:61]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'fifo_1c_dram_raw' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:38' bound to instance 'FIFO' of component 'fifo_1c_dram_raw' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram.vhd:71]
INFO: [Synth 8-638] synthesizing module 'fifo_1c_dram_raw' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:56]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_1ar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:50' bound to instance 'RAM' of component 'ram_1swar_1ar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:79]
INFO: [Synth 8-638] synthesizing module 'ram_1swar_1ar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:66]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* ram_style = "distributed" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:70]
INFO: [Synth 8-256] done synthesizing module 'ram_1swar_1ar_gen' (10#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:66]
WARNING: [Synth 8-6014] Unused sequential element r_reg[waddr] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:115]
WARNING: [Synth 8-6014] Unused sequential element r_reg[raddr] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:115]
WARNING: [Synth 8-6014] Unused sequential element r_reg[empty] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:115]
WARNING: [Synth 8-6014] Unused sequential element r_reg[full] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:115]
WARNING: [Synth 8-6014] Unused sequential element n_reg[waddr] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:116]
WARNING: [Synth 8-6014] Unused sequential element n_reg[raddr] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:116]
WARNING: [Synth 8-6014] Unused sequential element n_reg[empty] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:116]
WARNING: [Synth 8-6014] Unused sequential element n_reg[full] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:116]
WARNING: [Synth 8-6014] Unused sequential element re_val_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:118]
WARNING: [Synth 8-6014] Unused sequential element we_val_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:119]
WARNING: [Synth 8-6014] Unused sequential element isize_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:120]
WARNING: [Synth 8-6014] Unused sequential element iram_we_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:121]
INFO: [Synth 8-256] done synthesizing module 'fifo_1c_dram_raw' (11#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:56]
INFO: [Synth 8-256] done synthesizing module 'fifo_1c_dram' (12#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_1c_dram.vhd:61]
	Parameter INIT bound to: 16'b0000000000000000 
INFO: [Synth 8-3491] module 'crc16' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/crc16.vhd:40' bound to instance 'ICRC' of component 'crc16' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:482]
INFO: [Synth 8-638] synthesizing module 'crc16' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/crc16.vhd:53]
	Parameter INIT bound to: 16'b0000000000000000 
INFO: [Synth 8-256] done synthesizing module 'crc16' (13#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/crc16.vhd:53]
	Parameter INIT bound to: 16'b0000000000000000 
INFO: [Synth 8-3491] module 'crc16' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/crc16.vhd:40' bound to instance 'OCRC' of component 'crc16' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:491]
	Parameter RB_ADDR bound to: 16'b1111111111111100 
	Parameter SAWIDTH bound to: 2 - type: integer 
INFO: [Synth 8-3491] module 'rb_sel' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rb_sel.vhd:38' bound to instance 'SEL' of component 'rb_sel' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:500]
INFO: [Synth 8-638] synthesizing module 'rb_sel' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rb_sel.vhd:49]
	Parameter RB_ADDR bound to: 16'b1111111111111100 
	Parameter SAWIDTH bound to: 2 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'rb_sel' (14#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rb_sel.vhd:49]
INFO: [Synth 8-3491] module 'rb_sres_or_2' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rb_sres_or_2.vhd:39' bound to instance 'RB_SRES_OR' of component 'rb_sres_or_2' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:510]
INFO: [Synth 8-638] synthesizing module 'rb_sres_or_2' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rb_sres_or_2.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'rb_sres_or_2' (15#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rb_sres_or_2.vhd:47]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1402]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1623]
WARNING: [Synth 8-6014] Unused sequential element datax01_reg was removed. 
WARNING: [Synth 8-6014] Unused sequential element data01_reg was removed. 
WARNING: [Synth 8-6014] Unused sequential element sres_reg[ack] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:522]
WARNING: [Synth 8-6014] Unused sequential element sres_reg[busy] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:522]
WARNING: [Synth 8-6014] Unused sequential element sres_reg[err] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:522]
WARNING: [Synth 8-6014] Unused sequential element sres_reg[dout] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:522]
WARNING: [Synth 8-6014] Unused sequential element r_reg[state] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rcmd] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[lcmd] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[addr] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[din] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[cnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[bcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[attn] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[anreq] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[anact] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[arpend] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[atocnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[babo] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[nakdone] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[nakcode] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[cmdseen] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[doretra] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[dinl] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rtaddra] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rtaddra_red] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rtaddra_bad] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rtaddra_zero] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rtaddrb] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rtaddrb_red] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rtaddrb_bad] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[moneop] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[monattn] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element n_reg[state] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rcmd] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[lcmd] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[addr] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[din] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[cnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[bcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[attn] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[anreq] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[anact] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[arpend] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[atocnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[babo] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[nakdone] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[nakcode] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[cmdseen] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[doretra] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[dinl] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rtaddra] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rtaddra_red] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rtaddra_bad] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rtaddra_zero] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rtaddrb] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rtaddrb_red] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rtaddrb_bad] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[moneop] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[monattn] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element ival_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:597]
WARNING: [Synth 8-6014] Unused sequential element ibusy_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:598]
WARNING: [Synth 8-6014] Unused sequential element ido_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:599]
WARNING: [Synth 8-6014] Unused sequential element crcreset_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:601]
WARNING: [Synth 8-6014] Unused sequential element icrcena_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:602]
WARNING: [Synth 8-6014] Unused sequential element ocrcena_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:603]
WARNING: [Synth 8-6014] Unused sequential element has_attn_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:605]
WARNING: [Synth 8-6014] Unused sequential element is_comma_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:607]
WARNING: [Synth 8-6014] Unused sequential element comma_typ_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:608]
WARNING: [Synth 8-6014] Unused sequential element idi8_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:609]
WARNING: [Synth 8-6014] Unused sequential element idohold_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:611]
WARNING: [Synth 8-6014] Unused sequential element cnt_iszero_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:613]
WARNING: [Synth 8-6014] Unused sequential element bcnt_load_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:618]
WARNING: [Synth 8-6014] Unused sequential element bcnt_val_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:619]
WARNING: [Synth 8-6014] Unused sequential element bcnt_dec_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:620]
WARNING: [Synth 8-6014] Unused sequential element bcnt_end_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:621]
WARNING: [Synth 8-6014] Unused sequential element irtwea_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:626]
WARNING: [Synth 8-6014] Unused sequential element irtreb_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:627]
WARNING: [Synth 8-6014] Unused sequential element irtweb_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:628]
WARNING: [Synth 8-6014] Unused sequential element addra_clear_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:629]
WARNING: [Synth 8-6014] Unused sequential element addrb_load_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:630]
WARNING: [Synth 8-6014] Unused sequential element addrb_sela_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:631]
WARNING: [Synth 8-6014] Unused sequential element ibcmd_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:633]
WARNING: [Synth 8-6014] Unused sequential element ibgo_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:634]
WARNING: [Synth 8-6014] Unused sequential element r_reg[state] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1354]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rbinit] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1354]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rbaval] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1354]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rbre] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1354]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rbwe] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1354]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rbdout] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1354]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rbtout] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1354]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rbnak] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1354]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rberr] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1354]
WARNING: [Synth 8-6014] Unused sequential element r_reg[blkabo] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1354]
WARNING: [Synth 8-6014] Unused sequential element r_reg[cnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1354]
WARNING: [Synth 8-6014] Unused sequential element r_reg[dcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1354]
WARNING: [Synth 8-6014] Unused sequential element r_reg[btocnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1354]
WARNING: [Synth 8-6014] Unused sequential element r_reg[dathpend] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1354]
WARNING: [Synth 8-6014] Unused sequential element r_reg[wfifo] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1354]
WARNING: [Synth 8-6014] Unused sequential element r_reg[stat] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1354]
WARNING: [Synth 8-6014] Unused sequential element n_reg[state] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1355]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rbinit] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1355]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rbaval] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1355]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rbre] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1355]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rbwe] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1355]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rbdout] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1355]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rbtout] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1355]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rbnak] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1355]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rberr] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1355]
WARNING: [Synth 8-6014] Unused sequential element n_reg[blkabo] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1355]
WARNING: [Synth 8-6014] Unused sequential element n_reg[cnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1355]
WARNING: [Synth 8-6014] Unused sequential element n_reg[dcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1355]
WARNING: [Synth 8-6014] Unused sequential element n_reg[btocnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1355]
WARNING: [Synth 8-6014] Unused sequential element n_reg[dathpend] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1355]
WARNING: [Synth 8-6014] Unused sequential element n_reg[wfifo] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1355]
WARNING: [Synth 8-6014] Unused sequential element n_reg[stat] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1355]
WARNING: [Synth 8-6014] Unused sequential element bto_go_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1357]
WARNING: [Synth 8-6014] Unused sequential element bto_end_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1358]
WARNING: [Synth 8-6014] Unused sequential element cnt_load_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1363]
WARNING: [Synth 8-6014] Unused sequential element cnt_dec_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1364]
WARNING: [Synth 8-6014] Unused sequential element cnt_end_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1365]
WARNING: [Synth 8-6014] Unused sequential element dcnt_clear_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1370]
WARNING: [Synth 8-6014] Unused sequential element dcnt_inc_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1371]
WARNING: [Synth 8-6014] Unused sequential element ival_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1373]
WARNING: [Synth 8-6014] Unused sequential element ido_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1374]
WARNING: [Synth 8-6014] Unused sequential element iwdone_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1376]
WARNING: [Synth 8-6014] Unused sequential element r_reg[anena] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1601]
WARNING: [Synth 8-6014] Unused sequential element r_reg[atoena] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1601]
WARNING: [Synth 8-6014] Unused sequential element r_reg[atoval] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1601]
WARNING: [Synth 8-6014] Unused sequential element n_reg[anena] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1602]
WARNING: [Synth 8-6014] Unused sequential element n_reg[atoena] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1602]
WARNING: [Synth 8-6014] Unused sequential element n_reg[atoval] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1602]
WARNING: [Synth 8-6014] Unused sequential element irb_ack_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1604]
WARNING: [Synth 8-6014] Unused sequential element irb_dout_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:1605]
WARNING: [Synth 8-6014] Unused sequential element OCRC_IN_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:496]
INFO: [Synth 8-256] done synthesizing module 'rlink_core' (16#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core.vhd:194]
INFO: [Synth 8-3491] module 'byte2cdata' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/byte2cdata.vhd:38' bound to instance 'B2CD' of component 'byte2cdata' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core8.vhd:117]
INFO: [Synth 8-638] synthesizing module 'byte2cdata' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/byte2cdata.vhd:53]
WARNING: [Synth 8-6014] Unused sequential element r_reg[data] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/byte2cdata.vhd:95]
WARNING: [Synth 8-6014] Unused sequential element r_reg[dataval] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/byte2cdata.vhd:95]
WARNING: [Synth 8-6014] Unused sequential element r_reg[edpend] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/byte2cdata.vhd:95]
WARNING: [Synth 8-6014] Unused sequential element n_reg[data] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/byte2cdata.vhd:96]
WARNING: [Synth 8-6014] Unused sequential element n_reg[dataval] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/byte2cdata.vhd:96]
WARNING: [Synth 8-6014] Unused sequential element n_reg[edpend] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/byte2cdata.vhd:96]
WARNING: [Synth 8-6014] Unused sequential element idata_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/byte2cdata.vhd:99]
WARNING: [Synth 8-6014] Unused sequential element iesc_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/byte2cdata.vhd:100]
WARNING: [Synth 8-6014] Unused sequential element ibusy_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/byte2cdata.vhd:126]
INFO: [Synth 8-256] done synthesizing module 'byte2cdata' (17#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/byte2cdata.vhd:53]
INFO: [Synth 8-3491] module 'cdata2byte' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/cdata2byte.vhd:38' bound to instance 'CD2B' of component 'cdata2byte' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core8.vhd:131]
INFO: [Synth 8-638] synthesizing module 'cdata2byte' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/cdata2byte.vhd:54]
WARNING: [Synth 8-6014] Unused sequential element r_reg[data] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/cdata2byte.vhd:99]
WARNING: [Synth 8-6014] Unused sequential element r_reg[ecode] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/cdata2byte.vhd:99]
WARNING: [Synth 8-6014] Unused sequential element r_reg[dataval] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/cdata2byte.vhd:99]
WARNING: [Synth 8-6014] Unused sequential element r_reg[ecodeval] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/cdata2byte.vhd:99]
WARNING: [Synth 8-6014] Unused sequential element n_reg[data] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/cdata2byte.vhd:100]
WARNING: [Synth 8-6014] Unused sequential element n_reg[ecode] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/cdata2byte.vhd:100]
WARNING: [Synth 8-6014] Unused sequential element n_reg[dataval] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/cdata2byte.vhd:100]
WARNING: [Synth 8-6014] Unused sequential element n_reg[ecodeval] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/cdata2byte.vhd:100]
WARNING: [Synth 8-6014] Unused sequential element iesc_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/cdata2byte.vhd:103]
WARNING: [Synth 8-6014] Unused sequential element iecode_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/cdata2byte.vhd:104]
WARNING: [Synth 8-6014] Unused sequential element idata_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/cdata2byte.vhd:132]
WARNING: [Synth 8-6014] Unused sequential element ibusy_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/cdata2byte.vhd:138]
INFO: [Synth 8-256] done synthesizing module 'cdata2byte' (18#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/comlib/cdata2byte.vhd:54]
INFO: [Synth 8-256] done synthesizing module 'rlink_core8' (19#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_core8.vhd:78]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
	Parameter RXFAWIDTH bound to: 5 - type: integer 
	Parameter TXFAWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'serport_2clock2' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:47' bound to instance 'SERPORT' of component 'serport_2clock2' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_sp2c.vhd:123]
INFO: [Synth 8-638] synthesizing module 'serport_2clock2' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:75]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
	Parameter RXFAWIDTH bound to: 5 - type: integer 
	Parameter TXFAWIDTH bound to: 5 - type: integer 
	Parameter POUT_SINGLE bound to: 0 - type: bool 
	Parameter BUSY_WACK bound to: 0 - type: bool 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_pulse' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.vhd:35' bound to instance 'CDC_RESET' of component 'cdc_pulse' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:135]
INFO: [Synth 8-638] synthesizing module 'cdc_pulse' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.vhd:51]
	Parameter POUT_SINGLE bound to: 0 - type: bool 
	Parameter BUSY_WACK bound to: 0 - type: bool 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.vhd:54]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.vhd:55]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.vhd:56]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.vhd:57]
INFO: [Synth 8-256] done synthesizing module 'cdc_pulse' (20#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.vhd:51]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_signal_s1' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:34' bound to instance 'CDC_ENAXON' of component 'cdc_signal_s1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:148]
INFO: [Synth 8-638] synthesizing module 'cdc_signal_s1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:45]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:47]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:48]
INFO: [Synth 8-256] done synthesizing module 'cdc_signal_s1' (21#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:45]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_signal_s1' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:34' bound to instance 'CDC_ENAESC' of component 'cdc_signal_s1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:150]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
INFO: [Synth 8-3491] module 'serport_uart_rxtx_ab' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rxtx_ab.vhd:47' bound to instance 'UART' of component 'serport_uart_rxtx_ab' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:153]
INFO: [Synth 8-638] synthesizing module 'serport_uart_rxtx_ab' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rxtx_ab.vhd:71]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
INFO: [Synth 8-3491] module 'serport_uart_autobaud' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:42' bound to instance 'AB' of component 'serport_uart_autobaud' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rxtx_ab.vhd:80]
INFO: [Synth 8-638] synthesizing module 'serport_uart_autobaud' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:59]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:133]
WARNING: [Synth 8-6014] Unused sequential element r_reg[ccnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:127]
WARNING: [Synth 8-6014] Unused sequential element r_reg[mcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:127]
WARNING: [Synth 8-6014] Unused sequential element r_reg[seen1] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:127]
WARNING: [Synth 8-6014] Unused sequential element r_reg[state] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:127]
WARNING: [Synth 8-6014] Unused sequential element n_reg[ccnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:128]
WARNING: [Synth 8-6014] Unused sequential element n_reg[mcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:128]
WARNING: [Synth 8-6014] Unused sequential element n_reg[seen1] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:128]
WARNING: [Synth 8-6014] Unused sequential element n_reg[state] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:128]
WARNING: [Synth 8-6014] Unused sequential element iact_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:130]
WARNING: [Synth 8-6014] Unused sequential element idone_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:131]
INFO: [Synth 8-256] done synthesizing module 'serport_uart_autobaud' (22#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:59]
	Parameter CDWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-3491] module 'serport_uart_rxtx' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rxtx.vhd:38' bound to instance 'RXTX' of component 'serport_uart_rxtx' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rxtx_ab.vhd:100]
INFO: [Synth 8-638] synthesizing module 'serport_uart_rxtx' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rxtx.vhd:57]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-3491] module 'serport_uart_rx' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rx.vhd:55' bound to instance 'RX' of component 'serport_uart_rx' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rxtx.vhd:61]
INFO: [Synth 8-638] synthesizing module 'serport_uart_rx' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rx.vhd:71]
	Parameter CDWIDTH bound to: 12 - type: integer 
WARNING: [Synth 8-6014] Unused sequential element r_reg[state] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rx.vhd:133]
WARNING: [Synth 8-6014] Unused sequential element r_reg[ccnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rx.vhd:133]
WARNING: [Synth 8-6014] Unused sequential element r_reg[dcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rx.vhd:133]
WARNING: [Synth 8-6014] Unused sequential element r_reg[bcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rx.vhd:133]
WARNING: [Synth 8-6014] Unused sequential element r_reg[sreg] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rx.vhd:133]
WARNING: [Synth 8-6014] Unused sequential element n_reg[state] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rx.vhd:134]
INFO: [Common 17-14] Message 'Synth 8-6014' appears 200 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-256] done synthesizing module 'serport_uart_rx' (23#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rx.vhd:71]
	Parameter CDWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-3491] module 'serport_uart_tx' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_tx.vhd:40' bound to instance 'TX' of component 'serport_uart_tx' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rxtx.vhd:75]
INFO: [Synth 8-638] synthesizing module 'serport_uart_tx' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_tx.vhd:55]
	Parameter CDWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'serport_uart_tx' (24#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_tx.vhd:55]
INFO: [Synth 8-256] done synthesizing module 'serport_uart_rxtx' (25#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rxtx.vhd:57]
INFO: [Synth 8-256] done synthesizing module 'serport_uart_rxtx_ab' (26#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_uart_rxtx_ab.vhd:71]
INFO: [Synth 8-3491] module 'serport_xonrx' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_xonrx.vhd:37' bound to instance 'XONRX' of component 'serport_xonrx' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:178]
INFO: [Synth 8-638] synthesizing module 'serport_xonrx' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_xonrx.vhd:54]
INFO: [Synth 8-256] done synthesizing module 'serport_xonrx' (27#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_xonrx.vhd:54]
INFO: [Synth 8-3491] module 'serport_xontx' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_xontx.vhd:38' bound to instance 'XONTX' of component 'serport_xontx' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:193]
INFO: [Synth 8-638] synthesizing module 'serport_xontx' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_xontx.vhd:56]
INFO: [Synth 8-256] done synthesizing module 'serport_xontx' (28#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_xontx.vhd:56]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'fifo_2c_dram2' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:41' bound to instance 'RXFIFO' of component 'fifo_2c_dram2' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:209]
INFO: [Synth 8-638] synthesizing module 'fifo_2c_dram2' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:62]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:66]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:67]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:71]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:72]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:73]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:74]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:80]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:81]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:85]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:86]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:87]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:88]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_1ar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:50' bound to instance 'RAM' of component 'ram_1swar_1ar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:124]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'gray_cnt_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray_cnt_gen.vhd:33' bound to instance 'GCW' of component 'gray_cnt_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:138]
INFO: [Synth 8-638] synthesizing module 'gray_cnt_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray_cnt_gen.vhd:45]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'gray_cnt_5' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray_cnt_5.vhd:38' bound to instance 'CNT' of component 'gray_cnt_5' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray_cnt_gen.vhd:67]
INFO: [Synth 8-638] synthesizing module 'gray_cnt_5' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray_cnt_5.vhd:48]
INFO: [Synth 8-5534] Detected attribute (* fsm_encoding = "none" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray_cnt_5.vhd:50]
INFO: [Synth 8-5534] Detected attribute (* rom_style = "distributed" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray_cnt_5.vhd:51]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray_cnt_5.vhd:88]
INFO: [Synth 8-256] done synthesizing module 'gray_cnt_5' (29#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray_cnt_5.vhd:48]
INFO: [Synth 8-256] done synthesizing module 'gray_cnt_gen' (30#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray_cnt_gen.vhd:45]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'gray_cnt_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray_cnt_gen.vhd:33' bound to instance 'GCR' of component 'gray_cnt_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:148]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'gray2bin_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray2bin_gen.vhd:32' bound to instance 'G2B_WW' of component 'gray2bin_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:158]
INFO: [Synth 8-638] synthesizing module 'gray2bin_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray2bin_gen.vhd:42]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'gray2bin_gen' (31#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray2bin_gen.vhd:42]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'gray2bin_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray2bin_gen.vhd:32' bound to instance 'G2B_WR' of component 'gray2bin_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:161]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'gray2bin_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray2bin_gen.vhd:32' bound to instance 'G2B_RR' of component 'gray2bin_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:164]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'gray2bin_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/gray2bin_gen.vhd:32' bound to instance 'G2B_RW' of component 'gray2bin_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:167]
INFO: [Synth 8-256] done synthesizing module 'fifo_2c_dram2' (32#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:62]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'fifo_2c_dram2' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:41' bound to instance 'TXFIFO' of component 'fifo_2c_dram2' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:228]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_signal_s1' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:34' bound to instance 'CDC_RXACT' of component 'cdc_signal_s1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:284]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_signal_s1' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:34' bound to instance 'CDC_TXACT' of component 'cdc_signal_s1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:286]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_signal_s1' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:34' bound to instance 'CDC_ABACT' of component 'cdc_signal_s1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:288]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_signal_s1' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:34' bound to instance 'CDC_RXOK' of component 'cdc_signal_s1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:290]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_signal_s1' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:34' bound to instance 'CDC_TXOK' of component 'cdc_signal_s1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:292]
	Parameter DWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-3491] module 'cdc_vector_s0' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.vhd:34' bound to instance 'CDC_CDIV' of component 'cdc_vector_s0' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:295]
INFO: [Synth 8-638] synthesizing module 'cdc_vector_s0' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.vhd:46]
	Parameter DWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.vhd:50]
INFO: [Synth 8-256] done synthesizing module 'cdc_vector_s0' (33#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.vhd:46]
	Parameter DWIDTH bound to: 3 - type: integer 
INFO: [Synth 8-3491] module 'cdc_vector_s0' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.vhd:34' bound to instance 'CDC_CDIVF' of component 'cdc_vector_s0' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:304]
INFO: [Synth 8-638] synthesizing module 'cdc_vector_s0__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.vhd:46]
	Parameter DWIDTH bound to: 3 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'cdc_vector_s0__parameterized1' (33#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.vhd:46]
	Parameter POUT_SINGLE bound to: 1 - type: bool 
	Parameter BUSY_WACK bound to: 0 - type: bool 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_pulse' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.vhd:35' bound to instance 'CDC_RXERR' of component 'cdc_pulse' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:313]
INFO: [Synth 8-638] synthesizing module 'cdc_pulse__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.vhd:51]
	Parameter POUT_SINGLE bound to: 1 - type: bool 
	Parameter BUSY_WACK bound to: 0 - type: bool 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'cdc_pulse__parameterized1' (33#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.vhd:51]
	Parameter POUT_SINGLE bound to: 1 - type: bool 
	Parameter BUSY_WACK bound to: 0 - type: bool 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_pulse' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.vhd:35' bound to instance 'CDC_RXOVR' of component 'cdc_pulse' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:326]
	Parameter POUT_SINGLE bound to: 1 - type: bool 
	Parameter BUSY_WACK bound to: 0 - type: bool 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_pulse' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.vhd:35' bound to instance 'CDC_ABDONE' of component 'cdc_pulse' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:339]
INFO: [Synth 8-256] done synthesizing module 'serport_2clock2' (34#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/serport/serport_2clock2.vhd:75]
INFO: [Synth 8-3491] module 'rb_sres_or_2' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rb_sres_or_2.vhd:39' bound to instance 'RB_SRES_OR' of component 'rb_sres_or_2' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_sp2c.vhd:164]
INFO: [Synth 8-256] done synthesizing module 'rlink_sp2c' (35#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/rlink_sp2c.vhd:81]
INFO: [Synth 8-3491] module 'pdp11_sys70' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sys70.vhd:64' bound to instance 'SYS70' of component 'pdp11_sys70' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd:303]
INFO: [Synth 8-638] synthesizing module 'pdp11_sys70' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sys70.vhd:94]
	Parameter RB_ADDR_CORE bound to: 16'b0000000000000000 
	Parameter RB_ADDR_IBUS bound to: 16'b0100000000000000 
INFO: [Synth 8-3491] module 'pdp11_core_rbus' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_core_rbus.vhd:108' bound to instance 'RB2CP' of component 'pdp11_core_rbus' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sys70.vhd:141]
INFO: [Synth 8-638] synthesizing module 'pdp11_core_rbus' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_core_rbus.vhd:129]
	Parameter RB_ADDR_CORE bound to: 16'b0000000000000000 
	Parameter RB_ADDR_IBUS bound to: 16'b0100000000000000 
INFO: [Synth 8-256] done synthesizing module 'pdp11_core_rbus' (36#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_core_rbus.vhd:129]
INFO: [Synth 8-3491] module 'pdp11_core' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_core.vhd:70' bound to instance 'W11A' of component 'pdp11_core' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sys70.vhd:160]
INFO: [Synth 8-638] synthesizing module 'pdp11_core' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_core.vhd:98]
INFO: [Synth 8-3491] module 'pdp11_vmbox' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_vmbox.vhd:77' bound to instance 'VMBOX' of component 'pdp11_vmbox' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_core.vhd:132]
INFO: [Synth 8-638] synthesizing module 'pdp11_vmbox' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_vmbox.vhd:99]
INFO: [Synth 8-3491] module 'pdp11_mmu' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu.vhd:61' bound to instance 'MMU' of component 'pdp11_mmu' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_vmbox.vhd:183]
INFO: [Synth 8-638] synthesizing module 'pdp11_mmu' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu.vhd:76]
INFO: [Synth 8-3491] module 'pdp11_mmu_sadr' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu_sadr.vhd:53' bound to instance 'SADR' of component 'pdp11_mmu_sadr' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu.vhd:122]
INFO: [Synth 8-638] synthesizing module 'pdp11_mmu_sadr' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu_sadr.vhd:67]
	Parameter AWIDTH bound to: 6 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:46' bound to instance 'SAR_HIGH' of component 'ram_1swar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu_sadr.vhd:108]
INFO: [Synth 8-638] synthesizing module 'ram_1swar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
	Parameter AWIDTH bound to: 6 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* ram_style = "distributed" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:64]
INFO: [Synth 8-256] done synthesizing module 'ram_1swar_gen' (37#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
	Parameter AWIDTH bound to: 6 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:46' bound to instance 'SAR_LOW' of component 'ram_1swar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu_sadr.vhd:119]
	Parameter AWIDTH bound to: 6 - type: integer 
	Parameter DWIDTH bound to: 7 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:46' bound to instance 'SDR_SLF' of component 'ram_1swar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu_sadr.vhd:130]
INFO: [Synth 8-638] synthesizing module 'ram_1swar_gen__parameterized2' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
	Parameter AWIDTH bound to: 6 - type: integer 
	Parameter DWIDTH bound to: 7 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ram_1swar_gen__parameterized2' (37#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
	Parameter AWIDTH bound to: 6 - type: integer 
	Parameter DWIDTH bound to: 2 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:46' bound to instance 'SDR_AIB' of component 'ram_1swar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu_sadr.vhd:141]
INFO: [Synth 8-638] synthesizing module 'ram_1swar_gen__parameterized4' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
	Parameter AWIDTH bound to: 6 - type: integer 
	Parameter DWIDTH bound to: 2 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ram_1swar_gen__parameterized4' (37#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
	Parameter AWIDTH bound to: 6 - type: integer 
	Parameter DWIDTH bound to: 4 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:46' bound to instance 'SDR_LOW' of component 'ram_1swar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu_sadr.vhd:152]
INFO: [Synth 8-638] synthesizing module 'ram_1swar_gen__parameterized6' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
	Parameter AWIDTH bound to: 6 - type: integer 
	Parameter DWIDTH bound to: 4 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ram_1swar_gen__parameterized6' (37#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
INFO: [Synth 8-256] done synthesizing module 'pdp11_mmu_sadr' (38#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu_sadr.vhd:67]
INFO: [Synth 8-3491] module 'pdp11_mmu_ssr12' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu_ssr12.vhd:47' bound to instance 'SSR12' of component 'pdp11_mmu_ssr12' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu.vhd:133]
INFO: [Synth 8-638] synthesizing module 'pdp11_mmu_ssr12' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu_ssr12.vhd:58]
	Parameter IB_ADDR bound to: 16'b1111111101111100 
	Parameter SAWIDTH bound to: 0 - type: integer 
INFO: [Synth 8-3491] module 'ib_sel' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:36' bound to instance 'SEL_SSR1' of component 'ib_sel' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu_ssr12.vhd:77]
INFO: [Synth 8-638] synthesizing module 'ib_sel' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
	Parameter IB_ADDR bound to: 16'b1111111101111100 
	Parameter SAWIDTH bound to: 0 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ib_sel' (39#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
	Parameter IB_ADDR bound to: 16'b1111111101111110 
	Parameter SAWIDTH bound to: 0 - type: integer 
INFO: [Synth 8-3491] module 'ib_sel' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:36' bound to instance 'SEL_SSR2' of component 'ib_sel' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu_ssr12.vhd:85]
INFO: [Synth 8-638] synthesizing module 'ib_sel__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
	Parameter IB_ADDR bound to: 16'b1111111101111110 
	Parameter SAWIDTH bound to: 0 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ib_sel__parameterized1' (39#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'pdp11_mmu_ssr12' (40#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu_ssr12.vhd:58]
INFO: [Synth 8-3491] module 'ib_sres_or_3' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sres_or_3.vhd:39' bound to instance 'SRES_OR' of component 'ib_sres_or_3' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu.vhd:141]
INFO: [Synth 8-638] synthesizing module 'ib_sres_or_3' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sres_or_3.vhd:48]
INFO: [Synth 8-256] done synthesizing module 'ib_sres_or_3' (41#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sres_or_3.vhd:48]
	Parameter IB_ADDR bound to: 16'b1111111101111010 
	Parameter SAWIDTH bound to: 0 - type: integer 
INFO: [Synth 8-3491] module 'ib_sel' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:36' bound to instance 'SEL_SSR0' of component 'ib_sel' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu.vhd:148]
INFO: [Synth 8-638] synthesizing module 'ib_sel__parameterized3' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
	Parameter IB_ADDR bound to: 16'b1111111101111010 
	Parameter SAWIDTH bound to: 0 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ib_sel__parameterized3' (41#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
	Parameter IB_ADDR bound to: 16'b1111010101001110 
	Parameter SAWIDTH bound to: 0 - type: integer 
INFO: [Synth 8-3491] module 'ib_sel' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:36' bound to instance 'SEL_SSR3' of component 'ib_sel' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu.vhd:156]
INFO: [Synth 8-638] synthesizing module 'ib_sel__parameterized5' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
	Parameter IB_ADDR bound to: 16'b1111010101001110 
	Parameter SAWIDTH bound to: 0 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ib_sel__parameterized5' (41#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'pdp11_mmu' (42#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mmu.vhd:76]
INFO: [Synth 8-3491] module 'pdp11_ubmap' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_ubmap.vhd:44' bound to instance 'UBMAP' of component 'pdp11_ubmap' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_vmbox.vhd:197]
INFO: [Synth 8-638] synthesizing module 'pdp11_ubmap' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_ubmap.vhd:55]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 6 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:46' bound to instance 'MAP_2' of component 'ram_1swar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_ubmap.vhd:69]
INFO: [Synth 8-638] synthesizing module 'ram_1swar_gen__parameterized8' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 6 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ram_1swar_gen__parameterized8' (42#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:46' bound to instance 'MAP_1' of component 'ram_1swar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_ubmap.vhd:80]
INFO: [Synth 8-638] synthesizing module 'ram_1swar_gen__parameterized10' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ram_1swar_gen__parameterized10' (42#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 7 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:46' bound to instance 'MAP_0' of component 'ram_1swar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_ubmap.vhd:91]
INFO: [Synth 8-638] synthesizing module 'ram_1swar_gen__parameterized12' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 7 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ram_1swar_gen__parameterized12' (42#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
	Parameter IB_ADDR bound to: 16'b1111000010000000 
	Parameter SAWIDTH bound to: 6 - type: integer 
INFO: [Synth 8-3491] module 'ib_sel' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:36' bound to instance 'SEL' of component 'ib_sel' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_ubmap.vhd:102]
INFO: [Synth 8-638] synthesizing module 'ib_sel__parameterized7' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
	Parameter IB_ADDR bound to: 16'b1111000010000000 
	Parameter SAWIDTH bound to: 6 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ib_sel__parameterized7' (42#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'pdp11_ubmap' (43#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_ubmap.vhd:55]
INFO: [Synth 8-3491] module 'ib_sres_or_4' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sres_or_4.vhd:39' bound to instance 'SRES_OR_INT' of component 'ib_sres_or_4' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_vmbox.vhd:207]
INFO: [Synth 8-638] synthesizing module 'ib_sres_or_4' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sres_or_4.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'ib_sres_or_4' (44#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sres_or_4.vhd:49]
INFO: [Synth 8-3491] module 'ib_sres_or_2' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sres_or_2.vhd:39' bound to instance 'SRES_OR_ALL' of component 'ib_sres_or_2' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_vmbox.vhd:216]
INFO: [Synth 8-638] synthesizing module 'ib_sres_or_2' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sres_or_2.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'ib_sres_or_2' (45#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sres_or_2.vhd:47]
	Parameter IB_ADDR bound to: 16'b1111111111111100 
	Parameter SAWIDTH bound to: 0 - type: integer 
INFO: [Synth 8-3491] module 'ib_sel' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:36' bound to instance 'SEL' of component 'ib_sel' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_vmbox.vhd:223]
INFO: [Synth 8-638] synthesizing module 'ib_sel__parameterized9' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
	Parameter IB_ADDR bound to: 16'b1111111111111100 
	Parameter SAWIDTH bound to: 0 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ib_sel__parameterized9' (45#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_vmbox.vhd:640]
INFO: [Synth 8-256] done synthesizing module 'pdp11_vmbox' (46#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_vmbox.vhd:99]
INFO: [Synth 8-3491] module 'pdp11_dpath' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dpath.vhd:60' bound to instance 'DPATH' of component 'pdp11_dpath' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_core.vhd:153]
INFO: [Synth 8-638] synthesizing module 'pdp11_dpath' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dpath.vhd:80]
INFO: [Synth 8-3491] module 'pdp11_gpr' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_gpr.vhd:43' bound to instance 'GPR' of component 'pdp11_gpr' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dpath.vhd:119]
INFO: [Synth 8-638] synthesizing module 'pdp11_gpr' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_gpr.vhd:60]
	Parameter AWIDTH bound to: 4 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_1ar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:50' bound to instance 'GPR_LOW' of component 'ram_1swar_1ar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_gpr.vhd:115]
INFO: [Synth 8-638] synthesizing module 'ram_1swar_1ar_gen__parameterized2' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:66]
	Parameter AWIDTH bound to: 4 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ram_1swar_1ar_gen__parameterized2' (46#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:66]
	Parameter AWIDTH bound to: 4 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_1ar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:50' bound to instance 'GPR_HIGH' of component 'ram_1swar_1ar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_gpr.vhd:128]
INFO: [Synth 8-256] done synthesizing module 'pdp11_gpr' (47#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_gpr.vhd:60]
INFO: [Synth 8-3491] module 'pdp11_psr' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_psr.vhd:47' bound to instance 'PSR' of component 'pdp11_psr' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dpath.vhd:134]
INFO: [Synth 8-638] synthesizing module 'pdp11_psr' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_psr.vhd:62]
	Parameter IB_ADDR bound to: 16'b1111111111111110 
	Parameter SAWIDTH bound to: 0 - type: integer 
INFO: [Synth 8-3491] module 'ib_sel' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:36' bound to instance 'SEL' of component 'ib_sel' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_psr.vhd:71]
INFO: [Synth 8-638] synthesizing module 'ib_sel__parameterized11' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
	Parameter IB_ADDR bound to: 16'b1111111111111110 
	Parameter SAWIDTH bound to: 0 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ib_sel__parameterized11' (47#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'pdp11_psr' (48#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_psr.vhd:62]
INFO: [Synth 8-3491] module 'pdp11_ounit' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_ounit.vhd:39' bound to instance 'OUNIT' of component 'pdp11_ounit' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dpath.vhd:147]
INFO: [Synth 8-638] synthesizing module 'pdp11_ounit' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_ounit.vhd:57]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_ounit.vhd:74]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_ounit.vhd:85]
INFO: [Synth 8-256] done synthesizing module 'pdp11_ounit' (49#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_ounit.vhd:57]
INFO: [Synth 8-3491] module 'pdp11_aunit' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_aunit.vhd:53' bound to instance 'AUNIT' of component 'pdp11_aunit' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dpath.vhd:163]
INFO: [Synth 8-638] synthesizing module 'pdp11_aunit' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_aunit.vhd:69]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_aunit.vhd:122]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_aunit.vhd:130]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_aunit.vhd:138]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_aunit.vhd:206]
INFO: [Synth 8-256] done synthesizing module 'pdp11_aunit' (50#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_aunit.vhd:69]
INFO: [Synth 8-3491] module 'pdp11_lunit' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_lunit.vhd:41' bound to instance 'LUNIT' of component 'pdp11_lunit' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dpath.vhd:177]
INFO: [Synth 8-638] synthesizing module 'pdp11_lunit' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_lunit.vhd:53]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_lunit.vhd:96]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_lunit.vhd:137]
INFO: [Synth 8-256] done synthesizing module 'pdp11_lunit' (51#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_lunit.vhd:53]
INFO: [Synth 8-3491] module 'pdp11_munit' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_munit.vhd:51' bound to instance 'MUNIT' of component 'pdp11_munit' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dpath.vhd:187]
INFO: [Synth 8-638] synthesizing module 'pdp11_munit' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_munit.vhd:77]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_munit.vhd:395]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_munit.vhd:415]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_munit.vhd:442]
INFO: [Synth 8-256] done synthesizing module 'pdp11_munit' (52#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_munit.vhd:77]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dpath.vhd:218]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dpath.vhd:234]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dpath.vhd:269]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dpath.vhd:316]
INFO: [Synth 8-256] done synthesizing module 'pdp11_dpath' (53#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dpath.vhd:80]
INFO: [Synth 8-3491] module 'pdp11_decode' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_decode.vhd:42' bound to instance 'IDEC' of component 'pdp11_decode' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_core.vhd:172]
INFO: [Synth 8-638] synthesizing module 'pdp11_decode' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_decode.vhd:49]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_decode.vhd:277]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_decode.vhd:338]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_decode.vhd:507]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_decode.vhd:519]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_decode.vhd:532]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_decode.vhd:545]
INFO: [Synth 8-256] done synthesizing module 'pdp11_decode' (54#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_decode.vhd:49]
INFO: [Synth 8-3491] module 'pdp11_sequencer' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sequencer.vhd:91' bound to instance 'SEQ' of component 'pdp11_sequencer' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_core.vhd:178]
INFO: [Synth 8-638] synthesizing module 'pdp11_sequencer' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sequencer.vhd:120]
INFO: [Synth 8-5534] Detected attribute (* fsm_encoding = "one_hot" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sequencer.vhd:259]
	Parameter IB_ADDR bound to: 16'b1111111111110110 
	Parameter SAWIDTH bound to: 0 - type: integer 
INFO: [Synth 8-3491] module 'ib_sel' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:36' bound to instance 'SEL' of component 'ib_sel' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sequencer.vhd:281]
INFO: [Synth 8-638] synthesizing module 'ib_sel__parameterized13' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
	Parameter IB_ADDR bound to: 16'b1111111111110110 
	Parameter SAWIDTH bound to: 0 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ib_sel__parameterized13' (54#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sequencer.vhd:961]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sequencer.vhd:492]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sequencer.vhd:971]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sequencer.vhd:492]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sequencer.vhd:492]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sequencer.vhd:492]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sequencer.vhd:1670]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sequencer.vhd:2038]
INFO: [Synth 8-256] done synthesizing module 'pdp11_sequencer' (55#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sequencer.vhd:120]
INFO: [Synth 8-3491] module 'pdp11_irq' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_irq.vhd:48' bound to instance 'IRQ' of component 'pdp11_irq' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_core.vhd:206]
INFO: [Synth 8-638] synthesizing module 'pdp11_irq' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_irq.vhd:63]
	Parameter IB_ADDR bound to: 16'b1111111111111010 
	Parameter SAWIDTH bound to: 0 - type: integer 
INFO: [Synth 8-3491] module 'ib_sel' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:36' bound to instance 'SEL' of component 'ib_sel' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_irq.vhd:80]
INFO: [Synth 8-638] synthesizing module 'ib_sel__parameterized15' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
	Parameter IB_ADDR bound to: 16'b1111111111111010 
	Parameter SAWIDTH bound to: 0 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ib_sel__parameterized15' (55#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sel.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'pdp11_irq' (56#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_irq.vhd:63]
INFO: [Synth 8-3491] module 'pdp11_reg70' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_reg70.vhd:42' bound to instance 'REG70' of component 'pdp11_reg70' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_core.vhd:220]
INFO: [Synth 8-638] synthesizing module 'pdp11_reg70' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_reg70.vhd:51]
INFO: [Synth 8-256] done synthesizing module 'pdp11_reg70' (57#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_reg70.vhd:51]
INFO: [Synth 8-3491] module 'ib_sres_or_4' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sres_or_4.vhd:39' bound to instance 'IB_SRES_OR' of component 'ib_sres_or_4' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_core.vhd:228]
INFO: [Synth 8-256] done synthesizing module 'pdp11_core' (58#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_core.vhd:98]
	Parameter TWIDTH bound to: 9 - type: integer 
INFO: [Synth 8-3491] module 'pdp11_cache' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_cache.vhd:55' bound to instance 'CACHE' of component 'pdp11_cache' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sys70.vhd:187]
INFO: [Synth 8-638] synthesizing module 'pdp11_cache' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_cache.vhd:77]
	Parameter TWIDTH bound to: 9 - type: integer 
	Parameter AWIDTH bound to: 11 - type: integer 
	Parameter DWIDTH bound to: 9 - type: integer 
INFO: [Synth 8-3491] module 'ram_2swsr_rfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:42' bound to instance 'CMEM_TAG' of component 'ram_2swsr_rfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_cache.vhd:152]
INFO: [Synth 8-638] synthesizing module 'ram_2swsr_rfirst_gen__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:63]
	Parameter AWIDTH bound to: 11 - type: integer 
	Parameter DWIDTH bound to: 9 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ram_2swsr_rfirst_gen__parameterized1' (58#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:63]
	Parameter AWIDTH bound to: 11 - type: integer 
	Parameter DWIDTH bound to: 9 - type: integer 
INFO: [Synth 8-3491] module 'ram_2swsr_rfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:42' bound to instance 'CMEM_DAT0' of component 'ram_2swsr_rfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_cache.vhd:171]
	Parameter AWIDTH bound to: 11 - type: integer 
	Parameter DWIDTH bound to: 9 - type: integer 
INFO: [Synth 8-3491] module 'ram_2swsr_rfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:42' bound to instance 'CMEM_DAT1' of component 'ram_2swsr_rfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_cache.vhd:190]
	Parameter AWIDTH bound to: 11 - type: integer 
	Parameter DWIDTH bound to: 9 - type: integer 
INFO: [Synth 8-3491] module 'ram_2swsr_rfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:42' bound to instance 'CMEM_DAT2' of component 'ram_2swsr_rfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_cache.vhd:209]
	Parameter AWIDTH bound to: 11 - type: integer 
	Parameter DWIDTH bound to: 9 - type: integer 
INFO: [Synth 8-3491] module 'ram_2swsr_rfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:42' bound to instance 'CMEM_DAT3' of component 'ram_2swsr_rfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_cache.vhd:228]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_cache.vhd:349]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_cache.vhd:479]
INFO: [Synth 8-256] done synthesizing module 'pdp11_cache' (59#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_cache.vhd:77]
INFO: [Synth 8-3491] module 'pdp11_mem70' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mem70.vhd:43' bound to instance 'MEM70' of component 'pdp11_mem70' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sys70.vhd:207]
INFO: [Synth 8-638] synthesizing module 'pdp11_mem70' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mem70.vhd:55]
INFO: [Synth 8-256] done synthesizing module 'pdp11_mem70' (60#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_mem70.vhd:55]
INFO: [Synth 8-3491] module 'ib_sres_or_3' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sres_or_3.vhd:39' bound to instance 'IB_SRES_OR' of component 'ib_sres_or_3' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sys70.vhd:236]
	Parameter RB_ADDR bound to: 16'b0000000001010000 
	Parameter NUNIT bound to: 2 - type: integer 
INFO: [Synth 8-3491] module 'pdp11_dmhbpt' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmhbpt.vhd:45' bound to instance 'I0' of component 'pdp11_dmhbpt' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sys70.vhd:281]
INFO: [Synth 8-638] synthesizing module 'pdp11_dmhbpt' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmhbpt.vhd:63]
	Parameter RB_ADDR bound to: 16'b0000000001010000 
	Parameter NUNIT bound to: 2 - type: integer 
	Parameter RB_ADDR bound to: 16'b0000000001010000 
	Parameter INDEX bound to: 1 - type: integer 
INFO: [Synth 8-3491] module 'pdp11_dmhbpt_unit' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmhbpt_unit.vhd:60' bound to instance 'HBPT' of component 'pdp11_dmhbpt_unit' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmhbpt.vhd:77]
INFO: [Synth 8-638] synthesizing module 'pdp11_dmhbpt_unit' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmhbpt_unit.vhd:78]
	Parameter RB_ADDR bound to: 16'b0000000001010000 
	Parameter INDEX bound to: 1 - type: integer 
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmhbpt_unit.vhd:175]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmhbpt_unit.vhd:207]
INFO: [Synth 8-256] done synthesizing module 'pdp11_dmhbpt_unit' (61#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmhbpt_unit.vhd:78]
	Parameter RB_ADDR bound to: 16'b0000000001010000 
	Parameter INDEX bound to: 0 - type: integer 
INFO: [Synth 8-3491] module 'pdp11_dmhbpt_unit' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmhbpt_unit.vhd:60' bound to instance 'HBPT' of component 'pdp11_dmhbpt_unit' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmhbpt.vhd:77]
INFO: [Synth 8-638] synthesizing module 'pdp11_dmhbpt_unit__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmhbpt_unit.vhd:78]
	Parameter RB_ADDR bound to: 16'b0000000001010000 
	Parameter INDEX bound to: 0 - type: integer 
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmhbpt_unit.vhd:175]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmhbpt_unit.vhd:207]
INFO: [Synth 8-256] done synthesizing module 'pdp11_dmhbpt_unit__parameterized1' (61#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmhbpt_unit.vhd:78]
INFO: [Synth 8-3491] module 'rb_sres_or_4' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rb_sres_or_4.vhd:39' bound to instance 'RB_SRES_OR' of component 'rb_sres_or_4' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmhbpt.vhd:98]
INFO: [Synth 8-638] synthesizing module 'rb_sres_or_4' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rb_sres_or_4.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'rb_sres_or_4' (62#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rb_sres_or_4.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'pdp11_dmhbpt' (63#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmhbpt.vhd:63]
	Parameter RB_ADDR bound to: 16'b0000000001100000 
	Parameter VERS bound to: 8'b00000001 
	Parameter CENA bound to: 32'b11111111111111111111111111111111 
INFO: [Synth 8-3491] module 'pdp11_dmpcnt' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmpcnt.vhd:106' bound to instance 'I0' of component 'pdp11_dmpcnt' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sys70.vhd:376]
INFO: [Synth 8-638] synthesizing module 'pdp11_dmpcnt' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmpcnt.vhd:121]
	Parameter RB_ADDR bound to: 16'b0000000001100000 
	Parameter VERS bound to: 8'b00000001 
	Parameter CENA bound to: -1 - type: integer 
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 32 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:46' bound to instance 'MEM' of component 'ram_1swar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmpcnt.vhd:176]
INFO: [Synth 8-638] synthesizing module 'ram_1swar_gen__parameterized14' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 32 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ram_1swar_gen__parameterized14' (63#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
INFO: [Synth 8-638] synthesizing module 'pdp11_dmpcnt_precnt' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmpcnt.vhd:74]
INFO: [Synth 8-256] done synthesizing module 'pdp11_dmpcnt_precnt' (64#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmpcnt.vhd:74]
INFO: [Synth 8-256] done synthesizing module 'pdp11_dmpcnt' (65#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dmpcnt.vhd:121]
INFO: [Synth 8-3491] module 'rb_sres_or_4' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rb_sres_or_4.vhd:39' bound to instance 'RB_SRES_DMOR' of component 'rb_sres_or_4' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sys70.vhd:392]
INFO: [Synth 8-3491] module 'rb_sres_or_2' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rb_sres_or_2.vhd:39' bound to instance 'RB_SRES_OR' of component 'rb_sres_or_2' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sys70.vhd:401]
INFO: [Synth 8-256] done synthesizing module 'pdp11_sys70' (66#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_sys70.vhd:94]
INFO: [Synth 8-3491] module 'ibdr_maxisys' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:110' bound to instance 'IBDR_SYS' of component 'ibdr_maxisys' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd:333]
INFO: [Synth 8-638] synthesizing module 'ibdr_maxisys' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:130]
	Parameter SID bound to: 2'b00 
INFO: [Synth 8-3491] module 'ibd_iist' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibd_iist.vhd:52' bound to instance 'I0' of component 'ibd_iist' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:237]
INFO: [Synth 8-638] synthesizing module 'ibd_iist' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibd_iist.vhd:72]
	Parameter SID bound to: 2'b00 
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibd_iist.vhd:317]
WARNING: [Synth 8-5858] RAM eff_bus_reg from Abstract Data Type (record/struct) for this pattern/configuration is not supported. This will most likely be implemented in registers
INFO: [Synth 8-256] done synthesizing module 'ibd_iist' (67#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibd_iist.vhd:72]
INFO: [Synth 8-3491] module 'ibd_kw11l' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibd_kw11l.vhd:49' bound to instance 'KW11L' of component 'ibd_kw11l' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:260]
INFO: [Synth 8-638] synthesizing module 'ibd_kw11l' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibd_kw11l.vhd:64]
INFO: [Synth 8-256] done synthesizing module 'ibd_kw11l' (68#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibd_kw11l.vhd:64]
INFO: [Synth 8-3491] module 'ibd_kw11p' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibd_kw11p.vhd:40' bound to instance 'I0' of component 'ibd_kw11p' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:275]
INFO: [Synth 8-638] synthesizing module 'ibd_kw11p' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibd_kw11p.vhd:57]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibd_kw11p.vhd:250]
INFO: [Synth 8-256] done synthesizing module 'ibd_kw11p' (69#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibd_kw11p.vhd:57]
INFO: [Synth 8-3491] module 'ibdr_deuna' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_deuna.vhd:44' bound to instance 'XUA' of component 'ibdr_deuna' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:293]
INFO: [Synth 8-638] synthesizing module 'ibdr_deuna' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_deuna.vhd:57]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_deuna.vhd:193]
INFO: [Synth 8-256] done synthesizing module 'ibdr_deuna' (70#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_deuna.vhd:57]
INFO: [Synth 8-3491] module 'ibdr_rhrp' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rhrp.vhd:49' bound to instance 'RPA' of component 'ibdr_rhrp' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:307]
INFO: [Synth 8-638] synthesizing module 'ibdr_rhrp' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rhrp.vhd:70]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:46' bound to instance 'MEM_1' of component 'ram_1swar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rhrp.vhd:419]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:46' bound to instance 'MEM_0' of component 'ram_1swar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rhrp.vhd:430]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rhrp.vhd:1348]
INFO: [Synth 8-256] done synthesizing module 'ibdr_rhrp' (71#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rhrp.vhd:70]
INFO: [Synth 8-3491] module 'ibdr_rl11' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rl11.vhd:45' bound to instance 'RLA' of component 'ibdr_rl11' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:323]
INFO: [Synth 8-638] synthesizing module 'ibdr_rl11' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rl11.vhd:59]
	Parameter AWIDTH bound to: 4 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:46' bound to instance 'MEM_1' of component 'ram_1swar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rl11.vhd:252]
INFO: [Synth 8-638] synthesizing module 'ram_1swar_gen__parameterized16' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
	Parameter AWIDTH bound to: 4 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'ram_1swar_gen__parameterized16' (71#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:60]
	Parameter AWIDTH bound to: 4 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:46' bound to instance 'MEM_0' of component 'ram_1swar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rl11.vhd:263]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rl11.vhd:340]
INFO: [Synth 8-256] done synthesizing module 'ibdr_rl11' (72#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rl11.vhd:59]
INFO: [Synth 8-3491] module 'ibdr_rk11' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rk11.vhd:62' bound to instance 'RKA' of component 'ibdr_rk11' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:338]
INFO: [Synth 8-638] synthesizing module 'ibdr_rk11' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rk11.vhd:76]
	Parameter AWIDTH bound to: 4 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:46' bound to instance 'MEM_1' of component 'ram_1swar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rk11.vhd:182]
	Parameter AWIDTH bound to: 4 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swar_gen.vhd:46' bound to instance 'MEM_0' of component 'ram_1swar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rk11.vhd:193]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rk11.vhd:271]
INFO: [Synth 8-256] done synthesizing module 'ibdr_rk11' (73#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_rk11.vhd:76]
INFO: [Synth 8-3491] module 'ibdr_tm11' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_tm11.vhd:43' bound to instance 'TMA' of component 'ibdr_tm11' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:353]
INFO: [Synth 8-638] synthesizing module 'ibdr_tm11' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_tm11.vhd:56]
INFO: [Synth 8-256] done synthesizing module 'ibdr_tm11' (74#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_tm11.vhd:56]
	Parameter IB_ADDR bound to: 16'b1111111101110000 
INFO: [Synth 8-3491] module 'ibdr_dl11' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_dl11.vhd:54' bound to instance 'DL11_0' of component 'ibdr_dl11' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:365]
INFO: [Synth 8-638] synthesizing module 'ibdr_dl11' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_dl11.vhd:72]
	Parameter IB_ADDR bound to: 16'b1111111101110000 
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_dl11.vhd:174]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_dl11.vhd:297]
INFO: [Synth 8-256] done synthesizing module 'ibdr_dl11' (75#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_dl11.vhd:72]
	Parameter IB_ADDR bound to: 16'b1111110101000000 
INFO: [Synth 8-3491] module 'ibdr_dl11' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_dl11.vhd:54' bound to instance 'TTB' of component 'ibdr_dl11' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:382]
INFO: [Synth 8-638] synthesizing module 'ibdr_dl11__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_dl11.vhd:72]
	Parameter IB_ADDR bound to: 16'b1111110101000000 
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_dl11.vhd:174]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_dl11.vhd:297]
INFO: [Synth 8-256] done synthesizing module 'ibdr_dl11__parameterized1' (75#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_dl11.vhd:72]
INFO: [Synth 8-3491] module 'ibdr_pc11' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_pc11.vhd:49' bound to instance 'PCA' of component 'ibdr_pc11' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:402]
INFO: [Synth 8-638] synthesizing module 'ibdr_pc11' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_pc11.vhd:65]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_pc11.vhd:165]
INFO: [Synth 8-256] done synthesizing module 'ibdr_pc11' (76#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_pc11.vhd:65]
INFO: [Synth 8-3491] module 'ibdr_lp11' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_lp11.vhd:53' bound to instance 'LPA' of component 'ibdr_lp11' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:419]
INFO: [Synth 8-638] synthesizing module 'ibdr_lp11' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_lp11.vhd:67]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_lp11.vhd:146]
INFO: [Synth 8-256] done synthesizing module 'ibdr_lp11' (77#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_lp11.vhd:67]
INFO: [Synth 8-3491] module 'ibdr_sdreg' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_sdreg.vhd:50' bound to instance 'SDREG' of component 'ibdr_sdreg' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:432]
INFO: [Synth 8-638] synthesizing module 'ibdr_sdreg' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_sdreg.vhd:61]
INFO: [Synth 8-256] done synthesizing module 'ibdr_sdreg' (78#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_sdreg.vhd:61]
INFO: [Synth 8-3491] module 'ib_sres_or_4' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sres_or_4.vhd:39' bound to instance 'SRES_OR_1' of component 'ib_sres_or_4' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:441]
INFO: [Synth 8-3491] module 'ib_sres_or_4' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sres_or_4.vhd:39' bound to instance 'SRES_OR_2' of component 'ib_sres_or_4' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:450]
INFO: [Synth 8-3491] module 'ib_sres_or_3' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sres_or_3.vhd:39' bound to instance 'SRES_OR_3' of component 'ib_sres_or_3' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:459]
INFO: [Synth 8-3491] module 'ib_sres_or_3' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sres_or_3.vhd:39' bound to instance 'SRES_OR_4' of component 'ib_sres_or_3' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:467]
INFO: [Synth 8-3491] module 'ib_sres_or_4' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_sres_or_4.vhd:39' bound to instance 'SRES_OR' of component 'ib_sres_or_4' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:475]
	Parameter INTMAP bound to: 1488'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000000000000000000000000000001100000000000000000000000010110000000000000000000000000000000011000000000000000000000000010000000000000000000000000000000000110000000000000000000000000101000000000000000000000000000000001010000000000000000000000010101100000000000000000000000000000010100000000000000000000000011100000000000000000000000000000000101000000000000000000000001001000000000000000000000000000000001010000000000000000000000010010100000000000000000000000000000010100000000000000000000000110010000000000000000000000000000000101000000000000000000000001100110000000000000000000000000000001010000000000000000000000000110000000000000000000000000000000010000000000000000000000000001101000000000000000000000000000000100000000000000000000000001100000000000000000000000000000000001000000000000000000000000011000100000000000000000000000000000010000000000000000000000000001110000000000000000000000000000000100000000000000000000000000011110000000000000000000000000000001000000000000000000000000010000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000 
INFO: [Synth 8-3491] module 'ib_intmap24' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_intmap24.vhd:42' bound to instance 'INTMAP' of component 'ib_intmap24' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:484]
INFO: [Synth 8-638] synthesizing module 'ib_intmap24' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_intmap24.vhd:54]
	Parameter INTMAP bound to: 1488'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100010000000000000000000000000000001100000000000000000000000010110000000000000000000000000000000011000000000000000000000000010000000000000000000000000000000000110000000000000000000000000101000000000000000000000000000000001010000000000000000000000010101100000000000000000000000000000010100000000000000000000000011100000000000000000000000000000000101000000000000000000000001001000000000000000000000000000000001010000000000000000000000010010100000000000000000000000000000010100000000000000000000000110010000000000000000000000000000000101000000000000000000000001100110000000000000000000000000000001010000000000000000000000000110000000000000000000000000000000010000000000000000000000000001101000000000000000000000000000000100000000000000000000000001100000000000000000000000000000000001000000000000000000000000011000100000000000000000000000000000010000000000000000000000000001110000000000000000000000000000000100000000000000000000000000011110000000000000000000000000000001000000000000000000000000010000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000 
INFO: [Synth 8-256] done synthesizing module 'ib_intmap24' (79#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ib_intmap24.vhd:54]
INFO: [Synth 8-256] done synthesizing module 'ibdr_maxisys' (80#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/ibus/ibdr_maxisys.vhd:130]
	Parameter MAWIDTH bound to: 4 - type: integer 
	Parameter NBLOCK bound to: 11 - type: integer 
INFO: [Synth 8-3491] module 'pdp11_bram_memctl' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:40' bound to instance 'BRAM_CTL' of component 'pdp11_bram_memctl' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd:352]
INFO: [Synth 8-638] synthesizing module 'pdp11_bram_memctl' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:61]
	Parameter MAWIDTH bound to: 4 - type: integer 
	Parameter NBLOCK bound to: 11 - type: integer 
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
INFO: [Synth 8-638] synthesizing module 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:61]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* ram_style = "block" *) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:66]
INFO: [Synth 8-256] done synthesizing module 'ram_1swsr_wfirst_gen' (81#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:61]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'MCELL' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:114]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:161]
INFO: [Synth 8-256] done synthesizing module 'pdp11_bram_memctl' (82#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_bram_memctl.vhd:61]
INFO: [Synth 8-3491] module 'ioleds_sp1c' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/ioleds_sp1c.vhd:37' bound to instance 'LED_IO' of component 'ioleds_sp1c' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd:372]
INFO: [Synth 8-638] synthesizing module 'ioleds_sp1c' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/ioleds_sp1c.vhd:45]
INFO: [Synth 8-256] done synthesizing module 'ioleds_sp1c' (83#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rlink/ioleds_sp1c.vhd:45]
	Parameter LWIDTH bound to: 16 - type: integer 
	Parameter DCWIDTH bound to: 2 - type: integer 
INFO: [Synth 8-3491] module 'pdp11_hio70' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_hio70.vhd:40' bound to instance 'HIO70' of component 'pdp11_hio70' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd:380]
INFO: [Synth 8-638] synthesizing module 'pdp11_hio70' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_hio70.vhd:58]
	Parameter LWIDTH bound to: 16 - type: integer 
	Parameter DCWIDTH bound to: 2 - type: integer 
INFO: [Synth 8-3491] module 'pdp11_statleds' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_statleds.vhd:50' bound to instance 'LED_CPU' of component 'pdp11_statleds' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_hio70.vhd:64]
INFO: [Synth 8-638] synthesizing module 'pdp11_statleds' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_statleds.vhd:60]
INFO: [Synth 8-256] done synthesizing module 'pdp11_statleds' (84#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_statleds.vhd:60]
	Parameter LWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-3491] module 'pdp11_ledmux' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_ledmux.vhd:39' bound to instance 'LED_MUX' of component 'pdp11_ledmux' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_hio70.vhd:73]
INFO: [Synth 8-638] synthesizing module 'pdp11_ledmux' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_ledmux.vhd:50]
	Parameter LWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'pdp11_ledmux' (85#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_ledmux.vhd:50]
	Parameter DCWIDTH bound to: 2 - type: integer 
INFO: [Synth 8-3491] module 'pdp11_dspmux' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dspmux.vhd:54' bound to instance 'DSP_MUX' of component 'pdp11_dspmux' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_hio70.vhd:83]
INFO: [Synth 8-638] synthesizing module 'pdp11_dspmux' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dspmux.vhd:66]
	Parameter DCWIDTH bound to: 2 - type: integer 
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dspmux.vhd:84]
INFO: [Synth 8-256] done synthesizing module 'pdp11_dspmux' (86#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_dspmux.vhd:66]
INFO: [Synth 8-256] done synthesizing module 'pdp11_hio70' (87#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/w11a/pdp11_hio70.vhd:58]
	Parameter SWIDTH bound to: 16 - type: integer 
	Parameter BWIDTH bound to: 5 - type: integer 
	Parameter LWIDTH bound to: 16 - type: integer 
	Parameter DCWIDTH bound to: 2 - type: integer 
	Parameter DEBOUNCE bound to: 1 - type: bool 
	Parameter RB_ADDR bound to: 16'b1111111011110000 
INFO: [Synth 8-3491] module 'sn_humanio_rbus' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/sn_humanio_rbus.vhd:94' bound to instance 'HIO' of component 'sn_humanio_rbus' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd:397]
INFO: [Synth 8-638] synthesizing module 'sn_humanio_rbus' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/sn_humanio_rbus.vhd:121]
	Parameter SWIDTH bound to: 16 - type: integer 
	Parameter BWIDTH bound to: 5 - type: integer 
	Parameter LWIDTH bound to: 16 - type: integer 
	Parameter DCWIDTH bound to: 2 - type: integer 
	Parameter DEBOUNCE bound to: 1 - type: bool 
	Parameter RB_ADDR bound to: 16'b1111111011110000 
	Parameter SWIDTH bound to: 16 - type: integer 
	Parameter BWIDTH bound to: 5 - type: integer 
	Parameter LWIDTH bound to: 16 - type: integer 
	Parameter DCWIDTH bound to: 2 - type: integer 
	Parameter DEBOUNCE bound to: 1 - type: bool 
INFO: [Synth 8-3491] module 'sn_humanio' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/sn_humanio.vhd:57' bound to instance 'HIO' of component 'sn_humanio' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/sn_humanio_rbus.vhd:214]
INFO: [Synth 8-638] synthesizing module 'sn_humanio' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/sn_humanio.vhd:81]
	Parameter SWIDTH bound to: 16 - type: integer 
	Parameter BWIDTH bound to: 5 - type: integer 
	Parameter LWIDTH bound to: 16 - type: integer 
	Parameter DCWIDTH bound to: 2 - type: integer 
	Parameter DEBOUNCE bound to: 1 - type: bool 
	Parameter DWIDTH bound to: 4 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'iob_reg_o_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:34' bound to instance 'IOB_ANO_N' of component 'iob_reg_o_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/sn_humanio.vhd:88]
INFO: [Synth 8-638] synthesizing module 'iob_reg_o_gen__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:47]
	Parameter DWIDTH bound to: 4 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'iob_reg_o_gen__parameterized1' (87#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:47]
	Parameter DWIDTH bound to: 8 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'iob_reg_o_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:34' bound to instance 'IOB_SEG_N' of component 'iob_reg_o_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/sn_humanio.vhd:92]
INFO: [Synth 8-638] synthesizing module 'iob_reg_o_gen__parameterized3' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:47]
	Parameter DWIDTH bound to: 8 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'iob_reg_o_gen__parameterized3' (87#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:47]
	Parameter SWIDTH bound to: 16 - type: integer 
	Parameter BWIDTH bound to: 5 - type: integer 
	Parameter LWIDTH bound to: 16 - type: integer 
	Parameter DEBOUNCE bound to: 1 - type: bool 
INFO: [Synth 8-3491] module 'bp_swibtnled' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/bp_swibtnled.vhd:43' bound to instance 'HIO' of component 'bp_swibtnled' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/sn_humanio.vhd:96]
INFO: [Synth 8-638] synthesizing module 'bp_swibtnled' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/bp_swibtnled.vhd:62]
	Parameter SWIDTH bound to: 16 - type: integer 
	Parameter BWIDTH bound to: 5 - type: integer 
	Parameter LWIDTH bound to: 16 - type: integer 
	Parameter DEBOUNCE bound to: 1 - type: bool 
	Parameter DWIDTH bound to: 16 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'iob_reg_i_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:34' bound to instance 'IOB_SWI' of component 'iob_reg_i_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/bp_swibtnled.vhd:69]
INFO: [Synth 8-638] synthesizing module 'iob_reg_i_gen__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:47]
	Parameter DWIDTH bound to: 16 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'iob_reg_i_gen__parameterized1' (87#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:47]
	Parameter DWIDTH bound to: 5 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'iob_reg_i_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:34' bound to instance 'IOB_BTN' of component 'iob_reg_i_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/bp_swibtnled.vhd:73]
INFO: [Synth 8-638] synthesizing module 'iob_reg_i_gen__parameterized3' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:47]
	Parameter DWIDTH bound to: 5 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'iob_reg_i_gen__parameterized3' (87#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:47]
	Parameter DWIDTH bound to: 16 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'iob_reg_o_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:34' bound to instance 'IOB_LED' of component 'iob_reg_o_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/bp_swibtnled.vhd:77]
INFO: [Synth 8-638] synthesizing module 'iob_reg_o_gen__parameterized5' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:47]
	Parameter DWIDTH bound to: 16 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'iob_reg_o_gen__parameterized5' (87#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:47]
	Parameter CWIDTH bound to: 2 - type: integer 
	Parameter CEDIV bound to: 3 - type: integer 
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-3491] module 'debounce_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/debounce_gen.vhd:36' bound to instance 'DEB_SWI' of component 'debounce_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/bp_swibtnled.vhd:83]
INFO: [Synth 8-638] synthesizing module 'debounce_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/debounce_gen.vhd:51]
	Parameter CWIDTH bound to: 2 - type: integer 
	Parameter CEDIV bound to: 3 - type: integer 
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'debounce_gen' (88#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/debounce_gen.vhd:51]
	Parameter CWIDTH bound to: 2 - type: integer 
	Parameter CEDIV bound to: 3 - type: integer 
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'debounce_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/debounce_gen.vhd:36' bound to instance 'DEB_BTN' of component 'debounce_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/bp_swibtnled.vhd:96]
INFO: [Synth 8-638] synthesizing module 'debounce_gen__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/debounce_gen.vhd:51]
	Parameter CWIDTH bound to: 2 - type: integer 
	Parameter CEDIV bound to: 3 - type: integer 
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'debounce_gen__parameterized1' (88#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/genlib/debounce_gen.vhd:51]
INFO: [Synth 8-256] done synthesizing module 'bp_swibtnled' (89#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/bp_swibtnled.vhd:62]
	Parameter DCWIDTH bound to: 2 - type: integer 
	Parameter CDWIDTH bound to: 7 - type: integer 
INFO: [Synth 8-3491] module 'sn_7segctl' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/sn_7segctl.vhd:49' bound to instance 'DRV' of component 'sn_7segctl' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/sn_humanio.vhd:114]
INFO: [Common 17-14] Message 'Synth 8-3491' appears 200 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-638] synthesizing module 'sn_7segctl' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/sn_7segctl.vhd:62]
	Parameter DCWIDTH bound to: 2 - type: integer 
	Parameter CDWIDTH bound to: 7 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'sn_7segctl' (90#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/sn_7segctl.vhd:62]
INFO: [Synth 8-256] done synthesizing module 'sn_humanio' (91#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/sn_humanio.vhd:81]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/sn_humanio_rbus.vhd:289]
INFO: [Synth 8-256] done synthesizing module 'sn_humanio_rbus' (92#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/bpgen/sn_humanio_rbus.vhd:121]
	Parameter INIT_TEMP_UP bound to: 85.000000 - type: float 
	Parameter INIT_TEMP_LOW bound to: 60.000000 - type: float 
	Parameter INIT_VCCINT_UP bound to: 1.050000 - type: float 
	Parameter INIT_VCCINT_LOW bound to: 0.950000 - type: float 
	Parameter INIT_VCCAUX_UP bound to: 1.890000 - type: float 
	Parameter INIT_VCCAUX_LOW bound to: 1.710000 - type: float 
	Parameter INIT_VCCBRAM_UP bound to: 1.050000 - type: float 
	Parameter INIT_VCCBRAM_LOW bound to: 0.950000 - type: float 
	Parameter CLK_MHZ bound to: 80 - type: integer 
	Parameter RB_ADDR bound to: 16'b1111101100000000 
INFO: [Synth 8-638] synthesizing module 'sysmonx_rbus_base' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/sysmon/sysmonx_rbus_base.vhd:73]
	Parameter INIT_TEMP_UP bound to: 85.000000 - type: float 
	Parameter INIT_TEMP_LOW bound to: 60.000000 - type: float 
	Parameter INIT_VCCINT_UP bound to: 1.050000 - type: float 
	Parameter INIT_VCCINT_LOW bound to: 0.950000 - type: float 
	Parameter INIT_VCCAUX_UP bound to: 1.890000 - type: float 
	Parameter INIT_VCCAUX_LOW bound to: 1.710000 - type: float 
	Parameter INIT_VCCBRAM_UP bound to: 1.050000 - type: float 
	Parameter INIT_VCCBRAM_LOW bound to: 0.950000 - type: float 
	Parameter CLK_MHZ bound to: 80 - type: integer 
	Parameter RB_ADDR bound to: 16'b1111101100000000 
	Parameter INIT_40 bound to: 16'b1001000000000000 
	Parameter INIT_41 bound to: 16'b0010111011110000 
	Parameter INIT_42 bound to: 16'b0000010000000000 
	Parameter INIT_43 bound to: 16'b0000000000000000 
	Parameter INIT_44 bound to: 16'b0000000000000000 
	Parameter INIT_45 bound to: 16'b0000000000000000 
	Parameter INIT_46 bound to: 16'b0000000000000000 
	Parameter INIT_47 bound to: 16'b0000000000000000 
	Parameter INIT_48 bound to: 16'b0100011100000001 
	Parameter INIT_49 bound to: 16'b0000000000000000 
	Parameter INIT_4A bound to: 16'b0000000000000000 
	Parameter INIT_4B bound to: 16'b0000000000000000 
	Parameter INIT_4C bound to: 16'b0000000000000000 
	Parameter INIT_4D bound to: 16'b0000000000000000 
	Parameter INIT_4E bound to: 16'b0000000000000000 
	Parameter INIT_4F bound to: 16'b0000000000000000 
	Parameter INIT_50 bound to: 16'b1011010111101100 
	Parameter INIT_51 bound to: 16'b0101100110011010 
	Parameter INIT_52 bound to: 16'b1010000101001000 
	Parameter INIT_53 bound to: 16'b1100101000110011 
	Parameter INIT_54 bound to: 16'b1010100100111001 
	Parameter INIT_55 bound to: 16'b0101000100010001 
	Parameter INIT_56 bound to: 16'b1001000111101100 
	Parameter INIT_57 bound to: 16'b1010111001000000 
	Parameter INIT_58 bound to: 16'b0101100110011010 
	Parameter INIT_59 bound to: 16'b0000000000000000 
	Parameter INIT_5A bound to: 16'b0000000000000000 
	Parameter INIT_5B bound to: 16'b0000000000000000 
	Parameter INIT_5C bound to: 16'b0101000100010001 
	Parameter INIT_5D bound to: 16'b0000000000000000 
	Parameter INIT_5E bound to: 16'b0000000000000000 
	Parameter INIT_5F bound to: 16'b0000000000000000 
	Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 
	Parameter IS_DCLK_INVERTED bound to: 1'b0 
	Parameter SIM_DEVICE bound to: 7SERIES - type: string 
	Parameter SIM_MONITOR_FILE bound to: sysmon_stim - type: string 
INFO: [Synth 8-113] binding component instance 'SM' to cell 'XADC' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/sysmon/sysmonx_rbus_base.vhd:96]
	Parameter DAWIDTH bound to: 7 - type: integer 
	Parameter ALWIDTH bound to: 8 - type: integer 
	Parameter TEWIDTH bound to: 12 - type: integer 
	Parameter IBASE bound to: 8'b01111000 
	Parameter RB_ADDR bound to: 16'b1111101100000000 
INFO: [Synth 8-638] synthesizing module 'sysmon_rbus_core' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/sysmon/sysmon_rbus_core.vhd:96]
	Parameter DAWIDTH bound to: 7 - type: integer 
	Parameter ALWIDTH bound to: 8 - type: integer 
	Parameter TEWIDTH bound to: 12 - type: integer 
	Parameter IBASE bound to: 8'b01111000 
	Parameter RB_ADDR bound to: 16'b1111101100000000 
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/sysmon/sysmon_rbus_core.vhd:240]
INFO: [Synth 8-256] done synthesizing module 'sysmon_rbus_core' (93#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/sysmon/sysmon_rbus_core.vhd:96]
INFO: [Synth 8-256] done synthesizing module 'sysmonx_rbus_base' (94#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/sysmon/sysmonx_rbus_base.vhd:73]
	Parameter RB_ADDR bound to: 16'b1111111111111010 
INFO: [Synth 8-638] synthesizing module 'rbd_usracc' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rbd_usracc.vhd:56]
	Parameter RB_ADDR bound to: 16'b1111111111111010 
	Parameter RB_ADDR bound to: 16'b1111111111111010 
	Parameter SAWIDTH bound to: 1 - type: integer 
INFO: [Synth 8-638] synthesizing module 'rb_sel__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rb_sel.vhd:49]
	Parameter RB_ADDR bound to: 16'b1111111111111010 
	Parameter SAWIDTH bound to: 1 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'rb_sel__parameterized1' (94#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rb_sel.vhd:49]
INFO: [Synth 8-638] synthesizing module 'usr_access_unisim' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/usr_access_unisim.vhd:43]
INFO: [Synth 8-113] binding component instance 'UA' to cell 'USR_ACCESSE2' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/usr_access_unisim.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'usr_access_unisim' (95#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/xlib/usr_access_unisim.vhd:43]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rbd_usracc.vhd:93]
INFO: [Synth 8-256] done synthesizing module 'rbd_usracc' (96#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/rbus/rbd_usracc.vhd:56]
INFO: [Synth 8-256] done synthesizing module 'sys_w11a_b3' (97#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd:146]
WARNING: [Synth 8-3331] design sysmon_rbus_core has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[re]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[we]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[addr][0]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][15]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][14]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][13]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][12]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][11]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][10]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][9]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][8]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][7]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][6]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][5]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][4]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][3]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][2]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][1]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][0]
WARNING: [Synth 8-3331] design sn_humanio_rbus has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design pdp11_dspmux has unconnected port DM_STAT_EXP[dp_psw][cmode][1]
WARNING: [Synth 8-3331] design pdp11_dspmux has unconnected port DM_STAT_EXP[dp_psw][cmode][0]
WARNING: [Synth 8-3331] design pdp11_dspmux has unconnected port DM_STAT_EXP[dp_psw][pmode][1]
WARNING: [Synth 8-3331] design pdp11_dspmux has unconnected port DM_STAT_EXP[dp_psw][pmode][0]
WARNING: [Synth 8-3331] design pdp11_dspmux has unconnected port DM_STAT_EXP[dp_psw][rset]
WARNING: [Synth 8-3331] design pdp11_dspmux has unconnected port DM_STAT_EXP[dp_psw][pri][2]
WARNING: [Synth 8-3331] design pdp11_dspmux has unconnected port DM_STAT_EXP[dp_psw][pri][1]
WARNING: [Synth 8-3331] design pdp11_dspmux has unconnected port DM_STAT_EXP[dp_psw][pri][0]
WARNING: [Synth 8-3331] design pdp11_dspmux has unconnected port DM_STAT_EXP[dp_psw][tflag]
WARNING: [Synth 8-3331] design pdp11_dspmux has unconnected port DM_STAT_EXP[dp_psw][cc][3]
WARNING: [Synth 8-3331] design pdp11_dspmux has unconnected port DM_STAT_EXP[dp_psw][cc][2]
WARNING: [Synth 8-3331] design pdp11_dspmux has unconnected port DM_STAT_EXP[dp_psw][cc][1]
WARNING: [Synth 8-3331] design pdp11_dspmux has unconnected port DM_STAT_EXP[dp_psw][cc][0]
WARNING: [Synth 8-3331] design pdp11_dspmux has unconnected port DM_STAT_EXP[se_idec]
WARNING: [Synth 8-3331] design pdp11_dspmux has unconnected port DM_STAT_EXP[se_itimer]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_pc][15]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_pc][14]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_pc][13]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_pc][12]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_pc][11]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_pc][10]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_pc][9]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_pc][8]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_pc][7]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_pc][6]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_pc][5]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_pc][4]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_pc][3]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_pc][2]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_pc][1]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_pc][0]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_psw][cmode][1]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_psw][cmode][0]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_psw][pmode][1]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_psw][pmode][0]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_psw][rset]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_psw][pri][2]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_psw][pri][1]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_psw][pri][0]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_psw][tflag]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_psw][cc][3]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_psw][cc][2]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_psw][cc][1]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[dp_psw][cc][0]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[se_idec]
WARNING: [Synth 8-3331] design pdp11_ledmux has unconnected port DM_STAT_EXP[se_itimer]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port CP_STAT[cmdack]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port CP_STAT[cmderr]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port CP_STAT[cmdmerr]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port CP_STAT[cpustep]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port CP_STAT[cpususp]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port CP_STAT[suspint]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port CP_STAT[suspext]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_pc][15]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_pc][14]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_pc][13]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_pc][12]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_pc][11]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_pc][10]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_pc][9]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_pc][8]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_pc][7]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_pc][6]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_pc][5]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_pc][4]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_pc][3]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_pc][2]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_pc][1]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_pc][0]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_psw][pmode][1]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_psw][pmode][0]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_psw][rset]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_psw][tflag]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_psw][cc][3]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_psw][cc][2]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_psw][cc][1]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_psw][cc][0]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_dsrc][15]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_dsrc][14]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_dsrc][13]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_dsrc][12]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_dsrc][11]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_dsrc][10]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_dsrc][9]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_dsrc][8]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_dsrc][7]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_dsrc][6]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_dsrc][5]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_dsrc][4]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_dsrc][3]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_dsrc][2]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_dsrc][1]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[dp_dsrc][0]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[se_idec]
WARNING: [Synth 8-3331] design pdp11_statleds has unconnected port DM_STAT_EXP[se_itimer]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[rxerr]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[rxovr]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abact]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abdone]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv][15]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv][14]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv][13]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv][12]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv][11]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv][10]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv][9]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv][8]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv][7]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv][6]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv][5]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv][4]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv][3]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv][2]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv][1]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv][0]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv_f][2]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv_f][1]
WARNING: [Synth 8-3331] design ioleds_sp1c has unconnected port SER_MONI[abclkdiv_f][0]
WARNING: [Synth 8-3331] design pdp11_bram_memctl has unconnected port ADDR[19]
WARNING: [Synth 8-3331] design pdp11_bram_memctl has unconnected port ADDR[18]
WARNING: [Synth 8-3331] design pdp11_bram_memctl has unconnected port ADDR[17]
WARNING: [Synth 8-3331] design pdp11_bram_memctl has unconnected port ADDR[16]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ibdr_dl11__parameterized1 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_dl11__parameterized1 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_dl11__parameterized1 has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design ibdr_dl11__parameterized1 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ibdr_dl11__parameterized1 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ibdr_dl11__parameterized1 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ibdr_dl11__parameterized1 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ibdr_tm11 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_tm11 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_rk11 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_rk11 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_rl11 has unconnected port CE_MSEC
WARNING: [Synth 8-3331] design ibdr_rl11 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_rl11 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_rhrp has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_rhrp has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_deuna has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_deuna has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_deuna has unconnected port EI_ACK
WARNING: [Synth 8-3331] design ibd_kw11p has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibd_kw11p has unconnected port IB_MREQ[be0]
WARNING: [Synth 8-3331] design ibd_kw11p has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design ibd_kw11p has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibd_kw11p has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design ibd_iist has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibd_iist has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design ibd_iist has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design ibd_iist has unconnected port IB_MREQ[din][6]
WARNING: [Synth 8-3331] design ibd_iist has unconnected port IB_MREQ[din][5]
WARNING: [Synth 8-3331] design ibd_iist has unconnected port IB_MREQ[din][4]
WARNING: [Synth 8-3331] design ibd_iist has unconnected port EI_ACK
WARNING: [Synth 8-3331] design ibdr_sdreg has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_sdreg has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_dl11 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_dl11 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_dl11 has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design ibdr_dl11 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ibdr_dl11 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ibdr_dl11 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ibdr_dl11 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][5]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][4]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][3]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][2]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][1]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][0]
WARNING: [Synth 8-3331] design pdp11_dmpcnt has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design pdp11_dmpcnt has unconnected port RB_MREQ[din][14]
WARNING: [Synth 8-3331] design pdp11_dmpcnt has unconnected port RB_MREQ[din][8]
WARNING: [Synth 8-3331] design pdp11_dmpcnt has unconnected port RB_MREQ[din][7]
WARNING: [Synth 8-3331] design pdp11_dmpcnt has unconnected port RB_MREQ[din][6]
WARNING: [Synth 8-3331] design pdp11_dmpcnt has unconnected port RB_MREQ[din][5]
WARNING: [Synth 8-3331] design pdp11_dmpcnt has unconnected port RB_MREQ[din][4]
WARNING: [Synth 8-3331] design pdp11_dmpcnt has unconnected port RB_MREQ[din][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port RB_MREQ[addr][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port RB_MREQ[addr][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port RB_MREQ[addr][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_SE[idle]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_SE[cpbusy]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_SE[idec]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_SE[idone]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_SE[itimer]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_SE[pcload]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_SE[vfetch]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_SE[snum][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_SE[snum][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_SE[snum][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_SE[snum][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_SE[snum][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_SE[snum][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_SE[snum][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_SE[snum][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[pc][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[pc][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[pc][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[pc][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[pc][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[pc][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[pc][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[pc][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[pc][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[pc][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[pc][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[pc][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[pc][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[pc][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[pc][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[pc][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[psw][cmode][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[psw][cmode][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[psw][pmode][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[psw][pmode][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[psw][rset]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[psw][pri][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[psw][pri][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[psw][pri][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[psw][tflag]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[psw][cc][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[psw][cc][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[psw][cc][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[psw][cc][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[psr_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ireg_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dsrc_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[ddst_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dtmp_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dres][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dres][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dres][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dres][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dres][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dres][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dres][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dres][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dres][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dres][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dres][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dres][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dres][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dres][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dres][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[dres][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[cpdout_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[gpr_adst][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[gpr_adst][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[gpr_adst][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[gpr_mode][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[gpr_mode][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[gpr_bytop]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_DP[gpr_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmcntl][macc]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmcntl][bytop]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmcntl][kstack]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmcntl][intrsv]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmcntl][trap_done]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmaddr][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdin][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdin][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdin][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdin][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdin][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdin][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdin][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdin][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdin][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdin][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdin][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdin][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdin][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdin][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdin][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdin][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmstat][ack]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmstat][err]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmstat][fail]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmstat][err_odd]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmstat][err_mmu]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmstat][err_nxm]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmstat][err_iobto]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmstat][err_rsv]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmstat][trap_ysv]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmstat][trap_mmu]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdout][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdout][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdout][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdout][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdout][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdout][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdout][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdout][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdout][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdout][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdout][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdout][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdout][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdout][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdout][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[vmdout][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][aval]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][re]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][rmw]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][be0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][be1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][cacc]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][racc]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][addr][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][addr][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][addr][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][addr][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][addr][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][addr][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][addr][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][addr][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][addr][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][addr][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][addr][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][addr][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][din][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][din][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][din][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][din][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][din][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][din][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][din][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][din][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][din][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][din][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][din][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][din][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][din][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][din][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][din][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibmreq][din][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][ack]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][busy]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][dout][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][dout][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][dout][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][dout][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][dout][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][dout][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][dout][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][dout][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][dout][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][dout][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][dout][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][dout][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][dout][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][dout][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][dout][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[ibsres][dout][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][req]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][be][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][be][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][cancel]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][21]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][20]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][19]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][18]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][17]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][16]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][addr][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][din][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][din][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][din][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][din][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][din][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][din][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][din][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][din][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][din][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][din][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][din][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][din][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][din][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][din][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][din][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emmreq][din][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][ack_r]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][ack_w]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][dout][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][dout][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][dout][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][dout][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][dout][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][dout][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][dout][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][dout][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][dout][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][dout][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][dout][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][dout][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][dout][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][dout][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][dout][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_VM[emsres][dout][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_CO[cpugo]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_CO[cpustep]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_CO[cpususp]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_CO[suspint]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit__parameterized1 has unconnected port DM_STAT_CO[suspext]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port RB_MREQ[addr][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port RB_MREQ[addr][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port RB_MREQ[addr][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_SE[idle]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_SE[cpbusy]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_SE[idec]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_SE[idone]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_SE[itimer]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_SE[pcload]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_SE[vfetch]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_SE[snum][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_SE[snum][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_SE[snum][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_SE[snum][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_SE[snum][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_SE[snum][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_SE[snum][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_SE[snum][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[pc][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[pc][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[pc][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[pc][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[pc][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[pc][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[pc][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[pc][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[pc][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[pc][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[pc][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[pc][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[pc][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[pc][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[pc][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[pc][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[psw][cmode][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[psw][cmode][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[psw][pmode][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[psw][pmode][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[psw][rset]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[psw][pri][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[psw][pri][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[psw][pri][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[psw][tflag]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[psw][cc][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[psw][cc][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[psw][cc][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[psw][cc][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[psr_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ireg_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dsrc_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[ddst_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dtmp_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dres][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dres][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dres][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dres][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dres][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dres][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dres][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dres][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dres][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dres][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dres][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dres][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dres][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dres][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dres][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[dres][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[cpdout_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[gpr_adst][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[gpr_adst][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[gpr_adst][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[gpr_mode][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[gpr_mode][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[gpr_bytop]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_DP[gpr_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmcntl][macc]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmcntl][bytop]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmcntl][kstack]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmcntl][intrsv]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmcntl][trap_done]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmaddr][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdin][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdin][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdin][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdin][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdin][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdin][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdin][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdin][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdin][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdin][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdin][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdin][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdin][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdin][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdin][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdin][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmstat][ack]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmstat][err]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmstat][fail]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmstat][err_odd]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmstat][err_mmu]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmstat][err_nxm]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmstat][err_iobto]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmstat][err_rsv]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmstat][trap_ysv]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmstat][trap_mmu]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdout][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdout][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdout][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdout][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdout][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdout][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdout][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdout][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdout][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdout][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdout][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdout][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdout][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdout][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdout][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[vmdout][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][aval]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][re]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][rmw]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][be0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][be1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][cacc]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][racc]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][addr][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][addr][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][addr][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][addr][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][addr][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][addr][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][addr][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][addr][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][addr][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][addr][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][addr][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][addr][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][din][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][din][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][din][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][din][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][din][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][din][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][din][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][din][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][din][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][din][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][din][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][din][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][din][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][din][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][din][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibmreq][din][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][ack]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][busy]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][dout][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][dout][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][dout][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][dout][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][dout][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][dout][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][dout][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][dout][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][dout][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][dout][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][dout][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][dout][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][dout][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][dout][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][dout][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[ibsres][dout][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][req]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][be][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][be][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][cancel]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][21]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][20]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][19]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][18]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][17]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][16]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][addr][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][din][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][din][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][din][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][din][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][din][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][din][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][din][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][din][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][din][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][din][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][din][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][din][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][din][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][din][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][din][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emmreq][din][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][ack_r]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][ack_w]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][dout][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][dout][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][dout][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][dout][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][dout][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][dout][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][dout][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][dout][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][dout][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][dout][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][dout][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][dout][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][dout][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][dout][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][dout][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_VM[emsres][dout][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_CO[cpugo]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_CO[cpustep]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_CO[cpususp]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_CO[suspint]
WARNING: [Synth 8-3331] design pdp11_dmhbpt_unit has unconnected port DM_STAT_CO[suspext]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][6]
WARNING: [Synth 8-3331] design pdp11_reg70 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design pdp11_reg70 has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design pdp11_reg70 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design pdp11_reg70 has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design pdp11_reg70 has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design pdp11_reg70 has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design pdp11_reg70 has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design pdp11_reg70 has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design pdp11_reg70 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design pdp11_reg70 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design pdp11_reg70 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design pdp11_reg70 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[re]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[we]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[be0]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[din][6]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[din][5]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[din][4]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[din][3]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[din][2]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[din][1]
WARNING: [Synth 8-3331] design ib_sel__parameterized15 has unconnected port IB_MREQ[din][0]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[re]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[we]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[be0]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[din][6]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[din][5]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[din][4]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[din][3]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[din][2]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[din][1]
WARNING: [Synth 8-3331] design ib_sel__parameterized13 has unconnected port IB_MREQ[din][0]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IREG[14]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IREG[13]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IREG[12]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IREG[11]
WARNING: [Synth 8-3331] design pdp11_lunit has unconnected port CCIN[2]
WARNING: [Synth 8-3331] design pdp11_lunit has unconnected port CCIN[1]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[re]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[we]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[be0]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[din][6]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[din][5]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[din][4]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[din][3]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[din][2]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[din][1]
WARNING: [Synth 8-3331] design ib_sel__parameterized11 has unconnected port IB_MREQ[din][0]
WARNING: [Synth 8-3331] design pdp11_psr has unconnected port DIN[10]
WARNING: [Synth 8-3331] design pdp11_psr has unconnected port DIN[9]
WARNING: [Synth 8-3331] design pdp11_psr has unconnected port DIN[8]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[re]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[we]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[be0]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[din][6]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[din][5]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[din][4]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[din][3]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[din][2]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[din][1]
WARNING: [Synth 8-3331] design ib_sel__parameterized9 has unconnected port IB_MREQ[din][0]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[re]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[we]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[be0]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[addr][6]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[addr][5]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[addr][4]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[addr][3]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[addr][2]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[addr][1]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[din][6]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[din][5]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[din][4]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[din][3]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[din][2]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[din][1]
WARNING: [Synth 8-3331] design ib_sel__parameterized7 has unconnected port IB_MREQ[din][0]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[re]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[we]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[be0]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[din][6]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[din][5]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[din][4]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[din][3]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[din][2]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[din][1]
WARNING: [Synth 8-3331] design ib_sel__parameterized5 has unconnected port IB_MREQ[din][0]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[re]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[we]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[be0]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[din][6]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[din][5]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[din][4]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[din][3]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[din][2]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[din][1]
WARNING: [Synth 8-3331] design ib_sel__parameterized3 has unconnected port IB_MREQ[din][0]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[re]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[we]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[be0]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[din][6]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[din][5]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[din][4]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[din][3]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[din][2]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[din][1]
WARNING: [Synth 8-3331] design ib_sel__parameterized1 has unconnected port IB_MREQ[din][0]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[re]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[we]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[be0]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[din][6]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[din][5]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[din][4]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[din][3]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[din][2]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[din][1]
WARNING: [Synth 8-3331] design ib_sel has unconnected port IB_MREQ[din][0]
WARNING: [Synth 8-3331] design pdp11_mmu_ssr12 has unconnected port MONI[idone]
WARNING: [Synth 8-3331] design pdp11_mmu_ssr12 has unconnected port MONI[trace_prev]
WARNING: [Synth 8-3331] design pdp11_mmu_sadr has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design pdp11_mmu_sadr has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design pdp11_mmu_sadr has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design pdp11_mmu has unconnected port CNTL[trap_done]
WARNING: [Synth 8-3331] design pdp11_mmu has unconnected port VADDR[5]
WARNING: [Synth 8-3331] design pdp11_mmu has unconnected port VADDR[4]
WARNING: [Synth 8-3331] design pdp11_mmu has unconnected port VADDR[3]
WARNING: [Synth 8-3331] design pdp11_mmu has unconnected port VADDR[2]
WARNING: [Synth 8-3331] design pdp11_mmu has unconnected port VADDR[1]
WARNING: [Synth 8-3331] design pdp11_mmu has unconnected port VADDR[0]
WARNING: [Synth 8-3331] design pdp11_core_rbus has unconnected port CP_STAT[cmdbusy]
WARNING: [Synth 8-3331] design pdp11_core_rbus has unconnected port CP_STAT[cpuwait]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[re]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[we]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[addr][1]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[addr][0]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][15]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][14]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][13]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][12]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][11]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][10]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][9]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][8]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][7]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][6]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][5]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][4]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][3]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][2]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][1]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][0]
WARNING: [Synth 8-3331] design rlink_sp2c has unconnected port CE_USEC
WARNING: [Synth 8-3331] design rlink_sp2c has unconnected port CE_MSEC
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1341.277 ; gain = 249.531 ; free physical = 1166 ; free virtual = 9205
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:18 ; elapsed = 00:00:19 . Memory (MB): peak = 1341.277 ; gain = 249.531 ; free physical = 1236 ; free virtual = 9261
---------------------------------------------------------------------------------
INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/basys3/basys3_pclk.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/basys3/basys3_pclk.xdc]
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/basys3/basys3_pins.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/basys3/basys3_pins.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/basys3/basys3_pins.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/sys_w11a_b3_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/sys_w11a_b3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RESET'
INFO: [Timing 38-2] Deriving generated clocks [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc:13]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RESET'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXERR'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXERR'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXOVR'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXOVR'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_ABDONE'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_ABDONE'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/sys_w11a_b3_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/sys_w11a_b3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAXON'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAXON'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAESC'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAESC'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXACT'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXACT'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXACT'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXACT'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ABACT'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ABACT'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXOK'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXOK'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXOK'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXOK'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/sys_w11a_b3_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/sys_w11a_b3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIV'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIV'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIVF'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIVF'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/sys_w11a_b3_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/sys_w11a_b3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/RXFIFO'
WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:56]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/RXFIFO'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/TXFIFO'
WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:56]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/TXFIFO'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/sys_w11a_b3_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/sys_w11a_b3_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc]
Completed Processing XDC Constraints

INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 2 instances were transformed.
  MMCME2_BASE => MMCME2_ADV: 1 instances
  PLLE2_BASE => PLLE2_ADV: 1 instances

Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1595.902 ; gain = 0.000 ; free physical = 970 ; free virtual = 8994
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 1595.902 ; gain = 504.156 ; free physical = 1075 ; free virtual = 9103
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tcpg236-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 1595.902 ; gain = 504.156 ; free physical = 1075 ; free virtual = 9103
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
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Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_ABDONE. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 9).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_RESET. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 9).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_RXERR. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 9).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_RXOVR. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 9).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_ABACT. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 12).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_ENAESC. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 12).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_ENAXON. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 12).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_RXACT. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 12).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_RXOK. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 12).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_TXACT. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 12).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_TXOK. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 12).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_CDIV. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 15).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_CDIVF. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 15).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/RXFIFO. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 18).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/TXFIFO. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 18).
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Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 1595.902 ; gain = 504.156 ; free physical = 1076 ; free virtual = 9105
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INFO: [Synth 8-5546] ROM "n[mcnt]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[msec]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[mcnt]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[msec]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[empty]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[full]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'R_LREGS_reg[state]' in module 'rlink_core'
INFO: [Synth 8-802] inferred FSM for state register 'R_BREGS_reg[state]' in module 'rlink_core'
INFO: [Synth 8-5546] ROM "bcnt_end" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "cnt_iszero" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "bto_end" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[doretra]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "n[atocnt]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[nakcode]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "n[nakcode]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[nakcode]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[cmdseen]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "n[rtaddra_red]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[rtaddra_zero]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[rtaddrb_red]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "cnt_end" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "n[anena]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "crcreset" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[rcmd]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[addr]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[cnt]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[anact]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[dinl]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "addrb_sela" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "n[state]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "bto_go" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[rbdout]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "iesc" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'serport_uart_autobaud'
INFO: [Synth 8-5546] ROM "n[state]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "n[seen1]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iact" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'serport_uart_rx'
INFO: [Synth 8-5546] ROM "tc_ccnt" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "tc_bcnt" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[sreg]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iact" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "ld_ccnt" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "n[busy]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-4490] FSM extraction disabled for register 'R_DATA_reg' through user attribute
INFO: [Synth 8-5546] ROM "ival" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ival" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'pdp11_core_rbus'
INFO: [Synth 8-5546] ROM "n[rbselc]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "n[rbseli]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[waitstep]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[doinc]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'pdp11_vmbox'
INFO: [Synth 8-5546] ROM "ato_end" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "ivm_stat[fail]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ivm_stat[err_iobto]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iubmap_mreq" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ato_go" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[paddr_iopage]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[paddr]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "nzo" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "inzstd" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "izo" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "izo" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "izo" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "SHC_TC_L" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "DDST_ZERO" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "DSRC_ZERO" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "DTMP_ZERO" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "DDST_NMAX" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "DSRC_ONES" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "nstat[is_dstmode0]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstat[is_srcpc]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstat[is_srcpcmode1]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstat[is_dstpc]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstat[do_fork_opg]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstat[updt_dstadsrc]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstat[aunit_cc1op]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstat[lunit_func]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstat[res_sel]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstat[fork_opa]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "is_srcmode0" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register 'R_STATE_reg' in module 'pdp11_sequencer'
INFO: [Synth 8-5544] ROM "is_kmode" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "ndpcntl[gpr_we]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[psr_we]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[psr_func]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[ddst_we]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[dtmp_sel]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[dres_sel]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "nvmcntl[req]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "nvmcntl[wacc]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "nstatus[cpustep]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "nmmumoni[isdec]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[ddst_sel]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[ounit_azero]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[ounit_bsel]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[ounit_opsub]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[munit_s_div]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[munit_s_div_cn]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[munit_s_div_cr]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[munit_s_div_sr]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[munit_s_ash]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[munit_s_ash_cn]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[munit_s_ashc]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[munit_s_ashc_cn]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[vmaddr_sel]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idm_idle" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idm_idec" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idm_vfetch" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "isnum_err" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "isnum_vec" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "isnum_ins" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "isnum_con" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "is_kmode" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "ndpcntl[gpr_we]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[psr_we]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[psr_func]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[ddst_we]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[dtmp_sel]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[dres_sel]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "nvmcntl[req]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "nvmcntl[wacc]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "nstatus[cpustep]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "nmmumoni[isdec]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[ddst_sel]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[ounit_azero]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[ounit_bsel]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[ounit_opsub]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[munit_s_div]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[munit_s_div_cn]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[munit_s_div_cr]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[munit_s_div_sr]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[munit_s_ash]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[munit_s_ash_cn]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[munit_s_ashc]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[munit_s_ashc_cn]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ndpcntl[vmaddr_sel]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idm_idle" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idm_idec" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "idm_vfetch" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "isnum_err" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "isnum_vec" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "isnum_ins" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "isnum_con" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "nstate" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Common 17-14] Message 'Synth 8-5544' appears 200 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-5546] ROM "n[ibsel_mbrk]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[ibsel_sysid]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'pdp11_cache'
INFO: [Synth 8-5546] ROM "n[ibsel_cr]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[ibsel_hm]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[ibsel_ls]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "irb_busy" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[rbsel]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[zbusy]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[moni]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "conf_intp[23]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "conf_intv[23]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "tcntsnd_end" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "tcnt256_end" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[stc_tmo]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[done]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[evtline]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'ibdr_rhrp'
INFO: [Synth 8-5546] ROM "n[cs1rdy]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[fxfer]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[runit]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[eunit]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[eunit]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[dsata]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[idlyval]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[poredone]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[packdone]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "iscinc" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[clrreg]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'ibdr_rl11'
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'pdp11_bram_memctl'
INFO: [Synth 8-5546] ROM "n[dcnt]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'sysmon_rbus_core'
INFO: [Synth 8-3971] The signal sv_ram_reg was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 sb_idle |                    0000000000001 |                             0000
               sb_rstart |                    0000000000010 |                             0001
                sb_rreg0 |                    0000000000100 |                             0010
                sb_rreg1 |                    0000000001000 |                             0011
                 sb_rend |                    0000000010000 |                             0101
                sb_rabo1 |                    0000000100000 |                             0111
                sb_rabo0 |                    0000001000000 |                             0110
                sb_rwait |                    0000010000000 |                             0100
               sb_wstart |                    0000100000000 |                             1000
                sb_wreg0 |                    0001000000000 |                             1001
                sb_wreg1 |                    0010000000000 |                             1010
                sb_wabo0 |                    0100000000000 |                             1011
                sb_wabo1 |                    1000000000000 |                             1100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_BREGS_reg[state]' using encoding 'one-hot' in module 'rlink_core'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 sl_idle | 0000000000000000000000000000000000000001 |                           000000
               sl_txanot | 0000000000000000000000000000000000000010 |                           000001
                sl_txsop | 0000000000000000000000000000000000000100 |                           000010
                sl_rxcmd | 0000000000000000000000000000000000001000 |                           001000
              sl_rxaddrl | 0000000000000000000000000000000000010000 |                           001001
              sl_rxaddrh | 0000000000000000000000000000000000100000 |                           001010
               sl_rxdatl | 0000000000000000000000000000000001000000 |                           001011
               sl_rxdath | 0000000000000000000000000000000010000000 |                           001100
               sl_rxcntl | 0000000000000000000000000000000100000000 |                           001101
               sl_rxcnth | 0000000000000000000000000000001000000000 |                           001110
              sl_rxccrcl | 0000000000000000000000000000010000000000 |                           001111
              sl_rxccrch | 0000000000000000000000000000100000000000 |                           010000
                sl_txcmd | 0000000000000000000000000001000000000000 |                           010001
               sl_txlabo | 0000000000000000000000000010000000000000 |                           100011
                 sl_attn | 0000000000000000000000000100000000000000 |                           100100
               sl_txcntl | 0000000000000000000000001000000000000000 |                           010010
               sl_txcnth | 0000000000000000000000010000000000000000 |                           010011
               sl_rstart | 0000000000000000000000100000000000000000 |                           010100
                sl_txdat | 0000000000000000000001000000000000000000 |                           010101
                 sl_wblk | 0000000000000000000010000000000000000000 |                           010110
               sl_rxwblk | 0000000000000000000100000000000000000000 |                           010111
              sl_rxdcrcl | 0000000000000000001000000000000000000000 |                           011000
              sl_rxdcrch | 0000000000000000010000000000000000000000 |                           011001
                sl_wblk0 | 0000000000000000100000000000000000000000 |                           011010
                sl_wblk1 | 0000000000000001000000000000000000000000 |                           011011
                sl_wblk2 | 0000000000000010000000000000000000000000 |                           011100
                sl_wblkl | 0000000000000100000000000000000000000000 |                           011101
                sl_wblkh | 0000000000001000000000000000000000000000 |                           011110
               sl_wwait0 | 0000000000010000000000000000000000000000 |                           011111
               sl_wwait1 | 0000000000100000000000000000000000000000 |                           100000
              sl_txdcntl | 0000000001000000000000000000000000000000 |                           100001
              sl_txdcnth | 0000000010000000000000000000000000000000 |                           100010
               sl_txstat | 0000000100000000000000000000000000000000 |                           100101
               sl_txcrcl | 0000001000000000000000000000000000000000 |                           100110
               sl_txcrch | 0000010000000000000000000000000000000000 |                           100111
              sl_txrtbuf | 0000100000000000000000000000000000000000 |                           000101
                sl_txnak | 0001000000000000000000000000000000000000 |                           000011
            sl_txnakcode | 0010000000000000000000000000000000000000 |                           000100
                sl_rxeop | 0100000000000000000000000000000000000000 |                           000111
                sl_txeop | 1000000000000000000000000000000000000000 |                           000110
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_LREGS_reg[state]' using encoding 'one-hot' in module 'rlink_core'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_idle |                             0001 |                               00
                 s_break |                             0010 |                               01
                  s_wait |                             0100 |                               10
                  s_sync |                             1000 |                               11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'serport_uart_autobaud'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_idle |                          0000001 |                              000
                 s_colb0 |                          0000010 |                              001
                 s_endb0 |                          0000100 |                              010
                 s_colbx |                          0001000 |                              011
                 s_endbx |                          0010000 |                              100
                 s_colb9 |                          0100000 |                              101
                 s_endb9 |                          1000000 |                              110
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'serport_uart_rx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_idle |                              001 |                               00
                s_cpwait |                              010 |                               01
                s_cpstep |                              100 |                               10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'pdp11_core_rbus'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_idle |                      00000000001 |                             0000
                s_errrsv |                      00000000010 |                             1001
                 s_mem_w |                      00000000100 |                             0001
                  s_ib_w |                      00000001000 |                             0010
               s_ib_wend |                      00000010000 |                             0011
               s_ib_rend |                      00000100000 |                             0100
            s_idle_mw_ib |                      00001000000 |                             0101
                 s_errib |                      00010000000 |                             1010
           s_idle_mw_mem |                      00100000000 |                             0110
                  s_fail |                      01000000000 |                             1000
              s_mem_mw_w |                      10000000000 |                             0111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'pdp11_vmbox'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_idle | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001 |                          0000000
            s_cp_regread | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010 |                          0000001
                s_cp_rps | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100 |                          0000010
             s_cp_memr_w | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000 |                          0000011
             s_cp_memw_w | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000 |                          0000100
               s_int_ext | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000 |                          1011111
                s_ifetch | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000 |                          0000101
              s_ifetch_w | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000 |                          0000110
               s_idecode | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000 |                          0000111
               s_op_halt | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000 |                          0101100
             s_rti_getpc | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000 |                          1101010
           s_rti_getpc_w | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000 |                          1101011
             s_rti_getps | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000 |                          1101100
           s_rti_getps_w | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000 |                          1101101
             s_rti_newpc | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000 |                          1101110
               s_op_trap | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000 |                          0101110
              s_op_reset | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000 |                          0101111
                s_op_rts | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000 |                          0110000
            s_op_rts_pop | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000 |                          0110001
          s_op_rts_pop_w | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000 |                          0110010
                s_op_spl | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000 |                          0110011
                s_op_mcc | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000 |                          0110100
                 s_op_br | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000 |                          0110101
               s_op_mark | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000 |                          0110110
              s_op_mark1 | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000 |                          0110111
           s_op_mark_pop | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000 |                          0111000
         s_op_mark_pop_w | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000 |                          0111001
                s_op_sob | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000 |                          0111010
               s_op_sob1 | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000 |                          0111011
               s_opa_mtp | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000 |                          1010001
         s_opa_mtp_pop_w | 00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000 |                          1010010
           s_opa_mtp_reg | 00000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000 |                          1010011
              s_srcr_inc | 00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000 |                          0001010
              s_srcr_dec | 00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000 |                          0001100
             s_srcr_dec1 | 00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000 |                          0001101
            s_srcr_inc_w | 00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000 |                          0001011
              s_srcr_ind | 00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000 |                          0001110
           s_srcr_ind1_w | 00000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000 |                          0001111
             s_srcr_ind2 | 00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000 |                          0010000
           s_srcr_ind2_w | 00000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000 |                          0010001
              s_srcr_def | 00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000 |                          0001000
            s_srcr_def_w | 00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000 |                          0001001
              s_dstr_inc | 00000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000 |                          0010100
              s_dstr_dec | 00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000 |                          0010110
             s_dstr_dec1 | 00000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000 |                          0010111
            s_dstr_inc_w | 00000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000 |                          0010101
              s_dstr_ind | 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000 |                          0011000
           s_dstr_ind1_w | 00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000 |                          0011001
             s_dstr_ind2 | 00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000 |                          0011010
           s_dstr_ind2_w | 00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000 |                          0011011
              s_dstr_def | 00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000 |                          0010010
            s_dstr_def_w | 00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000 |                          0010011
              s_dsta_inc | 00000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000 |                          0100110
              s_dsta_dec | 00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000 |                          0101000
              s_dsta_ind | 00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000 |                          0101010
            s_dsta_ind_w | 00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000 |                          0101011
             s_dsta_dec1 | 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000 |                          0101001
         s_dsta_incdef_w | 00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000 |                          0100111
               s_opa_jmp | 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000 |                          1010000
               s_opa_jsr | 00000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000 |                          1001011
              s_opa_jsr1 | 00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000 |                          1001100
          s_opa_jsr_push | 00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000 |                          1001101
        s_opa_jsr_push_w | 00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000 |                          1001110
              s_opa_jsr2 | 00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000 |                          1001111
           s_opa_mtp_mem | 00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000 |                          1010100
         s_opa_mtp_mem_w | 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000 |                          1010101
           s_opa_mfp_reg | 00000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000 |                          1010110
           s_opa_mfp_mem | 00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000 |                          1010111
         s_opa_mfp_mem_w | 00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000 |                          1011000
           s_opa_mfp_dec | 00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000 |                          1011001
          s_opa_mfp_push | 00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000 |                          1011010
        s_opa_mfp_push_w | 00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000 |                          1011011
               s_opg_gen | 00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000 |                          0111100
         s_opg_gen_rmw_w | 00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000 |                          0111101
              s_dstw_def | 00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000 |                          0011100
              s_dstw_inc | 00000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000 |                          0011110
            s_dstw_inc_w | 00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000 |                          0011111
              s_dstw_dec | 00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000 |                          0100001
              s_dstw_ind | 00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          0100011
            s_dstw_ind_w | 00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          0100100
             s_dstw_dec1 | 00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          0100010
         s_dstw_incdef_w | 00000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          0100000
           s_dstw_def246 | 00000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          0100101
            s_dstw_def_w | 00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          0011101
               s_opg_mul | 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          0111110
              s_opg_mul1 | 00000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          0111111
               s_opg_div | 00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1000000
            s_opg_div_cn | 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1000001
            s_opg_div_cr | 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1000010
            s_opg_div_sq | 00000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1000011
            s_opg_div_sr | 00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1000100
          s_opg_div_quit | 00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1000101
               s_opg_ash | 00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1000110
            s_opg_ash_cn | 00000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1000111
              s_opg_ashc | 00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1001000
           s_opg_ashc_cn | 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1001001
           s_opg_ashc_wl | 00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1001010
               s_trap_10 | 00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1011101
                 s_vmerr | 00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1101111
               s_cpufail | 00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1110000
                s_trap_4 | 00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1011100
             s_int_getpc | 00000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1100000
           s_int_getpc_w | 00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1100001
             s_int_getps | 00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1100010
           s_int_getps_w | 00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1100011
             s_int_getsp | 00000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1100100
             s_int_decsp | 00000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1100101
            s_int_pushps | 00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1100110
          s_int_pushps_w | 00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1100111
            s_int_pushpc | 00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1101000
          s_int_pushpc_w | 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1101001
             s_trap_disp | 01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          1011110
               s_op_wait | 10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 |                          0101101
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_STATE_reg' using encoding 'one-hot' in module 'pdp11_sequencer'
INFO: [Synth 8-3971] The signal sv_ram_reg was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_idle |                             0001 |                               00
                  s_read |                             0010 |                               01
                 s_rmiss |                             0100 |                               10
                 s_write |                             1000 |                               11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'pdp11_cache'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_idle |           0000000000000000000001 |                            00000
                  s_read |           0000000000000000000010 |                            10001
                  s_wcs1 |           0000000000000000000100 |                            00001
               s_funcchk |           0000000000000000001000 |                            01100
                s_funcgo |           0000000000000000010000 |                            01101
                 s_chkdc |           0000000000000000100000 |                            01110
                 s_chkda |           0000000000000001000000 |                            01111
                 s_chkdo |           0000000000000010000000 |                            10000
                s_wmembe |           0000000000000100000000 |                            01010
                  s_wmem |           0000000000001000000000 |                            01001
                  s_wcs2 |           0000000000010000000000 |                            00010
              s_oot_clr0 |           0000000000100000000000 |                            10011
              s_oot_clr1 |           0000000001000000000000 |                            10100
              s_oot_clr2 |           0000000010000000000000 |                            10101
                   s_wds |           0000000100000000000000 |                            00111
                  s_wer1 |           0000001000000000000000 |                            00100
                   s_was |           0000010000000000000000 |                            00101
                   s_wdt |           0000100000000000000000 |                            00110
                   s_whr |           0001000000000000000000 |                            01011
                  s_wbae |           0010000000000000000000 |                            01000
                  s_wcs3 |           0100000000000000000000 |                            00011
                s_setrmr |           1000000000000000000000 |                            10010
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'ibdr_rhrp'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_init |                        000000001 |                             1000
                  s_idle |                        000000010 |                             0000
                s_csread |                        000000100 |                             0001
               s_gs_rpos |                        000001000 |                             0010
                s_gs_sta |                        000010000 |                             0011
             s_seek_rsta |                        000100000 |                             0100
             s_seek_rpos |                        001000000 |                             0101
             s_seek_clip |                        010000000 |                             0110
             s_seek_wpos |                        100000000 |                             0111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'ibdr_rl11'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_idle |                             0001 |                               00
                 s_write |                             0010 |                               11
                 s_read0 |                             0100 |                               01
                 s_read1 |                             1000 |                               10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'pdp11_bram_memctl'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_init |                             0001 |                               00
                  s_idle |                             0010 |                               01
                 s_twait |                             0100 |                               11
                  s_wait |                             1000 |                               10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'sysmon_rbus_core'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:01:06 ; elapsed = 00:01:10 . Memory (MB): peak = 1595.902 ; gain = 504.156 ; free physical = 1071 ; free virtual = 9101
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   3 Input     32 Bit       Adders := 1     
	   2 Input     21 Bit       Adders := 2     
	   2 Input     16 Bit       Adders := 4     
	   3 Input     16 Bit       Adders := 2     
	   2 Input     15 Bit       Adders := 2     
	   2 Input     12 Bit       Adders := 1     
	   2 Input     11 Bit       Adders := 2     
	   2 Input     10 Bit       Adders := 5     
	   3 Input     10 Bit       Adders := 1     
	   3 Input      9 Bit       Adders := 2     
	   2 Input      8 Bit       Adders := 5     
	   2 Input      7 Bit       Adders := 6     
	   2 Input      6 Bit       Adders := 3     
	   2 Input      5 Bit       Adders := 41    
	   3 Input      5 Bit       Adders := 7     
	   2 Input      4 Bit       Adders := 7     
	   2 Input      3 Bit       Adders := 2     
	   2 Input      2 Bit       Adders := 4     
+---XORs : 
	   2 Input     16 Bit         XORs := 1     
	   2 Input      8 Bit         XORs := 2     
	   2 Input      1 Bit         XORs := 79    
	   3 Input      1 Bit         XORs := 2     
	  10 Input      1 Bit         XORs := 4     
+---Registers : 
	               32 Bit    Registers := 4     
	               22 Bit    Registers := 1     
	               21 Bit    Registers := 1     
	               17 Bit    Registers := 1     
	               16 Bit    Registers := 38    
	               15 Bit    Registers := 6     
	               12 Bit    Registers := 4     
	               11 Bit    Registers := 3     
	               10 Bit    Registers := 6     
	                9 Bit    Registers := 15    
	                8 Bit    Registers := 73    
	                7 Bit    Registers := 9     
	                6 Bit    Registers := 7     
	                5 Bit    Registers := 68    
	                4 Bit    Registers := 61    
	                3 Bit    Registers := 22    
	                2 Bit    Registers := 32    
	                1 Bit    Registers := 412   
+---RAMs : 
	              32K Bit         RAMs := 45    
	              18K Bit         RAMs := 5     
+---Muxes : 
	 428 Input    113 Bit        Muxes := 1     
	  94 Input     40 Bit        Muxes := 1     
	   4 Input     32 Bit        Muxes := 1     
	   2 Input     32 Bit        Muxes := 6     
	   2 Input     24 Bit        Muxes := 1     
	   4 Input     22 Bit        Muxes := 1     
	   2 Input     22 Bit        Muxes := 2     
	 120 Input     22 Bit        Muxes := 1     
	  11 Input     21 Bit        Muxes := 1     
	   3 Input     21 Bit        Muxes := 3     
	   2 Input     21 Bit        Muxes := 5     
	   2 Input     17 Bit        Muxes := 1     
	   4 Input     17 Bit        Muxes := 1     
	  40 Input     16 Bit        Muxes := 6     
	   2 Input     16 Bit        Muxes := 92    
	   4 Input     16 Bit        Muxes := 22    
	   5 Input     16 Bit        Muxes := 1     
	   3 Input     16 Bit        Muxes := 1     
	  11 Input     16 Bit        Muxes := 2     
	  23 Input     16 Bit        Muxes := 1     
	  22 Input     16 Bit        Muxes := 2     
	   6 Input     16 Bit        Muxes := 1     
	   9 Input     16 Bit        Muxes := 3     
	   7 Input     16 Bit        Muxes := 1     
	   8 Input     16 Bit        Muxes := 1     
	   4 Input     15 Bit        Muxes := 1     
	   2 Input     15 Bit        Muxes := 1     
	   7 Input     15 Bit        Muxes := 1     
	  24 Input     13 Bit        Muxes := 1     
	  40 Input     12 Bit        Muxes := 1     
	   2 Input     12 Bit        Muxes := 1     
	   2 Input     11 Bit        Muxes := 1     
	  30 Input     11 Bit        Muxes := 1     
	   2 Input     10 Bit        Muxes := 7     
	   8 Input     10 Bit        Muxes := 2     
	   7 Input     10 Bit        Muxes := 1     
	  40 Input      9 Bit        Muxes := 1     
	   2 Input      9 Bit        Muxes := 5     
	   4 Input      9 Bit        Muxes := 3     
	   6 Input      9 Bit        Muxes := 1     
	 113 Input      9 Bit        Muxes := 1     
	  15 Input      9 Bit        Muxes := 1     
	  13 Input      8 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 48    
	   6 Input      8 Bit        Muxes := 4     
	  11 Input      8 Bit        Muxes := 2     
	   9 Input      8 Bit        Muxes := 1     
	   4 Input      8 Bit        Muxes := 4     
	  22 Input      8 Bit        Muxes := 1     
	   7 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 4     
	  18 Input      7 Bit        Muxes := 1     
	   4 Input      7 Bit        Muxes := 1     
	   2 Input      6 Bit        Muxes := 7     
	   4 Input      6 Bit        Muxes := 1     
	   7 Input      6 Bit        Muxes := 2     
	  22 Input      6 Bit        Muxes := 2     
	   2 Input      5 Bit        Muxes := 30    
	   5 Input      5 Bit        Muxes := 1     
	   4 Input      5 Bit        Muxes := 4     
	  23 Input      5 Bit        Muxes := 1     
	   7 Input      5 Bit        Muxes := 2     
	  22 Input      5 Bit        Muxes := 1     
	   8 Input      5 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 150   
	   6 Input      4 Bit        Muxes := 3     
	   4 Input      4 Bit        Muxes := 10    
	   7 Input      4 Bit        Muxes := 10    
	   9 Input      4 Bit        Muxes := 5     
	  15 Input      4 Bit        Muxes := 1     
	 113 Input      4 Bit        Muxes := 1     
	   3 Input      4 Bit        Muxes := 3     
	  11 Input      4 Bit        Muxes := 6     
	  24 Input      4 Bit        Muxes := 1     
	   5 Input      4 Bit        Muxes := 2     
	   8 Input      4 Bit        Muxes := 5     
	  22 Input      4 Bit        Muxes := 21    
	   4 Input      3 Bit        Muxes := 3     
	   2 Input      3 Bit        Muxes := 30    
	  40 Input      3 Bit        Muxes := 1     
	   5 Input      3 Bit        Muxes := 1     
	  11 Input      3 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 2     
	   6 Input      3 Bit        Muxes := 1     
	  13 Input      3 Bit        Muxes := 1     
	   3 Input      3 Bit        Muxes := 1     
	  16 Input      3 Bit        Muxes := 2     
	 113 Input      3 Bit        Muxes := 4     
	  24 Input      3 Bit        Muxes := 1     
	  22 Input      3 Bit        Muxes := 1     
	  10 Input      3 Bit        Muxes := 1     
	   9 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 44    
	   9 Input      2 Bit        Muxes := 1     
	  40 Input      2 Bit        Muxes := 1     
	  11 Input      2 Bit        Muxes := 4     
	   3 Input      2 Bit        Muxes := 5     
	   6 Input      2 Bit        Muxes := 3     
	   4 Input      2 Bit        Muxes := 4     
	  10 Input      2 Bit        Muxes := 3     
	   7 Input      2 Bit        Muxes := 7     
	   8 Input      2 Bit        Muxes := 4     
	  15 Input      2 Bit        Muxes := 2     
	 113 Input      2 Bit        Muxes := 6     
	   5 Input      2 Bit        Muxes := 1     
	  22 Input      2 Bit        Muxes := 3     
	   2 Input      1 Bit        Muxes := 1142  
	   4 Input      1 Bit        Muxes := 179   
	  13 Input      1 Bit        Muxes := 24    
	   5 Input      1 Bit        Muxes := 10    
	   8 Input      1 Bit        Muxes := 19    
	   3 Input      1 Bit        Muxes := 37    
	  40 Input      1 Bit        Muxes := 31    
	   7 Input      1 Bit        Muxes := 47    
	  11 Input      1 Bit        Muxes := 59    
	   6 Input      1 Bit        Muxes := 24    
	  10 Input      1 Bit        Muxes := 2     
	   9 Input      1 Bit        Muxes := 20    
	  15 Input      1 Bit        Muxes := 17    
	 113 Input      1 Bit        Muxes := 72    
	  23 Input      1 Bit        Muxes := 2     
	  22 Input      1 Bit        Muxes := 41    
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics 
---------------------------------------------------------------------------------
Hierarchical RTL Component report 
Module clkdivce 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     10 Bit       Adders := 1     
	   2 Input      7 Bit       Adders := 1     
+---Registers : 
	               10 Bit    Registers := 1     
	                7 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 3     
Module clkdivce__parameterized1 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     10 Bit       Adders := 1     
	   2 Input      7 Bit       Adders := 1     
+---Registers : 
	               10 Bit    Registers := 1     
	                7 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 3     
Module iob_reg_i_gen 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module iob_reg_o_gen 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module ram_2swsr_rfirst_gen 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 2     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module fifo_1c_dram_raw 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      5 Bit       Adders := 2     
	   3 Input      5 Bit       Adders := 1     
+---Registers : 
	                5 Bit    Registers := 2     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 4     
Module crc16 
Detailed RTL Component Info : 
+---XORs : 
	   2 Input      8 Bit         XORs := 1     
	   2 Input      1 Bit         XORs := 14    
	   3 Input      1 Bit         XORs := 1     
+---Registers : 
	               16 Bit    Registers := 1     
Module rb_sel 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rlink_core 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     11 Bit       Adders := 2     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      7 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 5     
	               11 Bit    Registers := 2     
	                8 Bit    Registers := 5     
	                7 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 26    
+---Muxes : 
	  94 Input     40 Bit        Muxes := 1     
	  40 Input     16 Bit        Muxes := 6     
	   2 Input     16 Bit        Muxes := 1     
	   4 Input     16 Bit        Muxes := 1     
	  24 Input     13 Bit        Muxes := 1     
	  40 Input     12 Bit        Muxes := 1     
	   2 Input     11 Bit        Muxes := 1     
	  40 Input      9 Bit        Muxes := 1     
	  13 Input      8 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	  40 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   9 Input      2 Bit        Muxes := 1     
	  40 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 41    
	   4 Input      1 Bit        Muxes := 3     
	  13 Input      1 Bit        Muxes := 22    
	   5 Input      1 Bit        Muxes := 2     
	   8 Input      1 Bit        Muxes := 2     
	   3 Input      1 Bit        Muxes := 1     
	  40 Input      1 Bit        Muxes := 31    
Module byte2cdata 
Detailed RTL Component Info : 
+---Registers : 
	                9 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input      9 Bit        Muxes := 4     
	   4 Input      9 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 5     
Module cdata2byte 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 1     
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input      8 Bit        Muxes := 3     
	   2 Input      3 Bit        Muxes := 4     
	   5 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 6     
	   5 Input      1 Bit        Muxes := 1     
Module cdc_pulse 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 5     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module cdc_signal_s1 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
Module serport_uart_autobaud 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     15 Bit       Adders := 1     
	   2 Input      7 Bit       Adders := 1     
+---Registers : 
	               15 Bit    Registers := 1     
	                7 Bit    Registers := 1     
	                1 Bit    Registers := 1     
+---Muxes : 
	   4 Input     15 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 5     
Module serport_uart_rx 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      4 Bit       Adders := 1     
+---Registers : 
	                8 Bit    Registers := 1     
	                4 Bit    Registers := 1     
+---Muxes : 
	  18 Input      7 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 12    
	   7 Input      1 Bit        Muxes := 8     
Module serport_uart_tx 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     12 Bit       Adders := 1     
	   2 Input      4 Bit       Adders := 1     
+---Registers : 
	               12 Bit    Registers := 1     
	                9 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                1 Bit    Registers := 1     
+---Muxes : 
	   2 Input     12 Bit        Muxes := 1     
	   2 Input      9 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 6     
Module serport_xonrx 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 4     
+---Muxes : 
	   2 Input      8 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 9     
	   5 Input      1 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 1     
Module serport_xontx 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 2     
	                1 Bit    Registers := 5     
+---Muxes : 
	   2 Input      8 Bit        Muxes := 6     
	   6 Input      8 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 2     
	   5 Input      5 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 20    
Module gray_cnt_5 
Detailed RTL Component Info : 
+---Registers : 
	                5 Bit    Registers := 1     
Module gray2bin_gen 
Detailed RTL Component Info : 
+---XORs : 
	   2 Input      1 Bit         XORs := 4     
Module fifo_2c_dram2 
Detailed RTL Component Info : 
+---Adders : 
	   3 Input      5 Bit       Adders := 2     
+---Registers : 
	                5 Bit    Registers := 6     
	                1 Bit    Registers := 12    
+---Muxes : 
	   2 Input      1 Bit        Muxes := 6     
Module cdc_vector_s0 
Detailed RTL Component Info : 
+---Registers : 
	               12 Bit    Registers := 1     
Module cdc_vector_s0__parameterized1 
Detailed RTL Component Info : 
+---Registers : 
	                3 Bit    Registers := 1     
Module cdc_pulse__parameterized1 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 7     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module serport_2clock2 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 2     
Module pdp11_core_rbus 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     21 Bit       Adders := 1     
+---Registers : 
	               21 Bit    Registers := 1     
	                5 Bit    Registers := 1     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 10    
+---Muxes : 
	  11 Input     21 Bit        Muxes := 1     
	   3 Input     21 Bit        Muxes := 3     
	   2 Input     21 Bit        Muxes := 5     
	   5 Input     16 Bit        Muxes := 1     
	   2 Input     16 Bit        Muxes := 3     
	   3 Input     16 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 1     
	  11 Input      3 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	  11 Input      2 Bit        Muxes := 1     
	   3 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 10    
	  11 Input      1 Bit        Muxes := 10    
	   3 Input      1 Bit        Muxes := 10    
Module pdp11_mmu_sadr 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
	   2 Input      6 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module ib_sel 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module ib_sel__parameterized1 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module pdp11_mmu_ssr12 
Detailed RTL Component Info : 
+---Adders : 
	   3 Input      5 Bit       Adders := 2     
	   2 Input      5 Bit       Adders := 2     
+---Registers : 
	               16 Bit    Registers := 1     
	                5 Bit    Registers := 2     
	                3 Bit    Registers := 2     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
	   2 Input      5 Bit        Muxes := 6     
	   2 Input      3 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 4     
Module ib_sel__parameterized3 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module ib_sel__parameterized5 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module pdp11_mmu 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     16 Bit       Adders := 1     
+---Registers : 
	                3 Bit    Registers := 1     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 14    
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 9     
	   7 Input      1 Bit        Muxes := 5     
	   4 Input      1 Bit        Muxes := 1     
Module ib_sel__parameterized7 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module pdp11_ubmap 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     21 Bit       Adders := 1     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
	   2 Input      5 Bit        Muxes := 1     
Module ib_sel__parameterized9 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module pdp11_vmbox 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      6 Bit       Adders := 1     
+---Registers : 
	               22 Bit    Registers := 1     
	               16 Bit    Registers := 2     
	                9 Bit    Registers := 1     
	                8 Bit    Registers := 1     
	                6 Bit    Registers := 1     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 13    
+---Muxes : 
	   4 Input     22 Bit        Muxes := 1     
	   2 Input     22 Bit        Muxes := 2     
	  11 Input     16 Bit        Muxes := 2     
	   2 Input     16 Bit        Muxes := 1     
	  30 Input     11 Bit        Muxes := 1     
	   6 Input      9 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 6     
	  11 Input      8 Bit        Muxes := 1     
	   2 Input      6 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
	   3 Input      2 Bit        Muxes := 2     
	   2 Input      2 Bit        Muxes := 4     
	  11 Input      2 Bit        Muxes := 3     
	   2 Input      1 Bit        Muxes := 16    
	  11 Input      1 Bit        Muxes := 27    
Module pdp11_gpr 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     15 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 1     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 4     
	   2 Input      8 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 4     
Module ib_sel__parameterized11 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module pdp11_psr 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 1     
	                3 Bit    Registers := 1     
	                2 Bit    Registers := 2     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 4     
	   6 Input      4 Bit        Muxes := 1     
	   6 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 2     
	   6 Input      2 Bit        Muxes := 2     
	   2 Input      2 Bit        Muxes := 4     
	   6 Input      1 Bit        Muxes := 4     
	   2 Input      1 Bit        Muxes := 15    
Module pdp11_ounit 
Detailed RTL Component Info : 
+---Adders : 
	   3 Input     16 Bit       Adders := 1     
	   2 Input     16 Bit       Adders := 1     
+---Muxes : 
	   4 Input     16 Bit        Muxes := 2     
	   2 Input     16 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
Module pdp11_aunit 
Detailed RTL Component Info : 
+---Adders : 
	   3 Input      9 Bit       Adders := 2     
+---XORs : 
	   2 Input      1 Bit         XORs := 3     
+---Muxes : 
	   4 Input     16 Bit        Muxes := 2     
	   4 Input      1 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 10    
	   7 Input      1 Bit        Muxes := 1     
Module pdp11_lunit 
Detailed RTL Component Info : 
+---XORs : 
	   2 Input     16 Bit         XORs := 1     
	   2 Input      1 Bit         XORs := 8     
+---Muxes : 
	   4 Input     16 Bit        Muxes := 1     
	   2 Input     16 Bit        Muxes := 3     
	   5 Input      1 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 9     
	   4 Input      1 Bit        Muxes := 2     
	   8 Input      1 Bit        Muxes := 2     
	   3 Input      1 Bit        Muxes := 1     
Module pdp11_munit 
Detailed RTL Component Info : 
+---Adders : 
	   3 Input     16 Bit       Adders := 1     
	   2 Input     16 Bit       Adders := 1     
	   2 Input      6 Bit       Adders := 1     
+---XORs : 
	   2 Input      1 Bit         XORs := 7     
+---Registers : 
	               16 Bit    Registers := 1     
	                6 Bit    Registers := 1     
	                1 Bit    Registers := 8     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 3     
	   4 Input     16 Bit        Muxes := 2     
	   2 Input      6 Bit        Muxes := 1     
	   4 Input      4 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 3     
	   4 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 28    
Module pdp11_dpath 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 5     
+---Muxes : 
	   4 Input     16 Bit        Muxes := 2     
	   2 Input     16 Bit        Muxes := 2     
Module pdp11_decode 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      4 Bit        Muxes := 14    
	   7 Input      4 Bit        Muxes := 3     
	   9 Input      4 Bit        Muxes := 1     
	  13 Input      3 Bit        Muxes := 1     
	   8 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 6     
	   3 Input      3 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 2     
	  10 Input      2 Bit        Muxes := 3     
	   2 Input      2 Bit        Muxes := 14    
	   7 Input      2 Bit        Muxes := 7     
	   8 Input      2 Bit        Muxes := 2     
	   4 Input      2 Bit        Muxes := 1     
	   3 Input      2 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 65    
	   3 Input      1 Bit        Muxes := 11    
	   8 Input      1 Bit        Muxes := 4     
	   7 Input      1 Bit        Muxes := 12    
	  10 Input      1 Bit        Muxes := 2     
	   9 Input      1 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 1     
Module ib_sel__parameterized13 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module pdp11_sequencer 
Detailed RTL Component Info : 
+---XORs : 
	   2 Input      1 Bit         XORs := 1     
+---Registers : 
	                7 Bit    Registers := 1     
	                5 Bit    Registers := 1     
	                4 Bit    Registers := 3     
	                3 Bit    Registers := 5     
	                2 Bit    Registers := 6     
	                1 Bit    Registers := 45    
+---Muxes : 
	 428 Input    113 Bit        Muxes := 1     
	   2 Input     16 Bit        Muxes := 1     
	 113 Input      9 Bit        Muxes := 1     
	   9 Input      8 Bit        Muxes := 1     
	   2 Input      6 Bit        Muxes := 1     
	  15 Input      4 Bit        Muxes := 1     
	 113 Input      4 Bit        Muxes := 1     
	   3 Input      4 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 5     
	  16 Input      3 Bit        Muxes := 2     
	 113 Input      3 Bit        Muxes := 4     
	   2 Input      2 Bit        Muxes := 4     
	  15 Input      2 Bit        Muxes := 2     
	 113 Input      2 Bit        Muxes := 6     
	   2 Input      1 Bit        Muxes := 59    
	  15 Input      1 Bit        Muxes := 17    
	   3 Input      1 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 1     
	 113 Input      1 Bit        Muxes := 72    
Module ib_sel__parameterized15 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module pdp11_irq 
Detailed RTL Component Info : 
+---Registers : 
	                7 Bit    Registers := 1     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 1     
Module pdp11_reg70 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 2     
Module ram_2swsr_rfirst_gen__parameterized1 
Detailed RTL Component Info : 
+---Registers : 
	                9 Bit    Registers := 2     
+---RAMs : 
	              18K Bit         RAMs := 1     
Module pdp11_cache 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
	               11 Bit    Registers := 1     
	                9 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                1 Bit    Registers := 1     
+---Muxes : 
	   4 Input     32 Bit        Muxes := 1     
	   4 Input     16 Bit        Muxes := 1     
	   4 Input      9 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 7     
	   4 Input      4 Bit        Muxes := 4     
	   9 Input      4 Bit        Muxes := 1     
	   4 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 5     
	   4 Input      1 Bit        Muxes := 12    
Module pdp11_mem70 
Detailed RTL Component Info : 
+---Registers : 
	                6 Bit    Registers := 1     
	                2 Bit    Registers := 2     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   2 Input      6 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 4     
Module pdp11_dmhbpt_unit 
Detailed RTL Component Info : 
+---Registers : 
	               15 Bit    Registers := 2     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 7     
+---Muxes : 
	   4 Input     16 Bit        Muxes := 1     
	   2 Input     16 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 5     
	   2 Input      1 Bit        Muxes := 4     
Module pdp11_dmhbpt_unit__parameterized1 
Detailed RTL Component Info : 
+---Registers : 
	               15 Bit    Registers := 2     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 7     
+---Muxes : 
	   4 Input     16 Bit        Muxes := 1     
	   2 Input     16 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 5     
	   2 Input      1 Bit        Muxes := 4     
Module pdp11_dmpcnt_precnt 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      5 Bit       Adders := 1     
+---Registers : 
	                5 Bit    Registers := 1     
Module pdp11_dmpcnt 
Detailed RTL Component Info : 
+---Adders : 
	   3 Input     32 Bit       Adders := 1     
	   2 Input      5 Bit       Adders := 3     
+---Registers : 
	               32 Bit    Registers := 2     
	                5 Bit    Registers := 2     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	   2 Input     16 Bit        Muxes := 2     
	   4 Input     16 Bit        Muxes := 1     
	   4 Input      5 Bit        Muxes := 4     
	   2 Input      5 Bit        Muxes := 5     
	   2 Input      1 Bit        Muxes := 21    
	   7 Input      1 Bit        Muxes := 2     
	   4 Input      1 Bit        Muxes := 17    
Module pdp11_sys70 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     32 Bit        Muxes := 4     
	   2 Input      6 Bit        Muxes := 2     
	   4 Input      6 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 1     
Module ibd_kw11l 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      5 Bit       Adders := 1     
+---Registers : 
	                5 Bit    Registers := 1     
	                1 Bit    Registers := 4     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 3     
	   2 Input      1 Bit        Muxes := 6     
Module ibdr_dl11 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     10 Bit       Adders := 1     
+---Registers : 
	               10 Bit    Registers := 1     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 10    
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
	   4 Input     16 Bit        Muxes := 1     
	   2 Input     10 Bit        Muxes := 3     
	   8 Input     10 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   2 Input      2 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 14    
	   2 Input      1 Bit        Muxes := 48    
Module ibdr_sdreg 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 4     
Module ib_intmap24 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     24 Bit        Muxes := 1     
	  24 Input      3 Bit        Muxes := 1     
Module ibd_iist 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      8 Bit       Adders := 3     
	   2 Input      4 Bit       Adders := 1     
+---XORs : 
	  10 Input      1 Bit         XORs := 4     
+---Registers : 
	                8 Bit    Registers := 3     
	                4 Bit    Registers := 15    
	                2 Bit    Registers := 2     
	                1 Bit    Registers := 21    
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 6     
	  11 Input      8 Bit        Muxes := 1     
	   4 Input      8 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 63    
	  11 Input      4 Bit        Muxes := 6     
	   4 Input      4 Bit        Muxes := 2     
	   6 Input      2 Bit        Muxes := 1     
	   4 Input      2 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 393   
	  11 Input      1 Bit        Muxes := 22    
	   4 Input      1 Bit        Muxes := 6     
Module ibd_kw11p 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     16 Bit       Adders := 1     
	   2 Input      5 Bit       Adders := 1     
	   2 Input      4 Bit       Adders := 2     
+---Registers : 
	               16 Bit    Registers := 2     
	                5 Bit    Registers := 1     
	                4 Bit    Registers := 2     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 14    
+---Muxes : 
	   2 Input     16 Bit        Muxes := 7     
	   4 Input     16 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 3     
	   2 Input      4 Bit        Muxes := 6     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 44    
	   4 Input      1 Bit        Muxes := 8     
	   3 Input      1 Bit        Muxes := 1     
Module ibdr_deuna 
Detailed RTL Component Info : 
+---Registers : 
	               17 Bit    Registers := 1     
	                4 Bit    Registers := 3     
	                1 Bit    Registers := 21    
+---Muxes : 
	   2 Input     17 Bit        Muxes := 1     
	   4 Input     17 Bit        Muxes := 1     
	   2 Input     16 Bit        Muxes := 2     
	   4 Input     16 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 20    
	   2 Input      1 Bit        Muxes := 24    
Module ibdr_rhrp 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      8 Bit       Adders := 1     
	   2 Input      7 Bit       Adders := 1     
	   2 Input      6 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 1     
	               10 Bit    Registers := 1     
	                8 Bit    Registers := 2     
	                7 Bit    Registers := 1     
	                6 Bit    Registers := 4     
	                5 Bit    Registers := 3     
	                4 Bit    Registers := 19    
	                3 Bit    Registers := 1     
	                2 Bit    Registers := 5     
	                1 Bit    Registers := 22    
+---Muxes : 
	 120 Input     22 Bit        Muxes := 1     
	   2 Input     16 Bit        Muxes := 1     
	  23 Input     16 Bit        Muxes := 1     
	  22 Input     16 Bit        Muxes := 2     
	   7 Input     10 Bit        Muxes := 1     
	  22 Input      8 Bit        Muxes := 1     
	   7 Input      6 Bit        Muxes := 2     
	  22 Input      6 Bit        Muxes := 2     
	   2 Input      5 Bit        Muxes := 3     
	  23 Input      5 Bit        Muxes := 1     
	   7 Input      5 Bit        Muxes := 1     
	  22 Input      5 Bit        Muxes := 1     
	   9 Input      4 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 32    
	  24 Input      4 Bit        Muxes := 1     
	   3 Input      4 Bit        Muxes := 2     
	   5 Input      4 Bit        Muxes := 1     
	   8 Input      4 Bit        Muxes := 5     
	  22 Input      4 Bit        Muxes := 21    
	  22 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 6     
	   5 Input      2 Bit        Muxes := 1     
	   8 Input      2 Bit        Muxes := 2     
	  22 Input      2 Bit        Muxes := 3     
	   2 Input      1 Bit        Muxes := 24    
	   8 Input      1 Bit        Muxes := 5     
	   3 Input      1 Bit        Muxes := 1     
	   7 Input      1 Bit        Muxes := 1     
	  23 Input      1 Bit        Muxes := 2     
	   5 Input      1 Bit        Muxes := 4     
	  13 Input      1 Bit        Muxes := 2     
	   9 Input      1 Bit        Muxes := 2     
	  22 Input      1 Bit        Muxes := 41    
Module ibdr_rl11 
Detailed RTL Component Info : 
+---Adders : 
	   3 Input     10 Bit       Adders := 1     
	   2 Input     10 Bit       Adders := 1     
	   2 Input      4 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 1     
	               10 Bit    Registers := 1     
	                9 Bit    Registers := 1     
	                5 Bit    Registers := 1     
	                4 Bit    Registers := 2     
	                3 Bit    Registers := 2     
	                2 Bit    Registers := 2     
	                1 Bit    Registers := 9     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 6     
	   4 Input     16 Bit        Muxes := 2     
	   6 Input     16 Bit        Muxes := 1     
	   9 Input     16 Bit        Muxes := 3     
	   2 Input     10 Bit        Muxes := 1     
	   4 Input      9 Bit        Muxes := 1     
	  15 Input      9 Bit        Muxes := 1     
	   7 Input      5 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 6     
	   4 Input      4 Bit        Muxes := 2     
	   6 Input      4 Bit        Muxes := 1     
	   9 Input      4 Bit        Muxes := 2     
	  10 Input      3 Bit        Muxes := 1     
	   9 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 44    
	   4 Input      1 Bit        Muxes := 24    
	   3 Input      1 Bit        Muxes := 6     
	   7 Input      1 Bit        Muxes := 1     
	   9 Input      1 Bit        Muxes := 17    
Module ibdr_rk11 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      4 Bit       Adders := 1     
	   2 Input      3 Bit       Adders := 1     
+---Registers : 
	                8 Bit    Registers := 2     
	                4 Bit    Registers := 1     
	                3 Bit    Registers := 4     
	                1 Bit    Registers := 12    
+---Muxes : 
	   2 Input     16 Bit        Muxes := 3     
	   6 Input      8 Bit        Muxes := 3     
	   2 Input      8 Bit        Muxes := 14    
	   2 Input      4 Bit        Muxes := 5     
	   6 Input      4 Bit        Muxes := 1     
	   6 Input      1 Bit        Muxes := 20    
	   2 Input      1 Bit        Muxes := 17    
	   3 Input      1 Bit        Muxes := 1     
	   8 Input      1 Bit        Muxes := 1     
Module ibdr_tm11 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
	               15 Bit    Registers := 1     
	                4 Bit    Registers := 6     
	                3 Bit    Registers := 1     
	                2 Bit    Registers := 4     
	                1 Bit    Registers := 12    
+---Muxes : 
	   2 Input     16 Bit        Muxes := 4     
	   7 Input     16 Bit        Muxes := 1     
	   2 Input     15 Bit        Muxes := 1     
	   7 Input     15 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
	   7 Input      4 Bit        Muxes := 6     
	   7 Input      1 Bit        Muxes := 11    
	   2 Input      1 Bit        Muxes := 24    
	   3 Input      1 Bit        Muxes := 4     
Module ibdr_dl11__parameterized1 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     10 Bit       Adders := 1     
+---Registers : 
	               10 Bit    Registers := 1     
	                8 Bit    Registers := 2     
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 10    
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
	   4 Input     16 Bit        Muxes := 1     
	   2 Input     10 Bit        Muxes := 3     
	   8 Input     10 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	   2 Input      2 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 14    
	   2 Input      1 Bit        Muxes := 48    
Module ibdr_pc11 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 2     
	                1 Bit    Registers := 10    
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
	   4 Input     16 Bit        Muxes := 1     
	   4 Input      8 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 17    
	   2 Input      1 Bit        Muxes := 28    
Module ibdr_lp11 
Detailed RTL Component Info : 
+---Registers : 
	                7 Bit    Registers := 1     
	                1 Bit    Registers := 5     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 3     
	   2 Input      1 Bit        Muxes := 18    
Module ram_1swsr_wfirst_gen 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module pdp11_bram_memctl 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 2     
	               16 Bit    Registers := 1     
	               12 Bit    Registers := 1     
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 2     
	   4 Input      4 Bit        Muxes := 1     
	   5 Input      4 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 5     
Module pdp11_statleds 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input      8 Bit        Muxes := 3     
	   4 Input      8 Bit        Muxes := 1     
Module pdp11_ledmux 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
Module pdp11_dspmux 
Detailed RTL Component Info : 
+---Muxes : 
	   4 Input     16 Bit        Muxes := 1     
Module iob_reg_o_gen__parameterized1 
Detailed RTL Component Info : 
+---Registers : 
	                4 Bit    Registers := 1     
Module iob_reg_o_gen__parameterized3 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 1     
Module iob_reg_i_gen__parameterized1 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
Module iob_reg_i_gen__parameterized3 
Detailed RTL Component Info : 
+---Registers : 
	                5 Bit    Registers := 1     
Module iob_reg_o_gen__parameterized5 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
Module debounce_gen 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 3     
	                2 Bit    Registers := 1     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 5     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module debounce_gen__parameterized1 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                5 Bit    Registers := 3     
	                2 Bit    Registers := 1     
+---Muxes : 
	   2 Input      5 Bit        Muxes := 5     
	   2 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 2     
Module sn_7segctl 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      7 Bit       Adders := 1     
	   2 Input      2 Bit       Adders := 1     
+---Registers : 
	                7 Bit    Registers := 1     
	                2 Bit    Registers := 1     
+---Muxes : 
	   2 Input      4 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 4     
Module sn_humanio_rbus 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 7     
	                5 Bit    Registers := 2     
	                4 Bit    Registers := 2     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 5     
	   8 Input     16 Bit        Muxes := 1     
	   8 Input      5 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
	   8 Input      1 Bit        Muxes := 5     
	   2 Input      1 Bit        Muxes := 1     
Module rb_sel__parameterized1 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rbd_usracc 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     16 Bit        Muxes := 3     
Module sysmon_rbus_core 
Detailed RTL Component Info : 
+---Registers : 
	               12 Bit    Registers := 1     
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 4     
	   7 Input      8 Bit        Muxes := 1     
	   4 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 2     
	   4 Input      7 Bit        Muxes := 1     
	   7 Input      4 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 23    
	   7 Input      1 Bit        Muxes := 6     
	   4 Input      1 Bit        Muxes := 13    
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 90 (col length:60)
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-5546] ROM "DIV_CLK0/n[mcnt]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "DIV_CLK0/n[msec]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "DIV_CLK1/n[mcnt]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "DIV_CLK1/n[msec]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/RL/bto_end" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/RL/cnt_end" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/RL/n[rtaddra_red]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/RL/n[rtaddra_zero]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/RL/bcnt_end" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/RL/cnt_iszero" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/RL/n[atocnt]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/RL/n[rtaddrb_red]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/B2CD/iesc" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "SERPORT/UART/AB/n[state]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "SERPORT/UART/RXTX/RX/tc_ccnt" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[rbselc]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "nzo" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "izo" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "DDST_NMAX" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "DDST_ZERO" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "DTMP_ZERO" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "DSRC_ZERO" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "DSRC_ONES" won't be mapped to RAM because it is too sparse
DSP Report: Generating DSP DOUT0, operation Mode is: A*B.
DSP Report: operator DOUT0 is absorbed into DSP DOUT0.
WARNING: [Synth 8-115] binding instance 'i_10' in module 'partition' to reference 'logic__3780' which has no pins
INFO: [Synth 8-5546] ROM "REG70/n[ibsel_sysid]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "REG70/n[ibsel_mbrk]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[ibsel_cr]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[ibsel_hm]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[ibsel_ls]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[rbsel]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "tcnt256_end" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[stc_tmo]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "tcntsnd_end" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[done]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "iscinc" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[dsata]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "HIO/DRV/n[dcnt]" won't be mapped to RAM because it is too sparse
WARNING: [Synth 8-3331] design sysmonx_rbus_base has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][15]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][14]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][13]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][12]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][11]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][10]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][9]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][8]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][7]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][6]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][5]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][4]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][3]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][2]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][1]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][0]
WARNING: [Synth 8-3331] design sn_humanio_rbus has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port CP_STAT[cmdack]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port CP_STAT[cmderr]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port CP_STAT[cmdmerr]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port CP_STAT[cpustep]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port CP_STAT[cpususp]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port CP_STAT[suspint]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port CP_STAT[suspext]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port DM_STAT_EXP[dp_psw][pmode][1]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port DM_STAT_EXP[dp_psw][pmode][0]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port DM_STAT_EXP[dp_psw][rset]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port DM_STAT_EXP[dp_psw][tflag]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port DM_STAT_EXP[dp_psw][cc][3]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port DM_STAT_EXP[dp_psw][cc][2]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port DM_STAT_EXP[dp_psw][cc][1]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port DM_STAT_EXP[dp_psw][cc][0]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port DM_STAT_EXP[se_idec]
WARNING: [Synth 8-3331] design pdp11_hio70 has unconnected port DM_STAT_EXP[se_itimer]
WARNING: [Synth 8-3331] design pdp11_bram_memctl has unconnected port ADDR[19]
WARNING: [Synth 8-3331] design pdp11_bram_memctl has unconnected port ADDR[18]
WARNING: [Synth 8-3331] design pdp11_bram_memctl has unconnected port ADDR[17]
WARNING: [Synth 8-3331] design pdp11_bram_memctl has unconnected port ADDR[16]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ibdr_lp11 has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ibdr_pc11 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ibdr_tm11 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_tm11 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_rk11 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_rk11 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_rl11 has unconnected port CE_MSEC
WARNING: [Synth 8-3331] design ibdr_rl11 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_rl11 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_rhrp has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_rhrp has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_deuna has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_deuna has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibdr_deuna has unconnected port EI_ACK
WARNING: [Synth 8-3331] design ibd_kw11p has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibd_kw11p has unconnected port IB_MREQ[be0]
WARNING: [Synth 8-3331] design ibd_kw11p has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design ibd_kw11p has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibd_kw11p has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design ibd_iist has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibd_iist has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design ibd_iist has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design ibd_iist has unconnected port IB_MREQ[din][6]
WARNING: [Synth 8-3331] design ibd_iist has unconnected port IB_MREQ[din][5]
WARNING: [Synth 8-3331] design ibd_iist has unconnected port IB_MREQ[din][4]
WARNING: [Synth 8-3331] design ibd_iist has unconnected port EI_ACK
WARNING: [Synth 8-3331] design ibdr_sdreg has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibdr_sdreg has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][5]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][4]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][3]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][2]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][1]
WARNING: [Synth 8-3331] design ibd_kw11l has unconnected port IB_MREQ[din][0]
WARNING: [Synth 8-3331] design pdp11_dmpcnt has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port RB_MREQ[addr][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port RB_MREQ[addr][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port RB_MREQ[addr][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_SE[idle]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_SE[cpbusy]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_SE[idec]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_SE[idone]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_SE[itimer]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_SE[pcload]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_SE[vfetch]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_SE[snum][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_SE[snum][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_SE[snum][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_SE[snum][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_SE[snum][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_SE[snum][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_SE[snum][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_SE[snum][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[pc][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[pc][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[pc][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[pc][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[pc][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[pc][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[pc][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[pc][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[pc][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[pc][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[pc][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[pc][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[pc][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[pc][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[pc][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[pc][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[psw][cmode][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[psw][cmode][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[psw][pmode][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[psw][pmode][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[psw][rset]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[psw][pri][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[psw][pri][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[psw][pri][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[psw][tflag]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[psw][cc][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[psw][cc][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[psw][cc][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[psw][cc][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[psr_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ireg_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dsrc_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[ddst_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dtmp_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dres][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dres][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dres][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dres][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dres][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dres][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dres][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dres][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dres][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dres][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dres][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dres][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dres][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dres][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dres][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[dres][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[cpdout_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[gpr_adst][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[gpr_adst][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[gpr_adst][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[gpr_mode][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[gpr_mode][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[gpr_bytop]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_DP[gpr_we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmcntl][macc]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmcntl][bytop]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmcntl][kstack]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmcntl][intrsv]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmcntl][trap_done]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmaddr][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdin][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdin][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdin][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdin][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdin][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdin][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdin][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdin][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdin][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdin][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdin][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdin][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdin][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdin][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdin][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdin][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmstat][ack]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmstat][err]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmstat][fail]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmstat][err_odd]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmstat][err_mmu]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmstat][err_nxm]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmstat][err_iobto]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmstat][err_rsv]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmstat][trap_ysv]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmstat][trap_mmu]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdout][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdout][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdout][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdout][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdout][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdout][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdout][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdout][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdout][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdout][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdout][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdout][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdout][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdout][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdout][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[vmdout][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][aval]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][re]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][rmw]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][be0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][be1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][cacc]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][racc]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][addr][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][addr][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][addr][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][addr][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][addr][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][addr][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][addr][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][addr][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][addr][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][addr][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][addr][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][addr][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][din][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][din][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][din][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][din][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][din][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][din][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][din][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][din][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][din][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][din][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][din][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][din][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][din][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][din][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][din][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibmreq][din][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][ack]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][busy]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][dout][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][dout][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][dout][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][dout][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][dout][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][dout][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][dout][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][dout][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][dout][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][dout][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][dout][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][dout][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][dout][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][dout][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][dout][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[ibsres][dout][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][req]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][we]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][be][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][be][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][cancel]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][21]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][20]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][19]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][18]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][17]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][16]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][addr][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][din][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][din][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][din][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][din][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][din][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][din][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][din][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][din][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][din][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][din][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][din][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][din][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][din][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][din][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][din][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emmreq][din][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][ack_r]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][ack_w]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][dout][15]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][dout][14]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][dout][13]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][dout][12]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][dout][11]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][dout][10]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][dout][9]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][dout][8]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][dout][7]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][dout][6]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][dout][5]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][dout][4]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][dout][3]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][dout][2]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][dout][1]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_VM[emsres][dout][0]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_CO[cpugo]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_CO[cpustep]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_CO[cpususp]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_CO[suspint]
WARNING: [Synth 8-3331] design pdp11_dmhbpt has unconnected port DM_STAT_CO[suspext]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design pdp11_mem70 has unconnected port IB_MREQ[din][6]
WARNING: [Synth 8-3331] design pdp11_irq has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design pdp11_irq has unconnected port IB_MREQ[be0]
WARNING: [Synth 8-3331] design pdp11_irq has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design pdp11_irq has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design pdp11_irq has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design pdp11_irq has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design pdp11_irq has unconnected port IB_MREQ[din][6]
WARNING: [Synth 8-3331] design pdp11_irq has unconnected port IB_MREQ[din][5]
WARNING: [Synth 8-3331] design pdp11_irq has unconnected port IB_MREQ[din][4]
WARNING: [Synth 8-3331] design pdp11_irq has unconnected port IB_MREQ[din][3]
WARNING: [Synth 8-3331] design pdp11_irq has unconnected port IB_MREQ[din][2]
WARNING: [Synth 8-3331] design pdp11_irq has unconnected port IB_MREQ[din][1]
WARNING: [Synth 8-3331] design pdp11_irq has unconnected port IB_MREQ[din][0]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IREG[14]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IREG[13]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IREG[12]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IREG[11]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[be0]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[be1]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[din][15]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[din][14]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[din][13]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[din][12]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[din][11]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[din][7]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[din][6]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[din][5]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[din][4]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[din][3]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[din][2]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[din][1]
WARNING: [Synth 8-3331] design pdp11_sequencer has unconnected port IB_MREQ[din][0]
WARNING: [Synth 8-3331] design pdp11_lunit has unconnected port CCIN[2]
WARNING: [Synth 8-3331] design pdp11_lunit has unconnected port CCIN[1]
WARNING: [Synth 8-3331] design pdp11_psr has unconnected port DIN[10]
WARNING: [Synth 8-3331] design pdp11_psr has unconnected port DIN[9]
WARNING: [Synth 8-3331] design pdp11_psr has unconnected port DIN[8]
WARNING: [Synth 8-3331] design pdp11_psr has unconnected port IB_MREQ[rmw]
WARNING: [Synth 8-3331] design pdp11_psr has unconnected port IB_MREQ[cacc]
WARNING: [Synth 8-3331] design pdp11_psr has unconnected port IB_MREQ[racc]
WARNING: [Synth 8-3331] design pdp11_psr has unconnected port IB_MREQ[din][10]
WARNING: [Synth 8-3331] design pdp11_psr has unconnected port IB_MREQ[din][9]
WARNING: [Synth 8-3331] design pdp11_psr has unconnected port IB_MREQ[din][8]
WARNING: [Synth 8-3331] design pdp11_psr has unconnected port IB_MREQ[din][4]
WARNING: [Synth 8-3331] design pdp11_core_rbus has unconnected port CP_STAT[cmdbusy]
WARNING: [Synth 8-3331] design pdp11_core_rbus has unconnected port CP_STAT[cpuwait]
WARNING: [Synth 8-3331] design rlink_sp2c has unconnected port CE_USEC
WARNING: [Synth 8-3331] design rlink_sp2c has unconnected port CE_MSEC
INFO: [Synth 8-3971] The signal CORE/RL/RTBUF/sv_ram_reg was recognized as a true dual port RAM template.
INFO: [Synth 8-3971] The signal CACHE/CMEM_TAG/sv_ram_reg was recognized as a true dual port RAM template.
INFO: [Synth 8-3971] The signal CACHE/CMEM_DAT0/sv_ram_reg was recognized as a true dual port RAM template.
INFO: [Synth 8-3971] The signal CACHE/CMEM_DAT1/sv_ram_reg was recognized as a true dual port RAM template.
INFO: [Synth 8-3971] The signal CACHE/CMEM_DAT2/sv_ram_reg was recognized as a true dual port RAM template.
INFO: [Synth 8-3971] The signal CACHE/CMEM_DAT3/sv_ram_reg was recognized as a true dual port RAM template.
INFO: [Synth 8-3333] propagating constant 0 across sequential element (SYS70/\DMPCNT.I0/R_REGS_reg[psig][26] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (SYS70/\DMPCNT.I0/R_REGS_reg[psig][25] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (SYS70/\DMPCNT.I0/R_REGS_reg[psig][24] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (IBDR_SYS/\RHRP.RPA /\R_REGS_reg[dtyp][3] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (SYS70/W11A/SEQ/\R_STATUS_reg[suspext] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (SYS70/W11A/VMBOX/\MMU/R_SSR0_reg[inst_compl] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (SYS70/W11A/SEQ/\R_STATUS_reg[intvect][8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (SYS70/W11A/SEQ/\R_IDSTAT_reg[res_sel][2] )
WARNING: [Synth 8-3332] Sequential element (DIV_CLK1/R_REGS_reg[usec]) is unused and will be removed from module s7_cmt_1ce1ce.
WARNING: [Synth 8-3332] Sequential element (CORE/RL/R_LREGS_reg[attn][15]) is unused and will be removed from module rlink_sp2c.
WARNING: [Synth 8-3332] Sequential element (CORE/RL/R_LREGS_reg[attn][14]) is unused and will be removed from module rlink_sp2c.
WARNING: [Synth 8-3332] Sequential element (CORE/RL/R_LREGS_reg[attn][13]) is unused and will be removed from module rlink_sp2c.
WARNING: [Synth 8-3332] Sequential element (CORE/RL/R_LREGS_reg[attn][12]) is unused and will be removed from module rlink_sp2c.
WARNING: [Synth 8-3332] Sequential element (CORE/RL/R_LREGS_reg[attn][11]) is unused and will be removed from module rlink_sp2c.
WARNING: [Synth 8-3332] Sequential element (CORE/RL/R_LREGS_reg[attn][3]) is unused and will be removed from module rlink_sp2c.
WARNING: [Synth 8-3332] Sequential element (CORE/RL/R_LREGS_reg[moneop]) is unused and will be removed from module rlink_sp2c.
WARNING: [Synth 8-3332] Sequential element (CORE/RL/R_LREGS_reg[monattn]) is unused and will be removed from module rlink_sp2c.
WARNING: [Synth 8-3332] Sequential element (MMU/R_SSR0_reg[inst_compl]) is unused and will be removed from module pdp11_vmbox.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[ibcacc]) is unused and will be removed from module pdp11_vmbox.
WARNING: [Synth 8-3332] Sequential element (R_STATUS_reg[suspext]) is unused and will be removed from module pdp11_sequencer.
WARNING: [Synth 8-3332] Sequential element (R_STATUS_reg[intvect][8]) is unused and will be removed from module pdp11_sequencer.
WARNING: [Synth 8-3332] Sequential element (R_IDSTAT_reg[res_sel][2]) is unused and will be removed from module pdp11_sequencer.
WARNING: [Synth 8-3332] Sequential element (SNUM0.R_VMWAIT_reg) is unused and will be removed from module pdp11_sequencer.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/R_REGS_reg[psig][26]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/R_REGS_reg[psig][25]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/R_REGS_reg[psig][24]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/PRE[26].ENA.CNT/R_CNT_reg[4]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/PRE[26].ENA.CNT/R_CNT_reg[3]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/PRE[26].ENA.CNT/R_CNT_reg[2]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/PRE[26].ENA.CNT/R_CNT_reg[1]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/PRE[26].ENA.CNT/R_CNT_reg[0]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/PRE[25].ENA.CNT/R_CNT_reg[4]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/PRE[25].ENA.CNT/R_CNT_reg[3]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/PRE[25].ENA.CNT/R_CNT_reg[2]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/PRE[25].ENA.CNT/R_CNT_reg[1]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/PRE[25].ENA.CNT/R_CNT_reg[0]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/PRE[24].ENA.CNT/R_CNT_reg[4]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/PRE[24].ENA.CNT/R_CNT_reg[3]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/PRE[24].ENA.CNT/R_CNT_reg[2]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/PRE[24].ENA.CNT/R_CNT_reg[1]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (DMPCNT.I0/PRE[24].ENA.CNT/R_CNT_reg[0]) is unused and will be removed from module pdp11_sys70.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[req_lock]) is unused and will be removed from module ibd_iist.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[req_boot]) is unused and will be removed from module ibd_iist.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[dtyp][3]) is unused and will be removed from module ibdr_rhrp.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[cellen][15]) is unused and will be removed from module pdp11_bram_memctl.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[cellen][14]) is unused and will be removed from module pdp11_bram_memctl.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[cellen][13]) is unused and will be removed from module pdp11_bram_memctl.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[cellen][12]) is unused and will be removed from module pdp11_bram_memctl.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[cellen][11]) is unused and will be removed from module pdp11_bram_memctl.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swi][15]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swi][14]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swi][13]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swi][12]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swi][11]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swi][10]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swi][9]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swi][8]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swi][7]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swi][6]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swi][2]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swi][1]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swi][0]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swieff][15]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swieff][14]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swieff][13]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swieff][12]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swieff][11]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swieff][10]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swieff][9]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swieff][8]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swieff][7]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swieff][6]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swieff][2]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swieff][1]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[swieff][0]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[btn][4]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[btn][3]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[btn][2]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[btn][1]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[btn][0]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[btneff][4]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[btneff][3]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[btneff][2]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[btneff][1]) is unused and will be removed from module sn_humanio_rbus.
WARNING: [Synth 8-3332] Sequential element (R_REGS_reg[btneff][0]) is unused and will be removed from module sn_humanio_rbus.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:02:45 ; elapsed = 00:02:55 . Memory (MB): peak = 1643.121 ; gain = 551.375 ; free physical = 857 ; free virtual = 8888
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

ROM:
+--------------+-----------------------+---------------+----------------+
|Module Name   | RTL Object            | Depth x Width | Implemented As | 
+--------------+-----------------------+---------------+----------------+
|gray_cnt_5    | N_DATA                | 32x5          | LUT            | 
|ibdr_rhrp     | imbreg                | 32x1          | LUT            | 
|fifo_2c_dram2 | GCW/GRAY_5.CNT/N_DATA | 32x5          | LUT            | 
|fifo_2c_dram2 | GCR/GRAY_5.CNT/N_DATA | 32x5          | LUT            | 
|fifo_2c_dram2 | GCW/GRAY_5.CNT/N_DATA | 32x5          | LUT            | 
|fifo_2c_dram2 | GCR/GRAY_5.CNT/N_DATA | 32x5          | LUT            | 
|ibdr_rhrp     | imbreg                | 32x1          | LUT            | 
+--------------+-----------------------+---------------+----------------+


Block RAM: Preliminary Mapping  Report (see note below)
+--------------------------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name                           | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | 
+--------------------------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|ram_2swsr_rfirst_gen:                 | sv_ram_reg | 4 K x 8(READ_FIRST)    | W | R | 4 K x 8(READ_FIRST)    | W | R | Port A and B     | 0      | 1      | 
|ram_2swsr_rfirst_gen__parameterized1: | sv_ram_reg | 2 K x 9(READ_FIRST)    | W | R | 2 K x 9(READ_FIRST)    | W | R | Port A and B     | 1      | 0      | 
|ram_2swsr_rfirst_gen__parameterized1: | sv_ram_reg | 2 K x 9(READ_FIRST)    | W | R | 2 K x 9(READ_FIRST)    | W | R | Port A and B     | 1      | 0      | 
|ram_2swsr_rfirst_gen__parameterized1: | sv_ram_reg | 2 K x 9(READ_FIRST)    | W | R | 2 K x 9(READ_FIRST)    | W | R | Port A and B     | 1      | 0      | 
|ram_2swsr_rfirst_gen__parameterized1: | sv_ram_reg | 2 K x 9(READ_FIRST)    | W | R | 2 K x 9(READ_FIRST)    | W | R | Port A and B     | 1      | 0      | 
|ram_2swsr_rfirst_gen__parameterized1: | sv_ram_reg | 2 K x 9(READ_FIRST)    | W | R | 2 K x 9(READ_FIRST)    | W | R | Port A and B     | 1      | 0      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen:                 | sv_ram_reg | 4 K x 8(WRITE_FIRST)   | W | R |                        |   |   | Port A           | 0      | 1      | 
+--------------------------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+

Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. 

Distributed RAM: Preliminary Mapping  Report (see note below)
+--------------------+---------------------------------+----------------+----------------------+-----------------+
|Module Name         | RTL Object                      | Inference      | Size (Depth x Width) | Primitives      | 
+--------------------+---------------------------------+----------------+----------------------+-----------------+
|fifo_2c_dram2:      | RAM/RAM_reg                     | User Attribute | 32 x 8               | RAM32M x 2      | 
|fifo_2c_dram2:      | RAM/RAM_reg                     | User Attribute | 32 x 8               | RAM32M x 2      | 
|RLINK               | CORE/RL/DOFIFO/FIFO/RAM/RAM_reg | User Attribute | 32 x 8               | RAM32M x 2      | 
|SYS70/W11A/VMBOX    | MMU/SADR/SDR_LOW/RAM_reg        | User Attribute | 64 x 4               | RAM64X1S x 4    | 
|SYS70/W11A/VMBOX    | MMU/SADR/SDR_AIB/RAM_reg        | User Attribute | 64 x 2               | RAM64X1S x 2    | 
|SYS70/W11A/VMBOX    | MMU/SADR/SDR_SLF/RAM_reg        | User Attribute | 64 x 7               | RAM64X1S x 7    | 
|SYS70/W11A/VMBOX    | MMU/SADR/SAR_LOW/RAM_reg        | User Attribute | 64 x 8               | RAM64X1S x 8    | 
|SYS70/W11A/VMBOX    | MMU/SADR/SAR_HIGH/RAM_reg       | User Attribute | 64 x 8               | RAM64X1S x 8    | 
|SYS70/W11A/VMBOX    | UBMAP/MAP_0/RAM_reg             | User Attribute | 32 x 7               | RAM32X1S x 7    | 
|SYS70/W11A/VMBOX    | UBMAP/MAP_1/RAM_reg             | User Attribute | 32 x 8               | RAM32X1S x 8    | 
|SYS70/W11A/VMBOX    | UBMAP/MAP_2/RAM_reg             | User Attribute | 32 x 6               | RAM32X1S x 6    | 
|SYS70/W11A/DPATH    | GPR/GPR_LOW/RAM_reg             | User Attribute | 16 x 8               | RAM16X1D x 8    | 
|SYS70/W11A/DPATH    | GPR/GPR_HIGH/RAM_reg            | User Attribute | 16 x 8               | RAM16X1D x 8    | 
|SYS70               | DMPCNT.I0/MEM/RAM_reg           | User Attribute | 32 x 32              | RAM32X1S x 32   | 
|IBDR_SYS/\RHRP.RPA  | MEM_0/RAM_reg                   | User Attribute | 32 x 8               | RAM32X1S x 8    | 
|IBDR_SYS/\RHRP.RPA  | MEM_1/RAM_reg                   | User Attribute | 32 x 8               | RAM32X1S x 8    | 
|IBDR_SYS/\RL11.RLA  | MEM_1/RAM_reg                   | User Attribute | 16 x 8               | RAM16X1S x 8    | 
|IBDR_SYS/\RL11.RLA  | MEM_0/RAM_reg                   | User Attribute | 16 x 8               | RAM16X1S x 8    | 
|IBDR_SYS/\RK11.RKA  | MEM_0/RAM_reg                   | User Attribute | 16 x 8               | RAM16X1S x 8    | 
|IBDR_SYS/\RK11.RKA  | MEM_1/RAM_reg                   | User Attribute | 16 x 8               | RAM16X1S x 8    | 
+--------------------+---------------------------------+----------------+----------------------+-----------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.

DSP: Preliminary Mapping  Report (see note below)
+------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
+------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|pdp11_munit | A*B         | 16     | 16     | -      | -      | 32     | 0    | 0    | -    | -    | -     | 0    | 0    | 
+------------+-------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:03:03 ; elapsed = 00:03:13 . Memory (MB): peak = 1751.410 ; gain = 659.664 ; free physical = 716 ; free virtual = 8746
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:03:09 ; elapsed = 00:03:19 . Memory (MB): peak = 1775.426 ; gain = 683.680 ; free physical = 700 ; free virtual = 8730
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-4480] The timing for the instance RLINK/CORE/RL/RTBUF/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance SYS70/CACHE/CMEM_TAG/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance SYS70/CACHE/CMEM_DAT0/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance SYS70/CACHE/CMEM_DAT1/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance SYS70/CACHE/CMEM_DAT2/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance SYS70/CACHE/CMEM_DAT3/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[10].MROW[3].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[10].MROW[2].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[10].MROW[1].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[10].MROW[0].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[9].MROW[3].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[9].MROW[2].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[9].MROW[1].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[9].MROW[0].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[8].MROW[3].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[8].MROW[2].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[8].MROW[1].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[8].MROW[0].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[7].MROW[3].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[7].MROW[2].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[7].MROW[1].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[7].MROW[0].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[6].MROW[3].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[6].MROW[2].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[6].MROW[1].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[6].MROW[0].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[5].MROW[3].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[5].MROW[2].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[5].MROW[1].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[5].MROW[0].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[4].MROW[3].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[4].MROW[2].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[4].MROW[1].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[4].MROW[0].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[3].MROW[3].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[3].MROW[2].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[3].MROW[1].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[3].MROW[0].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[2].MROW[3].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[2].MROW[2].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[2].MROW[1].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[2].MROW[0].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[1].MROW[3].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[1].MROW[2].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[1].MROW[1].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[1].MROW[0].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[0].MROW[3].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[0].MROW[2].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[0].MROW[1].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance BRAM_CTL/MARRAY[0].MROW[0].MCELL/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:03:19 ; elapsed = 00:03:30 . Memory (MB): peak = 1868.895 ; gain = 777.148 ; free physical = 692 ; free virtual = 8722
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_BTN/R_DI_reg[0]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_BTN/R_DI_reg[1]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_BTN/R_DI_reg[2]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_BTN/R_DI_reg[3]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_BTN/R_DI_reg[4]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[0]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[1]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[2]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[3]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[4]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[5]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[6]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[7]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[8]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[9]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[10]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[11]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[12]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[13]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[14]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \HIO/HIO/HIO/IOB_SWI/R_DI_reg[15]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]  to handle IOB=TRUE attribute
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:03:20 ; elapsed = 00:03:31 . Memory (MB): peak = 1868.895 ; gain = 777.148 ; free physical = 687 ; free virtual = 8717
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:03:20 ; elapsed = 00:03:31 . Memory (MB): peak = 1868.895 ; gain = 777.148 ; free physical = 687 ; free virtual = 8717
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:03:21 ; elapsed = 00:03:32 . Memory (MB): peak = 1868.895 ; gain = 777.148 ; free physical = 686 ; free virtual = 8717
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:03:21 ; elapsed = 00:03:32 . Memory (MB): peak = 1868.895 ; gain = 777.148 ; free physical = 686 ; free virtual = 8717
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:03:21 ; elapsed = 00:03:32 . Memory (MB): peak = 1868.895 ; gain = 777.148 ; free physical = 685 ; free virtual = 8716
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:03:21 ; elapsed = 00:03:32 . Memory (MB): peak = 1868.895 ; gain = 777.148 ; free physical = 685 ; free virtual = 8716
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+-------------+------+
|      |Cell         |Count |
+------+-------------+------+
|1     |BUFG         |     4|
|2     |CARRY4       |   109|
|3     |DSP48E1_1    |     1|
|4     |LUT1         |   194|
|5     |LUT2         |   579|
|6     |LUT3         |   708|
|7     |LUT4         |   814|
|8     |LUT5         |  1116|
|9     |LUT6         |  2548|
|10    |MMCME2_BASE  |     1|
|11    |MUXF7        |    42|
|12    |MUXF8        |     5|
|13    |PLLE2_BASE   |     1|
|14    |RAM16X1D     |    16|
|15    |RAM16X1S     |    32|
|16    |RAM32M       |     6|
|17    |RAM32X1S     |    69|
|18    |RAM64X1S     |    29|
|19    |RAMB18E1     |     5|
|20    |RAMB36E1     |     1|
|21    |RAMB36E1_1   |    44|
|22    |USR_ACCESSE2 |     1|
|23    |XADC         |     1|
|24    |FDRE         |  2733|
|25    |FDSE         |    61|
|26    |IBUF         |    23|
|27    |OBUF         |    29|
+------+-------------+------+

Report Instance Areas: 
+------+-------------------------------+----------------------------------------+------+
|      |Instance                       |Module                                  |Cells |
+------+-------------------------------+----------------------------------------+------+
|1     |top                            |                                        |  9172|
|2     |  BRAM_CTL                     |pdp11_bram_memctl                       |   323|
|3     |    \MARRAY[0].MROW[0].MCELL   |ram_1swsr_wfirst_gen                    |     1|
|4     |    \MARRAY[0].MROW[1].MCELL   |ram_1swsr_wfirst_gen_51                 |     1|
|5     |    \MARRAY[0].MROW[2].MCELL   |ram_1swsr_wfirst_gen_52                 |     1|
|6     |    \MARRAY[0].MROW[3].MCELL   |ram_1swsr_wfirst_gen_53                 |     1|
|7     |    \MARRAY[10].MROW[0].MCELL  |ram_1swsr_wfirst_gen_54                 |     1|
|8     |    \MARRAY[10].MROW[1].MCELL  |ram_1swsr_wfirst_gen_55                 |     1|
|9     |    \MARRAY[10].MROW[2].MCELL  |ram_1swsr_wfirst_gen_56                 |     1|
|10    |    \MARRAY[10].MROW[3].MCELL  |ram_1swsr_wfirst_gen_57                 |     1|
|11    |    \MARRAY[1].MROW[0].MCELL   |ram_1swsr_wfirst_gen_58                 |     1|
|12    |    \MARRAY[1].MROW[1].MCELL   |ram_1swsr_wfirst_gen_59                 |     1|
|13    |    \MARRAY[1].MROW[2].MCELL   |ram_1swsr_wfirst_gen_60                 |     1|
|14    |    \MARRAY[1].MROW[3].MCELL   |ram_1swsr_wfirst_gen_61                 |     1|
|15    |    \MARRAY[2].MROW[0].MCELL   |ram_1swsr_wfirst_gen_62                 |     1|
|16    |    \MARRAY[2].MROW[1].MCELL   |ram_1swsr_wfirst_gen_63                 |     1|
|17    |    \MARRAY[2].MROW[2].MCELL   |ram_1swsr_wfirst_gen_64                 |     1|
|18    |    \MARRAY[2].MROW[3].MCELL   |ram_1swsr_wfirst_gen_65                 |     1|
|19    |    \MARRAY[3].MROW[0].MCELL   |ram_1swsr_wfirst_gen_66                 |     1|
|20    |    \MARRAY[3].MROW[1].MCELL   |ram_1swsr_wfirst_gen_67                 |     1|
|21    |    \MARRAY[3].MROW[2].MCELL   |ram_1swsr_wfirst_gen_68                 |     1|
|22    |    \MARRAY[3].MROW[3].MCELL   |ram_1swsr_wfirst_gen_69                 |     1|
|23    |    \MARRAY[4].MROW[0].MCELL   |ram_1swsr_wfirst_gen_70                 |     1|
|24    |    \MARRAY[4].MROW[1].MCELL   |ram_1swsr_wfirst_gen_71                 |     1|
|25    |    \MARRAY[4].MROW[2].MCELL   |ram_1swsr_wfirst_gen_72                 |     1|
|26    |    \MARRAY[4].MROW[3].MCELL   |ram_1swsr_wfirst_gen_73                 |     1|
|27    |    \MARRAY[5].MROW[0].MCELL   |ram_1swsr_wfirst_gen_74                 |     1|
|28    |    \MARRAY[5].MROW[1].MCELL   |ram_1swsr_wfirst_gen_75                 |     1|
|29    |    \MARRAY[5].MROW[2].MCELL   |ram_1swsr_wfirst_gen_76                 |     1|
|30    |    \MARRAY[5].MROW[3].MCELL   |ram_1swsr_wfirst_gen_77                 |     1|
|31    |    \MARRAY[6].MROW[0].MCELL   |ram_1swsr_wfirst_gen_78                 |     1|
|32    |    \MARRAY[6].MROW[1].MCELL   |ram_1swsr_wfirst_gen_79                 |     1|
|33    |    \MARRAY[6].MROW[2].MCELL   |ram_1swsr_wfirst_gen_80                 |     1|
|34    |    \MARRAY[6].MROW[3].MCELL   |ram_1swsr_wfirst_gen_81                 |     1|
|35    |    \MARRAY[7].MROW[0].MCELL   |ram_1swsr_wfirst_gen_82                 |     1|
|36    |    \MARRAY[7].MROW[1].MCELL   |ram_1swsr_wfirst_gen_83                 |     1|
|37    |    \MARRAY[7].MROW[2].MCELL   |ram_1swsr_wfirst_gen_84                 |     1|
|38    |    \MARRAY[7].MROW[3].MCELL   |ram_1swsr_wfirst_gen_85                 |     1|
|39    |    \MARRAY[8].MROW[0].MCELL   |ram_1swsr_wfirst_gen_86                 |     1|
|40    |    \MARRAY[8].MROW[1].MCELL   |ram_1swsr_wfirst_gen_87                 |     1|
|41    |    \MARRAY[8].MROW[2].MCELL   |ram_1swsr_wfirst_gen_88                 |     1|
|42    |    \MARRAY[8].MROW[3].MCELL   |ram_1swsr_wfirst_gen_89                 |     1|
|43    |    \MARRAY[9].MROW[0].MCELL   |ram_1swsr_wfirst_gen_90                 |     1|
|44    |    \MARRAY[9].MROW[1].MCELL   |ram_1swsr_wfirst_gen_91                 |     1|
|45    |    \MARRAY[9].MROW[2].MCELL   |ram_1swsr_wfirst_gen_92                 |     1|
|46    |    \MARRAY[9].MROW[3].MCELL   |ram_1swsr_wfirst_gen_93                 |     1|
|47    |  GEN_CLKALL                   |s7_cmt_1ce1ce                           |    91|
|48    |    DIV_CLK0                   |clkdivce                                |    44|
|49    |    DIV_CLK1                   |clkdivce__parameterized1                |    41|
|50    |    GEN_CLK0                   |s7_cmt_sfs                              |     3|
|51    |    GEN_CLK1                   |s7_cmt_sfs__parameterized1              |     3|
|52    |  HIO                          |sn_humanio_rbus                         |   364|
|53    |    HIO                        |sn_humanio                              |   222|
|54    |      DRV                      |sn_7segctl                              |    37|
|55    |      HIO                      |bp_swibtnled                            |   170|
|56    |        \DEB.DEB_BTN           |debounce_gen__parameterized1            |    30|
|57    |        \DEB.DEB_SWI           |debounce_gen                            |   103|
|58    |        IOB_BTN                |iob_reg_i_gen__parameterized3           |     5|
|59    |        IOB_LED                |iob_reg_o_gen__parameterized5           |    16|
|60    |        IOB_SWI                |iob_reg_i_gen__parameterized1           |    16|
|61    |      IOB_ANO_N                |iob_reg_o_gen__parameterized1           |     4|
|62    |      IOB_SEG_N                |iob_reg_o_gen__parameterized3           |     8|
|63    |  IBDR_SYS                     |ibdr_maxisys                            |  2110|
|64    |    \DEUNA.XUA                 |ibdr_deuna                              |    78|
|65    |    DL11_0                     |ibdr_dl11                               |    81|
|66    |    \DL11_1.TTB                |ibdr_dl11__parameterized1               |    79|
|67    |    \IIST.I0                   |ibd_iist                                |   358|
|68    |    KW11L                      |ibd_kw11l                               |    21|
|69    |    \KW11P.I0                  |ibd_kw11p                               |   137|
|70    |    \LP11.LPA                  |ibdr_lp11                               |    18|
|71    |    \PC11.PCA                  |ibdr_pc11                               |    32|
|72    |    \RHRP.RPA                  |ibdr_rhrp                               |   683|
|73    |      MEM_0                    |ram_1swar_gen__parameterized10_49       |    54|
|74    |      MEM_1                    |ram_1swar_gen__parameterized10_50       |    65|
|75    |    \RK11.RKA                  |ibdr_rk11                               |   161|
|76    |      MEM_0                    |ram_1swar_gen__parameterized16_47       |    23|
|77    |      MEM_1                    |ram_1swar_gen__parameterized16_48       |     9|
|78    |    \RL11.RLA                  |ibdr_rl11                               |   235|
|79    |      MEM_0                    |ram_1swar_gen__parameterized16          |    60|
|80    |      MEM_1                    |ram_1swar_gen__parameterized16_46       |    55|
|81    |    SDREG                      |ibdr_sdreg                              |    36|
|82    |    SRES_OR                    |ib_sres_or_4_42                         |    25|
|83    |    SRES_OR_1                  |ib_sres_or_4_43                         |    16|
|84    |    SRES_OR_2                  |ib_sres_or_4_44                         |    22|
|85    |    SRES_OR_3                  |ib_sres_or_3                            |     8|
|86    |    SRES_OR_4                  |ib_sres_or_3_45                         |    13|
|87    |    \TM11.TMA                  |ibdr_tm11                               |   107|
|88    |  IOB_RS232                    |bp_rs232_2line_iob                      |     2|
|89    |    IOB_RXD                    |iob_reg_i                               |     1|
|90    |      IOB                      |iob_reg_i_gen                           |     1|
|91    |    IOB_TXD                    |iob_reg_o                               |     1|
|92    |      IOB                      |iob_reg_o_gen                           |     1|
|93    |  LED_IO                       |ioleds_sp1c                             |     2|
|94    |  RB_SRES_OR                   |rb_sres_or_4                            |    29|
|95    |  RLINK                        |rlink_sp2c                              |  1696|
|96    |    CORE                       |rlink_core8                             |  1029|
|97    |      B2CD                     |byte2cdata                              |    36|
|98    |      CD2B                     |cdata2byte                              |    19|
|99    |      RL                       |rlink_core                              |   974|
|100   |        DOFIFO                 |fifo_1c_dram                            |   103|
|101   |          FIFO                 |fifo_1c_dram_raw                        |   103|
|102   |            RAM                |ram_1swar_1ar_gen_41                    |    45|
|103   |        ICRC                   |crc16                                   |    49|
|104   |        OCRC                   |crc16_40                                |    50|
|105   |        RTBUF                  |ram_2swsr_rfirst_gen                    |    33|
|106   |        SEL                    |rb_sel                                  |    25|
|107   |    SERPORT                    |serport_2clock2                         |   667|
|108   |      CDC_RESET                |cdc_pulse                               |     6|
|109   |      CDC_ENAXON               |cdc_signal_s1__1                        |     2|
|110   |      CDC_ENAESC               |cdc_signal_s1__2                        |     2|
|111   |      RXFIFO                   |fifo_2c_dram2__1                        |   108|
|112   |        GCR                    |gray_cnt_gen_35                         |    12|
|113   |          \GRAY_5.CNT          |gray_cnt_5_39                           |    12|
|114   |        GCW                    |gray_cnt_gen_36                         |    12|
|115   |          \GRAY_5.CNT          |gray_cnt_5_38                           |    12|
|116   |        RAM                    |ram_1swar_1ar_gen_37                    |     2|
|117   |      TXFIFO                   |fifo_2c_dram2                           |   108|
|118   |        GCR                    |gray_cnt_gen                            |    12|
|119   |          \GRAY_5.CNT          |gray_cnt_5_34                           |    12|
|120   |        GCW                    |gray_cnt_gen_33                         |    12|
|121   |          \GRAY_5.CNT          |gray_cnt_5                              |    12|
|122   |        RAM                    |ram_1swar_1ar_gen                       |     2|
|123   |      CDC_RXACT                |cdc_signal_s1__3                        |     2|
|124   |      CDC_TXACT                |cdc_signal_s1__4                        |     2|
|125   |      CDC_ABACT                |cdc_signal_s1__5                        |     2|
|126   |      CDC_RXOK                 |cdc_signal_s1__6                        |     2|
|127   |      CDC_TXOK                 |cdc_signal_s1                           |     2|
|128   |      CDC_CDIV                 |cdc_vector_s0                           |    12|
|129   |      CDC_CDIVF                |cdc_vector_s0__parameterized1           |     3|
|130   |      CDC_RXERR                |cdc_pulse__parameterized1__1            |     9|
|131   |      CDC_RXOVR                |cdc_pulse__parameterized1__2            |     9|
|132   |      CDC_ABDONE               |cdc_pulse__parameterized1               |     9|
|133   |      UART                     |serport_uart_rxtx_ab                    |   305|
|134   |        AB                     |serport_uart_autobaud                   |    81|
|135   |        RXTX                   |serport_uart_rxtx                       |   224|
|136   |          RX                   |serport_uart_rx                         |   152|
|137   |          TX                   |serport_uart_tx                         |    72|
|138   |      XONRX                    |serport_xonrx                           |    21|
|139   |      XONTX                    |serport_xontx                           |    47|
|140   |  \SMRB.I0                     |sysmonx_rbus_base                       |   129|
|141   |    SMRB                       |sysmon_rbus_core                        |   128|
|142   |  SYS70                        |pdp11_sys70                             |  4275|
|143   |    CACHE                      |pdp11_cache                             |   158|
|144   |      CMEM_DAT0                |ram_2swsr_rfirst_gen__parameterized1    |    10|
|145   |      CMEM_DAT1                |ram_2swsr_rfirst_gen__parameterized1_29 |    11|
|146   |      CMEM_DAT2                |ram_2swsr_rfirst_gen__parameterized1_30 |    19|
|147   |      CMEM_DAT3                |ram_2swsr_rfirst_gen__parameterized1_31 |    18|
|148   |      CMEM_TAG                 |ram_2swsr_rfirst_gen__parameterized1_32 |    45|
|149   |    \DMHBPT.I0                 |pdp11_dmhbpt                            |   153|
|150   |      \GU[0].HBPT              |pdp11_dmhbpt_unit__parameterized1       |    74|
|151   |      \GU[1].HBPT              |pdp11_dmhbpt_unit                       |    79|
|152   |    \DMPCNT.I0                 |pdp11_dmpcnt                            |   544|
|153   |      \PRE[0].ENA.CNT          |pdp11_dmpcnt_precnt                     |    11|
|154   |      \PRE[10].ENA.CNT         |pdp11_dmpcnt_precnt_1                   |    11|
|155   |      \PRE[11].ENA.CNT         |pdp11_dmpcnt_precnt_2                   |    21|
|156   |      \PRE[12].ENA.CNT         |pdp11_dmpcnt_precnt_3                   |    11|
|157   |      \PRE[13].ENA.CNT         |pdp11_dmpcnt_precnt_4                   |    11|
|158   |      \PRE[14].ENA.CNT         |pdp11_dmpcnt_precnt_5                   |    11|
|159   |      \PRE[15].ENA.CNT         |pdp11_dmpcnt_precnt_6                   |    16|
|160   |      \PRE[16].ENA.CNT         |pdp11_dmpcnt_precnt_7                   |    11|
|161   |      \PRE[17].ENA.CNT         |pdp11_dmpcnt_precnt_8                   |    11|
|162   |      \PRE[18].ENA.CNT         |pdp11_dmpcnt_precnt_9                   |    11|
|163   |      \PRE[19].ENA.CNT         |pdp11_dmpcnt_precnt_10                  |    21|
|164   |      \PRE[1].ENA.CNT          |pdp11_dmpcnt_precnt_11                  |    11|
|165   |      \PRE[20].ENA.CNT         |pdp11_dmpcnt_precnt_12                  |    11|
|166   |      \PRE[21].ENA.CNT         |pdp11_dmpcnt_precnt_13                  |    11|
|167   |      \PRE[22].ENA.CNT         |pdp11_dmpcnt_precnt_14                  |    11|
|168   |      \PRE[23].ENA.CNT         |pdp11_dmpcnt_precnt_15                  |    16|
|169   |      \PRE[27].ENA.CNT         |pdp11_dmpcnt_precnt_16                  |    13|
|170   |      \PRE[28].ENA.CNT         |pdp11_dmpcnt_precnt_17                  |    11|
|171   |      \PRE[29].ENA.CNT         |pdp11_dmpcnt_precnt_18                  |    11|
|172   |      \PRE[2].ENA.CNT          |pdp11_dmpcnt_precnt_19                  |    11|
|173   |      \PRE[30].ENA.CNT         |pdp11_dmpcnt_precnt_20                  |    11|
|174   |      \PRE[31].ENA.CNT         |pdp11_dmpcnt_precnt_21                  |    20|
|175   |      \PRE[3].ENA.CNT          |pdp11_dmpcnt_precnt_22                  |    26|
|176   |      \PRE[4].ENA.CNT          |pdp11_dmpcnt_precnt_23                  |    11|
|177   |      \PRE[5].ENA.CNT          |pdp11_dmpcnt_precnt_24                  |    11|
|178   |      \PRE[6].ENA.CNT          |pdp11_dmpcnt_precnt_25                  |    11|
|179   |      \PRE[7].ENA.CNT          |pdp11_dmpcnt_precnt_26                  |    16|
|180   |      \PRE[8].ENA.CNT          |pdp11_dmpcnt_precnt_27                  |    11|
|181   |      \PRE[9].ENA.CNT          |pdp11_dmpcnt_precnt_28                  |    11|
|182   |    MEM70                      |pdp11_mem70                             |    26|
|183   |    RB2CP                      |pdp11_core_rbus                         |   168|
|184   |    W11A                       |pdp11_core                              |  3226|
|185   |      REG70                    |pdp11_reg70                             |    11|
|186   |      DPATH                    |pdp11_dpath                             |   737|
|187   |        GPR                    |pdp11_gpr                               |   139|
|188   |        MUNIT                  |pdp11_munit                             |   174|
|189   |        OUNIT                  |pdp11_ounit                             |    31|
|190   |        PSR                    |pdp11_psr                               |    72|
|191   |          SEL__0               |ib_sel__parameterized11                 |     6|
|192   |      IB_SRES_OR               |ib_sres_or_4                            |    15|
|193   |      IRQ                      |pdp11_irq                               |    19|
|194   |        SEL__0                 |ib_sel__parameterized15                 |     7|
|195   |      SEQ                      |pdp11_sequencer                         |  1292|
|196   |        SEL__0                 |ib_sel__parameterized13                 |     9|
|197   |      VMBOX                    |pdp11_vmbox                             |  1152|
|198   |        MMU                    |pdp11_mmu                               |   283|
|199   |          SADR                 |pdp11_mmu_sadr                          |   120|
|200   |            SAR_HIGH           |ram_1swar_gen                           |    43|
|201   |            SAR_LOW            |ram_1swar_gen_0                         |    16|
|202   |            SDR_AIB            |ram_1swar_gen__parameterized4           |     7|
|203   |            SDR_LOW            |ram_1swar_gen__parameterized6           |    14|
|204   |            SDR_SLF            |ram_1swar_gen__parameterized2           |    19|
|205   |          SEL_SSR0             |ib_sel__parameterized3                  |    12|
|206   |          SEL_SSR3             |ib_sel__parameterized5                  |     7|
|207   |          SSR12                |pdp11_mmu_ssr12                         |    94|
|208   |            SEL_SSR1           |ib_sel                                  |    37|
|209   |            SEL_SSR2           |ib_sel__parameterized1                  |    16|
|210   |        SEL__0                 |ib_sel__parameterized9                  |     7|
|211   |        UBMAP                  |pdp11_ubmap                             |    73|
|212   |          MAP_0                |ram_1swar_gen__parameterized12          |    19|
|213   |          MAP_1                |ram_1swar_gen__parameterized10          |    21|
|214   |          MAP_2                |ram_1swar_gen__parameterized8           |    19|
|215   |          SEL                  |ib_sel__parameterized7                  |    14|
|216   |  UARB                         |rbd_usracc                              |    17|
|217   |    RBSEL                      |rb_sel__parameterized1                  |     2|
|218   |    UA                         |usr_access_unisim                       |    15|
+------+-------------------------------+----------------------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:03:21 ; elapsed = 00:03:32 . Memory (MB): peak = 1868.895 ; gain = 777.148 ; free physical = 685 ; free virtual = 8716
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 664 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:03:12 ; elapsed = 00:03:23 . Memory (MB): peak = 1868.895 ; gain = 522.523 ; free physical = 749 ; free virtual = 8779
Synthesis Optimization Complete : Time (s): cpu = 00:03:21 ; elapsed = 00:03:32 . Memory (MB): peak = 1868.902 ; gain = 777.148 ; free physical = 749 ; free virtual = 8779
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 338 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 154 instances were transformed.
  MMCME2_BASE => MMCME2_ADV: 1 instances
  PLLE2_BASE => PLLE2_ADV: 1 instances
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 16 instances
  RAM16X1S => RAM32X1S (RAMS32): 32 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 6 instances
  RAM32X1S => RAM32X1S (RAMS32): 69 instances
  RAM64X1S => RAM64X1S (RAMS64E): 29 instances

1048 Infos, 1891 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:03:28 ; elapsed = 00:03:39 . Memory (MB): peak = 1868.902 ; gain = 789.848 ; free physical = 874 ; free virtual = 8905
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/basys3/project_mflow/project_mflow.runs/synth_1/sys_w11a_b3.dcp' has been generated.
report_utilization: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1872.902 ; gain = 0.000 ; free physical = 872 ; free virtual = 8905
INFO: [Common 17-206] Exiting Vivado at Sun Feb 10 12:37:18 2019...
