
*** Running vivado
    with args -log sys_w11a_arty.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source sys_w11a_arty.tcl -notrace


****** Vivado v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source sys_w11a_arty.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Project 1-454] Reading design checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty.dcp' for cell 'MEMCTL/MIG_CTL'
INFO: [Netlist 29-17] Analyzing 647 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.2
INFO: [Device 21-403] Loading part xc7a35ticsg324-1L
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/constraints/migui_arty.xdc] for cell 'MEMCTL/MIG_CTL'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/constraints/migui_arty.xdc] for cell 'MEMCTL/MIG_CTL'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/arty/arty_pclk.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/arty/arty_pclk.xdc]
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/arty/arty_pins.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/bplib/arty/arty_pins.xdc]
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_ABDONE'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc:13]
INFO: [Timing 38-2] Deriving generated clocks [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc:13]
get_clocks: Time (s): cpu = 00:00:13 ; elapsed = 00:00:14 . Memory (MB): peak = 1848.684 ; gain = 457.438 ; free physical = 734 ; free virtual = 8638
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_ABDONE'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RESET'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RESET'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXERR'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXERR'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXOVR'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXOVR'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'MEMCTL/CDC_SYSRST'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'MEMCTL/CDC_SYSRST'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'MEMCTL/CDC_TEMP/CDC_ENA'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'MEMCTL/CDC_TEMP/CDC_ENA'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ABACT'
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ABACT'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAESC'
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAESC'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAXON'
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAXON'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXACT'
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXACT'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXOK'
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXOK'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXACT'
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXACT'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXOK'
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXOK'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'MEMCTL/SR2MIG/CDC_CACO'
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'MEMCTL/SR2MIG/CDC_CACO'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'MEMCTL/SR2MIG/CDC_CRDY'
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'MEMCTL/SR2MIG/CDC_CRDY'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'MEMCTL/SR2MIG/CDC_UIRST'
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'MEMCTL/SR2MIG/CDC_UIRST'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'MEMCTL/SR2MIG/CDC_WRDY'
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'MEMCTL/SR2MIG/CDC_WRDY'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIV'
WARNING: [Vivado 12-2489] -delay contains time 4.166500 which will be rounded to 4.167 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc:34]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIV'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIVF'
WARNING: [Vivado 12-2489] -delay contains time 4.166500 which will be rounded to 4.167 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc:34]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIVF'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'MEMCTL/CDC_TEMP/CDC_DOUT'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'MEMCTL/CDC_TEMP/CDC_DOUT'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/RXFIFO'
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:23]
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:28]
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:35]
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:40]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/RXFIFO'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/TXFIFO'
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:23]
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:28]
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:35]
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:40]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/TXFIFO'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'MEMCTL/SR2MIG/REQFIFO'
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:23]
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:28]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'MEMCTL/SR2MIG/REQFIFO'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'MEMCTL/SR2MIG/RESFIFO'
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:35]
WARNING: [Vivado 12-2489] -delay contains time 10.666400 which will be rounded to 10.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:40]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'MEMCTL/SR2MIG/RESFIFO'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 329 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 16 instances
  IOBUFDS_INTERMDISABLE => IOBUFDS_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT, IBUFDS_INTERMDISABLE_INT, INV, OBUFTDS, OBUFTDS): 2 instances
  OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS, OBUFDS): 1 instances
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 16 instances
  RAM16X1S => RAM32X1S (RAMS32): 32 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 164 instances
  RAM32X1S => RAM32X1S (RAMS32): 69 instances
  RAM64X1S => RAM64X1S (RAMS64E): 29 instances

link_design: Time (s): cpu = 00:00:23 ; elapsed = 00:00:24 . Memory (MB): peak = 1848.684 ; gain = 750.609 ; free physical = 775 ; free virtual = 8651
Command: opt_design -directive Explore
INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
Running DRC as a precondition to command opt_design

Starting DRC Task
Command: report_drc (run_mandatory_drcs) for: opt_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1852.691 ; gain = 4.008 ; free physical = 769 ; free virtual = 8646
INFO: [Timing 38-35] Done setting XDC timing constraints.

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 2 inverter(s) to 2 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: fb25a126

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1852.691 ; gain = 0.000 ; free physical = 765 ; free virtual = 8642
INFO: [Opt 31-389] Phase Retarget created 1 cells and removed 280 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: c5d483d5

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1852.691 ; gain = 0.000 ; free physical = 760 ; free virtual = 8637
INFO: [Opt 31-389] Phase Constant propagation created 59 cells and removed 129 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 15b44335c

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1852.691 ; gain = 0.000 ; free physical = 760 ; free virtual = 8637
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 272 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 15b44335c

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1852.691 ; gain = 0.000 ; free physical = 760 ; free virtual = 8636
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 15b44335c

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1852.691 ; gain = 0.000 ; free physical = 760 ; free virtual = 8636
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1852.691 ; gain = 0.000 ; free physical = 760 ; free virtual = 8636
Ending Logic Optimization Task | Checksum: 15b44335c

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1852.691 ; gain = 0.000 ; free physical = 760 ; free virtual = 8636

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Power 33-23] Power model is not available for UA
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.
WARNING: [Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 21 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 22 newly gated: 0 Total Ports: 42
Ending PowerOpt Patch Enables Task | Checksum: bd5def14

Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.09 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 728 ; free virtual = 8606
Ending Power Optimization Task | Checksum: bd5def14

Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 2177.465 ; gain = 324.773 ; free physical = 739 ; free virtual = 8616
31 Infos, 27 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:20 ; elapsed = 00:00:18 . Memory (MB): peak = 2177.465 ; gain = 328.781 ; free physical = 739 ; free virtual = 8616
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.12 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 736 ; free virtual = 8616
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.runs/impl_1/sys_w11a_arty_opt.dcp' has been generated.
Command: report_drc -file sys_w11a_arty_drc_opted.rpt
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.runs/impl_1/sys_w11a_arty_drc_opted.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 730 ; free virtual = 8611
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
Command: report_drc (run_mandatory_drcs) for: incr_eco_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
Command: report_drc (run_mandatory_drcs) for: placer_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 46-5] The placer was invoked with the 'Explore' directive.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 729 ; free virtual = 8611
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 55ccaa4b

Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 729 ; free virtual = 8611
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 732 ; free virtual = 8614

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1c54140d5

Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 713 ; free virtual = 8596

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1f7f1d036

Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 675 ; free virtual = 8558

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1f7f1d036

Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 674 ; free virtual = 8557
Phase 1 Placer Initialization | Checksum: 1f7f1d036

Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 674 ; free virtual = 8557

Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 20848195d

Time (s): cpu = 00:01:02 ; elapsed = 00:01:05 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 647 ; free virtual = 8539

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 20848195d

Time (s): cpu = 00:01:02 ; elapsed = 00:01:05 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 646 ; free virtual = 8539

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 240373f42

Time (s): cpu = 00:01:08 ; elapsed = 00:01:11 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 651 ; free virtual = 8536

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 19a17d9b3

Time (s): cpu = 00:01:08 ; elapsed = 00:01:11 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 651 ; free virtual = 8536

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 25fe2aea2

Time (s): cpu = 00:01:08 ; elapsed = 00:01:11 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 651 ; free virtual = 8536

Phase 3.5 Timing Path Optimizer
Phase 3.5 Timing Path Optimizer | Checksum: 1eb4ea877

Time (s): cpu = 00:01:10 ; elapsed = 00:01:13 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 652 ; free virtual = 8536

Phase 3.6 Fast Optimization
Phase 3.6 Fast Optimization | Checksum: 25d836b3c

Time (s): cpu = 00:01:10 ; elapsed = 00:01:13 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 651 ; free virtual = 8536

Phase 3.7 Small Shape Detail Placement
Phase 3.7 Small Shape Detail Placement | Checksum: 14cbc21f8

Time (s): cpu = 00:01:18 ; elapsed = 00:01:21 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 797 ; free virtual = 8682

Phase 3.8 Re-assign LUT pins
Phase 3.8 Re-assign LUT pins | Checksum: 10dd56b7c

Time (s): cpu = 00:01:19 ; elapsed = 00:01:22 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 798 ; free virtual = 8682

Phase 3.9 Pipeline Register Optimization
Phase 3.9 Pipeline Register Optimization | Checksum: 10dd56b7c

Time (s): cpu = 00:01:19 ; elapsed = 00:01:23 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 798 ; free virtual = 8682

Phase 3.10 Fast Optimization
Phase 3.10 Fast Optimization | Checksum: 22d5bc452

Time (s): cpu = 00:01:22 ; elapsed = 00:01:25 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 800 ; free virtual = 8684
Phase 3 Detail Placement | Checksum: 22d5bc452

Time (s): cpu = 00:01:22 ; elapsed = 00:01:25 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 800 ; free virtual = 8684

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1cc035769

Phase 4.1.1.1 BUFG Insertion
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
INFO: [Place 46-41] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
Phase 4.1.1.1 BUFG Insertion | Checksum: 1cc035769

Time (s): cpu = 00:01:29 ; elapsed = 00:01:30 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 808 ; free virtual = 8693
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.531. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 25d0c1ec2

Time (s): cpu = 00:01:32 ; elapsed = 00:01:33 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 807 ; free virtual = 8692
Phase 4.1 Post Commit Optimization | Checksum: 25d0c1ec2

Time (s): cpu = 00:01:33 ; elapsed = 00:01:33 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 807 ; free virtual = 8692

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 25d0c1ec2

Time (s): cpu = 00:01:33 ; elapsed = 00:01:33 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 807 ; free virtual = 8693

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 25d0c1ec2

Time (s): cpu = 00:01:33 ; elapsed = 00:01:33 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 807 ; free virtual = 8693

Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 1e57d47a5

Time (s): cpu = 00:01:33 ; elapsed = 00:01:34 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 807 ; free virtual = 8693
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1e57d47a5

Time (s): cpu = 00:01:33 ; elapsed = 00:01:34 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 807 ; free virtual = 8693
Ending Placer Task | Checksum: 13fe2d79f

Time (s): cpu = 00:01:33 ; elapsed = 00:01:34 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 819 ; free virtual = 8704
51 Infos, 27 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:01:38 ; elapsed = 00:01:39 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 819 ; free virtual = 8704
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 797 ; free virtual = 8704
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.runs/impl_1/sys_w11a_arty_placed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 815 ; free virtual = 8705
report_io: Time (s): cpu = 00:00:00.20 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 807 ; free virtual = 8697
report_utilization: Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 814 ; free virtual = 8705
report_control_sets: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.27 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 813 ; free virtual = 8704
Command: phys_opt_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.500 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
56 Infos, 27 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 780 ; free virtual = 8693
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.runs/impl_1/sys_w11a_arty_physopt.dcp' has been generated.
Command: route_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
Running DRC as a precondition to command route_design
Command: report_drc (run_mandatory_drcs) for: router_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-270] Using Router directive 'Explore'.
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: ee030a8c ConstDB: 0 ShapeSum: 51dfcd13 RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 8b9dfc05

Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 611 ; free virtual = 8523

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 8b9dfc05

Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 615 ; free virtual = 8528

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 8b9dfc05

Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 607 ; free virtual = 8520

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 8b9dfc05

Time (s): cpu = 00:00:24 ; elapsed = 00:00:20 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 607 ; free virtual = 8520
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 1b64e44d8

Time (s): cpu = 00:00:36 ; elapsed = 00:00:27 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 585 ; free virtual = 8498
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.586  | TNS=0.000  | WHS=-0.354 | THS=-367.856|

Phase 2 Router Initialization | Checksum: 19922d3ea

Time (s): cpu = 00:00:41 ; elapsed = 00:00:30 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 581 ; free virtual = 8495

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 19a2b29c5

Time (s): cpu = 00:00:48 ; elapsed = 00:00:34 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 580 ; free virtual = 8494

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 2502
 Number of Nodes with overlaps = 405
 Number of Nodes with overlaps = 128
 Number of Nodes with overlaps = 32
 Number of Nodes with overlaps = 8
 Number of Nodes with overlaps = 6
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.484  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: f05ece6f

Time (s): cpu = 00:01:12 ; elapsed = 00:00:49 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 590 ; free virtual = 8497

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 22
 Number of Nodes with overlaps = 15
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.665  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 1d38a67aa

Time (s): cpu = 00:01:20 ; elapsed = 00:00:57 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 590 ; free virtual = 8496
Phase 4 Rip-up And Reroute | Checksum: 1d38a67aa

Time (s): cpu = 00:01:20 ; elapsed = 00:00:57 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 590 ; free virtual = 8496

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 1d38a67aa

Time (s): cpu = 00:01:21 ; elapsed = 00:00:57 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 590 ; free virtual = 8496

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1d38a67aa

Time (s): cpu = 00:01:21 ; elapsed = 00:00:57 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 590 ; free virtual = 8496
Phase 5 Delay and Skew Optimization | Checksum: 1d38a67aa

Time (s): cpu = 00:01:21 ; elapsed = 00:00:57 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 590 ; free virtual = 8497

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 19cb1e378

Time (s): cpu = 00:01:24 ; elapsed = 00:00:59 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 590 ; free virtual = 8497
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.665  | TNS=0.000  | WHS=0.024  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 12f0c267e

Time (s): cpu = 00:01:24 ; elapsed = 00:00:59 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 590 ; free virtual = 8497
Phase 6 Post Hold Fix | Checksum: 12f0c267e

Time (s): cpu = 00:01:24 ; elapsed = 00:00:59 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 590 ; free virtual = 8497

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 5.77406 %
  Global Horizontal Routing Utilization  = 6.95315 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 1a7b0d2f1

Time (s): cpu = 00:01:24 ; elapsed = 00:00:59 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 589 ; free virtual = 8496

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 1a7b0d2f1

Time (s): cpu = 00:01:24 ; elapsed = 00:00:59 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 589 ; free virtual = 8496

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 182cf6d2b

Time (s): cpu = 00:01:26 ; elapsed = 00:01:01 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 589 ; free virtual = 8496

Phase 10 Post Router Timing
INFO: [Route 35-20] Post Routing Timing Summary | WNS=0.706  | TNS=0.000  | WHS=0.026  | THS=0.000  |

INFO: [Route 35-61] The design met the timing requirement.
Phase 10 Post Router Timing | Checksum: df8d969a

Time (s): cpu = 00:01:37 ; elapsed = 00:01:08 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 584 ; free virtual = 8483
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:01:37 ; elapsed = 00:01:08 . Memory (MB): peak = 2177.465 ; gain = 0.000 ; free physical = 652 ; free virtual = 8552

Routing Is Done.
70 Infos, 27 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:44 ; elapsed = 00:01:12 . Memory (MB): peak = 2211.418 ; gain = 33.953 ; free physical = 652 ; free virtual = 8552
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2211.418 ; gain = 0.000 ; free physical = 622 ; free virtual = 8548
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.runs/impl_1/sys_w11a_arty_routed.dcp' has been generated.
write_checkpoint: Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 2211.418 ; gain = 0.000 ; free physical = 643 ; free virtual = 8549
Command: report_drc -file sys_w11a_arty_drc_routed.rpt -pb sys_w11a_arty_drc_routed.pb -rpx sys_w11a_arty_drc_routed.rpx
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.runs/impl_1/sys_w11a_arty_drc_routed.rpt.
report_drc completed successfully
report_drc: Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 2221.289 ; gain = 9.871 ; free physical = 654 ; free virtual = 8568
Command: report_methodology -file sys_w11a_arty_methodology_drc_routed.rpt -rpx sys_w11a_arty_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.runs/impl_1/sys_w11a_arty_methodology_drc_routed.rpt.
report_methodology completed successfully
report_methodology: Time (s): cpu = 00:00:39 ; elapsed = 00:00:22 . Memory (MB): peak = 2221.289 ; gain = 0.000 ; free physical = 599 ; free virtual = 8513
Command: report_power -file sys_w11a_arty_power_routed.rpt -pb sys_w11a_arty_power_summary_routed.pb -rpx sys_w11a_arty_power_routed.rpx
INFO: [Power 33-23] Power model is not available for UA
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.
WARNING: [Designutils 20-266] Invalid Voltage Source VCCINTIO for the family artix7. Ignoring the voltage setting.
78 Infos, 29 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
report_power: Time (s): cpu = 00:00:13 ; elapsed = 00:00:10 . Memory (MB): peak = 2221.289 ; gain = 0.000 ; free physical = 579 ; free virtual = 8493
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Sun Feb 10 13:53:47 2019...
