Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017
| Date         : Sun Feb 10 13:51:38 2019
| Host         : athome running 64-bit Ubuntu 16.04.5 LTS
| Command      : report_control_sets -verbose -file sys_w11a_arty_control_sets_placed.rpt
| Design       : sys_w11a_arty
| Device       : xc7a35ti
------------------------------------------------------------------------------------------

Control Set Information

Table of Contents
-----------------
1. Summary
2. Flip-Flop Distribution
3. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets                            |   437 |
| Unused register locations in slices containing registers |  1121 |
+----------------------------------------------------------+-------+


2. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |            2186 |          773 |
| No           | No                    | Yes                    |              47 |           13 |
| No           | Yes                   | No                     |             806 |          397 |
| Yes          | No                    | No                     |            1443 |          547 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |            2093 |          805 |
+--------------+-----------------------+------------------------+-----------------+--------------+


3. Detailed Control Set Information
-----------------------------------

+------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+
|                        Clock Signal                        |                                                                                                                   Enable Signal                                                                                                                   |                                                                                     Set/Reset Signal                                                                                    | Slice Load Count | Bel Load Count |
+------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/tempmon_state_init                                                                                                                    | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/neutral_max_limit_reg[1]                                                                                                          |                1 |              1 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RL11.RLA/n[gshs]                                                                                                                                                                                                                         | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                1 |              1 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/tempmon_state_nxt                                                                                                                     | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/neutral_max_limit_reg[1]                                                                                                          |                1 |              1 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/out[0]                                                                                                                                                                                                                              |                                                                                                                                                                                         |                1 |              1 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RL11.RLA/out[3]                                                                                                                                                                                                                          | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                1 |              1 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/first_fail_detect                                                                                         | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/SS[0]                                                                                                                             |                1 |              1 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/rd_ptr_timing_reg[0][0]                                                                                                           |                1 |              1 |
|  GEN_CLKALL/GEN_CLK23/CLK2                                 |                                                                                                                                                                                                                                                   |                                                                                                                                                                                         |                1 |              2 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  |                                                                                                                                                                                                                                                   | RLINK/SERPORT/RXFIFO/RW_SIZEW0                                                                                                                                                          |                1 |              2 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/SDR_AIB_WE                                                                                                                                                                                                      |                                                                                                                                                                                         |                1 |              2 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/u_ui_top/ui_cmd0/E[0]                                                                                                                                                                           |                                                                                                                                                                                         |                1 |              2 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/RB2CP/out[0]                                                                                                                                                                                                                                |                                                                                                                                                                                         |                2 |              2 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/out[9]                                                                                                                                                                                                                             |                                                                                                                                                                                         |                3 |              3 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SMRB/SMRB/FSM_onehot_R_REGS[state][3]_i_1__5_n_0                                                                                                                                                                                                  |                                                                                                                                                                                         |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | HIO/DEB.DEB_SWI/R_RGB_G_reg[3][0]                                                                                                                                                       |                3 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | HIO/DEB.DEB_SWI/n[dref]                                                                                                                                                                 |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | HIO/DEB.DEB_SWI/SR[0]                                                                                                                                                                   |                2 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/u_ui_top/ui_cmd0/data_buf_address_counter.data_buf_addr_cnt_r_reg[3]_0[0]                                                                                                                       | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/reset_reg_n_0                                                                                                                         |                1 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/mc0/read_data_indx.rd_data_indx_r_reg[0][0]                                                                                                                                          | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/reset_reg_n_0                                                                                                                         |                1 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_queue0/E[0]                                                                                                                                  |                                                                                                                                                                                         |                1 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_queue0/E[0]                                                                                                                                  |                                                                                                                                                                                         |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | HIO/DEB.DEB_SWI/R_RGB_B_reg[3]                                                                                                                                                          |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | MEMCTL/SR2MIG/REQFIFO/RW_SIZEW0                                                                                                                                                         |                2 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/IIST.I0/n[ste_sbe]                                                                                                                                                                                                                       | SYS70/W11A/SEQ/R_REGS_reg[acr_ac][3][0]                                                                                                                                                 |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/IIST.I0/n[ste_sie]                                                                                                                                                                                                                       | SYS70/W11A/SEQ/R_REGS_reg[acr_ac][3][0]                                                                                                                                                 |                2 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cnt_shift_r_reg[0][0]                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/cnt_shift_r_reg[0][0]                                                                                                             |                1 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/cal2_state_r                                                                                                                            | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/my_empty_reg[8]                                                                                                                   |                3 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_wr_cnt[3]_i_2_n_0                                                                                                                  | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_wr_cnt[3]_i_1_n_0                                                        |                1 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/reg_ctrl_cnt_r                                                                                                                           | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/ddr2_pre_flag_r                                                                |                2 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/num_refresh0                                                                                                                             | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/num_refresh[3]_i_1_n_0                                                         |                1 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/p_0_in0_in                                                                                                                               | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/oclk_wr_cnt[3]_i_1_n_0                                                         |                2 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_num_reads_dec[3]_i_1_n_0                                                                                                         | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/SS[0]                                                                                                                             |                2 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/stable_cnt[3]_i_2_n_0                                                                                                     | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/stable_cnt0                                                     |                1 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/wait_cnt0                                                                                                                 | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/wait_cnt_reg[3]_0[0]                                                                                                              |                1 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/wait_cnt_r0                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/wait_cnt_r[3]_i_1_n_0                               |                2 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/detect_rd_cnt0                                                                                            | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/detect_rd_cnt[3]_i_1_n_0                        |                2 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/FSM_sequential_fine_adj_state_r[3]_i_1_n_0                                                                | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/FSM_sequential_fine_adj_state_r_reg[3][0]                                                                                         |                3 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/R_REGS_reg[lcnt][4]_0                                                                                                                                                                                                              | IBDR_SYS/KW11P.I0/R_REGS[lcnt][4]_i_1_n_0                                                                                                                                               |                2 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/RESFIFO/VAL                                                                                                                                                                                                                         | MEMCTL/SR2MIG/RESFIFO/GCR/GRAY_4.CNT/GCR_RST                                                                                                                                            |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/REQFIFO/RAM/GCW_CE                                                                                                                                                                                                                  | MEMCTL/SR2MIG/REQFIFO/GCW/GRAY_4.CNT/GCW_RST                                                                                                                                            |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | GEN_CLKALL/DIV_CLK0/CE0_MSEC                                                                                                                                                                                                                      | IBDR_SYS/RK11.RKA/R_REGS_reg[ibsel]0                                                                                                                                                    |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/n[waddr]                                                                                                                                                                                                                            |                                                                                                                                                                                         |                2 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/n[stat]                                                                                                                                                                                                                             |                                                                                                                                                                                         |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_REGS_reg[mal_raddr][3]_0                                                                                                                                                                                                          |                                                                                                                                                                                         |                2 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/N_REGS[rbtake_1]                                                                                                                                                                                                                    |                                                                                                                                                                                         |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][5]                                                                                                                                                                                        | RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][29]                                                                                                                             |                2 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | HIORGB/R_LED                                                                                                                                                                                                                                      |                                                                                                                                                                                         |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]_0[0]                                                                                                                                                                                                     | SYS70/DMCMON.I0/R_REGS_reg[dp_ireg_we_n_0_]                                                                                                                                             |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/MMU/SADR/SDR_LOW/SDR_LOW_WE                                                                                                                                                                                                      |                                                                                                                                                                                         |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/R_REGS_reg[d1cnt][0][0]                                                                                                                                                                                                            |                                                                                                                                                                                         |                2 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/R_PSW_reg[cc][0]_1[0]                                                                                                                                                                                                              |                                                                                                                                                                                         |                2 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/R_REGS_reg[lcnt][4]_0                                                                                                                                                                                                              | SYS70/W11A/SEQ/R_REGS_reg[tcnt][4]                                                                                                                                                      |                2 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | HIO/DEB.DEB_SWI/n[dref]                                                                                                                                                                                                                           |                                                                                                                                                                                         |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/CACHE/FSM_onehot_R_REGS[state][3]_i_1__4_n_0                                                                                                                                                                                                | SYS70/RB2CP/SR[0]                                                                                                                                                                       |                2 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RL11.RLA/MEM_0/E[0]                                                                                                                                                                                                                      | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                2 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/IIST.I0/n[pge_pie]                                                                                                                                                                                                                       | SYS70/W11A/SEQ/R_REGS_reg[acr_ac][3][0]                                                                                                                                                 |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/IIST.I0/n[pge_pbe]                                                                                                                                                                                                                       | SYS70/W11A/SEQ/R_REGS_reg[acr_ac][3][0]                                                                                                                                                 |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/DEUNA.XUA/n[pr0pcmd]                                                                                                                                                                                                                     |                                                                                                                                                                                         |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RHRP.RPA/FSM_onehot_R_REGS_reg[state][8]_0                                                                                                                                                                                               | SYS70/W11A/VMBOX/FSM_onehot_R_REGS_reg[state][8]_0                                                                                                                                      |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/KW11P.I0/R_REGS[d2cnt][3]_i_1_n_0                                                                                                                                                                                                        |                                                                                                                                                                                         |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/IIST.I0/n[mtc_mttp]                                                                                                                                                                                                                      | SYS70/W11A/SEQ/R_REGS_reg[acr_ac][3][0]                                                                                                                                                 |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/IIST.I0/n[mtc_dsbt]                                                                                                                                                                                                                      | SYS70/W11A/SEQ/R_REGS_reg[acr_ac][3][0]                                                                                                                                                 |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/IIST.I0/n[acr_ac]                                                                                                                                                                                                                        | SYS70/W11A/SEQ/R_REGS_reg[acr_ac][3][0]                                                                                                                                                 |                2 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RL11.RLA/n[iaddr]                                                                                                                                                                                                                        | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                3 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RHRP.RPA/R_REGS[bae][5]_i_2_n_0                                                                                                                                                                                                          | IBDR_SYS/RHRP.RPA/R_REGS[bae][5]_i_1_n_0                                                                                                                                                |                2 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/IIST.I0/R_REGS[msk_bm][3]_i_1_n_0                                                                                                                                                                                                        | SYS70/W11A/SEQ/R_REGS_reg[acr_ac][3][0]                                                                                                                                                 |                1 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/IIST.I0/R_REGS[msk_im][3]_i_1_n_0                                                                                                                                                                                                        | SYS70/W11A/SEQ/R_REGS_reg[acr_ac][3][0]                                                                                                                                                 |                1 |              4 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  | RLINK/SERPORT/UART/RXTX/RX/R_REGS[bcnt][3]_i_2_n_0                                                                                                                                                                                                | RLINK/SERPORT/UART/RXTX/RX/R_REGS[bcnt][3]_i_1_n_0                                                                                                                                      |                1 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/SR2MIG/RESFIFO/RAM/GCW_CE                                                                                                                                                                                                                  | MEMCTL/SR2MIG/RESFIFO/GCW/GRAY_4.CNT/GCW_RST                                                                                                                                            |                1 |              4 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  | RLINK/SERPORT/UART/AB/FSM_onehot_R_REGS[state][3]_i_1__1_n_0                                                                                                                                                                                      | RLINK/SERPORT/CDC_RESET/RS_REQ_S1                                                                                                                                                       |                1 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/regl_dqs_cnt[0]_i_1_n_0                                     |                2 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/incdec_wait_cnt[3]_i_1_n_0                                      |                2 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_wait_cnt[3]_i_1_n_0                                                    |                2 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/ocal_act_wait_cnt[3]_i_1_n_0                                                   |                1 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/SR2MIG/REQFIFO/GCR/GRAY_4.CNT/E[0]                                                                                                                                                                                                         | MEMCTL/SR2MIG/REQFIFO/GCR/GRAY_4.CNT/GCR_RST                                                                                                                                            |                1 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/wait_cnt_r0                                                                                                           | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/wait_cnt_r_reg[0][0]                                                                                                              |                1 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/tap_inc_wait_cnt[3]_i_1_n_0                                                   |                1 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_rst |                1 |              4 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  | RLINK/SERPORT/UART/RXTX/TX/n[sreg]                                                                                                                                                                                                                | RLINK/SERPORT/UART/RXTX/TX/R_REGS[bcnt][3]_i_1__0_n_0                                                                                                                                   |                2 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_rst |                2 |              4 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/temp_mon_enabled.u_tempmon/sync_cntr[3]_i_2_n_0                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/sync_cntr_reg[3][0]                                                                                                               |                1 |              4 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  | RLINK/SERPORT/XONTX/n[oval]12_out                                                                                                                                                                                                                 | RLINK/SERPORT/UART/AB/SR[0]                                                                                                                                                             |                2 |              4 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/UBMAP/SEL/R_REGS_reg[rcol]                                                                                                                                                                                                       |                                                                                                                                                                                         |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/MMU/SEL_SSR3/R_SSR3[ena_ubmap]                                                                                                                                                                                                   | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/MMU/SEL_SSR0/E[0]                                                                                                                                                                                                                | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][10]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[10].ENA.CNT/R_CNT[4]_i_1__16_n_0                                                                                                                                    |                2 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_common0/sel                                                                                                                                                      | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_common0/maint_prescaler.maint_prescaler_r[4]_i_1_n_0                                                   |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[rdlycnt][4]_0                                                                                                                                                                                                         |                                                                                                                                                                                         |                3 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[rdlycnt][4]_0                                                                                                                                                                                                         | SYS70/RB2CP/R_REGS_reg[rdlycnt][4]                                                                                                                                                      |                3 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_VMSTAT_reg[err]                                                                                                                                                                                                                |                                                                                                                                                                                         |                2 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_row_col0/col_arb0/E[0]                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/ui_clk_sync_rst                                                                                                                   |                1 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/n[srpae]20_out                                                                                                                                                                                                                   | IBDR_SYS/TM11.TMA/SR[0]                                                                                                                                                                 |                3 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt[4]_i_1__0_n_0           | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ofifo_rst |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/E[0]                                                                                                                                                                                                                             | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[pr1pcto][0]                                                                                                                                                                                                           | IBDR_SYS/DEUNA.XUA/R_REGS_reg[resreq]__0                                                                                                                                                |                1 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][0]                                                                                                                                                                                                          | SYS70/DMPCNT.I0/PRE[0].ENA.CNT/R_CNT[4]_i_1__27_n_0                                                                                                                                     |                2 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt[4]_i_1_n_0              | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ofifo_rst |                1 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/mc0/bank_mach0/arb_mux0/arb_row_col0/col_arb0/cmd_pipe_plus.mc_data_offset_reg[0]                                          |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/R_REGS_reg[rdlycnt][4]                                                                                                                                                                                                             | SYS70/RB2CP/R_REGS_reg[rdlycnt][4]                                                                                                                                                      |                2 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/not_empty_wait_cnt[4]_i_1_n_0                                                 |                1 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RHRP.RPA/E[0]                                                                                                                                                                                                                            | IBDR_SYS/RHRP.RPA/R_REGS[samax][5]_i_1_n_0                                                                                                                                              |                2 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0                                                                | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0      |                2 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0                                                                | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0      |                1 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0                                                                | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0      |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | RLINK/CORE/RL/R_REGS_reg[saddr][4]                                                                                                                                                      |                4 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/calib_data_offset_0[5]_i_1_n_0                                                 |                1 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RL11.RLA/n[mprem]                                                                                                                                                                                                                        | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/R_REGS_reg[rdlycnt][4]                                                                                                                                                                                                             |                                                                                                                                                                                         |                3 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/u_ui_top/ui_rd_data0/rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0                                                                                                                                       | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/reset_reg_n_0                                                                                                                         |                1 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/immu_cntl[req]                                                                                                                                                                                                                     | SYS70/RB2CP/SR[0]                                                                                                                                                                       |                4 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0                                                                | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0      |                1 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0                                                                | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0      |                2 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0                                                                | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0      |                1 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0                                                                | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0      |                1 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/R_PSW_reg[rset][0]                                                                                                                                                                                                                 |                                                                                                                                                                                         |                2 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cal1_wait_cnt_r[4]_i_1_n_0                                  |                1 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/idel_dec_cnt[4]_i_1_n_0                                                                                               | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/my_empty_reg[8]                                                                                                                   |                3 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][31]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[31].ENA.CNT/clear                                                                                                                                                   |                2 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_row_cnt                                                                                                                          | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0                               |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][25]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[25].ENA.CNT/R_CNT[4]_i_1__1_n_0                                                                                                                                     |                3 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][26]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[26].ENA.CNT/R_CNT[4]_i_1__2_n_0                                                                                                                                     |                2 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_num_writes_dec[4]_i_2_n_0                                                                                                        | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_row0_rd_done1                                                          |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_REGS_reg[drena]                                                                                                                                                                                                                   |                                                                                                                                                                                         |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_LREGS[cnt][15]_i_2_n_0                                                                                                                                                                                                            | RLINK/CORE/RL/R_LREGS[cnt][15]_i_1_n_0                                                                                                                                                  |                1 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][27]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[27].ENA.CNT/R_CNT[4]_i_1__30_n_0                                                                                                                                    |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][28]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[28].ENA.CNT/R_CNT[4]_i_1__3_n_0                                                                                                                                     |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][29]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[29].ENA.CNT/R_CNT[4]_i_1__4_n_0                                                                                                                                     |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][2]                                                                                                                                                                                                          | SYS70/DMPCNT.I0/PRE[2].ENA.CNT/R_CNT[4]_i_1__15_n_0                                                                                                                                     |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][30]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[30].ENA.CNT/R_CNT[4]_i_1__5_n_0                                                                                                                                     |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][24]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[24].ENA.CNT/R_CNT[4]_i_1__0_n_0                                                                                                                                     |                3 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][3]                                                                                                                                                                                                          | SYS70/DMPCNT.I0/PRE[3].ENA.CNT/R_CNT[4]_i_1__11_n_0                                                                                                                                     |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][4]                                                                                                                                                                                                          | SYS70/DMPCNT.I0/PRE[4].ENA.CNT/R_CNT[4]_i_1__26_n_0                                                                                                                                     |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][5]                                                                                                                                                                                                          | SYS70/DMPCNT.I0/PRE[5].ENA.CNT/R_CNT[4]_i_1__20_n_0                                                                                                                                     |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/DOFIFO/FIFO/N_REGS[empty]                                                                                                                                                                                                           |                                                                                                                                                                                         |                3 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][6]                                                                                                                                                                                                          | SYS70/DMPCNT.I0/PRE[6].ENA.CNT/R_CNT[4]_i_1__14_n_0                                                                                                                                     |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][7]                                                                                                                                                                                                          | SYS70/DMPCNT.I0/PRE[7].ENA.CNT/R_CNT[4]_i_1__8_n_0                                                                                                                                      |                2 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/FSM_sequential_wl_state_r[4]_i_1_n_0                                                                                      | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/ui_clk_sync_rst                                                                                                                   |                5 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][8]                                                                                                                                                                                                          | SYS70/DMPCNT.I0/PRE[8].ENA.CNT/R_CNT[4]_i_1__28_n_0                                                                                                                                     |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][9]                                                                                                                                                                                                          | SYS70/DMPCNT.I0/PRE[9].ENA.CNT/R_CNT[4]_i_1__22_n_0                                                                                                                                     |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/n[raddr]                                                                                                                                                                                                                          |                                                                                                                                                                                         |                2 |              5 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  | RLINK/SERPORT/TXFIFO/GCR/GRAY_5.CNT/E[0]                                                                                                                                                                                                          | RLINK/SERPORT/TXFIFO/GCR/GRAY_5.CNT/GCR_RST                                                                                                                                             |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][12]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[12].ENA.CNT/R_CNT[4]_i_1__25_n_0                                                                                                                                    |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][13]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[13].ENA.CNT/R_CNT[4]_i_1__19_n_0                                                                                                                                    |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][11]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[11].ENA.CNT/R_CNT[4]_i_1__10_n_0                                                                                                                                    |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][14]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[14].ENA.CNT/R_CNT[4]_i_1__13_n_0                                                                                                                                    |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/E[0]                                                                                                                                                                                                          | RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/GCR_RST                                                                                                                                             |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/E[0]                                                                                                                                                                                                          | RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/GCW_RST                                                                                                                                             |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][15]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[15].ENA.CNT/R_CNT[4]_i_1__7_n_0                                                                                                                                     |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][16]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[16].ENA.CNT/R_CNT[4]_i_1__29_n_0                                                                                                                                    |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][17]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[17].ENA.CNT/R_CNT[4]_i_1__23_n_0                                                                                                                                    |                2 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pb_cnt_eye_size_r                                                                                                     | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0      |                1 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/n[cpfunc]                                                                                                                                                                                                                           |                                                                                                                                                                                         |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][18]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[18].ENA.CNT/R_CNT[4]_i_1__17_n_0                                                                                                                                    |                2 |              5 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  | RLINK/SERPORT/RXFIFO/GCW/GRAY_5.CNT/E[0]                                                                                                                                                                                                          | RLINK/SERPORT/RXFIFO/GCW/GRAY_5.CNT/GCW_RST                                                                                                                                             |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][19]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[19].ENA.CNT/R_CNT[4]_i_1__9_n_0                                                                                                                                     |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][1]                                                                                                                                                                                                          | SYS70/DMPCNT.I0/PRE[1].ENA.CNT/R_CNT[4]_i_1__21_n_0                                                                                                                                     |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][20]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[20].ENA.CNT/R_CNT[4]_i_1__24_n_0                                                                                                                                    |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_REGS_reg[rcol]                                                                                                                                                                                                                    |                                                                                                                                                                                         |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_REGS_reg[mode][1]                                                                                                                                                                                                                 |                                                                                                                                                                                         |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][21]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[21].ENA.CNT/R_CNT[4]_i_1__18_n_0                                                                                                                                    |                2 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][22]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[22].ENA.CNT/R_CNT[4]_i_1__12_n_0                                                                                                                                    |                3 |              5 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS_reg[psig_n_0_][23]                                                                                                                                                                                                         | SYS70/DMPCNT.I0/PRE[23].ENA.CNT/R_CNT[4]_i_1__6_n_0                                                                                                                                     |                2 |              5 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/dec_cnt[5]_i_1_n_0                                                                                        | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/en_cnt_div4.enable_wrlvl_cnt_reg[2]                                                                                               |                3 |              6 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RHRP.RPA/iscinc11_out                                                                                                                                                                                                                    | IBDR_SYS/RHRP.RPA/n[sc]                                                                                                                                                                 |                3 |              6 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RHRP.RPA/E[0]                                                                                                                                                                                                                            | IBDR_SYS/RHRP.RPA/R_REGS[samax][3]_i_1_n_0                                                                                                                                              |                1 |              6 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/CACHE/CMEM_TAG/E[0]                                                                                                                                                                                                                         | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                2 |              6 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/nstatus[intack]                                                                                                                                                                                                                    | SYS70/RB2CP/SR[0]                                                                                                                                                                       |                4 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_stg2_reg_l_timing[5]_i_1_n_0                             |                1 |              6 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/R_SHC_reg[0][0]                                                                                                                                                                                                                    | SYS70/W11A/SEQ/R_SHC_reg[4][0]                                                                                                                                                          |                3 |              6 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/UBMAP/SEL/iwe2                                                                                                                                                                                                                   |                                                                                                                                                                                         |                2 |              6 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/UBMAP/SEL/R_REGS_reg[ibracc]_rep__0[0]                                                                                                                                                                                           | SYS70/RB2CP/SR[0]                                                                                                                                                                       |                2 |              6 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/n[rcolw]                                                                                                                                                                                                                         |                                                                                                                                                                                         |                1 |              6 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[cr_distrap][0]                                                                                                                                                                                                        | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                3 |              6 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[crunit][1][0]                                                                                                                                                                                                         | IBDR_SYS/TM11.TMA/SR[0]                                                                                                                                                                 |                2 |              6 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/RB2CP/R_REGS[addr][21]_i_1_n_0                                                                                                                                                                                                              |                                                                                                                                                                                         |                2 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/fine_inc[0][5]_i_1_n_0                                                                                                    | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/corse_cnt_reg[1][0]                                                                                                               |                3 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/inc_cnt                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/ui_clk_sync_rst                                                                                                                   |                3 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dec_cnt                                                                                              | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/ui_clk_sync_rst                                                                                                                   |                2 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/wl_tap_count_r[5]_i_1_n_0                                                                                                 | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/po_rdval_cnt_reg[0][0]                                                                                                            |                4 |              6 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | SYS70/W11A/SEQ/R_CPUERR_reg[illhlt]0                                                                                                                                                    |                5 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest[0][5]_i_1_n_0                                                                                                    | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/po_rdval_cnt_reg[0][0]                                                                                                            |                1 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0                                                                                  | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/my_empty_reg[8]                                                                                                                   |                1 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/first_fail_detect                                                                                         | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/en_cnt_div4.enable_wrlvl_cnt_reg[2]                                                                                               |                2 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/p_0_in22_out                                                                                              | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/en_cnt_div4.enable_wrlvl_cnt_reg[2]                                                                                               |                1 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/rd_byte_data_offset                                                                                       | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/rd_byte_data_offset[0][5]_i_1_n_0               |                2 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/first_edge_taps_r[5]_i_2_n_0                                                                                          | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/first_edge_taps_r[5]_i_1_n_0                                |                2 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/rdlvl_dqs_tap_cnt_r                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/dqs_wl_po_stg2_c_incdec_reg[0]                                                                                                    |                1 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/smallest[1][5]_i_1_n_0                                                                                                    | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/po_rdval_cnt_reg[0][0]                                                                                                            |                1 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/fine_inc[1][5]_i_1_n_0                                                                                                    | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/corse_cnt_reg[1][0]                                                                                                               |                5 |              6 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | SYS70/RB2CP/SS[0]                                                                                                                                                                       |                2 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/right_edge_taps_r[5]_i_1_n_0                                                                                          | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/my_empty_reg[8]                                                                                                                   |                2 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/p_1_out[5]                                                                                                |                                                                                                                                                                                         |                1 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_rdval_cnt[5]_i_1_n_0                                                                                               | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/dqs_wl_po_stg2_c_incdec_reg[0]                                                                                                    |                3 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/tap_cnt_cpt_r                                                                                                         | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/tap_cnt_cpt_r_reg[0][0]                                                                                                           |                1 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_common0/refresh_timer_r0_0                                                                                                                                       | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_common0/refresh_timer.refresh_timer_r[5]_i_1_n_0                                                       |                3 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/FSM_sequential_cal1_state_r[5]_i_1_n_0                                                                                | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/cnt_pwron_r_reg[8][0]                                                                                                             |                4 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/second_edge_taps_r[5]_i_2_n_0                                                                                         | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/second_edge_taps_r[5]_i_1_n_0                               |                3 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/fine_dec_cnt_reg[5]_i_1_n_0                                                                                               | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/en_cnt_div4.enable_wrlvl_cnt_reg[2]                                                                                               |                4 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/stable_pass_cnt                                                                                           | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/ui_clk_sync_rst                                                                                                                   |                2 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cnt_idel_dec_cpt_r[5]_i_1_n_0                                                                                         |                                                                                                                                                                                         |                5 |              6 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delaydec_cnt_r0                                                                                               | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delaydec_cnt_r[5]_i_1_n_0                           |                1 |              6 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[ba][15][0]                                                                                                                                                                                                            | IBDR_SYS/TM11.TMA/SR[0]                                                                                                                                                                 |                2 |              7 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  | RLINK/SERPORT/UART/AB/n[mcnt]                                                                                                                                                                                                                     | RLINK/SERPORT/CDC_RESET/RS_REQ_S1                                                                                                                                                       |                3 |              7 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/SDR_SLF_WE                                                                                                                                                                                                      |                                                                                                                                                                                         |                2 |              7 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[buf][6][0]                                                                                                                                                                                                            | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                2 |              7 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][5]                                                                                                                                                                                        | RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][12]                                                                                                                             |                4 |              7 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_PIRQ_reg[7][0]                                                                                                                                                                                                                 | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                3 |              7 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/mc0/bank_mach0/bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1_n_0                                                                                                       |                                                                                                                                                                                         |                3 |              7 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/p_0_in_0[0]                                                                                                                                                                                                                        |                                                                                                                                                                                         |                4 |              7 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/UBMAP/SEL/iwe0                                                                                                                                                                                                                   |                                                                                                                                                                                         |                2 |              7 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  | RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_2__0_n_0                                                                                                                                                                                 | RLINK/SERPORT/UART/AB/in1                                                                                                                                                               |                3 |              7 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | GEN_CLKALL/DIV_CLK0/CE0_USEC                                                                                                                                                                                                                      |                                                                                                                                                                                         |                3 |              7 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  |                                                                                                                                                                                                                                                   | RLINK/SERPORT/UART/AB/in1                                                                                                                                                               |                4 |              7 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/cnt_cmd_r[6]_i_1_n_0                                                           |                2 |              7 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RHRP.RPA/n[ffunc]                                                                                                                                                                                                                        |                                                                                                                                                                                         |                4 |              7 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_timing[3]_i_1__0_n_0       | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ofifo_rst |                3 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/R_REGS[wrbuf][127]_i_1_n_0                                                                                                                                                                                                          | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                3 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/R_REGS[wrbuf][23]_i_1_n_0                                                                                                                                                                                                           | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                4 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/R_REGS[wrbuf][119]_i_1_n_0                                                                                                                                                                                                          | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                3 |              8 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_timing[3]_i_1__2_n_0       | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ofifo_rst |                2 |              8 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr0                           | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ofifo_rst |                3 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RHRP.RPA/R_REGS[idlycnt][7]_i_1_n_0                                                                                                                                                                                                      |                                                                                                                                                                                         |                4 |              8 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr0__0                        | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ofifo_rst |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/MEM_1_WE                                                                                                                                                                                                                         |                                                                                                                                                                                         |                2 |              8 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_timing[3]_i_1_n_0          | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ofifo_rst |                3 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/MEM_0_WE                                                                                                                                                                                                                         |                                                                                                                                                                                         |                2 |              8 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr0__0                        | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ofifo_rst |                3 |              8 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_reads[7]_i_2_n_0                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_reads05_out                                                              |                3 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/UBMAP/SEL/iwe1                                                                                                                                                                                                                   |                                                                                                                                                                                         |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[dreg][15][1]                                                                                                                                                                                                          | SYS70/RB2CP/SR[0]                                                                                                                                                                       |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[bc][15][1]                                                                                                                                                                                                            | IBDR_SYS/TM11.TMA/SR[0]                                                                                                                                                                 |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[idlyval][0][0]                                                                                                                                                                                                        |                                                                                                                                                                                         |                1 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[pbuf][0][0]                                                                                                                                                                                                           | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[rbuf][0]_0[0]                                                                                                                                                                                                         | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                5 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[dreg][15][0]                                                                                                                                                                                                          | SYS70/RB2CP/SR[0]                                                                                                                                                                       |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[da][8][1]                                                                                                                                                                                                             | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                3 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[da][8][0]                                                                                                                                                                                                             | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[rbuf][0]_2[0]                                                                                                                                                                                                         | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                7 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[rbuf][0]_3[0]                                                                                                                                                                                                         | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                7 |              8 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_row_cnt_ocal                                                                                                                     | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_row_cnt_ocal0                                                          |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[xbuf][7][0]                                                                                                                                                                                                           | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[bc][15][0]                                                                                                                                                                                                            | IBDR_SYS/TM11.TMA/SR[0]                                                                                                                                                                 |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[ba][15][1]                                                                                                                                                                                                            | IBDR_SYS/TM11.TMA/SR[0]                                                                                                                                                                 |                3 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[xbuf][7]_0[0]                                                                                                                                                                                                         | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                3 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/R_REGS[wrbuf][15]_i_1_n_0                                                                                                                                                                                                           | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                2 |              8 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/rd_ptr_timing[3]_i_1__1_n_0       | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ofifo_rst |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/RB2CP/E[0]                                                                                                                                                                                                                                  | SYS70/RB2CP/SR[0]                                                                                                                                                                       |                3 |              8 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_ptr0                           | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ofifo_rst |                2 |              8 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  | RLINK/SERPORT/UART/RXTX/TX/R_REGS[sreg][7]_i_1_n_0                                                                                                                                                                                                |                                                                                                                                                                                         |                3 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_LREGS[din][15]_i_1_n_0                                                                                                                                                                                                            |                                                                                                                                                                                         |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_LREGS[lcmd][7]_i_1_n_0                                                                                                                                                                                                            |                                                                                                                                                                                         |                1 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_REGS_reg[laddr][0]                                                                                                                                                                                                                |                                                                                                                                                                                         |                4 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/R_REGS[wrbuf][39]_i_1_n_0                                                                                                                                                                                                           | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/R_REGS[wrbuf][47]_i_1_n_0                                                                                                                                                                                                           | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/R_REGS[wrbuf][95]_i_1_n_0                                                                                                                                                                                                           | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/R_REGS[wrbuf][71]_i_1_n_0                                                                                                                                                                                                           | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                3 |              8 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  | RLINK/SERPORT/UART/RXTX/RX/E[0]                                                                                                                                                                                                                   | RLINK/SERPORT/UART/AB/in1                                                                                                                                                               |                1 |              8 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/E[0]                                                                                                                  |                                                                                                                                                                                         |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/R_REGS[wrbuf][55]_i_1_n_0                                                                                                                                                                                                           | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                3 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_LREGS[din][7]_i_1_n_0                                                                                                                                                                                                             |                                                                                                                                                                                         |                3 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/REG70/R_REGS_reg[mbrk]0__0                                                                                                                                                                                                             | SYS70/W11A/SEQ/CRESET                                                                                                                                                                   |                4 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/R_REGS[wrbuf][63]_i_1_n_0                                                                                                                                                                                                           | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/R_REGS[wrbuf][87]_i_1_n_0                                                                                                                                                                                                           | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/R_REGS[wrbuf][7]_i_1_n_0                                                                                                                                                                                                            | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                2 |              8 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  | RLINK/SERPORT/XONTX/R_REGS_reg[ibuf]0                                                                                                                                                                                                             | RLINK/SERPORT/UART/AB/in1                                                                                                                                                               |                1 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/IBMON.I0/BRAM0/sv_ram_reg_0                                                                                                                                                                                                                 |                                                                                                                                                                                         |                3 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/out[1]                                                                                                                                                                                                                              |                                                                                                                                                                                         |                4 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/R_REGS[wrbuf][79]_i_1_n_0                                                                                                                                                                                                           | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                3 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RL11.RLA/MEM_0/imem_we0                                                                                                                                                                                                                  |                                                                                                                                                                                         |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RL11.RLA/MEM_0/imem_we1                                                                                                                                                                                                                  |                                                                                                                                                                                         |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/DOFIFO/FIFO/n[dinl]                                                                                                                                                                                                                 |                                                                                                                                                                                         |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/MMU/SSR12/SEL_SSR1/E[0]                                                                                                                                                                                                          | SYS70/W11A/SEQ/CRESET                                                                                                                                                                   |                5 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/R_REGS[wrbuf][111]_i_1_n_0                                                                                                                                                                                                          | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/MMU/SADR/SAR_LOW/SAR_LOW_WE                                                                                                                                                                                                      |                                                                                                                                                                                         |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RHRP.RPA/MEM_1/imem_we1                                                                                                                                                                                                                  |                                                                                                                                                                                         |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/MMU/SADR/SAR_HIGH/SAR_HIGH_WE                                                                                                                                                                                                    |                                                                                                                                                                                         |                2 |              8 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/mpr_rd_rise0_prev_r0                                                                                                  |                                                                                                                                                                                         |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RHRP.RPA/MEM_0/imem_we0                                                                                                                                                                                                                  |                                                                                                                                                                                         |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/SEL/E[0]                                                                                                                                                                                                                         | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                3 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/p_0_in_0[1]                                                                                                                                                                                                                        |                                                                                                                                                                                         |                4 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/R_REGS[wrbuf][31]_i_1_n_0                                                                                                                                                                                                           | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/R_REGS[wrbuf][103]_i_1_n_0                                                                                                                                                                                                          | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                3 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/IIST.I0/R_REGS[stc_count][7]_i_1_n_0                                                                                                                                                                                                     | SYS70/W11A/SEQ/R_REGS_reg[acr_ac][3][0]                                                                                                                                                 |                4 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/IIST.I0/R_REGS[tcnt256][7]_i_2_n_0                                                                                                                                                                                                       | IBDR_SYS/IIST.I0/R_REGS[tcnt256][7]_i_1_n_0                                                                                                                                             |                3 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/MMU/SSR12/SEL_SSR1/R_SSR1_reg[ra_num][0]_0[0]                                                                                                                                                                                    | SYS70/W11A/SEQ/CRESET                                                                                                                                                                   |                5 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state_n_0_][5]                                                                                                                                                                                               |                                                                                                                                                                                         |                1 |              8 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/u_ui_top/ui_wr_data0/wr_data_addr_le                                                                                                                                                            | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/reset_reg_n_0                                                                                                                         |                2 |              8 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  | RLINK/SERPORT/UART/RXTX/RX/n[sreg]                                                                                                                                                                                                                |                                                                                                                                                                                         |                2 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_LREGS[atocnt][7]_i_1_n_0                                                                                                                                                                                                          |                                                                                                                                                                                         |                5 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_LREGS[cnt][7]_i_1_n_0                                                                                                                                                                                                             |                                                                                                                                                                                         |                4 |              8 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/CD2B/R_REGS[data][7]_i_1__0_n_0                                                                                                                                                                                                        |                                                                                                                                                                                         |                3 |              9 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/clear                                                                          |                2 |              9 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | RLINK/CORE/RL/R_BREGS[btocnt][8]_i_1_n_0                                                                                                                                                |                3 |              9 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/pwron_ce_r                                                                                                                               | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/cnt_pwron_r_reg[8][0]                                                                                                             |                4 |              9 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/stg1_wr_rd_cnt[8]_i_1_n_0                                                                                                                |                                                                                                                                                                                         |                4 |              9 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RL11.RLA/FSM_onehot_R_REGS[state][8]_i_1__0_n_0                                                                                                                                                                                          | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                6 |              9 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/cnt_dllk_zqinit_r                                                              |                2 |              9 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RL11.RLA/n[seekcac]                                                                                                                                                                                                                      | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                4 |              9 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_REGS_reg[laddr][8]                                                                                                                                                                                                                |                                                                                                                                                                                         |                4 |              9 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/wl_corse_cnt[0][1][2]_i_1_n_0                                                                                             | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/po_rdval_cnt_reg[0][0]                                                                                                            |                2 |              9 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/wl_corse_cnt                                                                                                              | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/corse_cnt_reg[1][0]                                                                                                               |                3 |              9 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_rdval_cnt[8]_i_1_n_0                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/po_rdval_cnt_reg[0][0]                                                                                                            |                4 |              9 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[laddr][8]                                                                                                                                                                                                             |                                                                                                                                                                                         |                5 |              9 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS[paddr_iopage][8]_i_1_n_0                                                                                                                                                                                                  |                                                                                                                                                                                         |                3 |              9 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/tempmon_state_nxt                                                                                                                     | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/FSM_sequential_fine_adj_state_r_reg[3][0]                                                                                         |                5 |             10 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/complex_address0                                                                                                                         | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/complex_address_reg[0]                                                                                                            |                4 |             10 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/E[0]                                                                                                                                                                                                                                |                                                                                                                                                                                         |                5 |             10 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | GEN_CLKALL/DIV_CLK0/n[mcnt]                                                                                                                                                                                                                       |                                                                                                                                                                                         |                3 |             10 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/SEL__0/n[anena]                                                                                                                                                                                                                     |                                                                                                                                                                                         |                2 |             10 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  | GEN_CLKALL/DIV_CLK1/n[mcnt]                                                                                                                                                                                                                       |                                                                                                                                                                                         |                4 |             10 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/RBMON.I0/R_REGS[rbnbusy][9]_i_2_n_0                                                                                                                                                                                                         | RLINK/RBMON.I0/R_REGS[rbnbusy][9]_i_1_n_0                                                                                                                                               |                4 |             10 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RL11.RLA/n[seekcan]                                                                                                                                                                                                                      | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                4 |             10 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/IBMON.I0/R_REGS[ibnbusy][9]_i_2_n_0                                                                                                                                                                                                         | SYS70/IBMON.I0/R_REGS[ibnbusy][9]_i_1_n_0                                                                                                                                               |                4 |             10 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | IBDR_SYS/DEUNA.XUA/R_REGS_reg[resreq]__0                                                                                                                                                |                8 |             10 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_BREGS[dcnt][10]_i_2_n_0                                                                                                                                                                                                           | RLINK/CORE/RL/dcnt_clear                                                                                                                                                                |                4 |             11 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_BREGS[cnt][10]_i_1_n_0                                                                                                                                                                                                            |                                                                                                                                                                                         |                5 |             11 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state_n_0_][4]                                                                                                                                                                                               |                                                                                                                                                                                         |                2 |             11 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/temp_mon_enabled.u_tempmon/device_temp_r[11]_i_1_n_0                                                                                                                                                              |                                                                                                                                                                                         |               12 |             12 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/sr_valid_r2                                                                                                           | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/clear                                                                                                                             |                3 |             12 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/tempmon_state_init                                                                                                                    | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/FSM_sequential_fine_adj_state_r_reg[3][0]                                                                                         |                3 |             12 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/CDC_TEMP/CDC_ENA/BUSY                                                                                                                                                                                                                      |                                                                                                                                                                                         |                3 |             12 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2_n_0                                                                                                                                                                                                         | RLINK/CORE/B2CD/n[rtaddrb_red]17_out                                                                                                                                                    |                3 |             12 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS_reg[rtaddra][0]                                                                                                                                                                                                 | RLINK/CORE/RL/addra_clear                                                                                                                                                               |                3 |             12 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS_reg[bcnt][0]                                                                                                                                                                                                    |                                                                                                                                                                                         |                3 |             12 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/CDC_TEMP/CDC_ENA/POUT                                                                                                                                                                                                                      |                                                                                                                                                                                         |               12 |             12 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/p_21_out                                                                                                                  | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/corse_cnt_reg[1][0]                                                                                                               |                2 |             12 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_full[1]_i_1__0_n_0 | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ififo_rst |                5 |             12 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SMRB/SMRB/n[temp]                                                                                                                                                                                                                                 |                                                                                                                                                                                         |                4 |             12 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_full[1]_i_1_n_0    | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ififo_rst |                3 |             12 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/n[hilim]                                                                                                                                                                                                                         |                                                                                                                                                                                         |                4 |             12 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt1_en_r                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/clear                                                                                                                             |                3 |             12 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/n[lolim]                                                                                                                                                                                                                         |                                                                                                                                                                                         |                4 |             12 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/FSM_onehot_R_BREGS[state][12]_i_1_n_0                                                                                                                                                                                               |                                                                                                                                                                                         |                8 |             13 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/po_rdval_cnt_reg[0][0]                                                                                                            |                6 |             13 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  | RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_1_n_0                                                                                                                                                                                                |                                                                                                                                                                                         |                4 |             13 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | IBDR_SYS/TM11.TMA/SR[0]                                                                                                                                                                 |                8 |             13 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/IBMON.I0/n[ibndly]                                                                                                                                                                                                                          | SYS70/IBMON.I0/R_REGS[ibndly][0]_i_1_n_0                                                                                                                                                |                4 |             14 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/n[rbndly]                                                                                                                                                                                                                           | RLINK/CORE/RL/R_REGS_reg[rbndly][0]                                                                                                                                                     |                4 |             14 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[addrsame]0                                                                                                                                                                                                            |                                                                                                                                                                                         |                4 |             14 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_REGS_reg[addr][12]                                                                                                                                                                                                                |                                                                                                                                                                                         |                7 |             15 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/p_0_in__0[0]                                                                                                                                                                                                                     | IBDR_SYS/DEUNA.XUA/R_REGS_reg[resreq]__0                                                                                                                                                |                4 |             15 |
|  GEN_CLKALL/GEN_CLK23/CLK3                                 |                                                                                                                                                                                                                                                   | MEMCTL/CDC_SYSRST/RS_REQ_S1                                                                                                                                                             |                2 |             15 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_REGS_reg[hilim][15]                                                                                                                                                                                                               |                                                                                                                                                                                         |                3 |             15 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_REGS_reg[lolim][15]                                                                                                                                                                                                               |                                                                                                                                                                                         |                6 |             15 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  | RLINK/SERPORT/UART/AB/n[ccnt]                                                                                                                                                                                                                     | RLINK/SERPORT/CDC_RESET/RS_REQ_S1                                                                                                                                                       |                5 |             15 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMCMON.I0/R_REGS_reg[dp_ireg_we_n_0_]                                                                                                                                                                                                       |                                                                                                                                                                                         |                6 |             15 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/R_REGS_reg[dp_pc_fet][15]_0                                                                                                                                                                                                        |                                                                                                                                                                                         |                5 |             15 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/n[hilim]                                                                                                                                                                                                                            |                                                                                                                                                                                         |                5 |             15 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/n[lolim]                                                                                                                                                                                                                            |                                                                                                                                                                                         |                6 |             15 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/corse_cnt_reg[1][0]                                                                                                               |                8 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_REGS_reg[rbdata]0                                                                                                                                                                                                                 |                                                                                                                                                                                         |                7 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/R_REGS_reg[dp_dres_val]                                                                                                                                                                                                            |                                                                                                                                                                                         |                2 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/R_IREG_reg[15][0]                                                                                                                                                                                                                  |                                                                                                                                                                                         |                8 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/n[hilim]_2                                                                                                                                                                                                                          |                                                                                                                                                                                         |                4 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/ICRC/icrcena                                                                                                                                                                                                                        | RLINK/CORE/RL/out[0]                                                                                                                                                                    |                7 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/n[lolim]_0                                                                                                                                                                                                                          |                                                                                                                                                                                         |                5 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/n[rbdout]                                                                                                                                                                                                                           |                                                                                                                                                                                         |                7 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/DM_STAT_DP[cpdout_we]                                                                                                                                                                                                              | SYS70/W11A/SEQ/CRESET                                                                                                                                                                   |                6 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/N_REGS[dp_dres_val]                                                                                                                                                                                                                |                                                                                                                                                                                         |                4 |             16 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/mc0/pointer_we                                                                                                                                                                       |                                                                                                                                                                                         |                2 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/UBMAP/SEL/E[0]                                                                                                                                                                                                                   | SYS70/RB2CP/SR[0]                                                                                                                                                                       |                6 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/E[0]                                                                                                                                                                                                          |                                                                                                                                                                                         |                2 |             16 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  | RLINK/SERPORT/RXFIFO/GCW/GRAY_5.CNT/E[0]                                                                                                                                                                                                          |                                                                                                                                                                                         |                2 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | MEMCTL/SR2MIG/R_REGS[wrpend][15]_i_1_n_0                                                                                                                                                |                7 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[csb][0]_0                                                                                                                                                                                                             | IBDR_SYS/KW11P.I0/R_REGS[csb][15]_i_1_n_0                                                                                                                                               |                4 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/KW11P.I0/R_REGS[ctr][15]_i_1_n_0                                                                                                                                                                                                         | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |                5 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/ibtake134_out                                                                                                                                                                                                                    |                                                                                                                                                                                         |                8 |             16 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 |                4 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SMRB/SM_EOS                                                                                                                                                                                                                                       |                                                                                                                                                                                         |                4 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/R_DTMP_reg[0][0]                                                                                                                                                                                                                   |                                                                                                                                                                                         |               13 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/WE1                                                                                                                                                                                                                                |                                                                                                                                                                                         |                2 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/DOFIFO/FIFO/E[0]                                                                                                                                                                                                                    | RLINK/CORE/RL/out[0]                                                                                                                                                                    |                7 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[sreg][0][0]                                                                                                                                                                                                           | SYS70/RB2CP/SR[0]                                                                                                                                                                       |                5 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/R_DD_L_reg[0][0]                                                                                                                                                                                                                   |                                                                                                                                                                                         |                7 |             16 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/u_ui_top/ui_wr_data0/occupied_counter.occ_cnt[15]_i_1_n_0                                                                                                                                       | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/reset_reg_n_0                                                                                                                         |                5 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/E[0]                                                                                                                                                                                                                               | SYS70/W11A/SEQ/CRESET                                                                                                                                                                   |                7 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/DOUT0_0[0]                                                                                                                                                                                                                         |                                                                                                                                                                                         |                8 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/DOUT0[0]                                                                                                                                                                                                                           |                                                                                                                                                                                         |                9 |             16 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/R_REGS_reg[addrsame]0                                                                                                                                                                                                               |                                                                                                                                                                                         |                3 |             17 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/E[0]                                                                                                                                                                                                                                | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                5 |             18 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RHRP.RPA/FSM_onehot_R_REGS_reg[state][8]_0                                                                                                                                                                                               |                                                                                                                                                                                         |               13 |             18 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/n[rdtag]                                                                                                                                                                                                                            | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |                3 |             18 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/n[wacc]                                                                                                                                                                                                                          | SYS70/RB2CP/SR[0]                                                                                                                                                                       |               14 |             18 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/u_ui_top/ui_cmd0/app_addr_r10                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/reset_reg_n_0                                                                                                                         |                5 |             18 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/ui_clk_sync_rst                                                                                                                   |               12 |             19 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_common0/zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0                                                                                                                  | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_common0/zq_timer_r0                                                                                    |                5 |             20 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/u_ui_top/ui_cmd0/E[0]                                                                                                                                                                           | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/reset_reg_n_0                                                                                                                         |                5 |             20 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | SYS70/DMPCNT.I0/R_REGS[psig][31]_i_1_n_0                                                                                                                                                |               12 |             21 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/DOFIFO/FIFO/RAM/N_REGS[full]                                                                                                                                                                                                        |                                                                                                                                                                                         |                4 |             21 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/mc0/bank_mach0/bank_cntrl[0].bank0/bank_queue0/idle_r_lcl_reg_0                                                                                                                      |                                                                                                                                                                                         |                5 |             21 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_queue0/idle_r_lcl_reg_0                                                                                                                      |                                                                                                                                                                                         |                3 |             21 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/my_empty_reg[8]                                                                                                                   |               16 |             22 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/FSM_sequential_fine_adj_state_r_reg[3][0]                                                                                         |                8 |             23 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]_0[0]                                                                                                                                                                                                     |                                                                                                                                                                                         |                3 |             24 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/en_cnt_div4.enable_wrlvl_cnt_reg[2]                                                                                               |               14 |             25 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pb_detect_edge_setup                                        |               14 |             25 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/R_REGS_reg[vm_req]                                                                                                                                                                                                                 |                                                                                                                                                                                         |               11 |             26 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/out[0]                                                                                                                                                                                                                           | SYS70/RB2CP/SR[0]                                                                                                                                                                       |               16 |             27 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][5]                                                                                                                                                                                        |                                                                                                                                                                                         |               18 |             29 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_iodelay_ctrl/rst_sync_r1_reg                                                                                                                          |                9 |             30 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | SYS70/W11A/SEQ/R_REGS_reg[acr_ac][3][0]                                                                                                                                                 |               20 |             30 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | IBDR_SYS/RK11.RKA/R_REGS_reg[ibsel]0                                                                                                                                                    |               20 |             31 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/n[res_do]                                                                                                                                                                                                                           | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |               14 |             32 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/R_REGS_reg[vm_addr_1][0]_0                                                                                                                                                                                                         |                                                                                                                                                                                         |                8 |             32 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/DMPCNT.I0/R_REGS[dout][31]_i_1_n_0                                                                                                                                                                                                          |                                                                                                                                                                                         |                9 |             32 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/cnt_pwron_r_reg[8][0]                                                                                                             |               10 |             34 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/VMBOX/R_REGS_reg[vm_ack]                                                                                                                                                                                                               |                                                                                                                                                                                         |               15 |             34 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/dqs_wl_po_stg2_c_incdec_reg[0]                                                                                                    |               16 |             37 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/complex_address_reg[0]                                                                                                            |               27 |             39 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/CACHE/out[0]                                                                                                                                                                                                                                | SYS70/RB2CP/SR[0]                                                                                                                                                                       |               20 |             41 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | IBDR_SYS/RHRP.RPA/E[0]                                                                                                                                                                                                                            |                                                                                                                                                                                         |               20 |             41 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/maintenance_request.maint_srx_r_lcl_reg                                                                                           |               18 |             43 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/SS[0]                                                                                                                             |               14 |             44 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/out[2]                                                                                                                                                                                                                             | SYS70/RB2CP/SR[0]                                                                                                                                                                       |               33 |             44 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | SYS70/RB2CP/SR[0]                                                                                                                                                                       |               31 |             46 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/neutral_max_limit_reg[1]                                                                                                          |               17 |             47 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   | MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/init_complete_r_timing_reg[0]                                                                                                     |               16 |             49 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                                                                                                                                                  |               41 |             54 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/rd_active_r                                                                                                                             |                                                                                                                                                                                         |               18 |             64 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/sr_valid_r_reg_n_0                                                                                                    |                                                                                                                                                                                         |               18 |             64 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/store_sr_r0                                                                                                           |                                                                                                                                                                                         |               20 |             64 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/n[req_addr]                                                                                                                                                                                                                         | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |               17 |             66 |
|  GEN_CLKALL/GEN_CLK1/CLK1                                  |                                                                                                                                                                                                                                                   |                                                                                                                                                                                         |               29 |             76 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en_2               |                                                                                                                                                                                         |               11 |             88 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/wr_en                 |                                                                                                                                                                                         |               11 |             88 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en_3                           |                                                                                                                                                                                         |               14 |            112 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en_5                           |                                                                                                                                                                                         |               14 |            112 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en                             |                                                                                                                                                                                         |               14 |            112 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/wr_en_4                           |                                                                                                                                                                                         |               14 |            112 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | SYS70/W11A/SEQ/FSM_onehot_R_STATE[112]_i_1_n_0                                                                                                                                                                                                    | SYS70/RB2CP/SR[0]                                                                                                                                                                       |               73 |            113 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/RESFIFO/VAL                                                                                                                                                                                                                         | CDC_CLK_LOCKED/SR[0]                                                                                                                                                                    |               26 |            128 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/u_ui_top/ui_wr_data0/app_wdf_rdy_r_copy2                                                                                                                                                        |                                                                                                                                                                                         |               45 |            144 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/SR2MIG/RESFIFO/RAM/GCW_CE                                                                                                                                                                                                                  |                                                                                                                                                                                         |               22 |            176 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK | MEMCTL/MIG_CTL/u_migui_arty_mig/u_memc_ui_top_std/u_ui_top/ui_wr_data0/wdf_rdy_ns                                                                                                                                                                 |                                                                                                                                                                                         |               24 |            192 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  | MEMCTL/SR2MIG/REQFIFO/RAM/GCW_CE                                                                                                                                                                                                                  |                                                                                                                                                                                         |               28 |            224 |
|  GEN_CLKALL/GEN_CLK0/CLK0                                  |                                                                                                                                                                                                                                                   |                                                                                                                                                                                         |              318 |            571 |
|  MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/CLK |                                                                                                                                                                                                                                                   |                                                                                                                                                                                         |              441 |           1595 |
+------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+


+--------+-----------------------+
| Fanout | Number of ControlSets |
+--------+-----------------------+
| 1      |                     7 |
| 2      |                     5 |
| 3      |                     1 |
| 4      |                    69 |
| 5      |                    80 |
| 6      |                    39 |
| 7      |                    14 |
| 8      |                    75 |
| 9      |                    14 |
| 10     |                    10 |
| 11     |                     3 |
| 12     |                    15 |
| 13     |                     4 |
| 14     |                     3 |
| 15     |                    10 |
| 16+    |                    88 |
+--------+-----------------------+


