
*** Running vivado
    with args -log migui_arty.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source migui_arty.tcl


****** Vivado v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source migui_arty.tcl -notrace
Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1177.656 ; gain = 66.996 ; free physical = 1612 ; free virtual = 9317
INFO: [Synth 8-638] synthesizing module 'migui_arty' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/migui_arty.vhd:121]
INFO: [Synth 8-638] synthesizing module 'migui_arty_mig' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/migui_arty_mig.vhd:550]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_iodelay_ctrl' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/clocking/mig_7series_v4_0_iodelay_ctrl.v:80]
INFO: [Synth 8-638] synthesizing module 'IDELAYCTRL' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16506]
INFO: [Synth 8-256] done synthesizing module 'IDELAYCTRL' (1#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16506]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_iodelay_ctrl' (2#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/clocking/mig_7series_v4_0_iodelay_ctrl.v:80]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_clk_ibuf' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/clocking/mig_7series_v4_0_clk_ibuf.v:68]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_clk_ibuf' (3#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/clocking/mig_7series_v4_0_clk_ibuf.v:68]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_tempmon' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/clocking/mig_7series_v4_0_tempmon.v:69]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_tempmon' (4#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/clocking/mig_7series_v4_0_tempmon.v:69]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_infrastructure' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/clocking/mig_7series_v4_0_infrastructure.v:78]
INFO: [Synth 8-638] synthesizing module 'MMCME2_ADV' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20759]
INFO: [Synth 8-256] done synthesizing module 'MMCME2_ADV' (5#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20759]
INFO: [Synth 8-638] synthesizing module 'BUFG' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:607]
INFO: [Synth 8-256] done synthesizing module 'BUFG' (6#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:607]
INFO: [Synth 8-638] synthesizing module 'PLLE2_ADV' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:33019]
INFO: [Synth 8-256] done synthesizing module 'PLLE2_ADV' (7#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:33019]
INFO: [Synth 8-638] synthesizing module 'BUFH' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:806]
INFO: [Synth 8-256] done synthesizing module 'BUFH' (8#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:806]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_infrastructure' (9#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/clocking/mig_7series_v4_0_infrastructure.v:78]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_memc_ui_top_std' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/ip_top/mig_7series_v4_0_memc_ui_top_std.v:72]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_mem_intfc' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/ip_top/mig_7series_v4_0_mem_intfc.v:70]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_mc' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_mc.v:73]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_rank_mach' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_rank_mach.v:71]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_rank_cntrl' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_rank_cntrl.v:79]
INFO: [Synth 8-638] synthesizing module 'SRLC32E' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:43823]
INFO: [Synth 8-256] done synthesizing module 'SRLC32E' (10#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:43823]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_rank_cntrl' (11#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_rank_cntrl.v:79]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_rank_common' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_rank_common.v:72]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_round_robin_arb' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_round_robin_arb.v:121]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_round_robin_arb' (12#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_round_robin_arb.v:121]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_round_robin_arb__parameterized0' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_round_robin_arb.v:121]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_round_robin_arb__parameterized0' (12#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_round_robin_arb.v:121]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_rank_common' (13#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_rank_common.v:72]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_rank_mach' (14#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_rank_mach.v:71]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_bank_mach' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_mach.v:72]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_bank_cntrl' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_cntrl.v:70]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_bank_compare' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_compare.v:74]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_bank_compare' (15#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_compare.v:74]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_bank_state' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_state.v:141]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_bank_state' (16#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_state.v:141]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_bank_queue' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_queue.v:174]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_bank_queue' (17#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_queue.v:174]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_bank_cntrl' (18#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_cntrl.v:70]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_bank_cntrl__parameterized0' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_cntrl.v:70]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_bank_state__parameterized0' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_state.v:141]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_bank_state__parameterized0' (18#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_state.v:141]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_bank_queue__parameterized0' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_queue.v:174]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_bank_queue__parameterized0' (18#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_queue.v:174]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_bank_cntrl__parameterized0' (18#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_cntrl.v:70]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_bank_common' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_common.v:73]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_bank_common' (19#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_common.v:73]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_arb_mux' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_arb_mux.v:69]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_arb_row_col' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_arb_row_col.v:83]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_round_robin_arb__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_round_robin_arb.v:121]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_round_robin_arb__parameterized1' (19#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_round_robin_arb.v:121]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_arb_row_col' (20#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_arb_row_col.v:83]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_arb_select' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_arb_select.v:75]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_arb_select' (21#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_arb_select.v:75]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_arb_mux' (22#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_arb_mux.v:69]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_bank_mach' (23#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_bank_mach.v:72]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_col_mach' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_col_mach.v:88]
INFO: [Synth 8-638] synthesizing module 'RAM32M' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:37094]
INFO: [Synth 8-256] done synthesizing module 'RAM32M' (24#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:37094]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_col_mach' (25#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_col_mach.v:88]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_mc' (26#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/controller/mig_7series_v4_0_mc.v:73]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_phy_top' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_top.vhd:371]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_mc_phy_wrapper' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy_wrapper.v:71]
INFO: [Synth 8-638] synthesizing module 'OBUF' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:22272]
INFO: [Synth 8-256] done synthesizing module 'OBUF' (27#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:22272]
INFO: [Synth 8-638] synthesizing module 'OBUFT' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:22488]
INFO: [Synth 8-256] done synthesizing module 'OBUFT' (28#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:22488]
INFO: [Synth 8-638] synthesizing module 'IOBUF' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17657]
INFO: [Synth 8-256] done synthesizing module 'IOBUF' (29#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17657]
INFO: [Synth 8-638] synthesizing module 'IOBUFDS_INTERMDISABLE' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17848]
INFO: [Synth 8-256] done synthesizing module 'IOBUFDS_INTERMDISABLE' (30#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17848]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_of_pre_fifo' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_of_pre_fifo.v:76]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_of_pre_fifo' (31#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_of_pre_fifo.v:76]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_of_pre_fifo__parameterized0' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_of_pre_fifo.v:76]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_of_pre_fifo__parameterized0' (31#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_of_pre_fifo.v:76]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_mc_phy' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy.v:70]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_phy_4lanes' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_4lanes.v:72]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_byte_lane' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_lane.v:70]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_of_pre_fifo__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_of_pre_fifo.v:76]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_of_pre_fifo__parameterized1' (31#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_of_pre_fifo.v:76]
INFO: [Synth 8-638] synthesizing module 'ODDR' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:25650]
INFO: [Synth 8-256] done synthesizing module 'ODDR' (32#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:25650]
INFO: [Synth 8-638] synthesizing module 'OBUFDS' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:22286]
INFO: [Synth 8-256] done synthesizing module 'OBUFDS' (33#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:22286]
INFO: [Synth 8-638] synthesizing module 'PHASER_OUT_PHY' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:32842]
INFO: [Synth 8-256] done synthesizing module 'PHASER_OUT_PHY' (34#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:32842]
INFO: [Synth 8-638] synthesizing module 'OUT_FIFO' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:26338]
INFO: [Synth 8-256] done synthesizing module 'OUT_FIFO' (35#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:26338]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_byte_group_io' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_group_io.v:69]
INFO: [Synth 8-638] synthesizing module 'OSERDESE2' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:26223]
INFO: [Synth 8-256] done synthesizing module 'OSERDESE2' (36#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:26223]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_byte_group_io' (37#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_group_io.v:69]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_byte_lane' (38#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_lane.v:70]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_byte_lane__parameterized0' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_lane.v:70]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_byte_group_io__parameterized0' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_group_io.v:69]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_byte_group_io__parameterized0' (38#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_group_io.v:69]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_byte_lane__parameterized0' (38#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_lane.v:70]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_byte_lane__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_lane.v:70]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_if_post_fifo' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_if_post_fifo.v:68]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_if_post_fifo' (39#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_if_post_fifo.v:68]
INFO: [Synth 8-638] synthesizing module 'PHASER_IN_PHY' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:32705]
INFO: [Synth 8-256] done synthesizing module 'PHASER_IN_PHY' (40#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:32705]
INFO: [Synth 8-638] synthesizing module 'IN_FIFO' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589]
INFO: [Synth 8-256] done synthesizing module 'IN_FIFO' (41#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:17589]
INFO: [Synth 8-638] synthesizing module 'PHASER_OUT_PHY__parameterized0' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:32842]
INFO: [Synth 8-256] done synthesizing module 'PHASER_OUT_PHY__parameterized0' (41#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:32842]
INFO: [Synth 8-638] synthesizing module 'OUT_FIFO__parameterized0' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:26338]
INFO: [Synth 8-256] done synthesizing module 'OUT_FIFO__parameterized0' (41#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:26338]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_byte_group_io__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_group_io.v:69]
INFO: [Synth 8-638] synthesizing module 'IDELAYE2' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16519]
INFO: [Synth 8-256] done synthesizing module 'IDELAYE2' (42#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:16519]
INFO: [Synth 8-638] synthesizing module 'ISERDESE2' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20009]
INFO: [Synth 8-256] done synthesizing module 'ISERDESE2' (43#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:20009]
INFO: [Synth 8-638] synthesizing module 'OSERDESE2__parameterized0' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:26223]
INFO: [Synth 8-256] done synthesizing module 'OSERDESE2__parameterized0' (43#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:26223]
INFO: [Synth 8-638] synthesizing module 'OSERDESE2__parameterized1' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:26223]
INFO: [Synth 8-256] done synthesizing module 'OSERDESE2__parameterized1' (43#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:26223]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_byte_group_io__parameterized1' (43#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_group_io.v:69]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_byte_lane__parameterized1' (43#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_lane.v:70]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_byte_lane__parameterized2' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_lane.v:70]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_byte_lane__parameterized2' (43#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_byte_lane.v:70]
INFO: [Synth 8-638] synthesizing module 'BUFIO' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:831]
INFO: [Synth 8-256] done synthesizing module 'BUFIO' (44#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:831]
INFO: [Synth 8-638] synthesizing module 'PHY_CONTROL' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:32933]
INFO: [Synth 8-256] done synthesizing module 'PHY_CONTROL' (45#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:32933]
INFO: [Synth 8-638] synthesizing module 'PHASER_REF' [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:32917]
INFO: [Synth 8-256] done synthesizing module 'PHASER_REF' (46#1) [/mnt/data/opt/Xilinx/Vivado/2017.2/scripts/rt/data/unisim_comp.v:32917]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_phy_4lanes' (47#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_4lanes.v:72]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_mc_phy' (48#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy.v:70]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_mc_phy_wrapper' (49#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_mc_phy_wrapper.v:71]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_calib_top' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_calib_top.v:82]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_phy_wrlvl' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrlvl.v:90]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_phy_wrlvl' (50#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrlvl.v:90]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v:68]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay' (51#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_ck_addr_cmd_delay.v:68]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_phy_dqs_found_cal_hr' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal_hr.v:79]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_phy_dqs_found_cal_hr' (52#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_dqs_found_cal_hr.v:79]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_phy_rdlvl' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_rdlvl.v:81]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_phy_rdlvl' (53#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_rdlvl.v:81]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_prbs_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_prbs_gen.v:92]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_prbs_gen' (54#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_prbs_gen.v:92]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_phy_init' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_init.v:89]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_phy_init' (55#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_init.v:89]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_phy_wrcal' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrcal.v:77]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_phy_wrcal' (56#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_wrcal.v:77]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ddr_phy_tempmon' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_tempmon.v:69]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_phy_tempmon' (57#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_tempmon.v:69]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_calib_top' (58#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_calib_top.v:82]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ddr_phy_top' (59#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/phy/mig_7series_v4_0_ddr_phy_top.vhd:371]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_mem_intfc' (60#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/ip_top/mig_7series_v4_0_mem_intfc.v:70]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ui_top' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/ui/mig_7series_v4_0_ui_top.v:71]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ui_cmd' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/ui/mig_7series_v4_0_ui_cmd.v:70]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ui_cmd' (61#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/ui/mig_7series_v4_0_ui_cmd.v:70]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ui_wr_data' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/ui/mig_7series_v4_0_ui_wr_data.v:131]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ui_wr_data' (62#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/ui/mig_7series_v4_0_ui_wr_data.v:131]
INFO: [Synth 8-638] synthesizing module 'mig_7series_v4_0_ui_rd_data' [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/ui/mig_7series_v4_0_ui_rd_data.v:140]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ui_rd_data' (63#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/ui/mig_7series_v4_0_ui_rd_data.v:140]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_ui_top' (64#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/ui/mig_7series_v4_0_ui_top.v:71]
INFO: [Synth 8-256] done synthesizing module 'mig_7series_v4_0_memc_ui_top_std' (65#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/ip_top/mig_7series_v4_0_memc_ui_top_std.v:72]
INFO: [Synth 8-256] done synthesizing module 'migui_arty_mig' (66#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/migui_arty_mig.vhd:550]
INFO: [Synth 8-256] done synthesizing module 'migui_arty' (67#1) [/mnt/dataold/tmp/tmp/w11-test/v0.76/w11/rtl/sys_gen/w11a/arty/project_mflow/project_mflow.srcs/sources_1/ip/migui_arty/migui_arty/user_design/rtl/migui_arty.vhd:121]
Finished RTL Elaboration : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 1339.727 ; gain = 229.066 ; free physical = 1508 ; free virtual = 9218
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 1339.727 ; gain = 229.066 ; free physical = 1542 ; free virtual = 9251
INFO: [Device 21-403] Loading part xc7a35ticsg324-1L
Constraint Validation Runtime : Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1608.664 ; gain = 0.000 ; free physical = 1242 ; free virtual = 8980
Finished Constraint Validation : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1608.664 ; gain = 498.004 ; free physical = 1353 ; free virtual = 9084
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1608.664 ; gain = 498.004 ; free physical = 1353 ; free virtual = 9084
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1608.664 ; gain = 498.004 ; free physical = 1356 ; free virtual = 9086
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:59 ; elapsed = 00:01:03 . Memory (MB): peak = 1608.664 ; gain = 498.004 ; free physical = 1337 ; free virtual = 9067
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:02:19 ; elapsed = 00:02:36 . Memory (MB): peak = 1628.672 ; gain = 518.012 ; free physical = 1156 ; free virtual = 8894
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

ROM:
+------------------------------+------------+---------------+----------------+
|Module Name                   | RTL Object | Depth x Width | Implemented As | 
+------------------------------+------------+---------------+----------------+
|mig_7series_v4_0_ddr_prbs_gen | mem_out    | 256x18        | LUT            | 
|mig_7series_v4_0_ddr_prbs_gen | mem_out    | 256x18        | LUT            | 
+------------------------------+------------+---------------+----------------+


Distributed RAM: Preliminary Mapping  Report (see note below)
+------------+---------------------------------------------------------------------------------------+-----------+----------------------+---------------+
|Module Name | RTL Object                                                                            | Inference | Size (Depth x Width) | Primitives    | 
+------------+---------------------------------------------------------------------------------------+-----------+----------------------+---------------+
|migui_arty  | of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg                                             | Implied   | 16 x 80              | RAM32M x 14   | 
|migui_arty  | ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg             | Implied   | 16 x 80              | RAM32M x 14   | 
|migui_arty  | ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied   | 4 x 80               | RAM32M x 14   | 
|migui_arty  | ddr_byte_lane_C.ddr_byte_lane_C/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg             | Implied   | 16 x 80              | RAM32M x 14   | 
|migui_arty  | ddr_byte_lane_D.ddr_byte_lane_D/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem_reg | Implied   | 4 x 80               | RAM32M x 14   | 
|migui_arty  | ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem_reg             | Implied   | 16 x 80              | RAM32M x 14   | 
+------------+---------------------------------------------------------------------------------------+-----------+----------------------+---------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:02:29 ; elapsed = 00:02:47 . Memory (MB): peak = 1714.961 ; gain = 604.301 ; free physical = 1026 ; free virtual = 8780
Finished Timing Optimization : Time (s): cpu = 00:02:31 ; elapsed = 00:02:48 . Memory (MB): peak = 1717.961 ; gain = 607.301 ; free physical = 1023 ; free virtual = 8777
Finished Technology Mapping : Time (s): cpu = 00:02:42 ; elapsed = 00:03:00 . Memory (MB): peak = 1734.977 ; gain = 624.316 ; free physical = 1156 ; free virtual = 8911
Finished IO Insertion : Time (s): cpu = 00:02:43 ; elapsed = 00:03:01 . Memory (MB): peak = 1734.977 ; gain = 624.316 ; free physical = 1157 ; free virtual = 8912
Finished Renaming Generated Instances : Time (s): cpu = 00:02:43 ; elapsed = 00:03:01 . Memory (MB): peak = 1734.977 ; gain = 624.316 ; free physical = 1157 ; free virtual = 8912
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:46 ; elapsed = 00:03:04 . Memory (MB): peak = 1734.977 ; gain = 624.316 ; free physical = 1158 ; free virtual = 8913
Finished Renaming Generated Ports : Time (s): cpu = 00:02:46 ; elapsed = 00:03:04 . Memory (MB): peak = 1734.977 ; gain = 624.316 ; free physical = 1158 ; free virtual = 8913
Finished Handling Custom Attributes : Time (s): cpu = 00:02:46 ; elapsed = 00:03:04 . Memory (MB): peak = 1734.977 ; gain = 624.316 ; free physical = 1158 ; free virtual = 8913
Finished Renaming Generated Nets : Time (s): cpu = 00:02:46 ; elapsed = 00:03:04 . Memory (MB): peak = 1734.977 ; gain = 624.316 ; free physical = 1158 ; free virtual = 8913

Report Cell Usage: 
+------+----------------------+------+
|      |Cell                  |Count |
+------+----------------------+------+
|1     |BUFG                  |     3|
|2     |BUFH                  |     1|
|3     |BUFIO                 |     1|
|4     |CARRY4                |   102|
|5     |IDELAYCTRL            |     1|
|6     |IDELAYE2              |    16|
|7     |IN_FIFO               |     2|
|8     |ISERDESE2             |    16|
|9     |LUT1                  |   444|
|10    |LUT2                  |   439|
|11    |LUT3                  |   739|
|12    |LUT4                  |   817|
|13    |LUT5                  |   830|
|14    |LUT6                  |  1115|
|15    |MMCME2_ADV            |     1|
|16    |MUXF7                 |    13|
|17    |ODDR                  |     5|
|18    |OSERDESE2             |    23|
|19    |OSERDESE2_1           |     2|
|20    |OSERDESE2_2           |    18|
|21    |OUT_FIFO              |     2|
|22    |OUT_FIFO_1            |     2|
|23    |PHASER_IN_PHY         |     2|
|24    |PHASER_OUT_PHY        |     2|
|25    |PHASER_OUT_PHY_1      |     2|
|26    |PHASER_REF            |     1|
|27    |PHY_CONTROL           |     1|
|28    |PLLE2_ADV             |     1|
|29    |RAM32M                |   105|
|30    |SRL16E                |    17|
|31    |SRLC32E               |     1|
|32    |XORCY                 |     6|
|33    |FDCE                  |     2|
|34    |FDPE                  |    71|
|35    |FDRE                  |  3129|
|36    |FDSE                  |    75|
|37    |IOBUF                 |    16|
|38    |IOBUFDS_INTERMDISABLE |     2|
|39    |OBUF                  |    24|
|40    |OBUFDS                |     1|
|41    |OBUFT                 |     2|
+------+----------------------+------+
Finished Writing Synthesis Report : Time (s): cpu = 00:02:46 ; elapsed = 00:03:04 . Memory (MB): peak = 1734.977 ; gain = 624.316 ; free physical = 1158 ; free virtual = 8913
synth_design: Time (s): cpu = 00:02:51 ; elapsed = 00:03:09 . Memory (MB): peak = 1734.984 ; gain = 636.910 ; free physical = 1200 ; free virtual = 8955
