Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017
| Date         : Sun Feb 10 13:53:10 2019
| Host         : athome running 64-bit Ubuntu 16.04.5 LTS
| Command      : report_drc -file sys_w11a_arty_drc_routed.rpt -pb sys_w11a_arty_drc_routed.pb -rpx sys_w11a_arty_drc_routed.rpx
| Design       : sys_w11a_arty
| Device       : xc7a35ticsg324-1L
| Speed File   : -1L
| Design State : Routed
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Report DRC

Table of Contents
-----------------
1. REPORT SUMMARY
2. REPORT DETAILS

1. REPORT SUMMARY
-----------------
            Netlist: netlist
          Floorplan: design_1
      Design limits: <entire design considered>
           Ruledeck: default
             Max violations: <unlimited>
             Violations found: 3
+-----------+----------+------------------------+------------+
| Rule      | Severity | Description            | Violations |
+-----------+----------+------------------------+------------+
| DPOP-1    | Warning  | PREG Output pipelining | 1          |
| DPOP-2    | Warning  | MREG Output pipelining | 1          |
| REQP-1709 | Warning  | Clock output buffering | 1          |
+-----------+----------+------------------------+------------+

2. REPORT DETAILS
-----------------
DPOP-1#1 Warning
PREG Output pipelining  
DSP SYS70/W11A/DPATH/MUNIT/DOUT0 output SYS70/W11A/DPATH/MUNIT/DOUT0/P[47:0] is not pipelined (PREG=0). Pipelining the DSP48 output will improve performance and often saves power so it is suggested whenever possible to fully pipeline this function.  If this DSP48 function was inferred, it is suggested to describe an additional register stage after this function.  If the DSP48 was instantiated in the design, it is suggested to set the PREG attribute to 1.
Related violations: <none>

DPOP-2#1 Warning
MREG Output pipelining  
DSP SYS70/W11A/DPATH/MUNIT/DOUT0 multiplier stage SYS70/W11A/DPATH/MUNIT/DOUT0/P[47:0] is not pipelined (MREG=0). Pipelining the multiplier function will improve performance and will save significant power so it is suggested whenever possible to fully pipeline this function.  If this multiplier was inferred, it is suggested to describe an additional register stage after this function.  If there is no registered adder/accumulator following the multiply function, two pipeline stages are suggested to allow both the MREG and PREG registers to be used.  If the DSP48 was instantiated in the design, it is suggested to set both the MREG and PREG attributes to 1 when performing multiply functions.
Related violations: <none>

REQP-1709#1 Warning
Clock output buffering  
PLLE2_ADV connectivity violation. The signal MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/pll_clk3_out on the MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/plle2_i/CLKOUT3 pin of MEMCTL/MIG_CTL/u_migui_arty_mig/u_ddr3_infrastructure/plle2_i does not drive the same kind of BUFFER load as the other CLKOUT pins. Routing from the different buffer types will not be phase aligned.
Related violations: <none>


