
*** Running vivado
    with args -log sys_tst_rlink_c7.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source sys_tst_rlink_c7.tcl -notrace


****** Vivado v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source sys_tst_rlink_c7.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 88 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.2
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.753/w11/rtl/bplib/cmoda7/cmoda7_pclk.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.753/w11/rtl/bplib/cmoda7/cmoda7_pclk.xdc]
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.753/w11/rtl/bplib/cmoda7/cmoda7_pins.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.753/w11/rtl/bplib/cmoda7/cmoda7_pins.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 9 instances were transformed.
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 9 instances

link_design: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1310.684 ; gain = 231.629 ; free physical = 1592 ; free virtual = 8732
Command: opt_design -directive Explore
INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
Running DRC as a precondition to command opt_design

Starting DRC Task
Command: report_drc (run_mandatory_drcs) for: opt_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1320.691 ; gain = 10.008 ; free physical = 1587 ; free virtual = 8727
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-2] Deriving generated clocks

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 161690a99

Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1785.121 ; gain = 0.000 ; free physical = 1201 ; free virtual = 8353
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 113 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 14d553b79

Time (s): cpu = 00:00:00.27 ; elapsed = 00:00:00.29 . Memory (MB): peak = 1785.121 ; gain = 0.000 ; free physical = 1200 ; free virtual = 8353
INFO: [Opt 31-389] Phase Constant propagation created 1 cells and removed 1 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 1217b35de

Time (s): cpu = 00:00:00.33 ; elapsed = 00:00:00.35 . Memory (MB): peak = 1785.121 ; gain = 0.000 ; free physical = 1200 ; free virtual = 8353
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 1217b35de

Time (s): cpu = 00:00:00.39 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1785.121 ; gain = 0.000 ; free physical = 1200 ; free virtual = 8353
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 1217b35de

Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:00.42 . Memory (MB): peak = 1785.121 ; gain = 0.000 ; free physical = 1200 ; free virtual = 8353
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1785.121 ; gain = 0.000 ; free physical = 1200 ; free virtual = 8353
Ending Logic Optimization Task | Checksum: 1217b35de

Time (s): cpu = 00:00:00.42 ; elapsed = 00:00:00.44 . Memory (MB): peak = 1785.121 ; gain = 0.000 ; free physical = 1200 ; free virtual = 8353

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Power 33-23] Power model is not available for UA
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 5 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 1 Total Ports: 10
Ending PowerOpt Patch Enables Task | Checksum: 143ab6c5f

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1186 ; free virtual = 8338
Ending Power Optimization Task | Checksum: 143ab6c5f

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1944.535 ; gain = 159.414 ; free physical = 1192 ; free virtual = 8344
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:19 ; elapsed = 00:00:19 . Memory (MB): peak = 1944.535 ; gain = 633.852 ; free physical = 1192 ; free virtual = 8344
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1190 ; free virtual = 8344
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.753/w11/rtl/sys_gen/tst_rlink/cmoda7/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_c7_opt.dcp' has been generated.
Command: report_drc -file sys_tst_rlink_c7_drc_opted.rpt
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file /mnt/dataold/tmp/tmp/w11-test/v0.753/w11/rtl/sys_gen/tst_rlink/cmoda7/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_c7_drc_opted.rpt.
report_drc completed successfully
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
Command: report_drc (run_mandatory_drcs) for: incr_eco_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
Command: report_drc (run_mandatory_drcs) for: placer_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 46-5] The placer was invoked with the 'Explore' directive.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1183 ; free virtual = 8337
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: a1d3da4d

Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1183 ; free virtual = 8337
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1184 ; free virtual = 8337

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 11f482313

Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1182 ; free virtual = 8335

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1b5eaeb2d

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1177 ; free virtual = 8332

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1b5eaeb2d

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1177 ; free virtual = 8332
Phase 1 Placer Initialization | Checksum: 1b5eaeb2d

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1177 ; free virtual = 8332

Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 1d980d341

Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1170 ; free virtual = 8324

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1d980d341

Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1170 ; free virtual = 8324

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 10d97c09f

Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1169 ; free virtual = 8323

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1895a1be7

Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1169 ; free virtual = 8323

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1895a1be7

Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1169 ; free virtual = 8323

Phase 3.5 Timing Path Optimizer
Phase 3.5 Timing Path Optimizer | Checksum: e77d5f1e

Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1169 ; free virtual = 8323

Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 208f20d5e

Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1167 ; free virtual = 8322

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 1ffe7bcd8

Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1167 ; free virtual = 8322

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 1ffe7bcd8

Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1167 ; free virtual = 8322
Phase 3 Detail Placement | Checksum: 1ffe7bcd8

Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1167 ; free virtual = 8322

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 176b38b20

Phase 4.1.1.1 BUFG Insertion
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
INFO: [Place 46-41] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
Phase 4.1.1.1 BUFG Insertion | Checksum: 176b38b20

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1167 ; free virtual = 8321
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.895. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: 1d793d8a2

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1167 ; free virtual = 8321
Phase 4.1 Post Commit Optimization | Checksum: 1d793d8a2

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1166 ; free virtual = 8321

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 1d793d8a2

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1168 ; free virtual = 8322

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: 1d793d8a2

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1168 ; free virtual = 8322

Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 25510f34e

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1168 ; free virtual = 8322
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 25510f34e

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1168 ; free virtual = 8322
Ending Placer Task | Checksum: 192eddd69

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1171 ; free virtual = 8326
49 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1171 ; free virtual = 8326
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1168 ; free virtual = 8326
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.753/w11/rtl/sys_gen/tst_rlink/cmoda7/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_c7_placed.dcp' has been generated.
report_io: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.26 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1166 ; free virtual = 8321
report_utilization: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1171 ; free virtual = 8326
report_control_sets: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1171 ; free virtual = 8326
Command: phys_opt_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.500 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.29 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1167 ; free virtual = 8326
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.753/w11/rtl/sys_gen/tst_rlink/cmoda7/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_c7_physopt.dcp' has been generated.
Command: route_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
Running DRC as a precondition to command route_design
Command: report_drc (run_mandatory_drcs) for: router_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-270] Using Router directive 'Explore'.
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: b3ce5267 ConstDB: 0 ShapeSum: df1f8b02 RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: f424776c

Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1053 ; free virtual = 8210

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: f424776c

Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1054 ; free virtual = 8211

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: f424776c

Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1047 ; free virtual = 8204

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: f424776c

Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1047 ; free virtual = 8204
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 10c853654

Time (s): cpu = 00:00:27 ; elapsed = 00:00:24 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1036 ; free virtual = 8193
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.251  | TNS=0.000  | WHS=-0.355 | THS=-85.721|

Phase 2 Router Initialization | Checksum: 1184af689

Time (s): cpu = 00:00:28 ; elapsed = 00:00:24 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1037 ; free virtual = 8194

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 1d4ed742f

Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1038 ; free virtual = 8195

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 292
 Number of Nodes with overlaps = 14
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.172  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 243053852

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1039 ; free virtual = 8196
Phase 4 Rip-up And Reroute | Checksum: 243053852

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1039 ; free virtual = 8196

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp
Phase 5.1 Delay CleanUp | Checksum: 243053852

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1039 ; free virtual = 8196

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 243053852

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1039 ; free virtual = 8196
Phase 5 Delay and Skew Optimization | Checksum: 243053852

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1039 ; free virtual = 8196

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 2416298b1

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1039 ; free virtual = 8196
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.265  | TNS=0.000  | WHS=0.032  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 217b13226

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1039 ; free virtual = 8196
Phase 6 Post Hold Fix | Checksum: 217b13226

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1039 ; free virtual = 8196

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.686678 %
  Global Horizontal Routing Utilization  = 0.802186 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 251642397

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1039 ; free virtual = 8196

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 251642397

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1039 ; free virtual = 8196

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 20bdd7793

Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1039 ; free virtual = 8196

Phase 10 Post Router Timing
INFO: [Route 35-20] Post Routing Timing Summary | WNS=1.267  | TNS=0.000  | WHS=0.037  | THS=0.000  |

INFO: [Route 35-61] The design met the timing requirement.
Phase 10 Post Router Timing | Checksum: 195f8e8f2

Time (s): cpu = 00:00:33 ; elapsed = 00:00:27 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1039 ; free virtual = 8196
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:33 ; elapsed = 00:00:28 . Memory (MB): peak = 1944.535 ; gain = 0.000 ; free physical = 1104 ; free virtual = 8261

Routing Is Done.
67 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:29 . Memory (MB): peak = 1978.488 ; gain = 33.953 ; free physical = 1104 ; free virtual = 8261
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.77 ; elapsed = 00:00:00.40 . Memory (MB): peak = 1978.488 ; gain = 0.000 ; free physical = 1100 ; free virtual = 8261
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.753/w11/rtl/sys_gen/tst_rlink/cmoda7/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_c7_routed.dcp' has been generated.
Command: report_drc -file sys_tst_rlink_c7_drc_routed.rpt -pb sys_tst_rlink_c7_drc_routed.pb -rpx sys_tst_rlink_c7_drc_routed.rpx
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file /mnt/dataold/tmp/tmp/w11-test/v0.753/w11/rtl/sys_gen/tst_rlink/cmoda7/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_c7_drc_routed.rpt.
report_drc completed successfully
Command: report_methodology -file sys_tst_rlink_c7_methodology_drc_routed.rpt -rpx sys_tst_rlink_c7_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /mnt/dataold/tmp/tmp/w11-test/v0.753/w11/rtl/sys_gen/tst_rlink/cmoda7/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_c7_methodology_drc_routed.rpt.
report_methodology completed successfully
Command: report_power -file sys_tst_rlink_c7_power_routed.rpt -pb sys_tst_rlink_c7_power_summary_routed.pb -rpx sys_tst_rlink_c7_power_routed.rpx
INFO: [Power 33-23] Power model is not available for UA
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
75 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Sat Dec 29 11:24:00 2018...

*** Running vivado
    with args -log sys_tst_rlink_c7.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source sys_tst_rlink_c7.tcl -notrace


****** Vivado v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source sys_tst_rlink_c7.tcl -notrace
Command: open_checkpoint sys_tst_rlink_c7_routed.dcp

Starting open_checkpoint Task

Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1077.039 ; gain = 0.000 ; free physical = 1189 ; free virtual = 8352
INFO: [Netlist 29-17] Analyzing 88 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.2
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.753/w11/rtl/sys_gen/tst_rlink/cmoda7/project_mflow/project_mflow.runs/impl_1/.Xil/Vivado-10076-athome/dcp3/sys_tst_rlink_c7_early.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.753/w11/rtl/sys_gen/tst_rlink/cmoda7/project_mflow/project_mflow.runs/impl_1/.Xil/Vivado-10076-athome/dcp3/sys_tst_rlink_c7_early.xdc]
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.753/w11/rtl/sys_gen/tst_rlink/cmoda7/project_mflow/project_mflow.runs/impl_1/.Xil/Vivado-10076-athome/dcp3/sys_tst_rlink_c7.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.753/w11/rtl/sys_gen/tst_rlink/cmoda7/project_mflow/project_mflow.runs/impl_1/.Xil/Vivado-10076-athome/dcp3/sys_tst_rlink_c7.xdc]
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.29 . Memory (MB): peak = 1306.949 ; gain = 1.000 ; free physical = 926 ; free virtual = 8093
Restored from archive | CPU: 0.290000 secs | Memory: 2.717216 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.28 ; elapsed = 00:00:00.29 . Memory (MB): peak = 1306.949 ; gain = 1.000 ; free physical = 926 ; free virtual = 8093
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 9 instances were transformed.
  RAM32M => RAM32M (RAMS32, RAMS32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32): 9 instances

INFO: [Project 1-604] Checkpoint was created with Vivado v2017.2 (64-bit) build 1909853
open_checkpoint: Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1306.949 ; gain = 229.910 ; free physical = 930 ; free virtual = 8093
Command: write_bitstream -force sys_tst_rlink_c7.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
Running DRC as a precondition to command write_bitstream
Command: report_drc (run_mandatory_drcs) for: bitstream_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado 12-3199] DRC finished with 0 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Project 1-821] Please set project.enableDesignId to be 'true'.
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Overwriting "TIMESTAMP" with "EE24B650" for option USR_ACCESS
Creating bitmap...
Creating bitstream...
Writing bitstream ./sys_tst_rlink_c7.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:24 ; elapsed = 00:00:22 . Memory (MB): peak = 1796.805 ; gain = 489.855 ; free physical = 821 ; free virtual = 7990
INFO: [Common 17-206] Exiting Vivado at Sat Dec 29 11:25:22 2018...
