Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017
| Date         : Sat Dec 29 11:24:00 2018
| Host         : athome running 64-bit Ubuntu 16.04.5 LTS
| Command      : report_timing_summary -warn_on_violation -max_paths 10 -file sys_tst_rlink_c7_timing_summary_routed.rpt -rpx sys_tst_rlink_c7_timing_summary_routed.rpx
| Design       : sys_tst_rlink_c7
| Device       : 7a35t-cpg236
| Speed File   : -1  PRODUCTION 1.17 2017-05-11
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  false

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
--------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock
--------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
--------------------------
 There is 1 input port with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
 There are 6 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
--------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops
------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      1.267        0.000                      0                 2574        0.037        0.000                      0                 2574        2.916        0.000                       0                  1009  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock       Waveform(ns)         Period(ns)      Frequency(MHz)
-----       ------------         ----------      --------------
I_CLK12     {0.000 41.660}       83.330          12.000          
  CLKFBOUT  {0.000 41.665}       83.330          12.000          
  CLKOUT0   {0.000 4.167}        8.333           120.005         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
I_CLK12                                                                                                                                                        16.670        0.000                       0                     1  
  CLKFBOUT                                                                                                                                                     16.670        0.000                       0                     3  
  CLKOUT0           1.267        0.000                      0                 2574        0.037        0.000                      0                 2574        2.916        0.000                       0                  1005  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  I_CLK12
  To Clock:  I_CLK12

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       16.670ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         I_CLK12
Waveform(ns):       { 0.000 41.660 }
Period(ns):         83.330
Sources:            { I_CLK12 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     MMCME2_ADV/CLKIN1  n/a            1.249         83.330      82.081     MMCME2_ADV_X0Y0  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
Max Period        n/a     MMCME2_ADV/CLKIN1  n/a            100.000       83.330      16.670     MMCME2_ADV_X0Y0  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
Low Pulse Width   Slow    MMCME2_ADV/CLKIN1  n/a            10.000        41.670      31.670     MMCME2_ADV_X0Y0  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
Low Pulse Width   Fast    MMCME2_ADV/CLKIN1  n/a            10.000        41.670      31.670     MMCME2_ADV_X0Y0  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
High Pulse Width  Slow    MMCME2_ADV/CLKIN1  n/a            10.000        41.660      31.660     MMCME2_ADV_X0Y0  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
High Pulse Width  Fast    MMCME2_ADV/CLKIN1  n/a            10.000        41.660      31.660     MMCME2_ADV_X0Y0  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  CLKFBOUT
  To Clock:  CLKFBOUT

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       16.670ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         CLKFBOUT
Waveform(ns):       { 0.000 41.665 }
Period(ns):         83.330
Sources:            { GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFG/I               n/a            2.155         83.330      81.175     BUFGCTRL_X0Y1    GEN_CLKSYS/USEMMCM.BUFG_CLKFB/I
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         83.330      82.081     MMCME2_ADV_X0Y0  GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT
Min Period  n/a     MMCME2_ADV/CLKFBIN   n/a            1.249         83.330      82.081     MMCME2_ADV_X0Y0  GEN_CLKSYS/USEMMCM.MMCM/CLKFBIN
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       83.330      16.670     MMCME2_ADV_X0Y0  GEN_CLKSYS/USEMMCM.MMCM/CLKFBIN
Max Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            213.360       83.330      130.030    MMCME2_ADV_X0Y0  GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT



---------------------------------------------------------------------------------------------------
From Clock:  CLKOUT0
  To Clock:  CLKOUT0

Setup :            0  Failing Endpoints,  Worst Slack        1.267ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.037ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.916ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.267ns  (required time - arrival time)
  Source:                 RBDTST/EMON/BRAM/sv_ram_reg/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/EMON/BRAM/sv_ram_reg/DIBDI[14]
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.763ns  (logic 4.431ns (65.515%)  route 2.332ns (34.485%))
  Logic Levels:           9  (CARRY4=8 LUT2=1)
  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.506ns = ( 6.827 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.906ns
    Clock Pessimism Removal (CPR):    0.574ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.709    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.587    -0.906    RBDTST/EMON/BRAM/CLKFX
    RAMB18_X2Y30         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X2Y30         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[1])
                                                      2.454     1.548 r  RBDTST/EMON/BRAM/sv_ram_reg/DOADO[1]
                         net (fo=2, routed)           0.791     2.340    RBDTST/EMON/BRAM_n_21
    SLICE_X57Y73         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.656     2.996 r  RBDTST/EMON/plusOp_inferred__0/i__carry/CO[3]
                         net (fo=1, routed)           0.000     2.996    RBDTST/EMON/plusOp_inferred__0/i__carry_n_0
    SLICE_X57Y74         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.110 r  RBDTST/EMON/plusOp_inferred__0/i__carry__0/CO[3]
                         net (fo=1, routed)           0.009     3.119    RBDTST/EMON/plusOp_inferred__0/i__carry__0_n_0
    SLICE_X57Y75         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.233 r  RBDTST/EMON/plusOp_inferred__0/i__carry__1/CO[3]
                         net (fo=1, routed)           0.000     3.233    RBDTST/EMON/plusOp_inferred__0/i__carry__1_n_0
    SLICE_X57Y76         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.347 r  RBDTST/EMON/plusOp_inferred__0/i__carry__2/CO[3]
                         net (fo=1, routed)           0.000     3.347    RBDTST/EMON/plusOp_inferred__0/i__carry__2_n_0
    SLICE_X57Y77         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.461 r  RBDTST/EMON/plusOp_inferred__0/i__carry__3/CO[3]
                         net (fo=1, routed)           0.000     3.461    RBDTST/EMON/plusOp_inferred__0/i__carry__3_n_0
    SLICE_X57Y78         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.575 r  RBDTST/EMON/plusOp_inferred__0/i__carry__4/CO[3]
                         net (fo=1, routed)           0.000     3.575    RBDTST/EMON/plusOp_inferred__0/i__carry__4_n_0
    SLICE_X57Y79         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     3.689 r  RBDTST/EMON/plusOp_inferred__0/i__carry__5/CO[3]
                         net (fo=1, routed)           0.000     3.689    RBDTST/EMON/plusOp_inferred__0/i__carry__5_n_0
    SLICE_X57Y80         CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334     4.023 r  RBDTST/EMON/plusOp_inferred__0/i__carry__6/O[1]
                         net (fo=1, routed)           0.812     4.834    RBDTST/EMON/BRAM/plusOp[29]
    SLICE_X59Y76         LUT2 (Prop_lut2_I0_O)        0.303     5.137 r  RBDTST/EMON/BRAM/sv_ram_reg_i_18__0/O
                         net (fo=1, routed)           0.720     5.858    RBDTST/EMON/BRAM/BRAM_DIB[30]
    RAMB18_X2Y30         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/DIBDI[14]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.900    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.470     6.827    RBDTST/EMON/BRAM/CLKFX
    RAMB18_X2Y30         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/CLKBWRCLK
                         clock pessimism              0.574     7.401    
                         clock uncertainty           -0.036     7.366    
    RAMB18_X2Y30         RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_DIBDI[14])
                                                     -0.241     7.125    RBDTST/EMON/BRAM/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          7.125    
                         arrival time                          -5.858    
  -------------------------------------------------------------------
                         slack                                  1.267    

Slack (MET) :             1.338ns  (required time - arrival time)
  Source:                 UARB/RBSEL/R_SEL_reg/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_BREGS_reg[rbdout][5]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.971ns  (logic 0.828ns (11.878%)  route 6.143ns (88.122%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        -0.019ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.550ns = ( 6.783 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.956ns
    Clock Pessimism Removal (CPR):    0.575ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.709    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.537    -0.956    UARB/RBSEL/CLKFX
    SLICE_X43Y77         FDRE                                         r  UARB/RBSEL/R_SEL_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y77         FDRE (Prop_fdre_C_Q)         0.456    -0.500 r  UARB/RBSEL/R_SEL_reg/Q
                         net (fo=18, routed)          2.968     2.468    UARB/UA/R_SEL_reg
    SLICE_X28Y33         LUT5 (Prop_lut5_I0_O)        0.124     2.592 r  UARB/UA/R_BREGS[rbdout][5]_i_7/O
                         net (fo=1, routed)           2.372     4.964    RB_SRES_OR1/RB_SRES_USRACC[dout][5]
    SLICE_X39Y74         LUT6 (Prop_lut6_I5_O)        0.124     5.088 r  RB_SRES_OR1/R_BREGS[rbdout][5]_i_2/O
                         net (fo=2, routed)           0.803     5.891    RLINK/CORE/RL/SEL/RB_SRES_OR[dout][5]
    SLICE_X40Y80         LUT5 (Prop_lut5_I0_O)        0.124     6.015 r  RLINK/CORE/RL/SEL/R_BREGS[rbdout][5]_i_1/O
                         net (fo=1, routed)           0.000     6.015    RLINK/CORE/RL/RB_SRES_OR[dout]_1[5]
    SLICE_X40Y80         FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][5]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.900    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.426     6.783    RLINK/CORE/RL/CLKFX
    SLICE_X40Y80         FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][5]/C
                         clock pessimism              0.575     7.358    
                         clock uncertainty           -0.036     7.322    
    SLICE_X40Y80         FDRE (Setup_fdre_C_D)        0.031     7.353    RLINK/CORE/RL/R_BREGS_reg[rbdout][5]
  -------------------------------------------------------------------
                         required time                          7.353    
                         arrival time                          -6.015    
  -------------------------------------------------------------------
                         slack                                  1.338    

Slack (MET) :             1.346ns  (required time - arrival time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[addr][6]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state][22]/R
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.492ns  (logic 1.336ns (20.579%)  route 5.156ns (79.421%))
  Logic Levels:           6  (LUT4=1 LUT6=5)
  Clock Path Skew:        -0.030ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.542ns = ( 6.791 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.951ns
    Clock Pessimism Removal (CPR):    0.561ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.709    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.542    -0.951    RLINK/CORE/RL/CLKFX
    SLICE_X41Y80         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[addr][6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y80         FDRE (Prop_fdre_C_Q)         0.419    -0.532 r  RLINK/CORE/RL/R_LREGS_reg[addr][6]/Q
                         net (fo=17, routed)          1.185     0.653    RLINK/CORE/RL/R_REGS_reg[rbaddr][6]
    SLICE_X35Y73         LUT4 (Prop_lut4_I0_O)        0.297     0.950 f  RLINK/CORE/RL/RB_SRES_OR[err]0_i_5/O
                         net (fo=24, routed)          0.843     1.793    SMRB.I0/SMRB/R_LREGS_reg[addr][6]
    SLICE_X33Y72         LUT6 (Prop_lut6_I1_O)        0.124     1.917 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           1.021     2.938    RLINK/CORE/RL/RB_SRES_SYSMON[busy]
    SLICE_X39Y80         LUT6 (Prop_lut6_I0_O)        0.124     3.062 f  RLINK/CORE/RL/R_REGS[rbtout]_i_1/O
                         net (fo=9, routed)           0.656     3.718    RLINK/CORE/RL/R_REGS_reg[rbtout]
    SLICE_X41Y85         LUT6 (Prop_lut6_I2_O)        0.124     3.842 r  RLINK/CORE/RL/R_LREGS[din][15]_i_3/O
                         net (fo=4, routed)           0.473     4.316    RLINK/CORE/RL/R_LREGS[din][15]_i_3_n_0
    SLICE_X41Y87         LUT6 (Prop_lut6_I5_O)        0.124     4.440 r  RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_6/O
                         net (fo=2, routed)           0.418     4.858    RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_6_n_0
    SLICE_X41Y87         LUT6 (Prop_lut6_I4_O)        0.124     4.982 r  RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_1/O
                         net (fo=4, routed)           0.559     5.541    RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_1_n_0
    SLICE_X45Y87         FDRE                                         r  RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state][22]/R
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.900    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.434     6.791    RLINK/CORE/RL/CLKFX
    SLICE_X45Y87         FDRE                                         r  RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state][22]/C
                         clock pessimism              0.561     7.352    
                         clock uncertainty           -0.036     7.316    
    SLICE_X45Y87         FDRE (Setup_fdre_C_R)       -0.429     6.887    RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state][22]
  -------------------------------------------------------------------
                         required time                          6.887    
                         arrival time                          -5.541    
  -------------------------------------------------------------------
                         slack                                  1.346    

Slack (MET) :             1.387ns  (required time - arrival time)
  Source:                 UARB/RBSEL/R_SEL_reg/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_BREGS_reg[rbdout][8]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.906ns  (logic 0.828ns (11.989%)  route 6.078ns (88.011%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        -0.035ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.552ns = ( 6.781 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.956ns
    Clock Pessimism Removal (CPR):    0.561ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.709    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.537    -0.956    UARB/RBSEL/CLKFX
    SLICE_X43Y77         FDRE                                         r  UARB/RBSEL/R_SEL_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y77         FDRE (Prop_fdre_C_Q)         0.456    -0.500 r  UARB/RBSEL/R_SEL_reg/Q
                         net (fo=18, routed)          3.004     2.504    UARB/UA/R_SEL_reg
    SLICE_X29Y32         LUT5 (Prop_lut5_I0_O)        0.124     2.628 r  UARB/UA/R_BREGS[rbdout][8]_i_7/O
                         net (fo=1, routed)           2.553     5.181    RB_SRES_OR1/RB_SRES_USRACC[dout][7]
    SLICE_X37Y75         LUT6 (Prop_lut6_I5_O)        0.124     5.305 r  RB_SRES_OR1/R_BREGS[rbdout][8]_i_2/O
                         net (fo=2, routed)           0.520     5.826    RLINK/CORE/RL/SEL/RB_SRES_OR[dout][7]
    SLICE_X39Y80         LUT5 (Prop_lut5_I4_O)        0.124     5.950 r  RLINK/CORE/RL/SEL/R_BREGS[rbdout][8]_i_1/O
                         net (fo=1, routed)           0.000     5.950    RLINK/CORE/RL/RB_SRES_OR[dout]_1[8]
    SLICE_X39Y80         FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][8]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.900    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.424     6.781    RLINK/CORE/RL/CLKFX
    SLICE_X39Y80         FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][8]/C
                         clock pessimism              0.561     7.342    
                         clock uncertainty           -0.036     7.306    
    SLICE_X39Y80         FDRE (Setup_fdre_C_D)        0.031     7.337    RLINK/CORE/RL/R_BREGS_reg[rbdout][8]
  -------------------------------------------------------------------
                         required time                          7.337    
                         arrival time                          -5.950    
  -------------------------------------------------------------------
                         slack                                  1.387    

Slack (MET) :             1.390ns  (required time - arrival time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[addr][0]_rep/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_BREGS_reg[rbdout][9]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.901ns  (logic 0.828ns (11.999%)  route 6.073ns (88.001%))
  Logic Levels:           3  (LUT5=2 LUT6=1)
  Clock Path Skew:        -0.039ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.551ns = ( 6.782 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.951ns
    Clock Pessimism Removal (CPR):    0.561ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.709    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.542    -0.951    RLINK/CORE/RL/CLKFX
    SLICE_X41Y80         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[addr][0]_rep/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y80         FDRE (Prop_fdre_C_Q)         0.456    -0.495 r  RLINK/CORE/RL/R_LREGS_reg[addr][0]_rep/Q
                         net (fo=115, routed)         3.057     2.562    UARB/UA/R_LREGS_reg[addr][0]_rep
    SLICE_X29Y32         LUT5 (Prop_lut5_I2_O)        0.124     2.686 r  UARB/UA/R_BREGS[rbdout][9]_i_7/O
                         net (fo=1, routed)           2.423     5.109    RB_SRES_OR1/RB_SRES_USRACC[dout][8]
    SLICE_X39Y75         LUT6 (Prop_lut6_I5_O)        0.124     5.233 r  RB_SRES_OR1/R_BREGS[rbdout][9]_i_2/O
                         net (fo=2, routed)           0.592     5.825    RLINK/CORE/RL/SEL/RB_SRES_OR[dout][8]
    SLICE_X39Y81         LUT5 (Prop_lut5_I0_O)        0.124     5.949 r  RLINK/CORE/RL/SEL/R_BREGS[rbdout][9]_i_1/O
                         net (fo=1, routed)           0.000     5.949    RLINK/CORE/RL/RB_SRES_OR[dout]_1[9]
    SLICE_X39Y81         FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][9]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.900    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.425     6.782    RLINK/CORE/RL/CLKFX
    SLICE_X39Y81         FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][9]/C
                         clock pessimism              0.561     7.343    
                         clock uncertainty           -0.036     7.307    
    SLICE_X39Y81         FDRE (Setup_fdre_C_D)        0.032     7.339    RLINK/CORE/RL/R_BREGS_reg[rbdout][9]
  -------------------------------------------------------------------
                         required time                          7.339    
                         arrival time                          -5.949    
  -------------------------------------------------------------------
                         slack                                  1.390    

Slack (MET) :             1.413ns  (required time - arrival time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[addr][0]_rep/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/MON/R_REGS_reg[rbdata][9]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.888ns  (logic 0.828ns (12.020%)  route 6.060ns (87.980%))
  Logic Levels:           3  (LUT4=1 LUT5=1 LUT6=1)
  Clock Path Skew:        -0.027ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.553ns = ( 6.780 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.951ns
    Clock Pessimism Removal (CPR):    0.575ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.709    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.542    -0.951    RLINK/CORE/RL/CLKFX
    SLICE_X41Y80         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[addr][0]_rep/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y80         FDRE (Prop_fdre_C_Q)         0.456    -0.495 r  RLINK/CORE/RL/R_LREGS_reg[addr][0]_rep/Q
                         net (fo=115, routed)         3.057     2.562    UARB/UA/R_LREGS_reg[addr][0]_rep
    SLICE_X29Y32         LUT5 (Prop_lut5_I2_O)        0.124     2.686 r  UARB/UA/R_BREGS[rbdout][9]_i_7/O
                         net (fo=1, routed)           2.423     5.109    RB_SRES_OR1/RB_SRES_USRACC[dout][8]
    SLICE_X39Y75         LUT6 (Prop_lut6_I5_O)        0.124     5.233 r  RB_SRES_OR1/R_BREGS[rbdout][9]_i_2/O
                         net (fo=2, routed)           0.580     5.813    RLINK/CORE/RL/RB_SRES_OR[dout][8]
    SLICE_X41Y77         LUT4 (Prop_lut4_I3_O)        0.124     5.937 r  RLINK/CORE/RL/R_REGS[rbdata][9]_i_1/O
                         net (fo=1, routed)           0.000     5.937    RBDTST/MON/N_REGS[rbdata][9]
    SLICE_X41Y77         FDRE                                         r  RBDTST/MON/R_REGS_reg[rbdata][9]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.900    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.423     6.780    RBDTST/MON/CLKFX
    SLICE_X41Y77         FDRE                                         r  RBDTST/MON/R_REGS_reg[rbdata][9]/C
                         clock pessimism              0.575     7.355    
                         clock uncertainty           -0.036     7.319    
    SLICE_X41Y77         FDRE (Setup_fdre_C_D)        0.031     7.350    RBDTST/MON/R_REGS_reg[rbdata][9]
  -------------------------------------------------------------------
                         required time                          7.350    
                         arrival time                          -5.937    
  -------------------------------------------------------------------
                         slack                                  1.413    

Slack (MET) :             1.424ns  (required time - arrival time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[addr][6]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state][23]/R
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.427ns  (logic 1.336ns (20.788%)  route 5.091ns (79.212%))
  Logic Levels:           6  (LUT4=1 LUT6=5)
  Clock Path Skew:        -0.018ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.544ns = ( 6.789 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.951ns
    Clock Pessimism Removal (CPR):    0.575ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.709    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.542    -0.951    RLINK/CORE/RL/CLKFX
    SLICE_X41Y80         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[addr][6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y80         FDRE (Prop_fdre_C_Q)         0.419    -0.532 r  RLINK/CORE/RL/R_LREGS_reg[addr][6]/Q
                         net (fo=17, routed)          1.185     0.653    RLINK/CORE/RL/R_REGS_reg[rbaddr][6]
    SLICE_X35Y73         LUT4 (Prop_lut4_I0_O)        0.297     0.950 f  RLINK/CORE/RL/RB_SRES_OR[err]0_i_5/O
                         net (fo=24, routed)          0.843     1.793    SMRB.I0/SMRB/R_LREGS_reg[addr][6]
    SLICE_X33Y72         LUT6 (Prop_lut6_I1_O)        0.124     1.917 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           1.021     2.938    RLINK/CORE/RL/RB_SRES_SYSMON[busy]
    SLICE_X39Y80         LUT6 (Prop_lut6_I0_O)        0.124     3.062 f  RLINK/CORE/RL/R_REGS[rbtout]_i_1/O
                         net (fo=9, routed)           0.656     3.718    RLINK/CORE/RL/R_REGS_reg[rbtout]
    SLICE_X41Y85         LUT6 (Prop_lut6_I2_O)        0.124     3.842 r  RLINK/CORE/RL/R_LREGS[din][15]_i_3/O
                         net (fo=4, routed)           0.473     4.316    RLINK/CORE/RL/R_LREGS[din][15]_i_3_n_0
    SLICE_X41Y87         LUT6 (Prop_lut6_I5_O)        0.124     4.440 r  RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_6/O
                         net (fo=2, routed)           0.418     4.858    RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_6_n_0
    SLICE_X41Y87         LUT6 (Prop_lut6_I4_O)        0.124     4.982 r  RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_1/O
                         net (fo=4, routed)           0.494     5.475    RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_1_n_0
    SLICE_X43Y86         FDRE                                         r  RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state][23]/R
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.900    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.432     6.789    RLINK/CORE/RL/CLKFX
    SLICE_X43Y86         FDRE                                         r  RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state][23]/C
                         clock pessimism              0.575     7.364    
                         clock uncertainty           -0.036     7.328    
    SLICE_X43Y86         FDRE (Setup_fdre_C_R)       -0.429     6.899    RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state][23]
  -------------------------------------------------------------------
                         required time                          6.899    
                         arrival time                          -5.475    
  -------------------------------------------------------------------
                         slack                                  1.424    

Slack (MET) :             1.424ns  (required time - arrival time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[addr][6]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state][26]/R
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.427ns  (logic 1.336ns (20.788%)  route 5.091ns (79.212%))
  Logic Levels:           6  (LUT4=1 LUT6=5)
  Clock Path Skew:        -0.018ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.544ns = ( 6.789 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.951ns
    Clock Pessimism Removal (CPR):    0.575ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.709    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.542    -0.951    RLINK/CORE/RL/CLKFX
    SLICE_X41Y80         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[addr][6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y80         FDRE (Prop_fdre_C_Q)         0.419    -0.532 r  RLINK/CORE/RL/R_LREGS_reg[addr][6]/Q
                         net (fo=17, routed)          1.185     0.653    RLINK/CORE/RL/R_REGS_reg[rbaddr][6]
    SLICE_X35Y73         LUT4 (Prop_lut4_I0_O)        0.297     0.950 f  RLINK/CORE/RL/RB_SRES_OR[err]0_i_5/O
                         net (fo=24, routed)          0.843     1.793    SMRB.I0/SMRB/R_LREGS_reg[addr][6]
    SLICE_X33Y72         LUT6 (Prop_lut6_I1_O)        0.124     1.917 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           1.021     2.938    RLINK/CORE/RL/RB_SRES_SYSMON[busy]
    SLICE_X39Y80         LUT6 (Prop_lut6_I0_O)        0.124     3.062 f  RLINK/CORE/RL/R_REGS[rbtout]_i_1/O
                         net (fo=9, routed)           0.656     3.718    RLINK/CORE/RL/R_REGS_reg[rbtout]
    SLICE_X41Y85         LUT6 (Prop_lut6_I2_O)        0.124     3.842 r  RLINK/CORE/RL/R_LREGS[din][15]_i_3/O
                         net (fo=4, routed)           0.473     4.316    RLINK/CORE/RL/R_LREGS[din][15]_i_3_n_0
    SLICE_X41Y87         LUT6 (Prop_lut6_I5_O)        0.124     4.440 r  RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_6/O
                         net (fo=2, routed)           0.418     4.858    RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_6_n_0
    SLICE_X41Y87         LUT6 (Prop_lut6_I4_O)        0.124     4.982 r  RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_1/O
                         net (fo=4, routed)           0.494     5.475    RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_1_n_0
    SLICE_X43Y86         FDRE                                         r  RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state][26]/R
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.900    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.432     6.789    RLINK/CORE/RL/CLKFX
    SLICE_X43Y86         FDRE                                         r  RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state][26]/C
                         clock pessimism              0.575     7.364    
                         clock uncertainty           -0.036     7.328    
    SLICE_X43Y86         FDRE (Setup_fdre_C_R)       -0.429     6.899    RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state][26]
  -------------------------------------------------------------------
                         required time                          6.899    
                         arrival time                          -5.475    
  -------------------------------------------------------------------
                         slack                                  1.424    

Slack (MET) :             1.450ns  (required time - arrival time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[addr][0]_rep/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_BREGS_reg[rbdout][14]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.853ns  (logic 0.704ns (10.273%)  route 6.149ns (89.727%))
  Logic Levels:           2  (LUT5=1 LUT6=1)
  Clock Path Skew:        -0.024ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.550ns = ( 6.783 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.951ns
    Clock Pessimism Removal (CPR):    0.575ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.709    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.542    -0.951    RLINK/CORE/RL/CLKFX
    SLICE_X41Y80         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[addr][0]_rep/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y80         FDRE (Prop_fdre_C_Q)         0.456    -0.495 r  RLINK/CORE/RL/R_LREGS_reg[addr][0]_rep/Q
                         net (fo=115, routed)         3.298     2.802    UARB/UA/R_LREGS_reg[addr][0]_rep
    SLICE_X28Y32         LUT5 (Prop_lut5_I2_O)        0.124     2.926 r  UARB/UA/R_BREGS[rbdout][14]_i_5/O
                         net (fo=2, routed)           2.851     5.777    RLINK/CORE/RL/SEL/RB_SRES_USRACC[dout][4]
    SLICE_X40Y79         LUT6 (Prop_lut6_I5_O)        0.124     5.901 r  RLINK/CORE/RL/SEL/R_BREGS[rbdout][14]_i_1/O
                         net (fo=1, routed)           0.000     5.901    RLINK/CORE/RL/RB_SRES_OR[dout]_1[14]
    SLICE_X40Y79         FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][14]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.900    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.426     6.783    RLINK/CORE/RL/CLKFX
    SLICE_X40Y79         FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][14]/C
                         clock pessimism              0.575     7.358    
                         clock uncertainty           -0.036     7.322    
    SLICE_X40Y79         FDRE (Setup_fdre_C_D)        0.029     7.351    RLINK/CORE/RL/R_BREGS_reg[rbdout][14]
  -------------------------------------------------------------------
                         required time                          7.351    
                         arrival time                          -5.901    
  -------------------------------------------------------------------
                         slack                                  1.450    

Slack (MET) :             1.452ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][12]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.668ns  (logic 1.928ns (28.913%)  route 4.740ns (71.087%))
  Logic Levels:           7  (CARRY4=4 LUT3=2 LUT6=1)
  Clock Path Skew:        -0.239ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.541ns = ( 6.792 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.819ns
    Clock Pessimism Removal (CPR):    0.483ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.709    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.674    -0.819    IOB_RS232/IOB_RXD/IOB/CLKFX
    ILOGIC_X0Y36         FDRE                                         r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y36         FDRE (Prop_fdre_C_Q)         0.517    -0.302 f  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=24, routed)          3.468     3.166    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X34Y98         LUT3 (Prop_lut3_I1_O)        0.180     3.346 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_10/O
                         net (fo=1, routed)           0.452     3.798    RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_10_n_0
    SLICE_X34Y98         LUT6 (Prop_lut6_I2_O)        0.124     3.922 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_3/O
                         net (fo=15, routed)          0.820     4.742    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][12]_0
    SLICE_X33Y92         LUT3 (Prop_lut3_I2_O)        0.124     4.866 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_8/O
                         net (fo=1, routed)           0.000     4.866    RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_8_n_0
    SLICE_X33Y92         CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     5.398 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][0]_i_2/CO[3]
                         net (fo=1, routed)           0.000     5.398    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][0]_i_2_n_0
    SLICE_X33Y93         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     5.512 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][4]_i_1/CO[3]
                         net (fo=1, routed)           0.000     5.512    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][4]_i_1_n_0
    SLICE_X33Y94         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     5.626 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][8]_i_1/CO[3]
                         net (fo=1, routed)           0.000     5.626    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][8]_i_1_n_0
    SLICE_X33Y95         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.223     5.849 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][12]_i_1/O[0]
                         net (fo=1, routed)           0.000     5.849    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][12]_i_1_n_7
    SLICE_X33Y95         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][12]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.900    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        1.435     6.792    RLINK/SERPORT/UART/RXTX/RX/CLKFX
    SLICE_X33Y95         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][12]/C
                         clock pessimism              0.483     7.274    
                         clock uncertainty           -0.036     7.239    
    SLICE_X33Y95         FDRE (Setup_fdre_C_D)        0.062     7.301    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][12]
  -------------------------------------------------------------------
                         required time                          7.301    
                         arrival time                          -5.849    
  -------------------------------------------------------------------
                         slack                                  1.452    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.037ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.841ns
    Source Clock Delay      (SCD):    -0.603ns
    Clock Pessimism Removal (CPR):    -0.251ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.684    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.561    -0.603    RLINK/SERPORT/XONRX/CLKFX
    SLICE_X39Y93         FDRE                                         r  RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y93         FDRE (Prop_fdre_C_Q)         0.141    -0.462 r  RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][0]/Q
                         net (fo=1, routed)           0.056    -0.406    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/DIA0
    SLICE_X38Y93         RAMD32                                       r  RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.912    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.829    -0.841    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X38Y93         RAMD32                                       r  RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA/CLK
                         clock pessimism              0.251    -0.590    
    SLICE_X38Y93         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.147    -0.443    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA
  -------------------------------------------------------------------
                         required time                          0.443    
                         arrival time                          -0.406    
  -------------------------------------------------------------------
                         slack                                  0.037    

Slack (MET) :             0.051ns  (arrival time - required time)
  Source:                 RBDTST/EMON/R_REGS_reg[laddr_1][1]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/EMON/BRAM/sv_ram_reg/ADDRBWRADDR[6]
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.288ns  (logic 0.141ns (48.973%)  route 0.147ns (51.027%))
  Logic Levels:           0  
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.809ns
    Source Clock Delay      (SCD):    -0.608ns
    Clock Pessimism Removal (CPR):    -0.254ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.684    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.556    -0.608    RBDTST/EMON/CLKFX
    SLICE_X57Y77         FDRE                                         r  RBDTST/EMON/R_REGS_reg[laddr_1][1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y77         FDRE (Prop_fdre_C_Q)         0.141    -0.467 r  RBDTST/EMON/R_REGS_reg[laddr_1][1]/Q
                         net (fo=1, routed)           0.147    -0.320    RBDTST/EMON/BRAM/ADDRBWRADDR[1]
    RAMB18_X2Y30         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/ADDRBWRADDR[6]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.912    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.862    -0.809    RBDTST/EMON/BRAM/CLKFX
    RAMB18_X2Y30         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/CLKBWRCLK
                         clock pessimism              0.254    -0.554    
    RAMB18_X2Y30         RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[6])
                                                      0.183    -0.371    RBDTST/EMON/BRAM/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.371    
                         arrival time                          -0.320    
  -------------------------------------------------------------------
                         slack                                  0.051    

Slack (MET) :             0.052ns  (arrival time - required time)
  Source:                 RBDTST/EMON/R_REGS_reg[laddr_1][6]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/EMON/BRAM/sv_ram_reg/ADDRBWRADDR[11]
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.289ns  (logic 0.141ns (48.803%)  route 0.148ns (51.197%))
  Logic Levels:           0  
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.809ns
    Source Clock Delay      (SCD):    -0.608ns
    Clock Pessimism Removal (CPR):    -0.254ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.684    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.556    -0.608    RBDTST/EMON/CLKFX
    SLICE_X57Y77         FDRE                                         r  RBDTST/EMON/R_REGS_reg[laddr_1][6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y77         FDRE (Prop_fdre_C_Q)         0.141    -0.467 r  RBDTST/EMON/R_REGS_reg[laddr_1][6]/Q
                         net (fo=1, routed)           0.148    -0.319    RBDTST/EMON/BRAM/ADDRBWRADDR[6]
    RAMB18_X2Y30         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/ADDRBWRADDR[11]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.912    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.862    -0.809    RBDTST/EMON/BRAM/CLKFX
    RAMB18_X2Y30         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/CLKBWRCLK
                         clock pessimism              0.254    -0.554    
    RAMB18_X2Y30         RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[11])
                                                      0.183    -0.371    RBDTST/EMON/BRAM/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.371    
                         arrival time                          -0.319    
  -------------------------------------------------------------------
                         slack                                  0.052    

Slack (MET) :             0.052ns  (arrival time - required time)
  Source:                 RBDTST/EMON/R_REGS_reg[laddr_1][3]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/EMON/BRAM/sv_ram_reg/ADDRBWRADDR[8]
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.289ns  (logic 0.141ns (48.803%)  route 0.148ns (51.197%))
  Logic Levels:           0  
  Clock Path Skew:        0.053ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.809ns
    Source Clock Delay      (SCD):    -0.608ns
    Clock Pessimism Removal (CPR):    -0.254ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.684    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.556    -0.608    RBDTST/EMON/CLKFX
    SLICE_X57Y77         FDRE                                         r  RBDTST/EMON/R_REGS_reg[laddr_1][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X57Y77         FDRE (Prop_fdre_C_Q)         0.141    -0.467 r  RBDTST/EMON/R_REGS_reg[laddr_1][3]/Q
                         net (fo=1, routed)           0.148    -0.319    RBDTST/EMON/BRAM/ADDRBWRADDR[3]
    RAMB18_X2Y30         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/ADDRBWRADDR[8]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.912    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.862    -0.809    RBDTST/EMON/BRAM/CLKFX
    RAMB18_X2Y30         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/CLKBWRCLK
                         clock pessimism              0.254    -0.554    
    RAMB18_X2Y30         RAMB18E1 (Hold_ramb18e1_CLKBWRCLK_ADDRBWRADDR[8])
                                                      0.183    -0.371    RBDTST/EMON/BRAM/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.371    
                         arrival time                          -0.319    
  -------------------------------------------------------------------
                         slack                                  0.052    

Slack (MET) :             0.058ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/R_BREGS_reg[rbdout][1]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1/I
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.439ns  (logic 0.186ns (42.415%)  route 0.253ns (57.585%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.261ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.851ns
    Source Clock Delay      (SCD):    -0.610ns
    Clock Pessimism Removal (CPR):    -0.502ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.684    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.554    -0.610    RLINK/CORE/RL/CLKFX
    SLICE_X39Y81         FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y81         FDRE (Prop_fdre_C_Q)         0.141    -0.469 r  RLINK/CORE/RL/R_BREGS_reg[rbdout][1]/Q
                         net (fo=1, routed)           0.087    -0.382    RLINK/CORE/RL/DOFIFO/FIFO/RAM/R_BREGS_reg[rbdout][1]
    SLICE_X38Y81         LUT5 (Prop_lut5_I3_O)        0.045    -0.337 r  RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5_i_2/O
                         net (fo=1, routed)           0.165    -0.171    RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/DIA1
    SLICE_X34Y81         RAMD32                                       r  RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1/I
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.912    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.819    -0.851    RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X34Y81         RAMD32                                       r  RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1/CLK
                         clock pessimism              0.502    -0.349    
    SLICE_X34Y81         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.120    -0.229    RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1
  -------------------------------------------------------------------
                         required time                          0.229    
                         arrival time                          -0.171    
  -------------------------------------------------------------------
                         slack                                  0.058    

Slack (MET) :             0.067ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/R_BREGS_reg[rbdout][2]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/I
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.475ns  (logic 0.186ns (39.198%)  route 0.289ns (60.802%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.262ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.851ns
    Source Clock Delay      (SCD):    -0.611ns
    Clock Pessimism Removal (CPR):    -0.502ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.684    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.553    -0.611    RLINK/CORE/RL/CLKFX
    SLICE_X39Y80         FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[rbdout][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y80         FDRE (Prop_fdre_C_Q)         0.141    -0.470 r  RLINK/CORE/RL/R_BREGS_reg[rbdout][2]/Q
                         net (fo=1, routed)           0.091    -0.379    RLINK/CORE/RL/DOFIFO/FIFO/RAM/R_BREGS_reg[rbdout][2]
    SLICE_X38Y80         LUT5 (Prop_lut5_I3_O)        0.045    -0.334 r  RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5_i_5/O
                         net (fo=1, routed)           0.197    -0.136    RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/DIB0
    SLICE_X34Y81         RAMD32                                       r  RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/I
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.912    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.819    -0.851    RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X34Y81         RAMD32                                       r  RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
                         clock pessimism              0.502    -0.349    
    SLICE_X34Y81         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.146    -0.203    RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB
  -------------------------------------------------------------------
                         required time                          0.203    
                         arrival time                          -0.136    
  -------------------------------------------------------------------
                         slack                                  0.067    

Slack (MET) :             0.078ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/R_RXOK_reg/C
                            (rising edge-triggered cell FDSE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/XONTX/R_REGS_reg[obuf][5]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.461ns  (logic 0.186ns (40.321%)  route 0.275ns (59.679%))
  Logic Levels:           1  (LUT3=1)
  Clock Path Skew:        0.262ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.843ns
    Source Clock Delay      (SCD):    -0.603ns
    Clock Pessimism Removal (CPR):    -0.502ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.684    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.561    -0.603    RLINK/SERPORT/CLKFX
    SLICE_X37Y94         FDSE                                         r  RLINK/SERPORT/R_RXOK_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y94         FDSE (Prop_fdse_C_Q)         0.141    -0.462 r  RLINK/SERPORT/R_RXOK_reg/Q
                         net (fo=8, routed)           0.275    -0.186    RLINK/SERPORT/XONTX/R_RXOK_reg
    SLICE_X34Y90         LUT3 (Prop_lut3_I1_O)        0.045    -0.141 r  RLINK/SERPORT/XONTX/R_REGS[obuf][5]_i_1/O
                         net (fo=1, routed)           0.000    -0.141    RLINK/SERPORT/XONTX/N_REGS[obuf]1_in[5]
    SLICE_X34Y90         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[obuf][5]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.912    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.827    -0.843    RLINK/SERPORT/XONTX/CLKFX
    SLICE_X34Y90         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[obuf][5]/C
                         clock pessimism              0.502    -0.341    
    SLICE_X34Y90         FDRE (Hold_fdre_C_D)         0.121    -0.220    RLINK/SERPORT/XONTX/R_REGS_reg[obuf][5]
  -------------------------------------------------------------------
                         required time                          0.220    
                         arrival time                          -0.141    
  -------------------------------------------------------------------
                         slack                                  0.078    

Slack (MET) :             0.080ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/R_RXOK_reg/C
                            (rising edge-triggered cell FDSE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/XONTX/R_REGS_reg[rxok]__0/D
                            (rising edge-triggered cell FDSE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.463ns  (logic 0.186ns (40.147%)  route 0.277ns (59.853%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.262ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.843ns
    Source Clock Delay      (SCD):    -0.603ns
    Clock Pessimism Removal (CPR):    -0.502ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.684    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.561    -0.603    RLINK/SERPORT/CLKFX
    SLICE_X37Y94         FDSE                                         r  RLINK/SERPORT/R_RXOK_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y94         FDSE (Prop_fdse_C_Q)         0.141    -0.462 r  RLINK/SERPORT/R_RXOK_reg/Q
                         net (fo=8, routed)           0.277    -0.184    RLINK/SERPORT/XONTX/R_RXOK_reg
    SLICE_X34Y91         LUT4 (Prop_lut4_I2_O)        0.045    -0.139 r  RLINK/SERPORT/XONTX/R_REGS[rxok]_i_1/O
                         net (fo=1, routed)           0.000    -0.139    RLINK/SERPORT/XONTX/R_REGS[rxok]_i_1_n_0
    SLICE_X34Y91         FDSE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[rxok]__0/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.912    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.827    -0.843    RLINK/SERPORT/XONTX/CLKFX
    SLICE_X34Y91         FDSE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[rxok]__0/C
                         clock pessimism              0.502    -0.341    
    SLICE_X34Y91         FDSE (Hold_fdse_C_D)         0.121    -0.220    RLINK/SERPORT/XONTX/R_REGS_reg[rxok]__0
  -------------------------------------------------------------------
                         required time                          0.220    
                         arrival time                          -0.139    
  -------------------------------------------------------------------
                         slack                                  0.080    

Slack (MET) :             0.084ns  (arrival time - required time)
  Source:                 RLINK/CORE/CD2B/R_REGS_reg[data][2]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/TXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/I
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.246ns  (logic 0.141ns (57.415%)  route 0.105ns (42.585%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.843ns
    Source Clock Delay      (SCD):    -0.605ns
    Clock Pessimism Removal (CPR):    -0.254ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.684    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.559    -0.605    RLINK/CORE/CD2B/CLKFX
    SLICE_X32Y89         FDRE                                         r  RLINK/CORE/CD2B/R_REGS_reg[data][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X32Y89         FDRE (Prop_fdre_C_Q)         0.141    -0.464 r  RLINK/CORE/CD2B/R_REGS_reg[data][2]/Q
                         net (fo=1, routed)           0.105    -0.359    RLINK/SERPORT/TXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/DIB0
    SLICE_X30Y89         RAMD32                                       r  RLINK/SERPORT/TXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/I
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.912    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.827    -0.843    RLINK/SERPORT/TXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X30Y89         RAMD32                                       r  RLINK/SERPORT/TXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
                         clock pessimism              0.254    -0.589    
    SLICE_X30Y89         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.146    -0.443    RLINK/SERPORT/TXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB
  -------------------------------------------------------------------
                         required time                          0.443    
                         arrival time                          -0.359    
  -------------------------------------------------------------------
                         slack                                  0.084    

Slack (MET) :             0.084ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][4]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC/I
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.187ns  (logic 0.128ns (68.397%)  route 0.059ns (31.603%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.841ns
    Source Clock Delay      (SCD):    -0.603ns
    Clock Pessimism Removal (CPR):    -0.251ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.684    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.561    -0.603    RLINK/SERPORT/XONRX/CLKFX
    SLICE_X39Y93         FDRE                                         r  RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y93         FDRE (Prop_fdre_C_Q)         0.128    -0.475 r  RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][4]/Q
                         net (fo=1, routed)           0.059    -0.416    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/DIC0
    SLICE_X38Y93         RAMD32                                       r  RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC/I
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.912    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1003, routed)        0.829    -0.841    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X38Y93         RAMD32                                       r  RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
                         clock pessimism              0.251    -0.590    
    SLICE_X38Y93         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.090    -0.500    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC
  -------------------------------------------------------------------
                         required time                          0.500    
                         arrival time                          -0.416    
  -------------------------------------------------------------------
                         slack                                  0.084    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         CLKOUT0
Waveform(ns):       { 0.000 4.167 }
Period(ns):         8.333
Sources:            { GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     XADC/DCLK           n/a            4.000         8.333       4.333      XADC_X0Y0        SMRB.I0/SM/DCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.944         8.333       5.389      RAMB18_X2Y30     RBDTST/EMON/BRAM/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.944         8.333       5.389      RAMB18_X2Y30     RBDTST/EMON/BRAM/sv_ram_reg/CLKBWRCLK
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.944         8.333       5.389      RAMB36_X1Y17     RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.944         8.333       5.389      RAMB36_X1Y17     RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         8.333       5.757      RAMB18_X1Y30     RBDTST/MON/BRAM0/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.576         8.333       5.757      RAMB18_X1Y30     RBDTST/MON/BRAM0/sv_ram_reg/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         8.333       5.757      RAMB18_X1Y32     RBDTST/BRAM/BRAM/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         8.333       5.757      RAMB18_X1Y29     RBDTST/MON/BRAM1/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.576         8.333       5.757      RAMB18_X1Y29     RBDTST/MON/BRAM1/sv_ram_reg/CLKBWRCLK
Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       8.333       205.027    MMCME2_ADV_X0Y0  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.166       2.916      SLICE_X30Y89     RLINK/SERPORT/TXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.166       2.916      SLICE_X30Y89     RLINK/SERPORT/TXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.166       2.916      SLICE_X30Y89     RLINK/SERPORT/TXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.166       2.916      SLICE_X30Y89     RLINK/SERPORT/TXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.166       2.916      SLICE_X30Y89     RLINK/SERPORT/TXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.166       2.916      SLICE_X30Y89     RLINK/SERPORT/TXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC_D1/CLK
Low Pulse Width   Fast    RAMS32/CLK          n/a            1.250         4.166       2.916      SLICE_X30Y89     RLINK/SERPORT/TXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMD/CLK
Low Pulse Width   Fast    RAMS32/CLK          n/a            1.250         4.166       2.916      SLICE_X30Y89     RLINK/SERPORT/TXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMD_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.166       2.916      SLICE_X38Y78     TEST/FIFO/RAM/RAM_reg_0_15_12_15/RAMA/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.166       2.916      SLICE_X38Y78     TEST/FIFO/RAM/RAM_reg_0_15_12_15/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.166       2.916      SLICE_X38Y93     RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.166       2.916      SLICE_X38Y93     RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.166       2.916      SLICE_X38Y93     RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.166       2.916      SLICE_X38Y93     RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.166       2.916      SLICE_X38Y93     RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.166       2.916      SLICE_X38Y93     RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC_D1/CLK
High Pulse Width  Fast    RAMS32/CLK          n/a            1.250         4.166       2.916      SLICE_X38Y93     RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMD/CLK
High Pulse Width  Fast    RAMS32/CLK          n/a            1.250         4.166       2.916      SLICE_X38Y93     RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMD_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.166       2.916      SLICE_X38Y94     RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.166       2.916      SLICE_X38Y94     RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA_D1/CLK



