Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017
| Date         : Sun Aug 26 13:29:04 2018
| Host         : athome running 64-bit Ubuntu 16.04.5 LTS
| Command      : report_timing_summary -warn_on_violation -max_paths 10 -file sys_tst_sram_c7_timing_summary_routed.rpt -rpx sys_tst_sram_c7_timing_summary_routed.rpx
| Design       : sys_tst_sram_c7
| Device       : 7a35t-cpg236
| Speed File   : -1  PRODUCTION 1.17 2017-05-11
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  false

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
--------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock
--------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
--------------------------
 There are 9 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
 There are 33 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
--------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops
------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      2.577        0.000                      0                 2963        0.080        0.000                      0                 2914        2.917        0.000                       0                  1159  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock         Waveform(ns)         Period(ns)      Frequency(MHz)
-----         ------------         ----------      --------------
I_CLK12       {0.000 41.660}       83.330          12.000          
  CLKFBOUT    {0.000 41.665}       83.330          12.000          
  CLKFBOUT_1  {0.000 41.665}       83.330          12.000          
  CLKOUT0     {0.000 4.167}        8.333           120.005         
  CLKOUT0_1   {0.000 6.250}        12.499          80.003          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
I_CLK12                                                                                                                                                        16.670        0.000                       0                     2  
  CLKFBOUT                                                                                                                                                     16.670        0.000                       0                     3  
  CLKFBOUT_1                                                                                                                                                   16.670        0.000                       0                     3  
  CLKOUT0           2.676        0.000                      0                  476        0.080        0.000                      0                  476        2.917        0.000                       0                   215  
  CLKOUT0_1         2.577        0.000                      0                 2438        0.082        0.000                      0                 2438        5.000        0.000                       0                   936  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  
CLKOUT0_1     CLKOUT0             5.037        0.000                      0                   23                                                                        
CLKOUT0       CLKOUT0_1           5.276        0.000                      0                   45                                                                        


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  I_CLK12
  To Clock:  I_CLK12

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       16.670ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         I_CLK12
Waveform(ns):       { 0.000 41.660 }
Period(ns):         83.330
Sources:            { I_CLK12 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     MMCME2_ADV/CLKIN1  n/a            1.249         83.330      82.081     MMCME2_ADV_X0Y0  GEN_CLKSER/USEMMCM.MMCM/CLKIN1
Min Period        n/a     MMCME2_ADV/CLKIN1  n/a            1.249         83.330      82.081     MMCME2_ADV_X0Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
Max Period        n/a     MMCME2_ADV/CLKIN1  n/a            100.000       83.330      16.670     MMCME2_ADV_X0Y0  GEN_CLKSER/USEMMCM.MMCM/CLKIN1
Max Period        n/a     MMCME2_ADV/CLKIN1  n/a            100.000       83.330      16.670     MMCME2_ADV_X0Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
Low Pulse Width   Fast    MMCME2_ADV/CLKIN1  n/a            10.000        41.670      31.670     MMCME2_ADV_X0Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
Low Pulse Width   Slow    MMCME2_ADV/CLKIN1  n/a            10.000        41.670      31.670     MMCME2_ADV_X0Y0  GEN_CLKSER/USEMMCM.MMCM/CLKIN1
Low Pulse Width   Fast    MMCME2_ADV/CLKIN1  n/a            10.000        41.670      31.670     MMCME2_ADV_X0Y0  GEN_CLKSER/USEMMCM.MMCM/CLKIN1
Low Pulse Width   Slow    MMCME2_ADV/CLKIN1  n/a            10.000        41.670      31.670     MMCME2_ADV_X0Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
High Pulse Width  Slow    MMCME2_ADV/CLKIN1  n/a            10.000        41.660      31.660     MMCME2_ADV_X0Y0  GEN_CLKSER/USEMMCM.MMCM/CLKIN1
High Pulse Width  Fast    MMCME2_ADV/CLKIN1  n/a            10.000        41.660      31.660     MMCME2_ADV_X0Y0  GEN_CLKSER/USEMMCM.MMCM/CLKIN1
High Pulse Width  Slow    MMCME2_ADV/CLKIN1  n/a            10.000        41.660      31.660     MMCME2_ADV_X0Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
High Pulse Width  Fast    MMCME2_ADV/CLKIN1  n/a            10.000        41.660      31.660     MMCME2_ADV_X0Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  CLKFBOUT
  To Clock:  CLKFBOUT

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       16.670ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         CLKFBOUT
Waveform(ns):       { 0.000 41.665 }
Period(ns):         83.330
Sources:            { GEN_CLKSER/USEMMCM.MMCM/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFG/I               n/a            2.155         83.330      81.175     BUFGCTRL_X0Y1    GEN_CLKSER/USEMMCM.BUFG_CLKFB/I
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         83.330      82.081     MMCME2_ADV_X0Y0  GEN_CLKSER/USEMMCM.MMCM/CLKFBOUT
Min Period  n/a     MMCME2_ADV/CLKFBIN   n/a            1.249         83.330      82.081     MMCME2_ADV_X0Y0  GEN_CLKSER/USEMMCM.MMCM/CLKFBIN
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       83.330      16.670     MMCME2_ADV_X0Y0  GEN_CLKSER/USEMMCM.MMCM/CLKFBIN
Max Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            213.360       83.330      130.030    MMCME2_ADV_X0Y0  GEN_CLKSER/USEMMCM.MMCM/CLKFBOUT



---------------------------------------------------------------------------------------------------
From Clock:  CLKFBOUT_1
  To Clock:  CLKFBOUT_1

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack       16.670ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         CLKFBOUT_1
Waveform(ns):       { 0.000 41.665 }
Period(ns):         83.330
Sources:            { GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFG/I               n/a            2.155         83.330      81.175     BUFGCTRL_X0Y17   GEN_CLKSYS/USEMMCM.BUFG_CLKFB/I
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         83.330      82.081     MMCME2_ADV_X0Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT
Min Period  n/a     MMCME2_ADV/CLKFBIN   n/a            1.249         83.330      82.081     MMCME2_ADV_X0Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKFBIN
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       83.330      16.670     MMCME2_ADV_X0Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKFBIN
Max Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            213.360       83.330      130.030    MMCME2_ADV_X0Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT



---------------------------------------------------------------------------------------------------
From Clock:  CLKOUT0
  To Clock:  CLKOUT0

Setup :            0  Failing Endpoints,  Worst Slack        2.676ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.080ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.917ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.676ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][9]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        5.714ns  (logic 2.773ns (48.526%)  route 2.941ns (51.474%))
  Logic Levels:           8  (CARRY4=5 LUT4=1 LUT6=2)
  Clock Path Skew:        0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.458ns = ( 6.875 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.926ns
    Clock Pessimism Removal (CPR):    0.563ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.709    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.567    -0.926    RLINK/SERPORT/UART/AB/I_CLK12
    SLICE_X9Y40          FDRE                                         r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y40          FDRE (Prop_fdre_C_Q)         0.456    -0.470 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/Q
                         net (fo=6, routed)           1.073     0.603    RLINK/SERPORT/UART/RXTX/RX/Q[2]
    SLICE_X4Y41          LUT4 (Prop_lut4_I1_O)        0.124     0.727 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8/O
                         net (fo=1, routed)           0.000     0.727    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8_n_0
    SLICE_X4Y41          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     1.259 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry/CO[3]
                         net (fo=1, routed)           0.000     1.259    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_n_0
    SLICE_X4Y42          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.250     1.509 f  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry__0/CO[2]
                         net (fo=11, routed)          0.562     2.071    RLINK/SERPORT/UART/RXTX/RX/n[state]1
    SLICE_X2Y43          LUT6 (Prop_lut6_I3_O)        0.313     2.384 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.591     2.976    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11_n_0
    SLICE_X2Y42          LUT6 (Prop_lut6_I1_O)        0.124     3.100 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=23, routed)          0.715     3.815    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_2__0_n_0
    SLICE_X3Y39          CARRY4 (Prop_carry4_DI[0]_CO[3])
                                                      0.526     4.341 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.341    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1_n_0
    SLICE_X3Y40          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.455 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.455    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1_n_0
    SLICE_X3Y41          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334     4.789 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1/O[1]
                         net (fo=1, routed)           0.000     4.789    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1_n_6
    SLICE_X3Y41          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][9]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.162    10.900    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.518     6.875    RLINK/SERPORT/UART/RXTX/RX/I_CLK12
    SLICE_X3Y41          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][9]/C
                         clock pessimism              0.563     7.438    
                         clock uncertainty           -0.036     7.402    
    SLICE_X3Y41          FDRE (Setup_fdre_C_D)        0.062     7.464    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][9]
  -------------------------------------------------------------------
                         required time                          7.464    
                         arrival time                          -4.789    
  -------------------------------------------------------------------
                         slack                                  2.676    

Slack (MET) :             2.697ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][11]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        5.693ns  (logic 2.752ns (48.336%)  route 2.941ns (51.664%))
  Logic Levels:           8  (CARRY4=5 LUT4=1 LUT6=2)
  Clock Path Skew:        0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.458ns = ( 6.875 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.926ns
    Clock Pessimism Removal (CPR):    0.563ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.709    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.567    -0.926    RLINK/SERPORT/UART/AB/I_CLK12
    SLICE_X9Y40          FDRE                                         r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y40          FDRE (Prop_fdre_C_Q)         0.456    -0.470 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/Q
                         net (fo=6, routed)           1.073     0.603    RLINK/SERPORT/UART/RXTX/RX/Q[2]
    SLICE_X4Y41          LUT4 (Prop_lut4_I1_O)        0.124     0.727 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8/O
                         net (fo=1, routed)           0.000     0.727    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8_n_0
    SLICE_X4Y41          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     1.259 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry/CO[3]
                         net (fo=1, routed)           0.000     1.259    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_n_0
    SLICE_X4Y42          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.250     1.509 f  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry__0/CO[2]
                         net (fo=11, routed)          0.562     2.071    RLINK/SERPORT/UART/RXTX/RX/n[state]1
    SLICE_X2Y43          LUT6 (Prop_lut6_I3_O)        0.313     2.384 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.591     2.976    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11_n_0
    SLICE_X2Y42          LUT6 (Prop_lut6_I1_O)        0.124     3.100 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=23, routed)          0.715     3.815    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_2__0_n_0
    SLICE_X3Y39          CARRY4 (Prop_carry4_DI[0]_CO[3])
                                                      0.526     4.341 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.341    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1_n_0
    SLICE_X3Y40          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.455 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.455    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1_n_0
    SLICE_X3Y41          CARRY4 (Prop_carry4_CI_O[3])
                                                      0.313     4.768 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1/O[3]
                         net (fo=1, routed)           0.000     4.768    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1_n_4
    SLICE_X3Y41          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][11]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.162    10.900    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.518     6.875    RLINK/SERPORT/UART/RXTX/RX/I_CLK12
    SLICE_X3Y41          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][11]/C
                         clock pessimism              0.563     7.438    
                         clock uncertainty           -0.036     7.402    
    SLICE_X3Y41          FDRE (Setup_fdre_C_D)        0.062     7.464    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][11]
  -------------------------------------------------------------------
                         required time                          7.464    
                         arrival time                          -4.768    
  -------------------------------------------------------------------
                         slack                                  2.697    

Slack (MET) :             2.771ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][10]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        5.619ns  (logic 2.678ns (47.656%)  route 2.941ns (52.344%))
  Logic Levels:           8  (CARRY4=5 LUT4=1 LUT6=2)
  Clock Path Skew:        0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.458ns = ( 6.875 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.926ns
    Clock Pessimism Removal (CPR):    0.563ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.709    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.567    -0.926    RLINK/SERPORT/UART/AB/I_CLK12
    SLICE_X9Y40          FDRE                                         r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y40          FDRE (Prop_fdre_C_Q)         0.456    -0.470 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/Q
                         net (fo=6, routed)           1.073     0.603    RLINK/SERPORT/UART/RXTX/RX/Q[2]
    SLICE_X4Y41          LUT4 (Prop_lut4_I1_O)        0.124     0.727 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8/O
                         net (fo=1, routed)           0.000     0.727    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8_n_0
    SLICE_X4Y41          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     1.259 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry/CO[3]
                         net (fo=1, routed)           0.000     1.259    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_n_0
    SLICE_X4Y42          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.250     1.509 f  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry__0/CO[2]
                         net (fo=11, routed)          0.562     2.071    RLINK/SERPORT/UART/RXTX/RX/n[state]1
    SLICE_X2Y43          LUT6 (Prop_lut6_I3_O)        0.313     2.384 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.591     2.976    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11_n_0
    SLICE_X2Y42          LUT6 (Prop_lut6_I1_O)        0.124     3.100 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=23, routed)          0.715     3.815    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_2__0_n_0
    SLICE_X3Y39          CARRY4 (Prop_carry4_DI[0]_CO[3])
                                                      0.526     4.341 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.341    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1_n_0
    SLICE_X3Y40          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.455 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.455    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1_n_0
    SLICE_X3Y41          CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     4.694 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1/O[2]
                         net (fo=1, routed)           0.000     4.694    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1_n_5
    SLICE_X3Y41          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][10]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.162    10.900    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.518     6.875    RLINK/SERPORT/UART/RXTX/RX/I_CLK12
    SLICE_X3Y41          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][10]/C
                         clock pessimism              0.563     7.438    
                         clock uncertainty           -0.036     7.402    
    SLICE_X3Y41          FDRE (Setup_fdre_C_D)        0.062     7.464    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][10]
  -------------------------------------------------------------------
                         required time                          7.464    
                         arrival time                          -4.694    
  -------------------------------------------------------------------
                         slack                                  2.771    

Slack (MET) :             2.787ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        5.603ns  (logic 2.662ns (47.507%)  route 2.941ns (52.493%))
  Logic Levels:           8  (CARRY4=5 LUT4=1 LUT6=2)
  Clock Path Skew:        0.031ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.458ns = ( 6.875 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.926ns
    Clock Pessimism Removal (CPR):    0.563ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.709    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.567    -0.926    RLINK/SERPORT/UART/AB/I_CLK12
    SLICE_X9Y40          FDRE                                         r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y40          FDRE (Prop_fdre_C_Q)         0.456    -0.470 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/Q
                         net (fo=6, routed)           1.073     0.603    RLINK/SERPORT/UART/RXTX/RX/Q[2]
    SLICE_X4Y41          LUT4 (Prop_lut4_I1_O)        0.124     0.727 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8/O
                         net (fo=1, routed)           0.000     0.727    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8_n_0
    SLICE_X4Y41          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     1.259 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry/CO[3]
                         net (fo=1, routed)           0.000     1.259    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_n_0
    SLICE_X4Y42          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.250     1.509 f  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry__0/CO[2]
                         net (fo=11, routed)          0.562     2.071    RLINK/SERPORT/UART/RXTX/RX/n[state]1
    SLICE_X2Y43          LUT6 (Prop_lut6_I3_O)        0.313     2.384 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.591     2.976    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11_n_0
    SLICE_X2Y42          LUT6 (Prop_lut6_I1_O)        0.124     3.100 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=23, routed)          0.715     3.815    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_2__0_n_0
    SLICE_X3Y39          CARRY4 (Prop_carry4_DI[0]_CO[3])
                                                      0.526     4.341 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.341    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1_n_0
    SLICE_X3Y40          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.455 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.455    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1_n_0
    SLICE_X3Y41          CARRY4 (Prop_carry4_CI_O[0])
                                                      0.223     4.678 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1/O[0]
                         net (fo=1, routed)           0.000     4.678    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1_n_7
    SLICE_X3Y41          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.162    10.900    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.518     6.875    RLINK/SERPORT/UART/RXTX/RX/I_CLK12
    SLICE_X3Y41          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]/C
                         clock pessimism              0.563     7.438    
                         clock uncertainty           -0.036     7.402    
    SLICE_X3Y41          FDRE (Setup_fdre_C_D)        0.062     7.464    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]
  -------------------------------------------------------------------
                         required time                          7.464    
                         arrival time                          -4.678    
  -------------------------------------------------------------------
                         slack                                  2.787    

Slack (MET) :             2.789ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][5]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        5.600ns  (logic 2.659ns (47.479%)  route 2.941ns (52.521%))
  Logic Levels:           7  (CARRY4=4 LUT4=1 LUT6=2)
  Clock Path Skew:        0.030ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.459ns = ( 6.874 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.926ns
    Clock Pessimism Removal (CPR):    0.563ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.709    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.567    -0.926    RLINK/SERPORT/UART/AB/I_CLK12
    SLICE_X9Y40          FDRE                                         r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y40          FDRE (Prop_fdre_C_Q)         0.456    -0.470 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/Q
                         net (fo=6, routed)           1.073     0.603    RLINK/SERPORT/UART/RXTX/RX/Q[2]
    SLICE_X4Y41          LUT4 (Prop_lut4_I1_O)        0.124     0.727 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8/O
                         net (fo=1, routed)           0.000     0.727    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8_n_0
    SLICE_X4Y41          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     1.259 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry/CO[3]
                         net (fo=1, routed)           0.000     1.259    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_n_0
    SLICE_X4Y42          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.250     1.509 f  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry__0/CO[2]
                         net (fo=11, routed)          0.562     2.071    RLINK/SERPORT/UART/RXTX/RX/n[state]1
    SLICE_X2Y43          LUT6 (Prop_lut6_I3_O)        0.313     2.384 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.591     2.976    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11_n_0
    SLICE_X2Y42          LUT6 (Prop_lut6_I1_O)        0.124     3.100 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=23, routed)          0.715     3.815    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_2__0_n_0
    SLICE_X3Y39          CARRY4 (Prop_carry4_DI[0]_CO[3])
                                                      0.526     4.341 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.341    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1_n_0
    SLICE_X3Y40          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334     4.675 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1/O[1]
                         net (fo=1, routed)           0.000     4.675    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1_n_6
    SLICE_X3Y40          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][5]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.162    10.900    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.517     6.874    RLINK/SERPORT/UART/RXTX/RX/I_CLK12
    SLICE_X3Y40          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][5]/C
                         clock pessimism              0.563     7.437    
                         clock uncertainty           -0.036     7.401    
    SLICE_X3Y40          FDRE (Setup_fdre_C_D)        0.062     7.463    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][5]
  -------------------------------------------------------------------
                         required time                          7.463    
                         arrival time                          -4.675    
  -------------------------------------------------------------------
                         slack                                  2.789    

Slack (MET) :             2.810ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][7]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        5.579ns  (logic 2.638ns (47.281%)  route 2.941ns (52.719%))
  Logic Levels:           7  (CARRY4=4 LUT4=1 LUT6=2)
  Clock Path Skew:        0.030ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.459ns = ( 6.874 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.926ns
    Clock Pessimism Removal (CPR):    0.563ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.709    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.567    -0.926    RLINK/SERPORT/UART/AB/I_CLK12
    SLICE_X9Y40          FDRE                                         r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y40          FDRE (Prop_fdre_C_Q)         0.456    -0.470 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/Q
                         net (fo=6, routed)           1.073     0.603    RLINK/SERPORT/UART/RXTX/RX/Q[2]
    SLICE_X4Y41          LUT4 (Prop_lut4_I1_O)        0.124     0.727 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8/O
                         net (fo=1, routed)           0.000     0.727    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8_n_0
    SLICE_X4Y41          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     1.259 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry/CO[3]
                         net (fo=1, routed)           0.000     1.259    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_n_0
    SLICE_X4Y42          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.250     1.509 f  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry__0/CO[2]
                         net (fo=11, routed)          0.562     2.071    RLINK/SERPORT/UART/RXTX/RX/n[state]1
    SLICE_X2Y43          LUT6 (Prop_lut6_I3_O)        0.313     2.384 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.591     2.976    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11_n_0
    SLICE_X2Y42          LUT6 (Prop_lut6_I1_O)        0.124     3.100 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=23, routed)          0.715     3.815    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_2__0_n_0
    SLICE_X3Y39          CARRY4 (Prop_carry4_DI[0]_CO[3])
                                                      0.526     4.341 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.341    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1_n_0
    SLICE_X3Y40          CARRY4 (Prop_carry4_CI_O[3])
                                                      0.313     4.654 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1/O[3]
                         net (fo=1, routed)           0.000     4.654    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1_n_4
    SLICE_X3Y40          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][7]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.162    10.900    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.517     6.874    RLINK/SERPORT/UART/RXTX/RX/I_CLK12
    SLICE_X3Y40          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][7]/C
                         clock pessimism              0.563     7.437    
                         clock uncertainty           -0.036     7.401    
    SLICE_X3Y40          FDRE (Setup_fdre_C_D)        0.062     7.463    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][7]
  -------------------------------------------------------------------
                         required time                          7.463    
                         arrival time                          -4.654    
  -------------------------------------------------------------------
                         slack                                  2.810    

Slack (MET) :             2.884ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][6]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        5.505ns  (logic 2.564ns (46.572%)  route 2.941ns (53.428%))
  Logic Levels:           7  (CARRY4=4 LUT4=1 LUT6=2)
  Clock Path Skew:        0.030ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.459ns = ( 6.874 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.926ns
    Clock Pessimism Removal (CPR):    0.563ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.709    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.567    -0.926    RLINK/SERPORT/UART/AB/I_CLK12
    SLICE_X9Y40          FDRE                                         r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y40          FDRE (Prop_fdre_C_Q)         0.456    -0.470 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/Q
                         net (fo=6, routed)           1.073     0.603    RLINK/SERPORT/UART/RXTX/RX/Q[2]
    SLICE_X4Y41          LUT4 (Prop_lut4_I1_O)        0.124     0.727 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8/O
                         net (fo=1, routed)           0.000     0.727    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8_n_0
    SLICE_X4Y41          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     1.259 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry/CO[3]
                         net (fo=1, routed)           0.000     1.259    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_n_0
    SLICE_X4Y42          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.250     1.509 f  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry__0/CO[2]
                         net (fo=11, routed)          0.562     2.071    RLINK/SERPORT/UART/RXTX/RX/n[state]1
    SLICE_X2Y43          LUT6 (Prop_lut6_I3_O)        0.313     2.384 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.591     2.976    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11_n_0
    SLICE_X2Y42          LUT6 (Prop_lut6_I1_O)        0.124     3.100 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=23, routed)          0.715     3.815    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_2__0_n_0
    SLICE_X3Y39          CARRY4 (Prop_carry4_DI[0]_CO[3])
                                                      0.526     4.341 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.341    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1_n_0
    SLICE_X3Y40          CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     4.580 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1/O[2]
                         net (fo=1, routed)           0.000     4.580    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1_n_5
    SLICE_X3Y40          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][6]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.162    10.900    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.517     6.874    RLINK/SERPORT/UART/RXTX/RX/I_CLK12
    SLICE_X3Y40          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][6]/C
                         clock pessimism              0.563     7.437    
                         clock uncertainty           -0.036     7.401    
    SLICE_X3Y40          FDRE (Setup_fdre_C_D)        0.062     7.463    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][6]
  -------------------------------------------------------------------
                         required time                          7.463    
                         arrival time                          -4.580    
  -------------------------------------------------------------------
                         slack                                  2.884    

Slack (MET) :             2.890ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][12]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        5.499ns  (logic 2.906ns (52.842%)  route 2.593ns (47.158%))
  Logic Levels:           10  (CARRY4=6 LUT3=2 LUT4=1 LUT6=1)
  Clock Path Skew:        0.030ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.459ns = ( 6.874 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.926ns
    Clock Pessimism Removal (CPR):    0.563ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.709    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.567    -0.926    RLINK/SERPORT/UART/AB/I_CLK12
    SLICE_X9Y40          FDRE                                         r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y40          FDRE (Prop_fdre_C_Q)         0.456    -0.470 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/Q
                         net (fo=6, routed)           1.073     0.603    RLINK/SERPORT/UART/RXTX/RX/Q[2]
    SLICE_X4Y41          LUT4 (Prop_lut4_I1_O)        0.124     0.727 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8/O
                         net (fo=1, routed)           0.000     0.727    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8_n_0
    SLICE_X4Y41          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     1.259 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry/CO[3]
                         net (fo=1, routed)           0.000     1.259    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_n_0
    SLICE_X4Y42          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.250     1.509 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry__0/CO[2]
                         net (fo=11, routed)          0.490     1.999    RLINK/SERPORT/UART/RXTX/RX/n[state]1
    SLICE_X2Y42          LUT3 (Prop_lut3_I2_O)        0.313     2.312 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_9/O
                         net (fo=1, routed)           0.303     2.615    RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_9_n_0
    SLICE_X2Y43          LUT6 (Prop_lut6_I1_O)        0.124     2.739 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_3/O
                         net (fo=15, routed)          0.728     3.467    RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_3_n_0
    SLICE_X5Y40          LUT3 (Prop_lut3_I2_O)        0.124     3.591 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_8/O
                         net (fo=1, routed)           0.000     3.591    RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_8_n_0
    SLICE_X5Y40          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     4.123 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][0]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.123    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][0]_i_2_n_0
    SLICE_X5Y41          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.237 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][4]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.237    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][4]_i_1_n_0
    SLICE_X5Y42          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.351 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][8]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.351    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][8]_i_1_n_0
    SLICE_X5Y43          CARRY4 (Prop_carry4_CI_O[0])
                                                      0.223     4.574 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][12]_i_1/O[0]
                         net (fo=1, routed)           0.000     4.574    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][12]_i_1_n_7
    SLICE_X5Y43          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][12]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.162    10.900    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.517     6.874    RLINK/SERPORT/UART/RXTX/RX/I_CLK12
    SLICE_X5Y43          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][12]/C
                         clock pessimism              0.563     7.437    
                         clock uncertainty           -0.036     7.401    
    SLICE_X5Y43          FDRE (Setup_fdre_C_D)        0.062     7.463    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][12]
  -------------------------------------------------------------------
                         required time                          7.463    
                         arrival time                          -4.574    
  -------------------------------------------------------------------
                         slack                                  2.890    

Slack (MET) :             2.892ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][9]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        5.496ns  (logic 2.903ns (52.816%)  route 2.593ns (47.184%))
  Logic Levels:           9  (CARRY4=5 LUT3=2 LUT4=1 LUT6=1)
  Clock Path Skew:        0.029ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.460ns = ( 6.873 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.926ns
    Clock Pessimism Removal (CPR):    0.563ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.709    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.567    -0.926    RLINK/SERPORT/UART/AB/I_CLK12
    SLICE_X9Y40          FDRE                                         r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y40          FDRE (Prop_fdre_C_Q)         0.456    -0.470 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/Q
                         net (fo=6, routed)           1.073     0.603    RLINK/SERPORT/UART/RXTX/RX/Q[2]
    SLICE_X4Y41          LUT4 (Prop_lut4_I1_O)        0.124     0.727 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8/O
                         net (fo=1, routed)           0.000     0.727    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8_n_0
    SLICE_X4Y41          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     1.259 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry/CO[3]
                         net (fo=1, routed)           0.000     1.259    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_n_0
    SLICE_X4Y42          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.250     1.509 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry__0/CO[2]
                         net (fo=11, routed)          0.490     1.999    RLINK/SERPORT/UART/RXTX/RX/n[state]1
    SLICE_X2Y42          LUT3 (Prop_lut3_I2_O)        0.313     2.312 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_9/O
                         net (fo=1, routed)           0.303     2.615    RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_9_n_0
    SLICE_X2Y43          LUT6 (Prop_lut6_I1_O)        0.124     2.739 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_3/O
                         net (fo=15, routed)          0.728     3.467    RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_3_n_0
    SLICE_X5Y40          LUT3 (Prop_lut3_I2_O)        0.124     3.591 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_8/O
                         net (fo=1, routed)           0.000     3.591    RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_8_n_0
    SLICE_X5Y40          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     4.123 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][0]_i_2/CO[3]
                         net (fo=1, routed)           0.000     4.123    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][0]_i_2_n_0
    SLICE_X5Y41          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     4.237 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][4]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.237    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][4]_i_1_n_0
    SLICE_X5Y42          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334     4.571 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][8]_i_1/O[1]
                         net (fo=1, routed)           0.000     4.571    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][8]_i_1_n_6
    SLICE_X5Y42          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][9]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.162    10.900    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.516     6.873    RLINK/SERPORT/UART/RXTX/RX/I_CLK12
    SLICE_X5Y42          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][9]/C
                         clock pessimism              0.563     7.436    
                         clock uncertainty           -0.036     7.400    
    SLICE_X5Y42          FDRE (Setup_fdre_C_D)        0.062     7.462    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[dcnt][9]
  -------------------------------------------------------------------
                         required time                          7.462    
                         arrival time                          -4.571    
  -------------------------------------------------------------------
                         slack                                  2.892    

Slack (MET) :             2.900ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        5.489ns  (logic 2.548ns (46.416%)  route 2.941ns (53.584%))
  Logic Levels:           7  (CARRY4=4 LUT4=1 LUT6=2)
  Clock Path Skew:        0.030ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.459ns = ( 6.874 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.926ns
    Clock Pessimism Removal (CPR):    0.563ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.009ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.233     2.709    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.965    -4.256 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.589    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096    -2.493 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.567    -0.926    RLINK/SERPORT/UART/AB/I_CLK12
    SLICE_X9Y40          FDRE                                         r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y40          FDRE (Prop_fdre_C_Q)         0.456    -0.470 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/Q
                         net (fo=6, routed)           1.073     0.603    RLINK/SERPORT/UART/RXTX/RX/Q[2]
    SLICE_X4Y41          LUT4 (Prop_lut4_I1_O)        0.124     0.727 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8/O
                         net (fo=1, routed)           0.000     0.727    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_i_8_n_0
    SLICE_X4Y41          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     1.259 r  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry/CO[3]
                         net (fo=1, routed)           0.000     1.259    RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry_n_0
    SLICE_X4Y42          CARRY4 (Prop_carry4_CI_CO[2])
                                                      0.250     1.509 f  RLINK/SERPORT/UART/RXTX/RX/n[state]1_carry__0/CO[2]
                         net (fo=11, routed)          0.562     2.071    RLINK/SERPORT/UART/RXTX/RX/n[state]1
    SLICE_X2Y43          LUT6 (Prop_lut6_I3_O)        0.313     2.384 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.591     2.976    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11_n_0
    SLICE_X2Y42          LUT6 (Prop_lut6_I1_O)        0.124     3.100 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=23, routed)          0.715     3.815    RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_2__0_n_0
    SLICE_X3Y39          CARRY4 (Prop_carry4_DI[0]_CO[3])
                                                      0.526     4.341 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     4.341    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1_n_0
    SLICE_X3Y40          CARRY4 (Prop_carry4_CI_O[0])
                                                      0.223     4.564 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1/O[0]
                         net (fo=1, routed)           0.000     4.564    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1_n_7
    SLICE_X3Y40          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.162    10.900    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.517     6.874    RLINK/SERPORT/UART/RXTX/RX/I_CLK12
    SLICE_X3Y40          FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]/C
                         clock pessimism              0.563     7.437    
                         clock uncertainty           -0.036     7.401    
    SLICE_X3Y40          FDRE (Setup_fdre_C_D)        0.062     7.463    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]
  -------------------------------------------------------------------
                         required time                          7.463    
                         arrival time                          -4.564    
  -------------------------------------------------------------------
                         slack                                  2.900    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.080ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][2]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMB/I
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.242ns  (logic 0.141ns (58.263%)  route 0.101ns (41.737%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.835ns
    Source Clock Delay      (SCD):    -0.598ns
    Clock Pessimism Removal (CPR):    -0.253ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.684    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.566    -0.598    RLINK/SERPORT/XONRX/I_CLK12
    SLICE_X13Y45         FDRE                                         r  RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y45         FDRE (Prop_fdre_C_Q)         0.141    -0.457 r  RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][2]/Q
                         net (fo=1, routed)           0.101    -0.356    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/DIB0
    SLICE_X14Y45         RAMD32                                       r  RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMB/I
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.912    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.836    -0.835    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X14Y45         RAMD32                                       r  RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
                         clock pessimism              0.253    -0.582    
    SLICE_X14Y45         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.146    -0.436    RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_0_5/RAMB
  -------------------------------------------------------------------
                         required time                          0.436    
                         arrival time                          -0.356    
  -------------------------------------------------------------------
                         slack                                  0.080    

Slack (MET) :             0.119ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.837ns
    Source Clock Delay      (SCD):    -0.600ns
    Clock Pessimism Removal (CPR):    -0.237ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.684    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.564    -0.600    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X11Y39         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X11Y39         FDRE (Prop_fdre_C_Q)         0.141    -0.459 r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[4]/Q
                         net (fo=1, routed)           0.056    -0.403    RLINK/SERPORT/TXFIFO/RR_WADDR_S0[4]
    SLICE_X11Y39         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.912    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.834    -0.837    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X11Y39         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[4]/C
                         clock pessimism              0.237    -0.600    
    SLICE_X11Y39         FDRE (Hold_fdre_C_D)         0.078    -0.522    RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[4]
  -------------------------------------------------------------------
                         required time                          0.522    
                         arrival time                          -0.403    
  -------------------------------------------------------------------
                         slack                                  0.119    

Slack (MET) :             0.121ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.837ns
    Source Clock Delay      (SCD):    -0.600ns
    Clock Pessimism Removal (CPR):    -0.237ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.684    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.564    -0.600    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X11Y39         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X11Y39         FDRE (Prop_fdre_C_Q)         0.141    -0.459 r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[3]/Q
                         net (fo=1, routed)           0.056    -0.403    RLINK/SERPORT/TXFIFO/RR_WADDR_S0[3]
    SLICE_X11Y39         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.912    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.834    -0.837    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X11Y39         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[3]/C
                         clock pessimism              0.237    -0.600    
    SLICE_X11Y39         FDRE (Hold_fdre_C_D)         0.076    -0.524    RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[3]
  -------------------------------------------------------------------
                         required time                          0.524    
                         arrival time                          -0.403    
  -------------------------------------------------------------------
                         slack                                  0.121    

Slack (MET) :             0.121ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.834ns
    Source Clock Delay      (SCD):    -0.597ns
    Clock Pessimism Removal (CPR):    -0.237ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.684    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.567    -0.597    RLINK/SERPORT/RXFIFO/CLKW
    SLICE_X13Y48         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y48         FDRE (Prop_fdre_C_Q)         0.141    -0.456 r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[4]/Q
                         net (fo=1, routed)           0.056    -0.400    RLINK/SERPORT/RXFIFO/RW_RADDR_S0[4]
    SLICE_X13Y48         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.912    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.837    -0.834    RLINK/SERPORT/RXFIFO/CLKW
    SLICE_X13Y48         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[4]/C
                         clock pessimism              0.237    -0.597    
    SLICE_X13Y48         FDRE (Hold_fdre_C_D)         0.076    -0.521    RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[4]
  -------------------------------------------------------------------
                         required time                          0.521    
                         arrival time                          -0.400    
  -------------------------------------------------------------------
                         slack                                  0.121    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/CDC_ENAXON/R_DO_S0_reg/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_ENAXON/R_DO_S1_reg/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.835ns
    Source Clock Delay      (SCD):    -0.598ns
    Clock Pessimism Removal (CPR):    -0.237ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.684    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.566    -0.598    RLINK/SERPORT/CDC_ENAXON/CLKO
    SLICE_X11Y44         FDRE                                         r  RLINK/SERPORT/CDC_ENAXON/R_DO_S0_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X11Y44         FDRE (Prop_fdre_C_Q)         0.141    -0.457 r  RLINK/SERPORT/CDC_ENAXON/R_DO_S0_reg/Q
                         net (fo=1, routed)           0.056    -0.401    RLINK/SERPORT/CDC_ENAXON/R_DO_S0
    SLICE_X11Y44         FDRE                                         r  RLINK/SERPORT/CDC_ENAXON/R_DO_S1_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.912    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.836    -0.835    RLINK/SERPORT/CDC_ENAXON/CLKO
    SLICE_X11Y44         FDRE                                         r  RLINK/SERPORT/CDC_ENAXON/R_DO_S1_reg/C
                         clock pessimism              0.237    -0.598    
    SLICE_X11Y44         FDRE (Hold_fdre_C_D)         0.075    -0.523    RLINK/SERPORT/CDC_ENAXON/R_DO_S1_reg
  -------------------------------------------------------------------
                         required time                          0.523    
                         arrival time                          -0.401    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.837ns
    Source Clock Delay      (SCD):    -0.600ns
    Clock Pessimism Removal (CPR):    -0.237ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.684    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.564    -0.600    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X11Y38         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X11Y38         FDRE (Prop_fdre_C_Q)         0.141    -0.459 r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[0]/Q
                         net (fo=1, routed)           0.056    -0.403    RLINK/SERPORT/TXFIFO/RR_WADDR_S0[0]
    SLICE_X11Y38         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.912    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.834    -0.837    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X11Y38         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[0]/C
                         clock pessimism              0.237    -0.600    
    SLICE_X11Y38         FDRE (Hold_fdre_C_D)         0.075    -0.525    RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[0]
  -------------------------------------------------------------------
                         required time                          0.525    
                         arrival time                          -0.403    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.837ns
    Source Clock Delay      (SCD):    -0.600ns
    Clock Pessimism Removal (CPR):    -0.237ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.684    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.564    -0.600    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X11Y39         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X11Y39         FDRE (Prop_fdre_C_Q)         0.141    -0.459 r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[1]/Q
                         net (fo=1, routed)           0.056    -0.403    RLINK/SERPORT/TXFIFO/RR_WADDR_S0[1]
    SLICE_X11Y39         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.912    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.834    -0.837    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X11Y39         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[1]/C
                         clock pessimism              0.237    -0.600    
    SLICE_X11Y39         FDRE (Hold_fdre_C_D)         0.075    -0.525    RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[1]
  -------------------------------------------------------------------
                         required time                          0.525    
                         arrival time                          -0.403    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.834ns
    Source Clock Delay      (SCD):    -0.597ns
    Clock Pessimism Removal (CPR):    -0.237ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.684    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.567    -0.597    RLINK/SERPORT/RXFIFO/CLKW
    SLICE_X11Y47         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X11Y47         FDRE (Prop_fdre_C_Q)         0.141    -0.456 r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[0]/Q
                         net (fo=1, routed)           0.056    -0.400    RLINK/SERPORT/RXFIFO/RW_RADDR_S0[0]
    SLICE_X11Y47         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.912    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.837    -0.834    RLINK/SERPORT/RXFIFO/CLKW
    SLICE_X11Y47         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[0]/C
                         clock pessimism              0.237    -0.597    
    SLICE_X11Y47         FDRE (Hold_fdre_C_D)         0.075    -0.522    RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[0]
  -------------------------------------------------------------------
                         required time                          0.522    
                         arrival time                          -0.400    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.834ns
    Source Clock Delay      (SCD):    -0.597ns
    Clock Pessimism Removal (CPR):    -0.237ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.684    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.567    -0.597    RLINK/SERPORT/RXFIFO/CLKW
    SLICE_X13Y48         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y48         FDRE (Prop_fdre_C_Q)         0.141    -0.456 r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[1]/Q
                         net (fo=1, routed)           0.056    -0.400    RLINK/SERPORT/RXFIFO/RW_RADDR_S0[1]
    SLICE_X13Y48         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.912    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.837    -0.834    RLINK/SERPORT/RXFIFO/CLKW
    SLICE_X13Y48         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[1]/C
                         clock pessimism              0.237    -0.597    
    SLICE_X13Y48         FDRE (Hold_fdre_C_D)         0.075    -0.522    RLINK/SERPORT/RXFIFO/RW_RADDR_S1_reg[1]
  -------------------------------------------------------------------
                         required time                          0.522    
                         arrival time                          -0.400    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.126ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.837ns
    Source Clock Delay      (SCD):    -0.600ns
    Clock Pessimism Removal (CPR):    -0.237ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.440     0.684    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.362    -1.678 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.189    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026    -1.163 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.564    -0.600    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X11Y39         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X11Y39         FDRE (Prop_fdre_C_Q)         0.141    -0.459 r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[2]/Q
                         net (fo=1, routed)           0.056    -0.403    RLINK/SERPORT/TXFIFO/RR_WADDR_S0[2]
    SLICE_X11Y39         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.480     0.912    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.145    -2.233 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.700    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029    -1.671 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         0.834    -0.837    RLINK/SERPORT/TXFIFO/CLKR
    SLICE_X11Y39         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[2]/C
                         clock pessimism              0.237    -0.600    
    SLICE_X11Y39         FDRE (Hold_fdre_C_D)         0.071    -0.529    RLINK/SERPORT/TXFIFO/RR_WADDR_S1_reg[2]
  -------------------------------------------------------------------
                         required time                          0.529    
                         arrival time                          -0.403    
  -------------------------------------------------------------------
                         slack                                  0.126    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         CLKOUT0
Waveform(ns):       { 0.000 4.167 }
Period(ns):         8.333
Sources:            { GEN_CLKSER/USEMMCM.MMCM/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     BUFG/I              n/a            2.155         8.333       6.178      BUFGCTRL_X0Y0    GEN_CLKSER/USEMMCM.BUFG_CLKOUT/I
Min Period        n/a     FDRE/C              n/a            1.474         8.333       6.859      ILOGIC_X0Y36     IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
Min Period        n/a     FDRE/C              n/a            1.474         8.333       6.859      OLOGIC_X0Y35     IOB_RS232/IOB_TXD/IOB/R_DO_reg[0]/C
Min Period        n/a     MMCME2_ADV/CLKOUT0  n/a            1.249         8.333       7.084      MMCME2_ADV_X0Y0  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
Min Period        n/a     FDSE/C              n/a            1.000         8.333       7.333      SLICE_X3Y43      RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS_reg[state][0]/C
Min Period        n/a     FDRE/C              n/a            1.000         8.333       7.333      SLICE_X4Y44      RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS_reg[state][1]/C
Min Period        n/a     FDRE/C              n/a            1.000         8.333       7.333      SLICE_X4Y44      RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS_reg[state][2]/C
Min Period        n/a     FDRE/C              n/a            1.000         8.333       7.333      SLICE_X2Y45      RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS_reg[state][3]/C
Min Period        n/a     FDRE/C              n/a            1.000         8.333       7.333      SLICE_X2Y45      RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS_reg[state][4]/C
Min Period        n/a     FDRE/C              n/a            1.000         8.333       7.333      SLICE_X3Y44      RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS_reg[state][5]/C
Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       8.333       205.027    MMCME2_ADV_X0Y0  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMB/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMB/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMB_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMC/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMC_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMC_D1/CLK
Low Pulse Width   Slow    RAMS32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMD/CLK
Low Pulse Width   Fast    RAMS32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMD/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMB/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMB_D1/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMC/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMC_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMC_D1/CLK
High Pulse Width  Slow    RAMS32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMD/CLK
High Pulse Width  Fast    RAMS32/CLK          n/a            1.250         4.167       2.917      SLICE_X12Y45     RLINK/SERPORT/RXFIFO/RAM/RAM_reg_0_31_6_7/RAMD/CLK



---------------------------------------------------------------------------------------------------
From Clock:  CLKOUT0_1
  To Clock:  CLKOUT0_1

Setup :            0  Failing Endpoints,  Worst Slack        2.577ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.082ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        5.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             2.577ns  (required time - arrival time)
  Source:                 SMRB/SMRB/R_REGS_reg[rbsel]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[bcnt][0]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.499ns  (CLKOUT0_1 rise@12.499ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        9.562ns  (logic 1.386ns (14.495%)  route 8.176ns (85.505%))
  Logic Levels:           7  (LUT2=1 LUT3=1 LUT5=1 LUT6=4)
  Clock Path Skew:        -0.120ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.424ns = ( 11.076 - 12.499 ) 
    Source Clock Delay      (SCD):    -0.809ns
    Clock Pessimism Removal (CPR):    0.494ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.010ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.336     2.812    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.950    -4.138 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.472    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.376 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.566    -0.809    SMRB/SMRB/CLKFX
    SLICE_X14Y36         FDRE                                         r  SMRB/SMRB/R_REGS_reg[rbsel]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y36         FDRE (Prop_fdre_C_Q)         0.518    -0.291 f  SMRB/SMRB/R_REGS_reg[rbsel]/Q
                         net (fo=24, routed)          2.279     1.987    SMRB/SMRB/R_BREGS_reg[rbdout][5]
    SLICE_X29Y71         LUT6 (Prop_lut6_I3_O)        0.124     2.111 f  SMRB/SMRB/R_BREGS[rbtout]_i_13/O
                         net (fo=1, routed)           0.492     2.603    SMRB/SMRB/R_BREGS[rbtout]_i_13_n_0
    SLICE_X28Y70         LUT6 (Prop_lut6_I5_O)        0.124     2.727 f  SMRB/SMRB/R_BREGS[rbtout]_i_9/O
                         net (fo=1, routed)           1.891     4.618    TST/RB_SRES_SYSMON[busy]
    SLICE_X5Y36          LUT6 (Prop_lut6_I5_O)        0.124     4.742 r  TST/R_BREGS[rbtout]_i_3/O
                         net (fo=6, routed)           1.033     5.775    RLINK/CORE/RL/FSM_onehot_R_REGS_reg[state][1]
    SLICE_X29Y34         LUT2 (Prop_lut2_I1_O)        0.124     5.899 f  RLINK/CORE/RL/R_BREGS[rbnak]_i_2/O
                         net (fo=5, routed)           0.344     6.243    RLINK/CORE/RL/R_BREGS[rbnak]_i_2_n_0
    SLICE_X30Y34         LUT5 (Prop_lut5_I1_O)        0.124     6.367 r  RLINK/CORE/RL/R_LREGS[din][15]_i_3/O
                         net (fo=4, routed)           0.806     7.172    RLINK/CORE/RL/R_LREGS[din][15]_i_3_n_0
    SLICE_X41Y36         LUT3 (Prop_lut3_I2_O)        0.124     7.296 r  RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_9/O
                         net (fo=2, routed)           0.697     7.993    RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][26]
    SLICE_X41Y33         LUT6 (Prop_lut6_I4_O)        0.124     8.117 r  RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS[bcnt][0]_i_1/O
                         net (fo=12, routed)          0.635     8.752    RLINK/CORE/RL/DOFIFO_n_1
    SLICE_X41Y29         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                     12.499    12.499 r  
    L17                                               0.000    12.499 r  I_CLK12 (IN)
                         net (fo=0)                   0.000    12.499    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406    13.905 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.261    15.166    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.208     7.958 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     9.545    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.636 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.439    11.076    RLINK/CORE/RL/CLKFX
    SLICE_X41Y29         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][0]/C
                         clock pessimism              0.494    11.570    
                         clock uncertainty           -0.036    11.534    
    SLICE_X41Y29         FDRE (Setup_fdre_C_CE)      -0.205    11.329    RLINK/CORE/RL/R_LREGS_reg[bcnt][0]
  -------------------------------------------------------------------
                         required time                         11.329    
                         arrival time                          -8.752    
  -------------------------------------------------------------------
                         slack                                  2.577    

Slack (MET) :             2.577ns  (required time - arrival time)
  Source:                 SMRB/SMRB/R_REGS_reg[rbsel]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[bcnt][1]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.499ns  (CLKOUT0_1 rise@12.499ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        9.562ns  (logic 1.386ns (14.495%)  route 8.176ns (85.505%))
  Logic Levels:           7  (LUT2=1 LUT3=1 LUT5=1 LUT6=4)
  Clock Path Skew:        -0.120ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.424ns = ( 11.076 - 12.499 ) 
    Source Clock Delay      (SCD):    -0.809ns
    Clock Pessimism Removal (CPR):    0.494ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.010ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.336     2.812    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.950    -4.138 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.472    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.376 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.566    -0.809    SMRB/SMRB/CLKFX
    SLICE_X14Y36         FDRE                                         r  SMRB/SMRB/R_REGS_reg[rbsel]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y36         FDRE (Prop_fdre_C_Q)         0.518    -0.291 f  SMRB/SMRB/R_REGS_reg[rbsel]/Q
                         net (fo=24, routed)          2.279     1.987    SMRB/SMRB/R_BREGS_reg[rbdout][5]
    SLICE_X29Y71         LUT6 (Prop_lut6_I3_O)        0.124     2.111 f  SMRB/SMRB/R_BREGS[rbtout]_i_13/O
                         net (fo=1, routed)           0.492     2.603    SMRB/SMRB/R_BREGS[rbtout]_i_13_n_0
    SLICE_X28Y70         LUT6 (Prop_lut6_I5_O)        0.124     2.727 f  SMRB/SMRB/R_BREGS[rbtout]_i_9/O
                         net (fo=1, routed)           1.891     4.618    TST/RB_SRES_SYSMON[busy]
    SLICE_X5Y36          LUT6 (Prop_lut6_I5_O)        0.124     4.742 r  TST/R_BREGS[rbtout]_i_3/O
                         net (fo=6, routed)           1.033     5.775    RLINK/CORE/RL/FSM_onehot_R_REGS_reg[state][1]
    SLICE_X29Y34         LUT2 (Prop_lut2_I1_O)        0.124     5.899 f  RLINK/CORE/RL/R_BREGS[rbnak]_i_2/O
                         net (fo=5, routed)           0.344     6.243    RLINK/CORE/RL/R_BREGS[rbnak]_i_2_n_0
    SLICE_X30Y34         LUT5 (Prop_lut5_I1_O)        0.124     6.367 r  RLINK/CORE/RL/R_LREGS[din][15]_i_3/O
                         net (fo=4, routed)           0.806     7.172    RLINK/CORE/RL/R_LREGS[din][15]_i_3_n_0
    SLICE_X41Y36         LUT3 (Prop_lut3_I2_O)        0.124     7.296 r  RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_9/O
                         net (fo=2, routed)           0.697     7.993    RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][26]
    SLICE_X41Y33         LUT6 (Prop_lut6_I4_O)        0.124     8.117 r  RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS[bcnt][0]_i_1/O
                         net (fo=12, routed)          0.635     8.752    RLINK/CORE/RL/DOFIFO_n_1
    SLICE_X41Y29         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                     12.499    12.499 r  
    L17                                               0.000    12.499 r  I_CLK12 (IN)
                         net (fo=0)                   0.000    12.499    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406    13.905 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.261    15.166    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.208     7.958 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     9.545    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.636 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.439    11.076    RLINK/CORE/RL/CLKFX
    SLICE_X41Y29         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][1]/C
                         clock pessimism              0.494    11.570    
                         clock uncertainty           -0.036    11.534    
    SLICE_X41Y29         FDRE (Setup_fdre_C_CE)      -0.205    11.329    RLINK/CORE/RL/R_LREGS_reg[bcnt][1]
  -------------------------------------------------------------------
                         required time                         11.329    
                         arrival time                          -8.752    
  -------------------------------------------------------------------
                         slack                                  2.577    

Slack (MET) :             2.577ns  (required time - arrival time)
  Source:                 SMRB/SMRB/R_REGS_reg[rbsel]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[bcnt][2]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.499ns  (CLKOUT0_1 rise@12.499ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        9.562ns  (logic 1.386ns (14.495%)  route 8.176ns (85.505%))
  Logic Levels:           7  (LUT2=1 LUT3=1 LUT5=1 LUT6=4)
  Clock Path Skew:        -0.120ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.424ns = ( 11.076 - 12.499 ) 
    Source Clock Delay      (SCD):    -0.809ns
    Clock Pessimism Removal (CPR):    0.494ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.010ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.336     2.812    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.950    -4.138 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.472    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.376 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.566    -0.809    SMRB/SMRB/CLKFX
    SLICE_X14Y36         FDRE                                         r  SMRB/SMRB/R_REGS_reg[rbsel]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y36         FDRE (Prop_fdre_C_Q)         0.518    -0.291 f  SMRB/SMRB/R_REGS_reg[rbsel]/Q
                         net (fo=24, routed)          2.279     1.987    SMRB/SMRB/R_BREGS_reg[rbdout][5]
    SLICE_X29Y71         LUT6 (Prop_lut6_I3_O)        0.124     2.111 f  SMRB/SMRB/R_BREGS[rbtout]_i_13/O
                         net (fo=1, routed)           0.492     2.603    SMRB/SMRB/R_BREGS[rbtout]_i_13_n_0
    SLICE_X28Y70         LUT6 (Prop_lut6_I5_O)        0.124     2.727 f  SMRB/SMRB/R_BREGS[rbtout]_i_9/O
                         net (fo=1, routed)           1.891     4.618    TST/RB_SRES_SYSMON[busy]
    SLICE_X5Y36          LUT6 (Prop_lut6_I5_O)        0.124     4.742 r  TST/R_BREGS[rbtout]_i_3/O
                         net (fo=6, routed)           1.033     5.775    RLINK/CORE/RL/FSM_onehot_R_REGS_reg[state][1]
    SLICE_X29Y34         LUT2 (Prop_lut2_I1_O)        0.124     5.899 f  RLINK/CORE/RL/R_BREGS[rbnak]_i_2/O
                         net (fo=5, routed)           0.344     6.243    RLINK/CORE/RL/R_BREGS[rbnak]_i_2_n_0
    SLICE_X30Y34         LUT5 (Prop_lut5_I1_O)        0.124     6.367 r  RLINK/CORE/RL/R_LREGS[din][15]_i_3/O
                         net (fo=4, routed)           0.806     7.172    RLINK/CORE/RL/R_LREGS[din][15]_i_3_n_0
    SLICE_X41Y36         LUT3 (Prop_lut3_I2_O)        0.124     7.296 r  RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_9/O
                         net (fo=2, routed)           0.697     7.993    RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][26]
    SLICE_X41Y33         LUT6 (Prop_lut6_I4_O)        0.124     8.117 r  RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS[bcnt][0]_i_1/O
                         net (fo=12, routed)          0.635     8.752    RLINK/CORE/RL/DOFIFO_n_1
    SLICE_X41Y29         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                     12.499    12.499 r  
    L17                                               0.000    12.499 r  I_CLK12 (IN)
                         net (fo=0)                   0.000    12.499    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406    13.905 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.261    15.166    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.208     7.958 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     9.545    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.636 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.439    11.076    RLINK/CORE/RL/CLKFX
    SLICE_X41Y29         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][2]/C
                         clock pessimism              0.494    11.570    
                         clock uncertainty           -0.036    11.534    
    SLICE_X41Y29         FDRE (Setup_fdre_C_CE)      -0.205    11.329    RLINK/CORE/RL/R_LREGS_reg[bcnt][2]
  -------------------------------------------------------------------
                         required time                         11.329    
                         arrival time                          -8.752    
  -------------------------------------------------------------------
                         slack                                  2.577    

Slack (MET) :             2.577ns  (required time - arrival time)
  Source:                 SMRB/SMRB/R_REGS_reg[rbsel]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[bcnt][3]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.499ns  (CLKOUT0_1 rise@12.499ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        9.562ns  (logic 1.386ns (14.495%)  route 8.176ns (85.505%))
  Logic Levels:           7  (LUT2=1 LUT3=1 LUT5=1 LUT6=4)
  Clock Path Skew:        -0.120ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.424ns = ( 11.076 - 12.499 ) 
    Source Clock Delay      (SCD):    -0.809ns
    Clock Pessimism Removal (CPR):    0.494ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.010ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.336     2.812    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.950    -4.138 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.472    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.376 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.566    -0.809    SMRB/SMRB/CLKFX
    SLICE_X14Y36         FDRE                                         r  SMRB/SMRB/R_REGS_reg[rbsel]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y36         FDRE (Prop_fdre_C_Q)         0.518    -0.291 f  SMRB/SMRB/R_REGS_reg[rbsel]/Q
                         net (fo=24, routed)          2.279     1.987    SMRB/SMRB/R_BREGS_reg[rbdout][5]
    SLICE_X29Y71         LUT6 (Prop_lut6_I3_O)        0.124     2.111 f  SMRB/SMRB/R_BREGS[rbtout]_i_13/O
                         net (fo=1, routed)           0.492     2.603    SMRB/SMRB/R_BREGS[rbtout]_i_13_n_0
    SLICE_X28Y70         LUT6 (Prop_lut6_I5_O)        0.124     2.727 f  SMRB/SMRB/R_BREGS[rbtout]_i_9/O
                         net (fo=1, routed)           1.891     4.618    TST/RB_SRES_SYSMON[busy]
    SLICE_X5Y36          LUT6 (Prop_lut6_I5_O)        0.124     4.742 r  TST/R_BREGS[rbtout]_i_3/O
                         net (fo=6, routed)           1.033     5.775    RLINK/CORE/RL/FSM_onehot_R_REGS_reg[state][1]
    SLICE_X29Y34         LUT2 (Prop_lut2_I1_O)        0.124     5.899 f  RLINK/CORE/RL/R_BREGS[rbnak]_i_2/O
                         net (fo=5, routed)           0.344     6.243    RLINK/CORE/RL/R_BREGS[rbnak]_i_2_n_0
    SLICE_X30Y34         LUT5 (Prop_lut5_I1_O)        0.124     6.367 r  RLINK/CORE/RL/R_LREGS[din][15]_i_3/O
                         net (fo=4, routed)           0.806     7.172    RLINK/CORE/RL/R_LREGS[din][15]_i_3_n_0
    SLICE_X41Y36         LUT3 (Prop_lut3_I2_O)        0.124     7.296 r  RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_9/O
                         net (fo=2, routed)           0.697     7.993    RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][26]
    SLICE_X41Y33         LUT6 (Prop_lut6_I4_O)        0.124     8.117 r  RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS[bcnt][0]_i_1/O
                         net (fo=12, routed)          0.635     8.752    RLINK/CORE/RL/DOFIFO_n_1
    SLICE_X41Y29         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][3]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                     12.499    12.499 r  
    L17                                               0.000    12.499 r  I_CLK12 (IN)
                         net (fo=0)                   0.000    12.499    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406    13.905 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.261    15.166    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.208     7.958 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     9.545    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.636 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.439    11.076    RLINK/CORE/RL/CLKFX
    SLICE_X41Y29         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][3]/C
                         clock pessimism              0.494    11.570    
                         clock uncertainty           -0.036    11.534    
    SLICE_X41Y29         FDRE (Setup_fdre_C_CE)      -0.205    11.329    RLINK/CORE/RL/R_LREGS_reg[bcnt][3]
  -------------------------------------------------------------------
                         required time                         11.329    
                         arrival time                          -8.752    
  -------------------------------------------------------------------
                         slack                                  2.577    

Slack (MET) :             2.717ns  (required time - arrival time)
  Source:                 SMRB/SMRB/R_REGS_reg[rbsel]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[bcnt][4]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.499ns  (CLKOUT0_1 rise@12.499ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        9.422ns  (logic 1.386ns (14.710%)  route 8.036ns (85.290%))
  Logic Levels:           7  (LUT2=1 LUT3=1 LUT5=1 LUT6=4)
  Clock Path Skew:        -0.120ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.424ns = ( 11.076 - 12.499 ) 
    Source Clock Delay      (SCD):    -0.809ns
    Clock Pessimism Removal (CPR):    0.494ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.010ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.336     2.812    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.950    -4.138 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.472    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.376 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.566    -0.809    SMRB/SMRB/CLKFX
    SLICE_X14Y36         FDRE                                         r  SMRB/SMRB/R_REGS_reg[rbsel]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y36         FDRE (Prop_fdre_C_Q)         0.518    -0.291 f  SMRB/SMRB/R_REGS_reg[rbsel]/Q
                         net (fo=24, routed)          2.279     1.987    SMRB/SMRB/R_BREGS_reg[rbdout][5]
    SLICE_X29Y71         LUT6 (Prop_lut6_I3_O)        0.124     2.111 f  SMRB/SMRB/R_BREGS[rbtout]_i_13/O
                         net (fo=1, routed)           0.492     2.603    SMRB/SMRB/R_BREGS[rbtout]_i_13_n_0
    SLICE_X28Y70         LUT6 (Prop_lut6_I5_O)        0.124     2.727 f  SMRB/SMRB/R_BREGS[rbtout]_i_9/O
                         net (fo=1, routed)           1.891     4.618    TST/RB_SRES_SYSMON[busy]
    SLICE_X5Y36          LUT6 (Prop_lut6_I5_O)        0.124     4.742 r  TST/R_BREGS[rbtout]_i_3/O
                         net (fo=6, routed)           1.033     5.775    RLINK/CORE/RL/FSM_onehot_R_REGS_reg[state][1]
    SLICE_X29Y34         LUT2 (Prop_lut2_I1_O)        0.124     5.899 f  RLINK/CORE/RL/R_BREGS[rbnak]_i_2/O
                         net (fo=5, routed)           0.344     6.243    RLINK/CORE/RL/R_BREGS[rbnak]_i_2_n_0
    SLICE_X30Y34         LUT5 (Prop_lut5_I1_O)        0.124     6.367 r  RLINK/CORE/RL/R_LREGS[din][15]_i_3/O
                         net (fo=4, routed)           0.806     7.172    RLINK/CORE/RL/R_LREGS[din][15]_i_3_n_0
    SLICE_X41Y36         LUT3 (Prop_lut3_I2_O)        0.124     7.296 r  RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_9/O
                         net (fo=2, routed)           0.697     7.993    RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][26]
    SLICE_X41Y33         LUT6 (Prop_lut6_I4_O)        0.124     8.117 r  RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS[bcnt][0]_i_1/O
                         net (fo=12, routed)          0.495     8.612    RLINK/CORE/RL/DOFIFO_n_1
    SLICE_X41Y30         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][4]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                     12.499    12.499 r  
    L17                                               0.000    12.499 r  I_CLK12 (IN)
                         net (fo=0)                   0.000    12.499    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406    13.905 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.261    15.166    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.208     7.958 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     9.545    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.636 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.439    11.076    RLINK/CORE/RL/CLKFX
    SLICE_X41Y30         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][4]/C
                         clock pessimism              0.494    11.570    
                         clock uncertainty           -0.036    11.534    
    SLICE_X41Y30         FDRE (Setup_fdre_C_CE)      -0.205    11.329    RLINK/CORE/RL/R_LREGS_reg[bcnt][4]
  -------------------------------------------------------------------
                         required time                         11.329    
                         arrival time                          -8.612    
  -------------------------------------------------------------------
                         slack                                  2.717    

Slack (MET) :             2.717ns  (required time - arrival time)
  Source:                 SMRB/SMRB/R_REGS_reg[rbsel]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[bcnt][5]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.499ns  (CLKOUT0_1 rise@12.499ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        9.422ns  (logic 1.386ns (14.710%)  route 8.036ns (85.290%))
  Logic Levels:           7  (LUT2=1 LUT3=1 LUT5=1 LUT6=4)
  Clock Path Skew:        -0.120ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.424ns = ( 11.076 - 12.499 ) 
    Source Clock Delay      (SCD):    -0.809ns
    Clock Pessimism Removal (CPR):    0.494ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.010ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.336     2.812    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.950    -4.138 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.472    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.376 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.566    -0.809    SMRB/SMRB/CLKFX
    SLICE_X14Y36         FDRE                                         r  SMRB/SMRB/R_REGS_reg[rbsel]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y36         FDRE (Prop_fdre_C_Q)         0.518    -0.291 f  SMRB/SMRB/R_REGS_reg[rbsel]/Q
                         net (fo=24, routed)          2.279     1.987    SMRB/SMRB/R_BREGS_reg[rbdout][5]
    SLICE_X29Y71         LUT6 (Prop_lut6_I3_O)        0.124     2.111 f  SMRB/SMRB/R_BREGS[rbtout]_i_13/O
                         net (fo=1, routed)           0.492     2.603    SMRB/SMRB/R_BREGS[rbtout]_i_13_n_0
    SLICE_X28Y70         LUT6 (Prop_lut6_I5_O)        0.124     2.727 f  SMRB/SMRB/R_BREGS[rbtout]_i_9/O
                         net (fo=1, routed)           1.891     4.618    TST/RB_SRES_SYSMON[busy]
    SLICE_X5Y36          LUT6 (Prop_lut6_I5_O)        0.124     4.742 r  TST/R_BREGS[rbtout]_i_3/O
                         net (fo=6, routed)           1.033     5.775    RLINK/CORE/RL/FSM_onehot_R_REGS_reg[state][1]
    SLICE_X29Y34         LUT2 (Prop_lut2_I1_O)        0.124     5.899 f  RLINK/CORE/RL/R_BREGS[rbnak]_i_2/O
                         net (fo=5, routed)           0.344     6.243    RLINK/CORE/RL/R_BREGS[rbnak]_i_2_n_0
    SLICE_X30Y34         LUT5 (Prop_lut5_I1_O)        0.124     6.367 r  RLINK/CORE/RL/R_LREGS[din][15]_i_3/O
                         net (fo=4, routed)           0.806     7.172    RLINK/CORE/RL/R_LREGS[din][15]_i_3_n_0
    SLICE_X41Y36         LUT3 (Prop_lut3_I2_O)        0.124     7.296 r  RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_9/O
                         net (fo=2, routed)           0.697     7.993    RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][26]
    SLICE_X41Y33         LUT6 (Prop_lut6_I4_O)        0.124     8.117 r  RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS[bcnt][0]_i_1/O
                         net (fo=12, routed)          0.495     8.612    RLINK/CORE/RL/DOFIFO_n_1
    SLICE_X41Y30         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][5]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                     12.499    12.499 r  
    L17                                               0.000    12.499 r  I_CLK12 (IN)
                         net (fo=0)                   0.000    12.499    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406    13.905 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.261    15.166    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.208     7.958 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     9.545    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.636 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.439    11.076    RLINK/CORE/RL/CLKFX
    SLICE_X41Y30         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][5]/C
                         clock pessimism              0.494    11.570    
                         clock uncertainty           -0.036    11.534    
    SLICE_X41Y30         FDRE (Setup_fdre_C_CE)      -0.205    11.329    RLINK/CORE/RL/R_LREGS_reg[bcnt][5]
  -------------------------------------------------------------------
                         required time                         11.329    
                         arrival time                          -8.612    
  -------------------------------------------------------------------
                         slack                                  2.717    

Slack (MET) :             2.717ns  (required time - arrival time)
  Source:                 SMRB/SMRB/R_REGS_reg[rbsel]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[bcnt][6]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.499ns  (CLKOUT0_1 rise@12.499ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        9.422ns  (logic 1.386ns (14.710%)  route 8.036ns (85.290%))
  Logic Levels:           7  (LUT2=1 LUT3=1 LUT5=1 LUT6=4)
  Clock Path Skew:        -0.120ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.424ns = ( 11.076 - 12.499 ) 
    Source Clock Delay      (SCD):    -0.809ns
    Clock Pessimism Removal (CPR):    0.494ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.010ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.336     2.812    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.950    -4.138 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.472    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.376 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.566    -0.809    SMRB/SMRB/CLKFX
    SLICE_X14Y36         FDRE                                         r  SMRB/SMRB/R_REGS_reg[rbsel]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y36         FDRE (Prop_fdre_C_Q)         0.518    -0.291 f  SMRB/SMRB/R_REGS_reg[rbsel]/Q
                         net (fo=24, routed)          2.279     1.987    SMRB/SMRB/R_BREGS_reg[rbdout][5]
    SLICE_X29Y71         LUT6 (Prop_lut6_I3_O)        0.124     2.111 f  SMRB/SMRB/R_BREGS[rbtout]_i_13/O
                         net (fo=1, routed)           0.492     2.603    SMRB/SMRB/R_BREGS[rbtout]_i_13_n_0
    SLICE_X28Y70         LUT6 (Prop_lut6_I5_O)        0.124     2.727 f  SMRB/SMRB/R_BREGS[rbtout]_i_9/O
                         net (fo=1, routed)           1.891     4.618    TST/RB_SRES_SYSMON[busy]
    SLICE_X5Y36          LUT6 (Prop_lut6_I5_O)        0.124     4.742 r  TST/R_BREGS[rbtout]_i_3/O
                         net (fo=6, routed)           1.033     5.775    RLINK/CORE/RL/FSM_onehot_R_REGS_reg[state][1]
    SLICE_X29Y34         LUT2 (Prop_lut2_I1_O)        0.124     5.899 f  RLINK/CORE/RL/R_BREGS[rbnak]_i_2/O
                         net (fo=5, routed)           0.344     6.243    RLINK/CORE/RL/R_BREGS[rbnak]_i_2_n_0
    SLICE_X30Y34         LUT5 (Prop_lut5_I1_O)        0.124     6.367 r  RLINK/CORE/RL/R_LREGS[din][15]_i_3/O
                         net (fo=4, routed)           0.806     7.172    RLINK/CORE/RL/R_LREGS[din][15]_i_3_n_0
    SLICE_X41Y36         LUT3 (Prop_lut3_I2_O)        0.124     7.296 r  RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_9/O
                         net (fo=2, routed)           0.697     7.993    RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][26]
    SLICE_X41Y33         LUT6 (Prop_lut6_I4_O)        0.124     8.117 r  RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS[bcnt][0]_i_1/O
                         net (fo=12, routed)          0.495     8.612    RLINK/CORE/RL/DOFIFO_n_1
    SLICE_X41Y30         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                     12.499    12.499 r  
    L17                                               0.000    12.499 r  I_CLK12 (IN)
                         net (fo=0)                   0.000    12.499    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406    13.905 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.261    15.166    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.208     7.958 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     9.545    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.636 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.439    11.076    RLINK/CORE/RL/CLKFX
    SLICE_X41Y30         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][6]/C
                         clock pessimism              0.494    11.570    
                         clock uncertainty           -0.036    11.534    
    SLICE_X41Y30         FDRE (Setup_fdre_C_CE)      -0.205    11.329    RLINK/CORE/RL/R_LREGS_reg[bcnt][6]
  -------------------------------------------------------------------
                         required time                         11.329    
                         arrival time                          -8.612    
  -------------------------------------------------------------------
                         slack                                  2.717    

Slack (MET) :             2.717ns  (required time - arrival time)
  Source:                 SMRB/SMRB/R_REGS_reg[rbsel]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[bcnt][7]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.499ns  (CLKOUT0_1 rise@12.499ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        9.422ns  (logic 1.386ns (14.710%)  route 8.036ns (85.290%))
  Logic Levels:           7  (LUT2=1 LUT3=1 LUT5=1 LUT6=4)
  Clock Path Skew:        -0.120ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.424ns = ( 11.076 - 12.499 ) 
    Source Clock Delay      (SCD):    -0.809ns
    Clock Pessimism Removal (CPR):    0.494ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.010ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.336     2.812    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.950    -4.138 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.472    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.376 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.566    -0.809    SMRB/SMRB/CLKFX
    SLICE_X14Y36         FDRE                                         r  SMRB/SMRB/R_REGS_reg[rbsel]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y36         FDRE (Prop_fdre_C_Q)         0.518    -0.291 f  SMRB/SMRB/R_REGS_reg[rbsel]/Q
                         net (fo=24, routed)          2.279     1.987    SMRB/SMRB/R_BREGS_reg[rbdout][5]
    SLICE_X29Y71         LUT6 (Prop_lut6_I3_O)        0.124     2.111 f  SMRB/SMRB/R_BREGS[rbtout]_i_13/O
                         net (fo=1, routed)           0.492     2.603    SMRB/SMRB/R_BREGS[rbtout]_i_13_n_0
    SLICE_X28Y70         LUT6 (Prop_lut6_I5_O)        0.124     2.727 f  SMRB/SMRB/R_BREGS[rbtout]_i_9/O
                         net (fo=1, routed)           1.891     4.618    TST/RB_SRES_SYSMON[busy]
    SLICE_X5Y36          LUT6 (Prop_lut6_I5_O)        0.124     4.742 r  TST/R_BREGS[rbtout]_i_3/O
                         net (fo=6, routed)           1.033     5.775    RLINK/CORE/RL/FSM_onehot_R_REGS_reg[state][1]
    SLICE_X29Y34         LUT2 (Prop_lut2_I1_O)        0.124     5.899 f  RLINK/CORE/RL/R_BREGS[rbnak]_i_2/O
                         net (fo=5, routed)           0.344     6.243    RLINK/CORE/RL/R_BREGS[rbnak]_i_2_n_0
    SLICE_X30Y34         LUT5 (Prop_lut5_I1_O)        0.124     6.367 r  RLINK/CORE/RL/R_LREGS[din][15]_i_3/O
                         net (fo=4, routed)           0.806     7.172    RLINK/CORE/RL/R_LREGS[din][15]_i_3_n_0
    SLICE_X41Y36         LUT3 (Prop_lut3_I2_O)        0.124     7.296 r  RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_9/O
                         net (fo=2, routed)           0.697     7.993    RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][26]
    SLICE_X41Y33         LUT6 (Prop_lut6_I4_O)        0.124     8.117 r  RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS[bcnt][0]_i_1/O
                         net (fo=12, routed)          0.495     8.612    RLINK/CORE/RL/DOFIFO_n_1
    SLICE_X41Y30         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                     12.499    12.499 r  
    L17                                               0.000    12.499 r  I_CLK12 (IN)
                         net (fo=0)                   0.000    12.499    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406    13.905 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.261    15.166    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.208     7.958 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     9.545    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.636 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.439    11.076    RLINK/CORE/RL/CLKFX
    SLICE_X41Y30         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][7]/C
                         clock pessimism              0.494    11.570    
                         clock uncertainty           -0.036    11.534    
    SLICE_X41Y30         FDRE (Setup_fdre_C_CE)      -0.205    11.329    RLINK/CORE/RL/R_LREGS_reg[bcnt][7]
  -------------------------------------------------------------------
                         required time                         11.329    
                         arrival time                          -8.612    
  -------------------------------------------------------------------
                         slack                                  2.717    

Slack (MET) :             2.731ns  (required time - arrival time)
  Source:                 SMRB/SMRB/R_REGS_reg[rbsel]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[bcnt][10]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.499ns  (CLKOUT0_1 rise@12.499ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        9.409ns  (logic 1.386ns (14.731%)  route 8.023ns (85.269%))
  Logic Levels:           7  (LUT2=1 LUT3=1 LUT5=1 LUT6=4)
  Clock Path Skew:        -0.119ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.423ns = ( 11.077 - 12.499 ) 
    Source Clock Delay      (SCD):    -0.809ns
    Clock Pessimism Removal (CPR):    0.494ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.010ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.336     2.812    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.950    -4.138 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.472    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.376 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.566    -0.809    SMRB/SMRB/CLKFX
    SLICE_X14Y36         FDRE                                         r  SMRB/SMRB/R_REGS_reg[rbsel]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y36         FDRE (Prop_fdre_C_Q)         0.518    -0.291 f  SMRB/SMRB/R_REGS_reg[rbsel]/Q
                         net (fo=24, routed)          2.279     1.987    SMRB/SMRB/R_BREGS_reg[rbdout][5]
    SLICE_X29Y71         LUT6 (Prop_lut6_I3_O)        0.124     2.111 f  SMRB/SMRB/R_BREGS[rbtout]_i_13/O
                         net (fo=1, routed)           0.492     2.603    SMRB/SMRB/R_BREGS[rbtout]_i_13_n_0
    SLICE_X28Y70         LUT6 (Prop_lut6_I5_O)        0.124     2.727 f  SMRB/SMRB/R_BREGS[rbtout]_i_9/O
                         net (fo=1, routed)           1.891     4.618    TST/RB_SRES_SYSMON[busy]
    SLICE_X5Y36          LUT6 (Prop_lut6_I5_O)        0.124     4.742 r  TST/R_BREGS[rbtout]_i_3/O
                         net (fo=6, routed)           1.033     5.775    RLINK/CORE/RL/FSM_onehot_R_REGS_reg[state][1]
    SLICE_X29Y34         LUT2 (Prop_lut2_I1_O)        0.124     5.899 f  RLINK/CORE/RL/R_BREGS[rbnak]_i_2/O
                         net (fo=5, routed)           0.344     6.243    RLINK/CORE/RL/R_BREGS[rbnak]_i_2_n_0
    SLICE_X30Y34         LUT5 (Prop_lut5_I1_O)        0.124     6.367 r  RLINK/CORE/RL/R_LREGS[din][15]_i_3/O
                         net (fo=4, routed)           0.806     7.172    RLINK/CORE/RL/R_LREGS[din][15]_i_3_n_0
    SLICE_X41Y36         LUT3 (Prop_lut3_I2_O)        0.124     7.296 r  RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_9/O
                         net (fo=2, routed)           0.697     7.993    RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][26]
    SLICE_X41Y33         LUT6 (Prop_lut6_I4_O)        0.124     8.117 r  RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS[bcnt][0]_i_1/O
                         net (fo=12, routed)          0.482     8.599    RLINK/CORE/RL/DOFIFO_n_1
    SLICE_X41Y31         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][10]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                     12.499    12.499 r  
    L17                                               0.000    12.499 r  I_CLK12 (IN)
                         net (fo=0)                   0.000    12.499    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406    13.905 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.261    15.166    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.208     7.958 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     9.545    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.636 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.440    11.077    RLINK/CORE/RL/CLKFX
    SLICE_X41Y31         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][10]/C
                         clock pessimism              0.494    11.571    
                         clock uncertainty           -0.036    11.535    
    SLICE_X41Y31         FDRE (Setup_fdre_C_CE)      -0.205    11.330    RLINK/CORE/RL/R_LREGS_reg[bcnt][10]
  -------------------------------------------------------------------
                         required time                         11.330    
                         arrival time                          -8.599    
  -------------------------------------------------------------------
                         slack                                  2.731    

Slack (MET) :             2.731ns  (required time - arrival time)
  Source:                 SMRB/SMRB/R_REGS_reg[rbsel]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[bcnt][11]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.499ns  (CLKOUT0_1 rise@12.499ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        9.409ns  (logic 1.386ns (14.731%)  route 8.023ns (85.269%))
  Logic Levels:           7  (LUT2=1 LUT3=1 LUT5=1 LUT6=4)
  Clock Path Skew:        -0.119ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.423ns = ( 11.077 - 12.499 ) 
    Source Clock Delay      (SCD):    -0.809ns
    Clock Pessimism Removal (CPR):    0.494ns
  Clock Uncertainty:      0.036ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.010ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.336     2.812    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.950    -4.138 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.472    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.376 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.566    -0.809    SMRB/SMRB/CLKFX
    SLICE_X14Y36         FDRE                                         r  SMRB/SMRB/R_REGS_reg[rbsel]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y36         FDRE (Prop_fdre_C_Q)         0.518    -0.291 f  SMRB/SMRB/R_REGS_reg[rbsel]/Q
                         net (fo=24, routed)          2.279     1.987    SMRB/SMRB/R_BREGS_reg[rbdout][5]
    SLICE_X29Y71         LUT6 (Prop_lut6_I3_O)        0.124     2.111 f  SMRB/SMRB/R_BREGS[rbtout]_i_13/O
                         net (fo=1, routed)           0.492     2.603    SMRB/SMRB/R_BREGS[rbtout]_i_13_n_0
    SLICE_X28Y70         LUT6 (Prop_lut6_I5_O)        0.124     2.727 f  SMRB/SMRB/R_BREGS[rbtout]_i_9/O
                         net (fo=1, routed)           1.891     4.618    TST/RB_SRES_SYSMON[busy]
    SLICE_X5Y36          LUT6 (Prop_lut6_I5_O)        0.124     4.742 r  TST/R_BREGS[rbtout]_i_3/O
                         net (fo=6, routed)           1.033     5.775    RLINK/CORE/RL/FSM_onehot_R_REGS_reg[state][1]
    SLICE_X29Y34         LUT2 (Prop_lut2_I1_O)        0.124     5.899 f  RLINK/CORE/RL/R_BREGS[rbnak]_i_2/O
                         net (fo=5, routed)           0.344     6.243    RLINK/CORE/RL/R_BREGS[rbnak]_i_2_n_0
    SLICE_X30Y34         LUT5 (Prop_lut5_I1_O)        0.124     6.367 r  RLINK/CORE/RL/R_LREGS[din][15]_i_3/O
                         net (fo=4, routed)           0.806     7.172    RLINK/CORE/RL/R_LREGS[din][15]_i_3_n_0
    SLICE_X41Y36         LUT3 (Prop_lut3_I2_O)        0.124     7.296 r  RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_9/O
                         net (fo=2, routed)           0.697     7.993    RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][26]
    SLICE_X41Y33         LUT6 (Prop_lut6_I4_O)        0.124     8.117 r  RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS[bcnt][0]_i_1/O
                         net (fo=12, routed)          0.482     8.599    RLINK/CORE/RL/DOFIFO_n_1
    SLICE_X41Y31         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][11]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                     12.499    12.499 r  
    L17                                               0.000    12.499 r  I_CLK12 (IN)
                         net (fo=0)                   0.000    12.499    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406    13.905 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.261    15.166    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.208     7.958 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     9.545    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.636 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.440    11.077    RLINK/CORE/RL/CLKFX
    SLICE_X41Y31         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[bcnt][11]/C
                         clock pessimism              0.494    11.571    
                         clock uncertainty           -0.036    11.535    
    SLICE_X41Y31         FDRE (Setup_fdre_C_CE)      -0.205    11.330    RLINK/CORE/RL/R_LREGS_reg[bcnt][11]
  -------------------------------------------------------------------
                         required time                         11.330    
                         arrival time                          -8.599    
  -------------------------------------------------------------------
                         slack                                  2.731    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.082ns  (arrival time - required time)
  Source:                 RLINK/CORE/CD2B/R_REGS_reg[data][4]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMC/I
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.242ns  (logic 0.141ns (58.263%)  route 0.101ns (41.737%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.793ns
    Source Clock Delay      (SCD):    -0.561ns
    Clock Pessimism Removal (CPR):    -0.248ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.472     0.716    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.359    -1.642 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.154    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.128 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.567    -0.561    RLINK/CORE/CD2B/CLKFX
    SLICE_X15Y40         FDRE                                         r  RLINK/CORE/CD2B/R_REGS_reg[data][4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y40         FDRE (Prop_fdre_C_Q)         0.141    -0.420 r  RLINK/CORE/CD2B/R_REGS_reg[data][4]/Q
                         net (fo=1, routed)           0.101    -0.319    RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/DIC0
    SLICE_X12Y40         RAMD32                                       r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMC/I
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.517     0.949    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.141    -2.192 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.659    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.630 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.837    -0.793    RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X12Y40         RAMD32                                       r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
                         clock pessimism              0.248    -0.545    
    SLICE_X12Y40         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.144    -0.401    RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMC
  -------------------------------------------------------------------
                         required time                          0.401    
                         arrival time                          -0.319    
  -------------------------------------------------------------------
                         slack                                  0.082    

Slack (MET) :             0.092ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[attn][0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[cnt][0]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.445ns  (logic 0.186ns (41.789%)  route 0.259ns (58.211%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.262ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.803ns
    Source Clock Delay      (SCD):    -0.568ns
    Clock Pessimism Removal (CPR):    -0.497ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.472     0.716    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.359    -1.642 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.154    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.128 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.560    -0.568    RLINK/CORE/RL/CLKFX
    SLICE_X35Y34         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[attn][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X35Y34         FDRE (Prop_fdre_C_Q)         0.141    -0.427 r  RLINK/CORE/RL/R_LREGS_reg[attn][0]/Q
                         net (fo=4, routed)           0.259    -0.168    RLINK/CORE/RL/R_LREGS_reg[attn_n_0_][0]
    SLICE_X39Y33         LUT6 (Prop_lut6_I1_O)        0.045    -0.123 r  RLINK/CORE/RL/R_LREGS[cnt][0]_i_1/O
                         net (fo=1, routed)           0.000    -0.123    RLINK/CORE/RL/R_LREGS[cnt][0]_i_1_n_0
    SLICE_X39Y33         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[cnt][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.517     0.949    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.141    -2.192 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.659    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.630 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.827    -0.803    RLINK/CORE/RL/CLKFX
    SLICE_X39Y33         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[cnt][0]/C
                         clock pessimism              0.497    -0.306    
    SLICE_X39Y33         FDRE (Hold_fdre_C_D)         0.091    -0.215    RLINK/CORE/RL/R_LREGS_reg[cnt][0]
  -------------------------------------------------------------------
                         required time                          0.215    
                         arrival time                          -0.123    
  -------------------------------------------------------------------
                         slack                                  0.092    

Slack (MET) :             0.101ns  (arrival time - required time)
  Source:                 RLINK/CORE/CD2B/R_REGS_reg[data][0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMA/I
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.264ns  (logic 0.164ns (62.120%)  route 0.100ns (37.880%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.793ns
    Source Clock Delay      (SCD):    -0.561ns
    Clock Pessimism Removal (CPR):    -0.248ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.472     0.716    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.359    -1.642 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.154    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.128 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.567    -0.561    RLINK/CORE/CD2B/CLKFX
    SLICE_X14Y40         FDRE                                         r  RLINK/CORE/CD2B/R_REGS_reg[data][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y40         FDRE (Prop_fdre_C_Q)         0.164    -0.397 r  RLINK/CORE/CD2B/R_REGS_reg[data][0]/Q
                         net (fo=1, routed)           0.100    -0.297    RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/DIA0
    SLICE_X12Y40         RAMD32                                       r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMA/I
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.517     0.949    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.141    -2.192 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.659    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.630 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.837    -0.793    RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X12Y40         RAMD32                                       r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMA/CLK
                         clock pessimism              0.248    -0.545    
    SLICE_X12Y40         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.147    -0.398    RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMA
  -------------------------------------------------------------------
                         required time                          0.398    
                         arrival time                          -0.297    
  -------------------------------------------------------------------
                         slack                                  0.101    

Slack (MET) :             0.106ns  (arrival time - required time)
  Source:                 TST/R_REGS_reg[saddr][5]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            TST/SMEM_B0/sv_ram_reg/ADDRARDADDR[9]
                            (rising edge-triggered cell RAMB36E1 clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.345ns  (logic 0.164ns (47.534%)  route 0.181ns (52.466%))
  Logic Levels:           0  
  Clock Path Skew:        0.056ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.757ns
    Source Clock Delay      (SCD):    -0.565ns
    Clock Pessimism Removal (CPR):    -0.248ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.472     0.716    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.359    -1.642 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.154    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.128 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.563    -0.565    TST/CLKFX
    SLICE_X8Y33          FDRE                                         r  TST/R_REGS_reg[saddr][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y33          FDRE (Prop_fdre_C_Q)         0.164    -0.401 r  TST/R_REGS_reg[saddr][5]/Q
                         net (fo=9, routed)           0.181    -0.220    TST/SMEM_B0/Q[5]
    RAMB36_X0Y6          RAMB36E1                                     r  TST/SMEM_B0/sv_ram_reg/ADDRARDADDR[9]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.517     0.949    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.141    -2.192 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.659    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.630 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.873    -0.757    TST/SMEM_B0/CLKFX
    RAMB36_X0Y6          RAMB36E1                                     r  TST/SMEM_B0/sv_ram_reg/CLKARDCLK
                         clock pessimism              0.248    -0.508    
    RAMB36_X0Y6          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_ADDRARDADDR[9])
                                                      0.183    -0.325    TST/SMEM_B0/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          0.325    
                         arrival time                          -0.220    
  -------------------------------------------------------------------
                         slack                                  0.106    

Slack (MET) :             0.115ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[cnt][1]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/CORE/RL/R_BREGS_reg[cnt][1]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.466ns  (logic 0.186ns (39.915%)  route 0.280ns (60.085%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.260ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.805ns
    Source Clock Delay      (SCD):    -0.568ns
    Clock Pessimism Removal (CPR):    -0.497ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.472     0.716    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.359    -1.642 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.154    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.128 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.560    -0.568    RLINK/CORE/RL/CLKFX
    SLICE_X41Y33         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[cnt][1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y33         FDRE (Prop_fdre_C_Q)         0.141    -0.427 r  RLINK/CORE/RL/R_LREGS_reg[cnt][1]/Q
                         net (fo=5, routed)           0.280    -0.147    RLINK/CORE/RL/p_0_in[2]
    SLICE_X33Y31         LUT4 (Prop_lut4_I0_O)        0.045    -0.102 r  RLINK/CORE/RL/R_BREGS[cnt][1]_i_1/O
                         net (fo=1, routed)           0.000    -0.102    RLINK/CORE/RL/N_BREGS[cnt][1]
    SLICE_X33Y31         FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[cnt][1]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.517     0.949    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.141    -2.192 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.659    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.630 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.825    -0.805    RLINK/CORE/RL/CLKFX
    SLICE_X33Y31         FDRE                                         r  RLINK/CORE/RL/R_BREGS_reg[cnt][1]/C
                         clock pessimism              0.497    -0.308    
    SLICE_X33Y31         FDRE (Hold_fdre_C_D)         0.091    -0.217    RLINK/CORE/RL/R_BREGS_reg[cnt][1]
  -------------------------------------------------------------------
                         required time                          0.217    
                         arrival time                          -0.102    
  -------------------------------------------------------------------
                         slack                                  0.115    

Slack (MET) :             0.117ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state][27]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[din][9]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.500ns  (logic 0.209ns (41.805%)  route 0.291ns (58.195%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.263ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.800ns
    Source Clock Delay      (SCD):    -0.566ns
    Clock Pessimism Removal (CPR):    -0.497ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.472     0.716    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.359    -1.642 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.154    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.128 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.562    -0.566    RLINK/CORE/RL/CLKFX
    SLICE_X42Y37         FDRE                                         r  RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state][27]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X42Y37         FDRE (Prop_fdre_C_Q)         0.164    -0.402 r  RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state][27]/Q
                         net (fo=22, routed)          0.291    -0.111    RLINK/CORE/RL/RTBUF/FSM_onehot_R_LREGS_reg[state][37][9]
    SLICE_X30Y37         LUT5 (Prop_lut5_I4_O)        0.045    -0.066 r  RLINK/CORE/RL/RTBUF/R_LREGS[din][9]_i_1/O
                         net (fo=1, routed)           0.000    -0.066    RLINK/CORE/RL/n[din][9]
    SLICE_X30Y37         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[din][9]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.517     0.949    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.141    -2.192 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.659    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.630 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.830    -0.800    RLINK/CORE/RL/CLKFX
    SLICE_X30Y37         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[din][9]/C
                         clock pessimism              0.497    -0.303    
    SLICE_X30Y37         FDRE (Hold_fdre_C_D)         0.120    -0.183    RLINK/CORE/RL/R_LREGS_reg[din][9]
  -------------------------------------------------------------------
                         required time                          0.183    
                         arrival time                          -0.066    
  -------------------------------------------------------------------
                         slack                                  0.117    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/CDC_RXOK/R_DO_S0_reg/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/SERPORT/CDC_RXOK/R_DO_S1_reg/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.793ns
    Source Clock Delay      (SCD):    -0.561ns
    Clock Pessimism Removal (CPR):    -0.232ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.472     0.716    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.359    -1.642 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.154    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.128 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.567    -0.561    RLINK/SERPORT/CDC_RXOK/CLKO
    SLICE_X11Y41         FDRE                                         r  RLINK/SERPORT/CDC_RXOK/R_DO_S0_reg/C
  -------------------------------------------------------------------    -------------------
    SLICE_X11Y41         FDRE (Prop_fdre_C_Q)         0.141    -0.420 r  RLINK/SERPORT/CDC_RXOK/R_DO_S0_reg/Q
                         net (fo=1, routed)           0.056    -0.364    RLINK/SERPORT/CDC_RXOK/R_DO_S0
    SLICE_X11Y41         FDRE                                         r  RLINK/SERPORT/CDC_RXOK/R_DO_S1_reg/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.517     0.949    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.141    -2.192 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.659    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.630 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.837    -0.793    RLINK/SERPORT/CDC_RXOK/CLKO
    SLICE_X11Y41         FDRE                                         r  RLINK/SERPORT/CDC_RXOK/R_DO_S1_reg/C
                         clock pessimism              0.232    -0.561    
    SLICE_X11Y41         FDRE (Hold_fdre_C_D)         0.075    -0.486    RLINK/SERPORT/CDC_RXOK/R_DO_S1_reg
  -------------------------------------------------------------------
                         required time                          0.486    
                         arrival time                          -0.364    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/RXFIFO/RR_WADDR_S0_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/SERPORT/RXFIFO/RR_WADDR_S1_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.791ns
    Source Clock Delay      (SCD):    -0.559ns
    Clock Pessimism Removal (CPR):    -0.232ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.472     0.716    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.359    -1.642 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.154    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.128 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.569    -0.559    RLINK/SERPORT/RXFIFO/CLKR
    SLICE_X15Y48         FDRE                                         r  RLINK/SERPORT/RXFIFO/RR_WADDR_S0_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y48         FDRE (Prop_fdre_C_Q)         0.141    -0.418 r  RLINK/SERPORT/RXFIFO/RR_WADDR_S0_reg[3]/Q
                         net (fo=1, routed)           0.056    -0.362    RLINK/SERPORT/RXFIFO/RR_WADDR_S0[3]
    SLICE_X15Y48         FDRE                                         r  RLINK/SERPORT/RXFIFO/RR_WADDR_S1_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.517     0.949    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.141    -2.192 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.659    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.630 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.839    -0.791    RLINK/SERPORT/RXFIFO/CLKR
    SLICE_X15Y48         FDRE                                         r  RLINK/SERPORT/RXFIFO/RR_WADDR_S1_reg[3]/C
                         clock pessimism              0.232    -0.559    
    SLICE_X15Y48         FDRE (Hold_fdre_C_D)         0.075    -0.484    RLINK/SERPORT/RXFIFO/RR_WADDR_S1_reg[3]
  -------------------------------------------------------------------
                         required time                          0.484    
                         arrival time                          -0.362    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/RXFIFO/RR_WADDR_S0_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/SERPORT/RXFIFO/RR_WADDR_S1_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.791ns
    Source Clock Delay      (SCD):    -0.559ns
    Clock Pessimism Removal (CPR):    -0.232ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.472     0.716    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.359    -1.642 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.154    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.128 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.569    -0.559    RLINK/SERPORT/RXFIFO/CLKR
    SLICE_X13Y47         FDRE                                         r  RLINK/SERPORT/RXFIFO/RR_WADDR_S0_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X13Y47         FDRE (Prop_fdre_C_Q)         0.141    -0.418 r  RLINK/SERPORT/RXFIFO/RR_WADDR_S0_reg[4]/Q
                         net (fo=1, routed)           0.056    -0.362    RLINK/SERPORT/RXFIFO/RR_WADDR_S0[4]
    SLICE_X13Y47         FDRE                                         r  RLINK/SERPORT/RXFIFO/RR_WADDR_S1_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.517     0.949    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.141    -2.192 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.659    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.630 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.839    -0.791    RLINK/SERPORT/RXFIFO/CLKR
    SLICE_X13Y47         FDRE                                         r  RLINK/SERPORT/RXFIFO/RR_WADDR_S1_reg[4]/C
                         clock pessimism              0.232    -0.559    
    SLICE_X13Y47         FDRE (Hold_fdre_C_D)         0.075    -0.484    RLINK/SERPORT/RXFIFO/RR_WADDR_S1_reg[4]
  -------------------------------------------------------------------
                         required time                          0.484    
                         arrival time                          -0.362    
  -------------------------------------------------------------------
                         slack                                  0.122    

Slack (MET) :             0.122ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/TXFIFO/RW_RADDR_S0_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/SERPORT/TXFIFO/RW_RADDR_S1_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0_1 rise@0.000ns - CLKOUT0_1 rise@0.000ns)
  Data Path Delay:        0.197ns  (logic 0.141ns (71.611%)  route 0.056ns (28.389%))
  Logic Levels:           0  
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.796ns
    Source Clock Delay      (SCD):    -0.563ns
    Clock Pessimism Removal (CPR):    -0.233ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.244     0.244 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.472     0.716    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.359    -1.642 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.489    -1.154    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.128 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.565    -0.563    RLINK/SERPORT/TXFIFO/CLKW
    SLICE_X11Y37         FDRE                                         r  RLINK/SERPORT/TXFIFO/RW_RADDR_S0_reg[0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X11Y37         FDRE (Prop_fdre_C_Q)         0.141    -0.422 r  RLINK/SERPORT/TXFIFO/RW_RADDR_S0_reg[0]/Q
                         net (fo=1, routed)           0.056    -0.366    RLINK/SERPORT/TXFIFO/RW_RADDR_S0[0]
    SLICE_X11Y37         FDRE                                         r  RLINK/SERPORT/TXFIFO/RW_RADDR_S1_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         0.432     0.432 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           0.517     0.949    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.141    -2.192 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.534    -1.659    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.630 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         0.834    -0.796    RLINK/SERPORT/TXFIFO/CLKW
    SLICE_X11Y37         FDRE                                         r  RLINK/SERPORT/TXFIFO/RW_RADDR_S1_reg[0]/C
                         clock pessimism              0.233    -0.563    
    SLICE_X11Y37         FDRE (Hold_fdre_C_D)         0.075    -0.488    RLINK/SERPORT/TXFIFO/RW_RADDR_S1_reg[0]
  -------------------------------------------------------------------
                         required time                          0.488    
                         arrival time                          -0.366    
  -------------------------------------------------------------------
                         slack                                  0.122    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         CLKOUT0_1
Waveform(ns):       { 0.000 6.250 }
Period(ns):         12.499
Sources:            { GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     XADC/DCLK           n/a            4.000         12.499      8.499      XADC_X0Y0        SMRB/SM/DCLK
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.944         12.499      9.555      RAMB36_X1Y6      RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.944         12.499      9.555      RAMB36_X1Y6      RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKBWRCLK
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.576         12.499      9.923      RAMB36_X0Y5      TST/SMEM_B1/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.576         12.499      9.923      RAMB36_X0Y5      TST/SMEM_B1/sv_ram_reg/CLKBWRCLK
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.576         12.499      9.923      RAMB36_X0Y7      TST/SMEM_B3/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.576         12.499      9.923      RAMB36_X0Y4      TST/SMEM_B2/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.576         12.499      9.923      RAMB36_X0Y6      TST/SMEM_B0/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.576         12.499      9.923      RAMB36_X0Y6      TST/SMEM_B0/sv_ram_reg/CLKBWRCLK
Min Period        n/a     BUFG/I              n/a            2.155         12.499      10.344     BUFGCTRL_X0Y16   GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/I
Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       12.499      200.861    MMCME2_ADV_X0Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y33     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y33     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC_D1/CLK
Low Pulse Width   Slow    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y33     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMD/CLK
Low Pulse Width   Slow    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y33     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMD_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y33     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y33     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y33     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y33     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB_D1/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y33     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y33     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y33     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y33     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC_D1/CLK
High Pulse Width  Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y33     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMD/CLK
High Pulse Width  Fast    RAMS32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y33     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMD_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y32     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y32     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y32     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y32     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y32     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X14Y32     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMC_D1/CLK



---------------------------------------------------------------------------------------------------
From Clock:  CLKOUT0_1
  To Clock:  CLKOUT0

Setup :            0  Failing Endpoints,  Worst Slack        5.037ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             5.037ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.524ns  (logic 0.518ns (33.986%)  route 1.006ns (66.014%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y38                                      0.000     0.000 r  RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[0]/C
    SLICE_X12Y38         FDRE (Prop_fdre_C_Q)         0.518     0.518 r  RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[0]/Q
                         net (fo=22, routed)          1.006     1.524    RLINK/SERPORT/TXFIFO/WADDR[0]
    SLICE_X11Y38         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X11Y38         FDRE (Setup_fdre_C_D)       -0.105     6.561    RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[0]
  -------------------------------------------------------------------
                         required time                          6.561    
                         arrival time                          -1.524    
  -------------------------------------------------------------------
                         slack                                  5.037    

Slack (MET) :             5.307ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][4]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (MaxDelay Path 8.333ns)
  Data Path Delay:        2.030ns  (logic 1.336ns (65.808%)  route 0.694ns (34.192%))
  Logic Levels:           0  
  Clock Path Skew:        -0.649ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.526ns
    Source Clock Delay      (SCD):    -0.806ns
    Clock Pessimism Removal (CPR):    0.071ns
  Clock Uncertainty:      0.080ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.019ns
    Phase Error              (PE):    0.043ns
  Timing Exception:       MaxDelay Path 8.333ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.336     2.812    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.950    -4.138 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.472    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.376 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.569    -0.806    RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X12Y40         RAMD32                                       r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y40         RAMD32 (Prop_ramd32_CLK_O)
                                                      1.336     0.530 r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMC/O
                         net (fo=1, routed)           0.694     1.224    RLINK/SERPORT/XONTX/D[4]
    SLICE_X13Y43         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][4]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    8.333     8.333    
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.162    10.900    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.450     6.807    RLINK/SERPORT/XONTX/I_CLK12
    SLICE_X13Y43         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][4]/C
                         clock pessimism              0.071     6.878    
                         clock uncertainty           -0.080     6.798    
    SLICE_X13Y43         FDRE (Setup_fdre_C_D)       -0.268     6.530    RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][4]
  -------------------------------------------------------------------
                         required time                          6.530    
                         arrival time                          -1.224    
  -------------------------------------------------------------------
                         slack                                  5.307    

Slack (MET) :             5.383ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/R_DATA_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.190ns  (logic 0.456ns (38.323%)  route 0.734ns (61.677%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y47                                      0.000     0.000 r  RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/R_DATA_reg[3]/C
    SLICE_X15Y47         FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/R_DATA_reg[3]/Q
                         net (fo=24, routed)          0.734     1.190    RLINK/SERPORT/RXFIFO/RADDR[3]
    SLICE_X13Y48         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X13Y48         FDRE (Setup_fdre_C_D)       -0.093     6.573    RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[3]
  -------------------------------------------------------------------
                         required time                          6.573    
                         arrival time                          -1.190    
  -------------------------------------------------------------------
                         slack                                  5.383    

Slack (MET) :             5.393ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_6_7/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][6]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (MaxDelay Path 8.333ns)
  Data Path Delay:        1.960ns  (logic 1.344ns (68.555%)  route 0.616ns (31.445%))
  Logic Levels:           0  
  Clock Path Skew:        -0.649ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.526ns
    Source Clock Delay      (SCD):    -0.806ns
    Clock Pessimism Removal (CPR):    0.071ns
  Clock Uncertainty:      0.080ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.019ns
    Phase Error              (PE):    0.043ns
  Timing Exception:       MaxDelay Path 8.333ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.336     2.812    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.950    -4.138 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.472    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.376 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.569    -0.806    RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_6_7/WCLK
    SLICE_X12Y39         RAMD32                                       r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_6_7/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y39         RAMD32 (Prop_ramd32_CLK_O)
                                                      1.344     0.538 r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_6_7/RAMA/O
                         net (fo=1, routed)           0.616     1.154    RLINK/SERPORT/XONTX/D[6]
    SLICE_X13Y43         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][6]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    8.333     8.333    
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.162    10.900    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.450     6.807    RLINK/SERPORT/XONTX/I_CLK12
    SLICE_X13Y43         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][6]/C
                         clock pessimism              0.071     6.878    
                         clock uncertainty           -0.080     6.798    
    SLICE_X13Y43         FDRE (Setup_fdre_C_D)       -0.251     6.547    RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][6]
  -------------------------------------------------------------------
                         required time                          6.547    
                         arrival time                          -1.154    
  -------------------------------------------------------------------
                         slack                                  5.393    

Slack (MET) :             5.398ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/R_DATA_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.173ns  (logic 0.518ns (44.143%)  route 0.655ns (55.857%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y47                                      0.000     0.000 r  RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/R_DATA_reg[0]/C
    SLICE_X14Y47         FDRE (Prop_fdre_C_Q)         0.518     0.518 r  RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/R_DATA_reg[0]/Q
                         net (fo=18, routed)          0.655     1.173    RLINK/SERPORT/RXFIFO/RADDR[0]
    SLICE_X11Y47         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X11Y47         FDRE (Setup_fdre_C_D)       -0.095     6.571    RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[0]
  -------------------------------------------------------------------
                         required time                          6.571    
                         arrival time                          -1.173    
  -------------------------------------------------------------------
                         slack                                  5.398    

Slack (MET) :             5.404ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.167ns  (logic 0.518ns (44.380%)  route 0.649ns (55.620%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y38                                      0.000     0.000 r  RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[1]/C
    SLICE_X12Y38         FDRE (Prop_fdre_C_Q)         0.518     0.518 r  RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/R_DATA_reg[1]/Q
                         net (fo=25, routed)          0.649     1.167    RLINK/SERPORT/TXFIFO/WADDR[1]
    SLICE_X11Y39         FDRE                                         r  RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X11Y39         FDRE (Setup_fdre_C_D)       -0.095     6.571    RLINK/SERPORT/TXFIFO/RR_WADDR_S0_reg[1]
  -------------------------------------------------------------------
                         required time                          6.571    
                         arrival time                          -1.167    
  -------------------------------------------------------------------
                         slack                                  5.404    

Slack (MET) :             5.472ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/R_DATA_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.147ns  (logic 0.456ns (39.767%)  route 0.691ns (60.233%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X15Y47                                      0.000     0.000 r  RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/R_DATA_reg[2]/C
    SLICE_X15Y47         FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/R_DATA_reg[2]/Q
                         net (fo=22, routed)          0.691     1.147    RLINK/SERPORT/RXFIFO/RADDR[2]
    SLICE_X12Y49         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X12Y49         FDRE (Setup_fdre_C_D)       -0.047     6.619    RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[2]
  -------------------------------------------------------------------
                         required time                          6.619    
                         arrival time                          -1.147    
  -------------------------------------------------------------------
                         slack                                  5.472    

Slack (MET) :             5.506ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][2]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (MaxDelay Path 8.333ns)
  Data Path Delay:        1.782ns  (logic 1.343ns (75.353%)  route 0.439ns (24.647%))
  Logic Levels:           0  
  Clock Path Skew:        -0.649ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.526ns
    Source Clock Delay      (SCD):    -0.806ns
    Clock Pessimism Removal (CPR):    0.071ns
  Clock Uncertainty:      0.080ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.019ns
    Phase Error              (PE):    0.043ns
  Timing Exception:       MaxDelay Path 8.333ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.336     2.812    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.950    -4.138 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.472    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.376 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.569    -0.806    RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X12Y40         RAMD32                                       r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y40         RAMD32 (Prop_ramd32_CLK_O)
                                                      1.343     0.537 r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMB/O
                         net (fo=1, routed)           0.439     0.976    RLINK/SERPORT/XONTX/D[2]
    SLICE_X13Y43         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    8.333     8.333    
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.162    10.900    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.450     6.807    RLINK/SERPORT/XONTX/I_CLK12
    SLICE_X13Y43         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][2]/C
                         clock pessimism              0.071     6.878    
                         clock uncertainty           -0.080     6.798    
    SLICE_X13Y43         FDRE (Setup_fdre_C_D)       -0.317     6.481    RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][2]
  -------------------------------------------------------------------
                         required time                          6.481    
                         arrival time                          -0.976    
  -------------------------------------------------------------------
                         slack                                  5.506    

Slack (MET) :             5.519ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/R_DATA_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.054ns  (logic 0.518ns (49.131%)  route 0.536ns (50.869%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X14Y47                                      0.000     0.000 r  RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/R_DATA_reg[4]/C
    SLICE_X14Y47         FDRE (Prop_fdre_C_Q)         0.518     0.518 r  RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/R_DATA_reg[4]/Q
                         net (fo=24, routed)          0.536     1.054    RLINK/SERPORT/RXFIFO/RADDR[4]
    SLICE_X13Y48         FDRE                                         r  RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X13Y48         FDRE (Setup_fdre_C_D)       -0.093     6.573    RLINK/SERPORT/RXFIFO/RW_RADDR_S0_reg[4]
  -------------------------------------------------------------------
                         required time                          6.573    
                         arrival time                          -1.054    
  -------------------------------------------------------------------
                         slack                                  5.519    

Slack (MET) :             5.520ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMA/CLK
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Destination:            RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][0]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (MaxDelay Path 8.333ns)
  Data Path Delay:        1.786ns  (logic 1.344ns (75.262%)  route 0.442ns (24.738%))
  Logic Levels:           0  
  Clock Path Skew:        -0.649ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.526ns
    Source Clock Delay      (SCD):    -0.806ns
    Clock Pessimism Removal (CPR):    0.071ns
  Clock Uncertainty:      0.080ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.019ns
    Phase Error              (PE):    0.043ns
  Timing Exception:       MaxDelay Path 8.333ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0_1 rise edge)
                                                      0.000     0.000 r  
    L17                                               0.000     0.000 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.476     1.476 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.336     2.812    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X0Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.950    -4.138 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.666    -2.472    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.376 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=934, routed)         1.569    -0.806    RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/WCLK
    SLICE_X12Y40         RAMD32                                       r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMA/CLK
  -------------------------------------------------------------------    -------------------
    SLICE_X12Y40         RAMD32 (Prop_ramd32_CLK_O)
                                                      1.344     0.538 r  RLINK/SERPORT/TXFIFO/RAM/RAM_reg_0_31_0_5/RAMA/O
                         net (fo=1, routed)           0.442     0.979    RLINK/SERPORT/XONTX/D[0]
    SLICE_X13Y43         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    8.333     8.333    
    L17                                               0.000     8.333 r  I_CLK12 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK12
    L17                  IBUF (Prop_ibuf_I_O)         1.406     9.739 r  I_CLK12_IBUF_inst/O
                         net (fo=2, routed)           1.162    10.900    GEN_CLKSER/CLKIN
    MMCME2_ADV_X0Y0      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.221     3.679 r  GEN_CLKSER/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.587     5.266    GEN_CLKSER/CLKOUT0
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091     5.357 r  GEN_CLKSER/USEMMCM.BUFG_CLKOUT/O
                         net (fo=213, routed)         1.450     6.807    RLINK/SERPORT/XONTX/I_CLK12
    SLICE_X13Y43         FDRE                                         r  RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][0]/C
                         clock pessimism              0.071     6.878    
                         clock uncertainty           -0.080     6.798    
    SLICE_X13Y43         FDRE (Setup_fdre_C_D)       -0.299     6.499    RLINK/SERPORT/XONTX/R_REGS_reg[ibuf][0]
  -------------------------------------------------------------------
                         required time                          6.499    
                         arrival time                          -0.979    
  -------------------------------------------------------------------
                         slack                                  5.520    





---------------------------------------------------------------------------------------------------
From Clock:  CLKOUT0
  To Clock:  CLKOUT0_1

Setup :            0  Failing Endpoints,  Worst Slack        5.276ns,  Total Violation        0.000ns
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             5.276ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.319ns  (logic 0.456ns (34.561%)  route 0.863ns (65.439%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y40                                       0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/C
    SLICE_X9Y40          FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][5]/Q
                         net (fo=6, routed)           0.863     1.319    RLINK/SERPORT/CDC_CDIV/DI[2]
    SLICE_X8Y39          FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X8Y39          FDRE (Setup_fdre_C_D)       -0.071     6.595    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[2]
  -------------------------------------------------------------------
                         required time                          6.595    
                         arrival time                          -1.319    
  -------------------------------------------------------------------
                         slack                                  5.276    

Slack (MET) :             5.279ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][13]/C
                            (rising edge-triggered cell FDSE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.324ns  (logic 0.456ns (34.451%)  route 0.868ns (65.549%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y42                                       0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][13]/C
    SLICE_X9Y42          FDSE (Prop_fdse_C_Q)         0.456     0.456 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][13]/Q
                         net (fo=7, routed)           0.868     1.324    RLINK/SERPORT/CDC_CDIV/DI[10]
    SLICE_X8Y42          FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X8Y42          FDRE (Setup_fdre_C_D)       -0.063     6.603    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[10]
  -------------------------------------------------------------------
                         required time                          6.603    
                         arrival time                          -1.324    
  -------------------------------------------------------------------
                         slack                                  5.279    

Slack (MET) :             5.283ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][7]/C
                            (rising edge-triggered cell FDSE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.322ns  (logic 0.456ns (34.502%)  route 0.866ns (65.499%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y40                                       0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][7]/C
    SLICE_X9Y40          FDSE (Prop_fdse_C_Q)         0.456     0.456 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][7]/Q
                         net (fo=7, routed)           0.866     1.322    RLINK/SERPORT/CDC_CDIV/DI[4]
    SLICE_X8Y40          FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X8Y40          FDRE (Setup_fdre_C_D)       -0.061     6.605    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[4]
  -------------------------------------------------------------------
                         required time                          6.605    
                         arrival time                          -1.322    
  -------------------------------------------------------------------
                         slack                                  5.283    

Slack (MET) :             5.413ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][14]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.182ns  (logic 0.456ns (38.580%)  route 0.726ns (61.420%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y42                                       0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][14]/C
    SLICE_X9Y42          FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][14]/Q
                         net (fo=7, routed)           0.726     1.182    RLINK/SERPORT/CDC_CDIV/DI[11]
    SLICE_X8Y42          FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X8Y42          FDRE (Setup_fdre_C_D)       -0.071     6.595    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[11]
  -------------------------------------------------------------------
                         required time                          6.595    
                         arrival time                          -1.182    
  -------------------------------------------------------------------
                         slack                                  5.413    

Slack (MET) :             5.456ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][9]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.149ns  (logic 0.456ns (39.673%)  route 0.693ns (60.327%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y41                                       0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][9]/C
    SLICE_X9Y41          FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][9]/Q
                         net (fo=7, routed)           0.693     1.149    RLINK/SERPORT/CDC_CDIV/DI[6]
    SLICE_X8Y41          FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X8Y41          FDRE (Setup_fdre_C_D)       -0.061     6.605    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[6]
  -------------------------------------------------------------------
                         required time                          6.605    
                         arrival time                          -1.149    
  -------------------------------------------------------------------
                         slack                                  5.456    

Slack (MET) :             5.457ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIVF/R_DO_S0_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.148ns  (logic 0.518ns (45.110%)  route 0.630ns (54.890%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X6Y39                                       0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][0]/C
    SLICE_X6Y39          FDRE (Prop_fdre_C_Q)         0.518     0.518 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][0]/Q
                         net (fo=3, routed)           0.630     1.148    RLINK/SERPORT/CDC_CDIVF/DI[0]
    SLICE_X4Y41          FDRE                                         r  RLINK/SERPORT/CDC_CDIVF/R_DO_S0_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X4Y41          FDRE (Setup_fdre_C_D)       -0.061     6.605    RLINK/SERPORT/CDC_CDIVF/R_DO_S0_reg[0]
  -------------------------------------------------------------------
                         required time                          6.605    
                         arrival time                          -1.148    
  -------------------------------------------------------------------
                         slack                                  5.457    

Slack (MET) :             5.510ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][2]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIVF/R_DO_S0_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.098ns  (logic 0.456ns (41.537%)  route 0.642ns (58.463%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y39                                       0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][2]/C
    SLICE_X9Y39          FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][2]/Q
                         net (fo=2, routed)           0.642     1.098    RLINK/SERPORT/CDC_CDIVF/DI[2]
    SLICE_X4Y41          FDRE                                         r  RLINK/SERPORT/CDC_CDIVF/R_DO_S0_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X4Y41          FDRE (Setup_fdre_C_D)       -0.058     6.608    RLINK/SERPORT/CDC_CDIVF/R_DO_S0_reg[2]
  -------------------------------------------------------------------
                         required time                          6.608    
                         arrival time                          -1.098    
  -------------------------------------------------------------------
                         slack                                  5.510    

Slack (MET) :             5.518ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][11]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        1.120ns  (logic 0.456ns (40.711%)  route 0.664ns (59.289%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y41                                       0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][11]/C
    SLICE_X9Y41          FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][11]/Q
                         net (fo=7, routed)           0.664     1.120    RLINK/SERPORT/CDC_CDIV/DI[8]
    SLICE_X10Y41         FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X10Y41         FDRE (Setup_fdre_C_D)       -0.028     6.638    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[8]
  -------------------------------------------------------------------
                         required time                          6.638    
                         arrival time                          -1.120    
  -------------------------------------------------------------------
                         slack                                  5.518    

Slack (MET) :             5.653ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][3]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[0]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        0.970ns  (logic 0.456ns (46.990%)  route 0.514ns (53.010%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y39                                       0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][3]/C
    SLICE_X9Y39          FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][3]/Q
                         net (fo=4, routed)           0.514     0.970    RLINK/SERPORT/CDC_CDIV/DI[0]
    SLICE_X11Y37         FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[0]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X11Y37         FDRE (Setup_fdre_C_D)       -0.043     6.623    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[0]
  -------------------------------------------------------------------
                         required time                          6.623    
                         arrival time                          -0.970    
  -------------------------------------------------------------------
                         slack                                  5.653    

Slack (MET) :             5.672ns  (required time - arrival time)
  Source:                 RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][10]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0_1  {rise@0.000ns fall@6.250ns period=12.499ns})
  Path Group:             CLKOUT0_1
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            6.666ns  (MaxDelay Path 6.666ns)
  Data Path Delay:        0.966ns  (logic 0.456ns (47.202%)  route 0.510ns (52.798%))
  Logic Levels:           0  
  Timing Exception:       MaxDelay Path 6.666ns -datapath_only

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
    SLICE_X9Y41                                       0.000     0.000 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][10]/C
    SLICE_X9Y41          FDRE (Prop_fdre_C_Q)         0.456     0.456 r  RLINK/SERPORT/UART/AB/R_REGS_reg[ccnt][10]/Q
                         net (fo=7, routed)           0.510     0.966    RLINK/SERPORT/CDC_CDIV/DI[7]
    SLICE_X10Y41         FDRE                                         r  RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         max delay                    6.666     6.666    
    SLICE_X10Y41         FDRE (Setup_fdre_C_D)       -0.028     6.638    RLINK/SERPORT/CDC_CDIV/R_DO_S0_reg[7]
  -------------------------------------------------------------------
                         required time                          6.638    
                         arrival time                          -0.966    
  -------------------------------------------------------------------
                         slack                                  5.672    





