
*** Running vivado
    with args -log sys_tst_sram_c7.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source sys_tst_sram_c7.tcl -notrace


****** Vivado v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source sys_tst_sram_c7.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 61 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.2
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/cmoda7_pclk.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/cmoda7_pclk.xdc]
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/cmoda7_pins.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/cmoda7_pins.xdc]
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/cmoda7_pins_sram.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/cmoda7_pins_sram.xdc]
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_ABDONE'
INFO: [Timing 38-35] Done setting XDC timing constraints. [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc:13]
INFO: [Timing 38-2] Deriving generated clocks [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc:13]
get_clocks: Time (s): cpu = 00:00:15 ; elapsed = 00:00:16 . Memory (MB): peak = 1776.121 ; gain = 465.438 ; free physical = 826 ; free virtual = 8279
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_ABDONE'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RESET'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RESET'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXERR'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXERR'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXOVR'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXOVR'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ABACT'
WARNING: [Vivado 12-2489] -delay contains time 9.999200 which will be rounded to 9.999 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ABACT'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAESC'
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAESC'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAXON'
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAXON'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXACT'
WARNING: [Vivado 12-2489] -delay contains time 9.999200 which will be rounded to 9.999 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXACT'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXOK'
WARNING: [Vivado 12-2489] -delay contains time 9.999200 which will be rounded to 9.999 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXOK'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXACT'
WARNING: [Vivado 12-2489] -delay contains time 9.999200 which will be rounded to 9.999 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXACT'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXOK'
WARNING: [Vivado 12-2489] -delay contains time 9.999200 which will be rounded to 9.999 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc:24]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXOK'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIV'
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc:30]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIV'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIVF'
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc:30]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIVF'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/RXFIFO'
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:23]
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:28]
WARNING: [Vivado 12-2489] -delay contains time 9.999200 which will be rounded to 9.999 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:35]
WARNING: [Vivado 12-2489] -delay contains time 9.999200 which will be rounded to 9.999 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:40]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/RXFIFO'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/TXFIFO'
WARNING: [Vivado 12-2489] -delay contains time 9.999200 which will be rounded to 9.999 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:23]
WARNING: [Vivado 12-2489] -delay contains time 9.999200 which will be rounded to 9.999 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:28]
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:35]
WARNING: [Vivado 12-2489] -delay contains time 6.666400 which will be rounded to 6.666 to ensure it is an integer multiple of 1 picosecond [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:40]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/TXFIFO'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 14 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 8 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 6 instances

link_design: Time (s): cpu = 00:00:25 ; elapsed = 00:00:26 . Memory (MB): peak = 1776.121 ; gain = 697.066 ; free physical = 830 ; free virtual = 8280
Command: opt_design -directive Explore
INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
Running DRC as a precondition to command opt_design

Starting DRC Task
Command: report_drc (run_mandatory_drcs) for: opt_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1780.129 ; gain = 4.008 ; free physical = 824 ; free virtual = 8274
INFO: [Timing 38-35] Done setting XDC timing constraints.

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 2 inverter(s) to 2 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 17c8113d5

Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:00.30 . Memory (MB): peak = 1780.129 ; gain = 0.000 ; free physical = 824 ; free virtual = 8273
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 82 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 172ae8113

Time (s): cpu = 00:00:00.43 ; elapsed = 00:00:00.40 . Memory (MB): peak = 1780.129 ; gain = 0.000 ; free physical = 824 ; free virtual = 8273
INFO: [Opt 31-389] Phase Constant propagation created 10 cells and removed 25 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: fe6b18f6

Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.47 . Memory (MB): peak = 1780.129 ; gain = 0.000 ; free physical = 824 ; free virtual = 8273
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 59 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: fe6b18f6

Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.54 . Memory (MB): peak = 1780.129 ; gain = 0.000 ; free physical = 824 ; free virtual = 8273
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: fe6b18f6

Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.54 . Memory (MB): peak = 1780.129 ; gain = 0.000 ; free physical = 824 ; free virtual = 8273
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1780.129 ; gain = 0.000 ; free physical = 824 ; free virtual = 8273
Ending Logic Optimization Task | Checksum: fe6b18f6

Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.56 . Memory (MB): peak = 1780.129 ; gain = 0.000 ; free physical = 824 ; free virtual = 8273

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Power 33-23] Power model is not available for UA
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 2 BRAM(s) out of a total of 5 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 10
Ending PowerOpt Patch Enables Task | Checksum: 1c69e8f74

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 813 ; free virtual = 8263
Ending Power Optimization Task | Checksum: 1c69e8f74

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1940.598 ; gain = 160.469 ; free physical = 820 ; free virtual = 8269
30 Infos, 17 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.03 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 819 ; free virtual = 8270
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/impl_1/sys_tst_sram_c7_opt.dcp' has been generated.
Command: report_drc -file sys_tst_sram_c7_drc_opted.rpt
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/impl_1/sys_tst_sram_c7_drc_opted.rpt.
report_drc completed successfully
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
Command: report_drc (run_mandatory_drcs) for: incr_eco_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
Command: report_drc (run_mandatory_drcs) for: placer_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 46-5] The placer was invoked with the 'Explore' directive.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 810 ; free virtual = 8261
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: ee51da83

Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 810 ; free virtual = 8261
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 810 ; free virtual = 8260

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: a4539299

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 809 ; free virtual = 8259

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: b5f96040

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 804 ; free virtual = 8254

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: b5f96040

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 804 ; free virtual = 8254
Phase 1 Placer Initialization | Checksum: b5f96040

Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 804 ; free virtual = 8254

Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 1ddea0231

Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 798 ; free virtual = 8248

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1ddea0231

Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 798 ; free virtual = 8248

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 145b91496

Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 797 ; free virtual = 8247

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 146522829

Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 797 ; free virtual = 8247

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1525c5eb3

Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 797 ; free virtual = 8247

Phase 3.5 Timing Path Optimizer
Phase 3.5 Timing Path Optimizer | Checksum: 178bd9a85

Time (s): cpu = 00:00:07 ; elapsed = 00:00:05 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 797 ; free virtual = 8247

Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 11ebb979e

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 796 ; free virtual = 8246

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 1b754a5b3

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 796 ; free virtual = 8246

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: f8cfb316

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 796 ; free virtual = 8246
Phase 3 Detail Placement | Checksum: f8cfb316

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 796 ; free virtual = 8246

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1531724e4

Phase 4.1.1.1 BUFG Insertion
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
INFO: [Place 46-41] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
Phase 4.1.1.1 BUFG Insertion | Checksum: 1531724e4

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 794 ; free virtual = 8245
INFO: [Place 30-746] Post Placement Timing Summary WNS=1.941. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: ef495b5c

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 794 ; free virtual = 8245
Phase 4.1 Post Commit Optimization | Checksum: ef495b5c

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 794 ; free virtual = 8245

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: ef495b5c

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 795 ; free virtual = 8245

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: ef495b5c

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 795 ; free virtual = 8245

Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 1810e70ca

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 795 ; free virtual = 8245
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1810e70ca

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 795 ; free virtual = 8245
Ending Placer Task | Checksum: 11facb534

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 799 ; free virtual = 8249
50 Infos, 17 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 799 ; free virtual = 8249
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.31 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 795 ; free virtual = 8249
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/impl_1/sys_tst_sram_c7_placed.dcp' has been generated.
report_io: Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 793 ; free virtual = 8245
report_utilization: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 799 ; free virtual = 8250
report_control_sets: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 799 ; free virtual = 8250
Command: phys_opt_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.500 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
55 Infos, 17 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.31 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 793 ; free virtual = 8248
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/impl_1/sys_tst_sram_c7_physopt.dcp' has been generated.
Command: route_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t-cpg236'
Running DRC as a precondition to command route_design
Command: report_drc (run_mandatory_drcs) for: router_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-270] Using Router directive 'Explore'.
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 37057eb7 ConstDB: 0 ShapeSum: e8a7367d RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 1101f0951

Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 640 ; free virtual = 8093

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 1101f0951

Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 642 ; free virtual = 8095

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 1101f0951

Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 635 ; free virtual = 8087

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 1101f0951

Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 634 ; free virtual = 8087
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 1773b4e0c

Time (s): cpu = 00:00:27 ; elapsed = 00:00:24 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 624 ; free virtual = 8077
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.136  | TNS=0.000  | WHS=-0.246 | THS=-61.904|

Phase 2 Router Initialization | Checksum: 11c90f5cf

Time (s): cpu = 00:00:28 ; elapsed = 00:00:24 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 623 ; free virtual = 8076

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 1ca831d58

Time (s): cpu = 00:00:29 ; elapsed = 00:00:25 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 665 ; free virtual = 8117

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 258
 Number of Nodes with overlaps = 7
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.564  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 1434bf864

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 666 ; free virtual = 8119
Phase 4 Rip-up And Reroute | Checksum: 1434bf864

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 666 ; free virtual = 8119

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 14adbd971

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 666 ; free virtual = 8119
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.571  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 5.1 Delay CleanUp | Checksum: 14adbd971

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 666 ; free virtual = 8119

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 14adbd971

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 666 ; free virtual = 8119
Phase 5 Delay and Skew Optimization | Checksum: 14adbd971

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 666 ; free virtual = 8119

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 145f0f84d

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 667 ; free virtual = 8120
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.571  | TNS=0.000  | WHS=0.079  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 1010d7c0a

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 667 ; free virtual = 8120
Phase 6 Post Hold Fix | Checksum: 1010d7c0a

Time (s): cpu = 00:00:31 ; elapsed = 00:00:26 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 667 ; free virtual = 8120

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.826437 %
  Global Horizontal Routing Utilization  = 0.754555 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 10d921b8d

Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 667 ; free virtual = 8120

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 10d921b8d

Time (s): cpu = 00:00:31 ; elapsed = 00:00:27 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 666 ; free virtual = 8120

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 1990d0cc7

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 666 ; free virtual = 8120

Phase 10 Post Router Timing
INFO: [Route 35-20] Post Routing Timing Summary | WNS=2.577  | TNS=0.000  | WHS=0.080  | THS=0.000  |

INFO: [Route 35-61] The design met the timing requirement.
Phase 10 Post Router Timing | Checksum: 17e70370b

Time (s): cpu = 00:00:33 ; elapsed = 00:00:28 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 669 ; free virtual = 8122
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:33 ; elapsed = 00:00:28 . Memory (MB): peak = 1940.598 ; gain = 0.000 ; free physical = 731 ; free virtual = 8185

Routing Is Done.
69 Infos, 17 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:30 . Memory (MB): peak = 1974.551 ; gain = 33.953 ; free physical = 731 ; free virtual = 8185
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.38 . Memory (MB): peak = 1974.551 ; gain = 0.000 ; free physical = 727 ; free virtual = 8185
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/impl_1/sys_tst_sram_c7_routed.dcp' has been generated.
Command: report_drc -file sys_tst_sram_c7_drc_routed.rpt -pb sys_tst_sram_c7_drc_routed.pb -rpx sys_tst_sram_c7_drc_routed.rpx
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/impl_1/sys_tst_sram_c7_drc_routed.rpt.
report_drc completed successfully
Command: report_methodology -file sys_tst_sram_c7_methodology_drc_routed.rpt -rpx sys_tst_sram_c7_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/impl_1/sys_tst_sram_c7_methodology_drc_routed.rpt.
report_methodology completed successfully
Command: report_power -file sys_tst_sram_c7_power_routed.rpt -pb sys_tst_sram_c7_power_summary_routed.pb -rpx sys_tst_sram_c7_power_routed.rpx
INFO: [Power 33-23] Power model is not available for UA
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
77 Infos, 17 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Sun Aug 26 13:29:04 2018...
