Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017
| Date         : Sun Aug 26 13:28:22 2018
| Host         : athome running 64-bit Ubuntu 16.04.5 LTS
| Command      : report_control_sets -verbose -file sys_tst_sram_c7_control_sets_placed.rpt
| Design       : sys_tst_sram_c7
| Device       : xc7a35t
--------------------------------------------------------------------------------------------

Control Set Information

Table of Contents
-----------------
1. Summary
2. Flip-Flop Distribution
3. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets                            |    79 |
| Unused register locations in slices containing registers |   198 |
+----------------------------------------------------------+-------+


2. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |             237 |          105 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |              39 |           24 |
| Yes          | No                    | No                     |             282 |          110 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |             484 |          168 |
+--------------+-----------------------+------------------------+-----------------+--------------+


3. Detailed Control Set Information
-----------------------------------

+-------------------+----------------------------------------------------------------+-------------------------------------------------------------+------------------+----------------+
|    Clock Signal   |                          Enable Signal                         |                       Set/Reset Signal                      | Slice Load Count | Bel Load Count |
+-------------------+----------------------------------------------------------------+-------------------------------------------------------------+------------------+----------------+
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/out[0]                                           |                                                             |                1 |              1 |
|  GEN_CLKSER/CLKFX |                                                                | RLINK/SERPORT/RXFIFO/RW_SIZEW0                              |                1 |              2 |
|  GEN_CLKSER/CLKFX | RLINK/SERPORT/XONTX/n[oval]12_out                              | RLINK/SERPORT/UART/AB/SR[0]                                 |                1 |              4 |
|  GEN_CLKSER/CLKFX | RLINK/SERPORT/UART/RXTX/TX/n[sreg]                             | RLINK/SERPORT/UART/RXTX/TX/R_REGS[bcnt][3]_i_1__0_n_0       |                2 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][5]     | RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][29] |                3 |              4 |
|  GEN_CLKSYS/CLKFX |                                                                | TST/SMEM_B3/SR[0]                                           |                2 |              4 |
|  GEN_CLKSER/CLKFX | RLINK/SERPORT/UART/RXTX/RX/R_REGS[bcnt][3]_i_2_n_0             | RLINK/SERPORT/UART/RXTX/RX/R_REGS[bcnt][3]_i_1_n_0          |                2 |              4 |
|  GEN_CLKSER/CLKFX | RLINK/SERPORT/UART/AB/FSM_onehot_R_REGS[state][3]_i_1_n_0      | RLINK/SERPORT/CDC_RESET/RS_REQ_S1                           |                1 |              4 |
|  GEN_CLKSYS/CLKFX | SRAMCTL/n[addrb]                                               | RLINK/CORE/RL/SR[0]                                         |                2 |              4 |
|  GEN_CLKSYS/CLKFX | SMRB/SMRB/FSM_onehot_R_REGS[state][3]_i_1__3_n_0               |                                                             |                2 |              4 |
|  GEN_CLKSER/CLKFX | RLINK/SERPORT/TXFIFO/GCR/GRAY_5.CNT/E[0]                       | RLINK/SERPORT/TXFIFO/GCR/GRAY_5.CNT/GCR_RST                 |                2 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/N_REGS[empty]                        |                                                             |                2 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/E[0]                       | RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/GCW_RST                 |                2 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/E[0]                       | RLINK/SERPORT/RXFIFO/GCR/GRAY_5.CNT/GCR_RST                 |                2 |              5 |
|  GEN_CLKSER/CLKFX | RLINK/SERPORT/RXFIFO/GCW/GRAY_5.CNT/E[0]                       | RLINK/SERPORT/RXFIFO/GCW/GRAY_5.CNT/GCW_RST                 |                2 |              5 |
|  GEN_CLKSYS/CLKFX | SRAMCTL/FSM_onehot_R_REGS[state][4]_i_1__1_n_0                 | RLINK/CORE/RL/SR[0]                                         |                2 |              5 |
|  GEN_CLKSYS/CLKFX |                                                                | HIO/R_REGS[btn][4]_i_1_n_0                                  |                4 |              5 |
|  GEN_CLKSYS/CLKFX |                                                                | RLINK/CORE/RL/SR[0]                                         |                3 |              5 |
|  GEN_CLKSYS/CLKFX |                                                                | RLINK/CORE/RL/R_BREGS[btocnt][5]_i_1_n_0                    |                2 |              6 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[sveri]                                         | RLINK/CORE/RL/R_REGS_reg[rbsel]_0[0]                        |                1 |              6 |
|  GEN_CLKSER/CLKFX | RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_2_n_0 | RLINK/SERPORT/UART/AB/in1                                   |                4 |              7 |
|  GEN_CLKSER/CLKFX | RLINK/SERPORT/UART/AB/n[mcnt]                                  | RLINK/SERPORT/CDC_RESET/RS_REQ_S1                           |                3 |              7 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][5]     | RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][12] |                2 |              7 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[cnt][7]_i_2_n_0                          | RLINK/CORE/RL/R_LREGS[cnt][7]_i_1_n_0                       |                2 |              7 |
|  GEN_CLKSYS/CLKFX | SRAMCTL/n[memdo][15]                                           | RLINK/CORE/RL/SR[0]                                         |                3 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[atocnt][7]_i_1_n_0                       |                                                             |                4 |              8 |
|  GEN_CLKSYS/CLKFX | SRAMCTL/n[memdo][23]                                           | RLINK/CORE/RL/SR[0]                                         |                2 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state_n_0_][4]            |                                                             |                2 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[din][7]_i_1_n_0                          |                                                             |                3 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/out[1]                                           |                                                             |                3 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[din][15]_i_1_n_0                         |                                                             |                3 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[cnt][15]_i_2_n_0                         | RLINK/CORE/RL/R_LREGS[cnt][15]_i_1_n_0                      |                2 |              8 |
|  GEN_CLKSER/CLKFX | RLINK/SERPORT/UART/RXTX/RX/n[sreg]                             |                                                             |                2 |              8 |
|  GEN_CLKSER/CLKFX | RLINK/SERPORT/UART/RXTX/RX/E[0]                                | RLINK/SERPORT/UART/AB/in1                                   |                1 |              8 |
|  GEN_CLKSER/CLKFX | RLINK/SERPORT/UART/RXTX/TX/R_REGS[sreg][7]_i_1_n_0             |                                                             |                3 |              8 |
|  GEN_CLKSYS/CLKFX |                                                                | RLINK/CORE/RL/R_REGS_reg[rbsel]_0[0]                        |                7 |              8 |
|  GEN_CLKSER/CLKFX | RLINK/SERPORT/XONTX/R_REGS_reg[ibuf]0                          | RLINK/SERPORT/UART/AB/in1                                   |                2 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state_n_0_][5]            |                                                             |                1 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[lcmd][7]_i_1_n_0                         |                                                             |                2 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/n[dinl]                              |                                                             |                1 |              8 |
|  GEN_CLKSYS/CLKFX | SRAMCTL/n[memdo][7]                                            | RLINK/CORE/RL/SR[0]                                         |                3 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/CD2B/R_REGS[data][7]_i_1__0_n_0                     |                                                             |                4 |              9 |
|  GEN_CLKSER/CLKFX |                                                                | RLINK/SERPORT/UART/AB/in1                                   |                5 |              9 |
|  GEN_CLKSYS/CLKFX | CLKDIV_CLK/n[mcnt]                                             |                                                             |                4 |             10 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dataval][0]                           |                                                             |                3 |             10 |
|  GEN_CLKSER/CLKFX | CLKDIV_CLKS/n[mcnt]                                            |                                                             |                4 |             10 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/SEL__0/n[anena]                                  |                                                             |                4 |             10 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_BREGS[cnt][10]_i_1_n_0                         |                                                             |                5 |             11 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/E[0]                                             | RLINK/CORE/RL/R_REGS_reg[rbsel]_0[0]                        |                4 |             11 |
|  GEN_CLKSYS/CLKFX | TST/sel                                                        | RLINK/CORE/RL/R_REGS_reg[rbsel]_0[0]                        |                7 |             11 |
|  GEN_CLKSYS/CLKFX | TST/SMEM_B0/R_REGS_reg[scaddr][10]                             | RLINK/CORE/RL/R_REGS_reg[rbsel]_0[0]                        |                3 |             11 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_BREGS[dcnt][10]_i_2_n_0                        | RLINK/CORE/RL/dcnt_clear                                    |                4 |             11 |
|  GEN_CLKSYS/CLKFX | SMRB/SMRB/n[temp]                                              |                                                             |                4 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS_reg[bcnt][0]                 |                                                             |                3 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS_reg[rtaddra][0]              | RLINK/CORE/RL/addra_clear                                   |                3 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2_n_0                      | RLINK/CORE/B2CD/n[rtaddrb_red]17_out                        |                3 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/FSM_onehot_R_BREGS[state][12]_i_1_n_0            |                                                             |                7 |             13 |
|  GEN_CLKSYS/CLKFX | TST/FSM_onehot_R_REGS[state][12]_i_2_n_0                       | RLINK/CORE/RL/R_REGS_reg[rbsel]_0[0]                        |                7 |             13 |
|  GEN_CLKSER/CLKFX | RLINK/SERPORT/UART/RXTX/RX/R_REGS[dcnt][0]_i_1_n_0             |                                                             |                4 |             13 |
|  GEN_CLKSER/CLKFX | RLINK/SERPORT/UART/AB/n[ccnt]                                  | RLINK/SERPORT/CDC_RESET/RS_REQ_S1                           |                5 |             15 |
|  GEN_CLKSYS/CLKFX | SMRB/SM_EOS                                                    |                                                             |                4 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[swi]                                           |                                                             |                5 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[rbdout]                                        |                                                             |                7 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[maddr][0][0]                          | RLINK/CORE/RL/R_REGS_reg[rbsel]_0[0]                        |                7 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/ICRC/icrcena                                     | RLINK/CORE/RL/out[0]                                        |                6 |             16 |
|  GEN_CLKSER/CLKFX | RLINK/SERPORT/RXFIFO/GCW/GRAY_5.CNT/E[0]                       |                                                             |                2 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dispval][0]                           | RLINK/CORE/RL/R_REGS_reg[rbsel]_0[0]                        |                5 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[mdi][24][0]                           | RLINK/CORE/RL/R_REGS_reg[rbsel]_0[0]                        |                6 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[mdi][24][1]                           | RLINK/CORE/RL/R_REGS_reg[rbsel]_0[0]                        |                5 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/E[0]                                 | RLINK/CORE/RL/out[0]                                        |                4 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/TXFIFO/GCW/GRAY_5.CNT/E[0]                       |                                                             |                2 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/RAM/N_REGS[full]                     |                                                             |                4 |             21 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/FSM_onehot_R_LREGS_reg[state][5]     |                                                             |               21 |             29 |
|  GEN_CLKSYS/CLKFX | TST/SMEM_B3/R_REGS_reg[memdi][31]_0[0]                         | RLINK/CORE/RL/SR[0]                                         |               14 |             32 |
|  GEN_CLKSYS/CLKFX | TST/R_REGS[se_addr][10]_i_1_n_0                                | RLINK/CORE/RL/R_REGS_reg[rbsel]_0[0]                        |               19 |             43 |
|  GEN_CLKSYS/CLKFX | SRAMCTL/E[0]                                                   | RLINK/CORE/RL/R_REGS_reg[rbsel]_0[0]                        |                9 |             43 |
|  GEN_CLKSYS/CLKFX | TST/SMEM_B3/E[0]                                               | RLINK/CORE/RL/R_REGS_reg[rbsel]_0[0]                        |               11 |             43 |
|  GEN_CLKSER/CLKFX |                                                                |                                                             |               28 |             74 |
|  GEN_CLKSYS/CLKFX |                                                                |                                                             |               77 |            163 |
+-------------------+----------------------------------------------------------------+-------------------------------------------------------------+------------------+----------------+


+--------+-----------------------+
| Fanout | Number of ControlSets |
+--------+-----------------------+
| 1      |                     1 |
| 2      |                     1 |
| 4      |                     8 |
| 5      |                     8 |
| 6      |                     2 |
| 7      |                     4 |
| 8      |                    17 |
| 9      |                     2 |
| 10     |                     4 |
| 11     |                     5 |
| 12     |                     4 |
| 13     |                     3 |
| 15     |                     1 |
| 16+    |                    19 |
+--------+-----------------------+


