
*** Running vivado
    with args -log sys_tst_sram_c7.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source sys_tst_sram_c7.tcl


****** Vivado v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source sys_tst_sram_c7.tcl -notrace
Command: synth_design -top sys_tst_sram_c7 -part xc7a35tcpg236-1 -fanout_limit 400 -fsm_extraction one_hot -keep_equivalent_registers -resource_sharing off -no_lc -shreg_min_size 5 -assert
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t-cpg236'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t-cpg236'
INFO: Launching helper process for spawning children vivado processes
INFO: Helper process launched with PID 6422 
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1131.637 ; gain = 39.949 ; free physical = 1454 ; free virtual = 8878
---------------------------------------------------------------------------------
INFO: [Synth 8-638] synthesizing module 'sys_tst_sram_c7' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:80]
	Parameter VCO_DIVIDE bound to: 1 - type: integer 
	Parameter VCO_MULTIPLY bound to: 60 - type: integer 
	Parameter OUT_DIVIDE bound to: 9 - type: integer 
	Parameter CLKIN_PERIOD bound to: 83.300000 - type: float 
	Parameter CLKIN_JITTER bound to: 0.010000 - type: float 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
	Parameter GEN_TYPE bound to: MMCM - type: string 
INFO: [Synth 8-3491] module 's7_cmt_sfs' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:37' bound to instance 'GEN_CLKSYS' of component 's7_cmt_sfs' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:138]
INFO: [Synth 8-638] synthesizing module 's7_cmt_sfs' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:54]
	Parameter VCO_DIVIDE bound to: 1 - type: integer 
	Parameter VCO_MULTIPLY bound to: 60 - type: integer 
	Parameter OUT_DIVIDE bound to: 9 - type: integer 
	Parameter CLKIN_PERIOD bound to: 83.300000 - type: float 
	Parameter CLKIN_JITTER bound to: 0.010000 - type: float 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
	Parameter GEN_TYPE bound to: MMCM - type: string 
	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
	Parameter CLKFBOUT_MULT_F bound to: 60.000000 - type: float 
	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 
	Parameter CLKIN1_PERIOD bound to: 83.300000 - type: float 
	Parameter CLKOUT0_DIVIDE_F bound to: 9.000000 - type: float 
	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT4_CASCADE bound to: 0 - type: bool 
	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float 
	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
	Parameter REF_JITTER1 bound to: 0.010000 - type: float 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
INFO: [Synth 8-113] binding component instance 'MMCM' to cell 'MMCME2_BASE' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:152]
INFO: [Synth 8-113] binding component instance 'BUFG_CLKFB' to cell 'BUFG' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:184]
INFO: [Synth 8-113] binding component instance 'BUFG_CLKOUT' to cell 'BUFG' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:190]
INFO: [Synth 8-256] done synthesizing module 's7_cmt_sfs' (1#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:54]
	Parameter CDUWIDTH bound to: 7 - type: integer 
	Parameter USECDIV bound to: 80 - type: integer 
	Parameter MSECDIV bound to: 1000 - type: integer 
INFO: [Synth 8-3491] module 'clkdivce' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:39' bound to instance 'CLKDIV_CLK' of component 'clkdivce' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:153]
INFO: [Synth 8-638] synthesizing module 'clkdivce' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:52]
	Parameter CDUWIDTH bound to: 7 - type: integer 
	Parameter USECDIV bound to: 80 - type: integer 
	Parameter MSECDIV bound to: 1000 - type: integer 
WARNING: [Synth 8-6014] Unused sequential element r_reg[ucnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element r_reg[mcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element r_reg[usec] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element r_reg[msec] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element n_reg[ucnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:94]
WARNING: [Synth 8-6014] Unused sequential element n_reg[mcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:94]
WARNING: [Synth 8-6014] Unused sequential element n_reg[usec] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:94]
WARNING: [Synth 8-6014] Unused sequential element n_reg[msec] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:94]
INFO: [Synth 8-256] done synthesizing module 'clkdivce' (2#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:52]
	Parameter VCO_DIVIDE bound to: 1 - type: integer 
	Parameter VCO_MULTIPLY bound to: 60 - type: integer 
	Parameter OUT_DIVIDE bound to: 6 - type: integer 
	Parameter CLKIN_PERIOD bound to: 83.300000 - type: float 
	Parameter CLKIN_JITTER bound to: 0.010000 - type: float 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
	Parameter GEN_TYPE bound to: MMCM - type: string 
INFO: [Synth 8-3491] module 's7_cmt_sfs' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:37' bound to instance 'GEN_CLKSER' of component 's7_cmt_sfs' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:164]
INFO: [Synth 8-638] synthesizing module 's7_cmt_sfs__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:54]
	Parameter VCO_DIVIDE bound to: 1 - type: integer 
	Parameter VCO_MULTIPLY bound to: 60 - type: integer 
	Parameter OUT_DIVIDE bound to: 6 - type: integer 
	Parameter CLKIN_PERIOD bound to: 83.300000 - type: float 
	Parameter CLKIN_JITTER bound to: 0.010000 - type: float 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
	Parameter GEN_TYPE bound to: MMCM - type: string 
	Parameter BANDWIDTH bound to: OPTIMIZED - type: string 
	Parameter CLKFBOUT_MULT_F bound to: 60.000000 - type: float 
	Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float 
	Parameter CLKIN1_PERIOD bound to: 83.300000 - type: float 
	Parameter CLKOUT0_DIVIDE_F bound to: 6.000000 - type: float 
	Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT1_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT2_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT3_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT4_CASCADE bound to: 0 - type: bool 
	Parameter CLKOUT4_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT5_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float 
	Parameter CLKOUT6_DIVIDE bound to: 1 - type: integer 
	Parameter CLKOUT6_DUTY_CYCLE bound to: 0.500000 - type: float 
	Parameter CLKOUT6_PHASE bound to: 0.000000 - type: float 
	Parameter DIVCLK_DIVIDE bound to: 1 - type: integer 
	Parameter REF_JITTER1 bound to: 0.010000 - type: float 
	Parameter STARTUP_WAIT bound to: 0 - type: bool 
INFO: [Synth 8-113] binding component instance 'MMCM' to cell 'MMCME2_BASE' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:152]
INFO: [Synth 8-113] binding component instance 'BUFG_CLKFB' to cell 'BUFG' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:184]
INFO: [Synth 8-113] binding component instance 'BUFG_CLKOUT' to cell 'BUFG' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:190]
INFO: [Synth 8-256] done synthesizing module 's7_cmt_sfs__parameterized1' (2#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/s7_cmt_sfs_unisim.vhd:54]
	Parameter CDUWIDTH bound to: 7 - type: integer 
	Parameter USECDIV bound to: 120 - type: integer 
	Parameter MSECDIV bound to: 1000 - type: integer 
INFO: [Synth 8-3491] module 'clkdivce' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:39' bound to instance 'CLKDIV_CLKS' of component 'clkdivce' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:179]
INFO: [Synth 8-638] synthesizing module 'clkdivce__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:52]
	Parameter CDUWIDTH bound to: 7 - type: integer 
	Parameter USECDIV bound to: 120 - type: integer 
	Parameter MSECDIV bound to: 1000 - type: integer 
WARNING: [Synth 8-6014] Unused sequential element r_reg[ucnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element r_reg[mcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element r_reg[usec] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element r_reg[msec] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:93]
WARNING: [Synth 8-6014] Unused sequential element n_reg[ucnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:94]
WARNING: [Synth 8-6014] Unused sequential element n_reg[mcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:94]
WARNING: [Synth 8-6014] Unused sequential element n_reg[usec] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:94]
WARNING: [Synth 8-6014] Unused sequential element n_reg[msec] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:94]
INFO: [Synth 8-256] done synthesizing module 'clkdivce__parameterized1' (2#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/clkdivce.vhd:52]
INFO: [Synth 8-3491] module 'bp_rs232_2line_iob' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd:41' bound to instance 'IOB_RS232' of component 'bp_rs232_2line_iob' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:190]
INFO: [Synth 8-638] synthesizing module 'bp_rs232_2line_iob' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd:51]
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-3491] module 'iob_reg_i' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_i.vhd:34' bound to instance 'IOB_RXD' of component 'iob_reg_i' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd:54]
INFO: [Synth 8-638] synthesizing module 'iob_reg_i' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_i.vhd:46]
	Parameter INIT bound to: 1'b1 
	Parameter DWIDTH bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-3491] module 'iob_reg_i_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:34' bound to instance 'IOB' of component 'iob_reg_i_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_i.vhd:50]
INFO: [Synth 8-638] synthesizing module 'iob_reg_i_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:47]
	Parameter DWIDTH bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'iob_reg_i_gen' (3#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_i_gen.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'iob_reg_i' (4#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_i.vhd:46]
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-3491] module 'iob_reg_o' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o.vhd:34' bound to instance 'IOB_TXD' of component 'iob_reg_o' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd:58]
INFO: [Synth 8-638] synthesizing module 'iob_reg_o' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o.vhd:46]
	Parameter INIT bound to: 1'b1 
	Parameter DWIDTH bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-3491] module 'iob_reg_o_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:34' bound to instance 'IOB' of component 'iob_reg_o_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o.vhd:50]
INFO: [Synth 8-638] synthesizing module 'iob_reg_o_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:47]
	Parameter DWIDTH bound to: 1 - type: integer 
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'iob_reg_o_gen' (5#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'iob_reg_o' (6#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o.vhd:46]
INFO: [Synth 8-256] done synthesizing module 'bp_rs232_2line_iob' (7#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd:51]
	Parameter BTOWIDTH bound to: 6 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 32'b00000001000001000000100100000000 
	Parameter IFAWIDTH bound to: 5 - type: integer 
	Parameter OFAWIDTH bound to: 5 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RLBMON bound to: -1 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
	Parameter RBMON_AWIDTH bound to: 0 - type: integer 
	Parameter RBMON_RBADDR bound to: 16'b1111111111101000 
INFO: [Synth 8-3491] module 'rlink_sp2c' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_sp2c.vhd:43' bound to instance 'RLINK' of component 'rlink_sp2c' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:199]
INFO: [Synth 8-638] synthesizing module 'rlink_sp2c' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_sp2c.vhd:81]
	Parameter BTOWIDTH bound to: 6 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 17041664 - type: integer 
	Parameter IFAWIDTH bound to: 5 - type: integer 
	Parameter OFAWIDTH bound to: 5 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RLBMON bound to: -1 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
	Parameter RBMON_AWIDTH bound to: 0 - type: integer 
	Parameter RBMON_RBADDR bound to: 16'b1111111111101000 
	Parameter BTOWIDTH bound to: 6 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 17041664 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RLBMON bound to: -1 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
INFO: [Synth 8-3491] module 'rlink_core8' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core8.vhd:49' bound to instance 'CORE' of component 'rlink_core8' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_sp2c.vhd:96]
INFO: [Synth 8-638] synthesizing module 'rlink_core8' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core8.vhd:78]
	Parameter BTOWIDTH bound to: 6 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 17041664 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RLBMON bound to: -1 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
	Parameter BTOWIDTH bound to: 6 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 17041664 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
INFO: [Synth 8-3491] module 'rlink_core' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:165' bound to instance 'RL' of component 'rlink_core' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core8.vhd:92]
INFO: [Synth 8-638] synthesizing module 'rlink_core' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:194]
	Parameter BTOWIDTH bound to: 6 - type: integer 
	Parameter RTAWIDTH bound to: 12 - type: integer 
	Parameter SYSID bound to: 17041664 - type: integer 
	Parameter ENAPIN_RLMON bound to: 15 - type: integer 
	Parameter ENAPIN_RBMON bound to: 13 - type: integer 
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_2swsr_rfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:42' bound to instance 'RTBUF' of component 'ram_2swsr_rfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:447]
INFO: [Synth 8-638] synthesizing module 'ram_2swsr_rfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:63]
	Parameter AWIDTH bound to: 12 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* ram_style = "block" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:67]
INFO: [Synth 8-256] done synthesizing module 'ram_2swsr_rfirst_gen' (8#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_2swsr_rfirst_gen.vhd:63]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'fifo_1c_dram' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram.vhd:43' bound to instance 'DOFIFO' of component 'fifo_1c_dram' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:466]
INFO: [Synth 8-638] synthesizing module 'fifo_1c_dram' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram.vhd:61]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'fifo_1c_dram_raw' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:38' bound to instance 'FIFO' of component 'fifo_1c_dram_raw' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram.vhd:71]
INFO: [Synth 8-638] synthesizing module 'fifo_1c_dram_raw' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:56]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_1ar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:50' bound to instance 'RAM' of component 'ram_1swar_1ar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:79]
INFO: [Synth 8-638] synthesizing module 'ram_1swar_1ar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:66]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* ram_style = "distributed" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:70]
INFO: [Synth 8-256] done synthesizing module 'ram_1swar_1ar_gen' (9#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:66]
WARNING: [Synth 8-6014] Unused sequential element r_reg[waddr] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:115]
WARNING: [Synth 8-6014] Unused sequential element r_reg[raddr] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:115]
WARNING: [Synth 8-6014] Unused sequential element r_reg[empty] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:115]
WARNING: [Synth 8-6014] Unused sequential element r_reg[full] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:115]
WARNING: [Synth 8-6014] Unused sequential element n_reg[waddr] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:116]
WARNING: [Synth 8-6014] Unused sequential element n_reg[raddr] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:116]
WARNING: [Synth 8-6014] Unused sequential element n_reg[empty] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:116]
WARNING: [Synth 8-6014] Unused sequential element n_reg[full] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:116]
WARNING: [Synth 8-6014] Unused sequential element re_val_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:118]
WARNING: [Synth 8-6014] Unused sequential element we_val_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:119]
WARNING: [Synth 8-6014] Unused sequential element isize_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:120]
WARNING: [Synth 8-6014] Unused sequential element iram_we_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:121]
INFO: [Synth 8-256] done synthesizing module 'fifo_1c_dram_raw' (10#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram_raw.vhd:56]
INFO: [Synth 8-256] done synthesizing module 'fifo_1c_dram' (11#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_1c_dram.vhd:61]
	Parameter INIT bound to: 16'b0000000000000000 
INFO: [Synth 8-3491] module 'crc16' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/comlib/crc16.vhd:40' bound to instance 'ICRC' of component 'crc16' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:482]
INFO: [Synth 8-638] synthesizing module 'crc16' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/comlib/crc16.vhd:53]
	Parameter INIT bound to: 16'b0000000000000000 
INFO: [Synth 8-256] done synthesizing module 'crc16' (12#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/comlib/crc16.vhd:53]
	Parameter INIT bound to: 16'b0000000000000000 
INFO: [Synth 8-3491] module 'crc16' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/comlib/crc16.vhd:40' bound to instance 'OCRC' of component 'crc16' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:491]
	Parameter RB_ADDR bound to: 16'b1111111111111100 
	Parameter SAWIDTH bound to: 2 - type: integer 
INFO: [Synth 8-3491] module 'rb_sel' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rb_sel.vhd:38' bound to instance 'SEL' of component 'rb_sel' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:500]
INFO: [Synth 8-638] synthesizing module 'rb_sel' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rb_sel.vhd:49]
	Parameter RB_ADDR bound to: 16'b1111111111111100 
	Parameter SAWIDTH bound to: 2 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'rb_sel' (13#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rb_sel.vhd:49]
INFO: [Synth 8-3491] module 'rb_sres_or_2' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rb_sres_or_2.vhd:39' bound to instance 'RB_SRES_OR' of component 'rb_sres_or_2' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:510]
INFO: [Synth 8-638] synthesizing module 'rb_sres_or_2' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rb_sres_or_2.vhd:47]
INFO: [Synth 8-256] done synthesizing module 'rb_sres_or_2' (14#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rb_sres_or_2.vhd:47]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:1402]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:1623]
WARNING: [Synth 8-6014] Unused sequential element datax01_reg was removed. 
WARNING: [Synth 8-6014] Unused sequential element data01_reg was removed. 
WARNING: [Synth 8-6014] Unused sequential element sres_reg[ack] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:522]
WARNING: [Synth 8-6014] Unused sequential element sres_reg[busy] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:522]
WARNING: [Synth 8-6014] Unused sequential element sres_reg[err] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:522]
WARNING: [Synth 8-6014] Unused sequential element sres_reg[dout] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:522]
WARNING: [Synth 8-6014] Unused sequential element r_reg[state] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rcmd] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[lcmd] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[addr] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[din] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[cnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[bcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[attn] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[anreq] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[anact] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[arpend] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[atocnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[babo] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[nakdone] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[nakcode] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[cmdseen] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[doretra] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[dinl] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rtaddra] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rtaddra_red] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rtaddra_bad] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rtaddra_zero] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rtaddrb] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rtaddrb_red] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[rtaddrb_bad] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[moneop] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element r_reg[monattn] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:591]
WARNING: [Synth 8-6014] Unused sequential element n_reg[state] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rcmd] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[lcmd] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[addr] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[din] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[cnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[bcnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[attn] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[anreq] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[anact] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[arpend] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[atocnt] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[babo] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[nakdone] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[nakcode] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[cmdseen] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[doretra] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[dinl] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rtaddra] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rtaddra_red] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rtaddra_bad] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rtaddra_zero] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rtaddrb] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rtaddrb_red] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[rtaddrb_bad] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[moneop] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element n_reg[monattn] was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:592]
WARNING: [Synth 8-6014] Unused sequential element ival_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:597]
WARNING: [Synth 8-6014] Unused sequential element ibusy_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:598]
WARNING: [Synth 8-6014] Unused sequential element ido_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:599]
WARNING: [Synth 8-6014] Unused sequential element crcreset_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:601]
WARNING: [Synth 8-6014] Unused sequential element icrcena_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:602]
WARNING: [Synth 8-6014] Unused sequential element ocrcena_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:603]
WARNING: [Synth 8-6014] Unused sequential element has_attn_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:605]
WARNING: [Synth 8-6014] Unused sequential element is_comma_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:607]
WARNING: [Synth 8-6014] Unused sequential element comma_typ_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:608]
WARNING: [Synth 8-6014] Unused sequential element idi8_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:609]
WARNING: [Synth 8-6014] Unused sequential element idohold_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:611]
WARNING: [Synth 8-6014] Unused sequential element cnt_iszero_reg was removed.  [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:613]
INFO: [Common 17-14] Message 'Synth 8-6014' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
INFO: [Synth 8-256] done synthesizing module 'rlink_core' (15#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core.vhd:194]
INFO: [Synth 8-3491] module 'byte2cdata' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/comlib/byte2cdata.vhd:38' bound to instance 'B2CD' of component 'byte2cdata' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core8.vhd:117]
INFO: [Synth 8-638] synthesizing module 'byte2cdata' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/comlib/byte2cdata.vhd:53]
INFO: [Synth 8-256] done synthesizing module 'byte2cdata' (16#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/comlib/byte2cdata.vhd:53]
INFO: [Synth 8-3491] module 'cdata2byte' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/comlib/cdata2byte.vhd:38' bound to instance 'CD2B' of component 'cdata2byte' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core8.vhd:131]
INFO: [Synth 8-638] synthesizing module 'cdata2byte' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/comlib/cdata2byte.vhd:54]
INFO: [Synth 8-256] done synthesizing module 'cdata2byte' (17#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/comlib/cdata2byte.vhd:54]
INFO: [Synth 8-256] done synthesizing module 'rlink_core8' (18#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_core8.vhd:78]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
	Parameter RXFAWIDTH bound to: 5 - type: integer 
	Parameter TXFAWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'serport_2clock2' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:47' bound to instance 'SERPORT' of component 'serport_2clock2' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_sp2c.vhd:123]
INFO: [Synth 8-638] synthesizing module 'serport_2clock2' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:75]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
	Parameter RXFAWIDTH bound to: 5 - type: integer 
	Parameter TXFAWIDTH bound to: 5 - type: integer 
	Parameter POUT_SINGLE bound to: 0 - type: bool 
	Parameter BUSY_WACK bound to: 0 - type: bool 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_pulse' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.vhd:35' bound to instance 'CDC_RESET' of component 'cdc_pulse' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:135]
INFO: [Synth 8-638] synthesizing module 'cdc_pulse' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.vhd:51]
	Parameter POUT_SINGLE bound to: 0 - type: bool 
	Parameter BUSY_WACK bound to: 0 - type: bool 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.vhd:54]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.vhd:55]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.vhd:56]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.vhd:57]
INFO: [Synth 8-256] done synthesizing module 'cdc_pulse' (19#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.vhd:51]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_signal_s1' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:34' bound to instance 'CDC_ENAXON' of component 'cdc_signal_s1' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:148]
INFO: [Synth 8-638] synthesizing module 'cdc_signal_s1' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:45]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:47]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:48]
INFO: [Synth 8-256] done synthesizing module 'cdc_signal_s1' (20#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:45]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_signal_s1' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:34' bound to instance 'CDC_ENAESC' of component 'cdc_signal_s1' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:150]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
INFO: [Synth 8-3491] module 'serport_uart_rxtx_ab' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_rxtx_ab.vhd:47' bound to instance 'UART' of component 'serport_uart_rxtx_ab' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:153]
INFO: [Synth 8-638] synthesizing module 'serport_uart_rxtx_ab' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_rxtx_ab.vhd:71]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
INFO: [Synth 8-3491] module 'serport_uart_autobaud' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:42' bound to instance 'AB' of component 'serport_uart_autobaud' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_rxtx_ab.vhd:80]
INFO: [Synth 8-638] synthesizing module 'serport_uart_autobaud' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:59]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDINIT bound to: 1040 - type: integer 
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:133]
INFO: [Synth 8-256] done synthesizing module 'serport_uart_autobaud' (21#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_autobaud.vhd:59]
	Parameter CDWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-3491] module 'serport_uart_rxtx' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_rxtx.vhd:38' bound to instance 'RXTX' of component 'serport_uart_rxtx' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_rxtx_ab.vhd:100]
INFO: [Synth 8-638] synthesizing module 'serport_uart_rxtx' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_rxtx.vhd:57]
	Parameter CDWIDTH bound to: 12 - type: integer 
	Parameter CDWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-3491] module 'serport_uart_rx' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_rx.vhd:55' bound to instance 'RX' of component 'serport_uart_rx' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_rxtx.vhd:61]
INFO: [Synth 8-638] synthesizing module 'serport_uart_rx' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_rx.vhd:71]
	Parameter CDWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'serport_uart_rx' (22#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_rx.vhd:71]
	Parameter CDWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-3491] module 'serport_uart_tx' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_tx.vhd:40' bound to instance 'TX' of component 'serport_uart_tx' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_rxtx.vhd:75]
INFO: [Synth 8-638] synthesizing module 'serport_uart_tx' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_tx.vhd:55]
	Parameter CDWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'serport_uart_tx' (23#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_tx.vhd:55]
INFO: [Synth 8-256] done synthesizing module 'serport_uart_rxtx' (24#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_rxtx.vhd:57]
INFO: [Synth 8-256] done synthesizing module 'serport_uart_rxtx_ab' (25#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_uart_rxtx_ab.vhd:71]
INFO: [Synth 8-3491] module 'serport_xonrx' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_xonrx.vhd:37' bound to instance 'XONRX' of component 'serport_xonrx' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:178]
INFO: [Synth 8-638] synthesizing module 'serport_xonrx' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_xonrx.vhd:54]
INFO: [Synth 8-256] done synthesizing module 'serport_xonrx' (26#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_xonrx.vhd:54]
INFO: [Synth 8-3491] module 'serport_xontx' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_xontx.vhd:38' bound to instance 'XONTX' of component 'serport_xontx' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:193]
INFO: [Synth 8-638] synthesizing module 'serport_xontx' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_xontx.vhd:56]
INFO: [Synth 8-256] done synthesizing module 'serport_xontx' (27#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_xontx.vhd:56]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'fifo_2c_dram2' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:41' bound to instance 'RXFIFO' of component 'fifo_2c_dram2' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:209]
INFO: [Synth 8-638] synthesizing module 'fifo_2c_dram2' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:62]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:66]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:67]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:71]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:72]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:73]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:74]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:80]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:81]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:85]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:86]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:87]
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:88]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swar_1ar_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_1swar_1ar_gen.vhd:50' bound to instance 'RAM' of component 'ram_1swar_1ar_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:124]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'gray_cnt_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray_cnt_gen.vhd:33' bound to instance 'GCW' of component 'gray_cnt_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:138]
INFO: [Synth 8-638] synthesizing module 'gray_cnt_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray_cnt_gen.vhd:45]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'gray_cnt_5' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray_cnt_5.vhd:38' bound to instance 'CNT' of component 'gray_cnt_5' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray_cnt_gen.vhd:67]
INFO: [Synth 8-638] synthesizing module 'gray_cnt_5' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray_cnt_5.vhd:48]
INFO: [Synth 8-5534] Detected attribute (* fsm_encoding = "none" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray_cnt_5.vhd:50]
INFO: [Synth 8-5534] Detected attribute (* rom_style = "distributed" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray_cnt_5.vhd:51]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray_cnt_5.vhd:88]
INFO: [Synth 8-256] done synthesizing module 'gray_cnt_5' (28#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray_cnt_5.vhd:48]
INFO: [Synth 8-256] done synthesizing module 'gray_cnt_gen' (29#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray_cnt_gen.vhd:45]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'gray_cnt_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray_cnt_gen.vhd:33' bound to instance 'GCR' of component 'gray_cnt_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:148]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'gray2bin_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray2bin_gen.vhd:32' bound to instance 'G2B_WW' of component 'gray2bin_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:158]
INFO: [Synth 8-638] synthesizing module 'gray2bin_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray2bin_gen.vhd:42]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'gray2bin_gen' (30#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray2bin_gen.vhd:42]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'gray2bin_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray2bin_gen.vhd:32' bound to instance 'G2B_WR' of component 'gray2bin_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:161]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'gray2bin_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray2bin_gen.vhd:32' bound to instance 'G2B_RR' of component 'gray2bin_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:164]
	Parameter DWIDTH bound to: 5 - type: integer 
INFO: [Synth 8-3491] module 'gray2bin_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/genlib/gray2bin_gen.vhd:32' bound to instance 'G2B_RW' of component 'gray2bin_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:167]
INFO: [Synth 8-256] done synthesizing module 'fifo_2c_dram2' (31#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:62]
	Parameter AWIDTH bound to: 5 - type: integer 
	Parameter DWIDTH bound to: 8 - type: integer 
INFO: [Synth 8-3491] module 'fifo_2c_dram2' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.vhd:41' bound to instance 'TXFIFO' of component 'fifo_2c_dram2' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:228]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_signal_s1' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:34' bound to instance 'CDC_RXACT' of component 'cdc_signal_s1' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:284]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_signal_s1' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:34' bound to instance 'CDC_TXACT' of component 'cdc_signal_s1' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:286]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_signal_s1' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:34' bound to instance 'CDC_ABACT' of component 'cdc_signal_s1' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:288]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_signal_s1' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:34' bound to instance 'CDC_RXOK' of component 'cdc_signal_s1' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:290]
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_signal_s1' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.vhd:34' bound to instance 'CDC_TXOK' of component 'cdc_signal_s1' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:292]
	Parameter DWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-3491] module 'cdc_vector_s0' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.vhd:33' bound to instance 'CDC_CDIV' of component 'cdc_vector_s0' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:295]
INFO: [Synth 8-638] synthesizing module 'cdc_vector_s0' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.vhd:44]
	Parameter DWIDTH bound to: 12 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* async_reg = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.vhd:48]
INFO: [Synth 8-256] done synthesizing module 'cdc_vector_s0' (32#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.vhd:44]
	Parameter DWIDTH bound to: 3 - type: integer 
INFO: [Synth 8-3491] module 'cdc_vector_s0' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.vhd:33' bound to instance 'CDC_CDIVF' of component 'cdc_vector_s0' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:304]
INFO: [Synth 8-638] synthesizing module 'cdc_vector_s0__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.vhd:44]
	Parameter DWIDTH bound to: 3 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'cdc_vector_s0__parameterized1' (32#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.vhd:44]
	Parameter POUT_SINGLE bound to: 1 - type: bool 
	Parameter BUSY_WACK bound to: 0 - type: bool 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_pulse' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.vhd:35' bound to instance 'CDC_RXERR' of component 'cdc_pulse' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:313]
INFO: [Synth 8-638] synthesizing module 'cdc_pulse__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.vhd:51]
	Parameter POUT_SINGLE bound to: 1 - type: bool 
	Parameter BUSY_WACK bound to: 0 - type: bool 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'cdc_pulse__parameterized1' (32#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.vhd:51]
	Parameter POUT_SINGLE bound to: 1 - type: bool 
	Parameter BUSY_WACK bound to: 0 - type: bool 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_pulse' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.vhd:35' bound to instance 'CDC_RXOVR' of component 'cdc_pulse' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:326]
	Parameter POUT_SINGLE bound to: 1 - type: bool 
	Parameter BUSY_WACK bound to: 0 - type: bool 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'cdc_pulse' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.vhd:35' bound to instance 'CDC_ABDONE' of component 'cdc_pulse' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:339]
INFO: [Synth 8-256] done synthesizing module 'serport_2clock2' (33#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/serport/serport_2clock2.vhd:75]
INFO: [Synth 8-3491] module 'rb_sres_or_2' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rb_sres_or_2.vhd:39' bound to instance 'RB_SRES_OR' of component 'rb_sres_or_2' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_sp2c.vhd:164]
INFO: [Synth 8-256] done synthesizing module 'rlink_sp2c' (34#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rlink/rlink_sp2c.vhd:81]
INFO: [Synth 8-638] synthesizing module 'tst_sram' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/tst_sram.vhd:201]
	Parameter RB_ADDR bound to: 16'b0000000000000000 
	Parameter AWIDTH bound to: 17 - type: integer 
	Parameter AWIDTH bound to: 11 - type: integer 
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'SMEM_B3' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/tst_sram.vhd:368]
INFO: [Synth 8-638] synthesizing module 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:61]
	Parameter AWIDTH bound to: 11 - type: integer 
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* ram_style = "block" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:66]
INFO: [Synth 8-256] done synthesizing module 'ram_1swsr_wfirst_gen' (35#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:61]
	Parameter AWIDTH bound to: 11 - type: integer 
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-3491] module 'ram_1swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_1swsr_wfirst_gen.vhd:46' bound to instance 'SMEM_B2' of component 'ram_1swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/tst_sram.vhd:381]
	Parameter AWIDTH bound to: 11 - type: integer 
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-3491] module 'ram_2swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd:41' bound to instance 'SMEM_B1' of component 'ram_2swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/tst_sram.vhd:394]
INFO: [Synth 8-638] synthesizing module 'ram_2swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd:62]
	Parameter AWIDTH bound to: 11 - type: integer 
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-5534] Detected attribute (* ram_style = "block" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd:66]
INFO: [Synth 8-256] done synthesizing module 'ram_2swsr_wfirst_gen' (36#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd:62]
	Parameter AWIDTH bound to: 11 - type: integer 
	Parameter DWIDTH bound to: 16 - type: integer 
INFO: [Synth 8-3491] module 'ram_2swsr_wfirst_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/ram_2swsr_wfirst_gen.vhd:41' bound to instance 'SMEM_B0' of component 'ram_2swsr_wfirst_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/tst_sram.vhd:413]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/tst_sram.vhd:865]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/tst_sram.vhd:874]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/tst_sram.vhd:1011]
INFO: [Synth 8-256] done synthesizing module 'tst_sram' (37#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/tst_sram.vhd:201]
INFO: [Synth 8-3491] module 'c7_sram_memctl' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/c7_sram_memctl.vhd:85' bound to instance 'SRAMCTL' of component 'c7_sram_memctl' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:263]
INFO: [Synth 8-638] synthesizing module 'c7_sram_memctl' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/c7_sram_memctl.vhd:109]
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-3491] module 'iob_reg_o' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o.vhd:34' bound to instance 'IOB_MEM_CE' of component 'iob_reg_o' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/c7_sram_memctl.vhd:157]
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-3491] module 'iob_reg_o' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o.vhd:34' bound to instance 'IOB_MEM_WE' of component 'iob_reg_o' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/c7_sram_memctl.vhd:167]
	Parameter INIT bound to: 1'b1 
INFO: [Synth 8-3491] module 'iob_reg_o' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o.vhd:34' bound to instance 'IOB_MEM_OE' of component 'iob_reg_o' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/c7_sram_memctl.vhd:177]
	Parameter DWIDTH bound to: 17 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'iob_reg_o_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:34' bound to instance 'IOB_MEM_ADDRW' of component 'iob_reg_o_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/c7_sram_memctl.vhd:187]
INFO: [Synth 8-638] synthesizing module 'iob_reg_o_gen__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:47]
	Parameter DWIDTH bound to: 17 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'iob_reg_o_gen__parameterized1' (37#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:47]
	Parameter DWIDTH bound to: 2 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-3491] module 'iob_reg_o_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:34' bound to instance 'IOB_MEM_ADDRB' of component 'iob_reg_o_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/c7_sram_memctl.vhd:197]
INFO: [Synth 8-638] synthesizing module 'iob_reg_o_gen__parameterized3' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:47]
	Parameter DWIDTH bound to: 2 - type: integer 
	Parameter INIT bound to: 1'b0 
INFO: [Synth 8-256] done synthesizing module 'iob_reg_o_gen__parameterized3' (37#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_o_gen.vhd:47]
	Parameter DWIDTH bound to: 8 - type: integer 
	Parameter INITI bound to: 1'b0 
	Parameter INITO bound to: 1'b0 
	Parameter INITE bound to: 1'b0 
	Parameter PULL bound to: NONE - type: string 
INFO: [Synth 8-3491] module 'iob_reg_io_gen' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_io_gen.vhd:37' bound to instance 'IOB_MEM_DATA' of component 'iob_reg_io_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/c7_sram_memctl.vhd:207]
INFO: [Synth 8-638] synthesizing module 'iob_reg_io_gen' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_io_gen.vhd:56]
	Parameter DWIDTH bound to: 8 - type: integer 
	Parameter INITI bound to: 1'b0 
	Parameter INITO bound to: 1'b0 
	Parameter INITE bound to: 1'b0 
	Parameter PULL bound to: NONE - type: string 
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_io_gen.vhd:58]
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_io_gen.vhd:59]
INFO: [Synth 8-5534] Detected attribute (* iob = "true" *) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_io_gen.vhd:60]
INFO: [Synth 8-256] done synthesizing module 'iob_reg_io_gen' (38#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/iob_reg_io_gen.vhd:56]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/c7_sram_memctl.vhd:313]
INFO: [Synth 8-256] done synthesizing module 'c7_sram_memctl' (39#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/c7_sram_memctl.vhd:109]
	Parameter SWIDTH bound to: 16 - type: integer 
	Parameter BWIDTH bound to: 5 - type: integer 
	Parameter LWIDTH bound to: 16 - type: integer 
	Parameter DCWIDTH bound to: 3 - type: integer 
	Parameter RB_ADDR bound to: 16'b1111111011110000 
INFO: [Synth 8-3491] module 'sn_humanio_emu_rbus' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/bpgen/sn_humanio_emu_rbus.vhd:64' bound to instance 'HIO' of component 'sn_humanio_emu_rbus' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:285]
INFO: [Synth 8-638] synthesizing module 'sn_humanio_emu_rbus' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/bpgen/sn_humanio_emu_rbus.vhd:84]
	Parameter SWIDTH bound to: 16 - type: integer 
	Parameter BWIDTH bound to: 5 - type: integer 
	Parameter LWIDTH bound to: 16 - type: integer 
	Parameter DCWIDTH bound to: 3 - type: integer 
	Parameter RB_ADDR bound to: 16'b1111111011110000 
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/bpgen/sn_humanio_emu_rbus.vhd:206]
INFO: [Synth 8-256] done synthesizing module 'sn_humanio_emu_rbus' (40#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/bpgen/sn_humanio_emu_rbus.vhd:84]
	Parameter INIT_TEMP_UP bound to: 85.000000 - type: float 
	Parameter INIT_TEMP_LOW bound to: 60.000000 - type: float 
	Parameter INIT_VCCINT_UP bound to: 1.050000 - type: float 
	Parameter INIT_VCCINT_LOW bound to: 0.950000 - type: float 
	Parameter INIT_VCCAUX_UP bound to: 1.890000 - type: float 
	Parameter INIT_VCCAUX_LOW bound to: 1.710000 - type: float 
	Parameter INIT_VCCBRAM_UP bound to: 1.050000 - type: float 
	Parameter INIT_VCCBRAM_LOW bound to: 0.950000 - type: float 
	Parameter CLK_MHZ bound to: 80 - type: integer 
	Parameter RB_ADDR bound to: 16'b1111101100000000 
INFO: [Synth 8-3491] module 'sysmonx_rbus_base' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/sysmon/sysmonx_rbus_base.vhd:50' bound to instance 'SMRB' of component 'sysmonx_rbus_base' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:303]
INFO: [Synth 8-638] synthesizing module 'sysmonx_rbus_base' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/sysmon/sysmonx_rbus_base.vhd:73]
	Parameter INIT_TEMP_UP bound to: 85.000000 - type: float 
	Parameter INIT_TEMP_LOW bound to: 60.000000 - type: float 
	Parameter INIT_VCCINT_UP bound to: 1.050000 - type: float 
	Parameter INIT_VCCINT_LOW bound to: 0.950000 - type: float 
	Parameter INIT_VCCAUX_UP bound to: 1.890000 - type: float 
	Parameter INIT_VCCAUX_LOW bound to: 1.710000 - type: float 
	Parameter INIT_VCCBRAM_UP bound to: 1.050000 - type: float 
	Parameter INIT_VCCBRAM_LOW bound to: 0.950000 - type: float 
	Parameter CLK_MHZ bound to: 80 - type: integer 
	Parameter RB_ADDR bound to: 16'b1111101100000000 
	Parameter INIT_40 bound to: 16'b1001000000000000 
	Parameter INIT_41 bound to: 16'b0010111011110000 
	Parameter INIT_42 bound to: 16'b0000010000000000 
	Parameter INIT_43 bound to: 16'b0000000000000000 
	Parameter INIT_44 bound to: 16'b0000000000000000 
	Parameter INIT_45 bound to: 16'b0000000000000000 
	Parameter INIT_46 bound to: 16'b0000000000000000 
	Parameter INIT_47 bound to: 16'b0000000000000000 
	Parameter INIT_48 bound to: 16'b0100011100000001 
	Parameter INIT_49 bound to: 16'b0000000000000000 
	Parameter INIT_4A bound to: 16'b0000000000000000 
	Parameter INIT_4B bound to: 16'b0000000000000000 
	Parameter INIT_4C bound to: 16'b0000000000000000 
	Parameter INIT_4D bound to: 16'b0000000000000000 
	Parameter INIT_4E bound to: 16'b0000000000000000 
	Parameter INIT_4F bound to: 16'b0000000000000000 
	Parameter INIT_50 bound to: 16'b1011010111101100 
	Parameter INIT_51 bound to: 16'b0101100110011010 
	Parameter INIT_52 bound to: 16'b1010000101001000 
	Parameter INIT_53 bound to: 16'b1100101000110011 
	Parameter INIT_54 bound to: 16'b1010100100111001 
	Parameter INIT_55 bound to: 16'b0101000100010001 
	Parameter INIT_56 bound to: 16'b1001000111101100 
	Parameter INIT_57 bound to: 16'b1010111001000000 
	Parameter INIT_58 bound to: 16'b0101100110011010 
	Parameter INIT_59 bound to: 16'b0000000000000000 
	Parameter INIT_5A bound to: 16'b0000000000000000 
	Parameter INIT_5B bound to: 16'b0000000000000000 
	Parameter INIT_5C bound to: 16'b0101000100010001 
	Parameter INIT_5D bound to: 16'b0000000000000000 
	Parameter INIT_5E bound to: 16'b0000000000000000 
	Parameter INIT_5F bound to: 16'b0000000000000000 
	Parameter IS_CONVSTCLK_INVERTED bound to: 1'b0 
	Parameter IS_DCLK_INVERTED bound to: 1'b0 
	Parameter SIM_DEVICE bound to: 7SERIES - type: string 
	Parameter SIM_MONITOR_FILE bound to: sysmon_stim - type: string 
INFO: [Synth 8-113] binding component instance 'SM' to cell 'XADC' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/sysmon/sysmonx_rbus_base.vhd:96]
	Parameter DAWIDTH bound to: 7 - type: integer 
	Parameter ALWIDTH bound to: 8 - type: integer 
	Parameter TEWIDTH bound to: 12 - type: integer 
	Parameter IBASE bound to: 8'b01111000 
	Parameter RB_ADDR bound to: 16'b1111101100000000 
INFO: [Synth 8-3491] module 'sysmon_rbus_core' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/sysmon/sysmon_rbus_core.vhd:67' bound to instance 'SMRB' of component 'sysmon_rbus_core' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/sysmon/sysmonx_rbus_base.vhd:161]
INFO: [Synth 8-638] synthesizing module 'sysmon_rbus_core' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/sysmon/sysmon_rbus_core.vhd:96]
	Parameter DAWIDTH bound to: 7 - type: integer 
	Parameter ALWIDTH bound to: 8 - type: integer 
	Parameter TEWIDTH bound to: 12 - type: integer 
	Parameter IBASE bound to: 8'b01111000 
	Parameter RB_ADDR bound to: 16'b1111101100000000 
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/sysmon/sysmon_rbus_core.vhd:240]
INFO: [Synth 8-256] done synthesizing module 'sysmon_rbus_core' (41#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/sysmon/sysmon_rbus_core.vhd:96]
INFO: [Synth 8-256] done synthesizing module 'sysmonx_rbus_base' (42#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/sysmon/sysmonx_rbus_base.vhd:73]
	Parameter RB_ADDR bound to: 16'b1111111111111010 
INFO: [Synth 8-3491] module 'rbd_usracc' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rbd_usracc.vhd:45' bound to instance 'UARB' of component 'rbd_usracc' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:317]
INFO: [Synth 8-638] synthesizing module 'rbd_usracc' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rbd_usracc.vhd:56]
	Parameter RB_ADDR bound to: 16'b1111111111111010 
	Parameter RB_ADDR bound to: 16'b1111111111111010 
	Parameter SAWIDTH bound to: 1 - type: integer 
INFO: [Synth 8-3491] module 'rb_sel' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rb_sel.vhd:38' bound to instance 'RBSEL' of component 'rb_sel' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rbd_usracc.vhd:63]
INFO: [Synth 8-638] synthesizing module 'rb_sel__parameterized1' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rb_sel.vhd:49]
	Parameter RB_ADDR bound to: 16'b1111111111111010 
	Parameter SAWIDTH bound to: 1 - type: integer 
INFO: [Synth 8-256] done synthesizing module 'rb_sel__parameterized1' (42#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rb_sel.vhd:49]
INFO: [Synth 8-3491] module 'usr_access_unisim' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/usr_access_unisim.vhd:36' bound to instance 'UA' of component 'usr_access_unisim' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rbd_usracc.vhd:73]
INFO: [Synth 8-638] synthesizing module 'usr_access_unisim' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/usr_access_unisim.vhd:43]
INFO: [Synth 8-113] binding component instance 'UA' to cell 'USR_ACCESSE2' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/usr_access_unisim.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'usr_access_unisim' (43#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/xlib/usr_access_unisim.vhd:43]
INFO: [Synth 8-226] default block is never used [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rbd_usracc.vhd:93]
INFO: [Synth 8-256] done synthesizing module 'rbd_usracc' (44#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rbd_usracc.vhd:56]
INFO: [Synth 8-3491] module 'rb_sres_or_4' declared at '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rb_sres_or_4.vhd:39' bound to instance 'RB_SRES_OR' of component 'rb_sres_or_4' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:324]
INFO: [Synth 8-638] synthesizing module 'rb_sres_or_4' [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rb_sres_or_4.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'rb_sres_or_4' (45#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/rbus/rb_sres_or_4.vhd:49]
INFO: [Synth 8-256] done synthesizing module 'sys_tst_sram_c7' (46#1) [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:80]
WARNING: [Synth 8-3917] design sys_tst_sram_c7 has port O_RGBLED0_N[2] driven by constant 1
WARNING: [Synth 8-3917] design sys_tst_sram_c7 has port O_RGBLED0_N[1] driven by constant 1
WARNING: [Synth 8-3917] design sys_tst_sram_c7 has port O_RGBLED0_N[0] driven by constant 1
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[re]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[we]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[addr][0]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][15]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][14]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][13]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][12]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][11]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][10]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][9]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][8]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][7]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][6]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][5]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][4]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][3]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][2]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][1]
WARNING: [Synth 8-3331] design rb_sel__parameterized1 has unconnected port RB_MREQ[din][0]
WARNING: [Synth 8-3331] design sysmon_rbus_core has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design sn_humanio_emu_rbus has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design tst_sram has unconnected port MEM_ACK_W
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[re]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[we]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[addr][1]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[addr][0]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][15]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][14]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][13]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][12]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][11]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][10]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][9]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][8]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][7]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][6]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][5]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][4]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][3]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][2]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][1]
WARNING: [Synth 8-3331] design rb_sel has unconnected port RB_MREQ[din][0]
WARNING: [Synth 8-3331] design rlink_sp2c has unconnected port CE_USEC
WARNING: [Synth 8-3331] design rlink_sp2c has unconnected port CE_MSEC
WARNING: [Synth 8-3331] design sys_tst_sram_c7 has unconnected port I_BTN[1]
WARNING: [Synth 8-3331] design sys_tst_sram_c7 has unconnected port I_BTN[0]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 1208.137 ; gain = 116.449 ; free physical = 1423 ; free virtual = 8848
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
WARNING: [Synth 8-3295] tying undriven pin RLINK:RB_LAM[15] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:199]
WARNING: [Synth 8-3295] tying undriven pin RLINK:RB_LAM[14] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:199]
WARNING: [Synth 8-3295] tying undriven pin RLINK:RB_LAM[13] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:199]
WARNING: [Synth 8-3295] tying undriven pin RLINK:RB_LAM[12] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:199]
WARNING: [Synth 8-3295] tying undriven pin RLINK:RB_LAM[11] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:199]
WARNING: [Synth 8-3295] tying undriven pin RLINK:RB_LAM[10] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:199]
WARNING: [Synth 8-3295] tying undriven pin RLINK:RB_LAM[9] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:199]
WARNING: [Synth 8-3295] tying undriven pin RLINK:RB_LAM[8] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:199]
WARNING: [Synth 8-3295] tying undriven pin RLINK:RB_LAM[7] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:199]
WARNING: [Synth 8-3295] tying undriven pin RLINK:RB_LAM[6] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:199]
WARNING: [Synth 8-3295] tying undriven pin RLINK:RB_LAM[5] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:199]
WARNING: [Synth 8-3295] tying undriven pin RLINK:RB_LAM[4] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:199]
WARNING: [Synth 8-3295] tying undriven pin RLINK:RB_LAM[3] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:199]
WARNING: [Synth 8-3295] tying undriven pin RLINK:RB_LAM[2] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:199]
WARNING: [Synth 8-3295] tying undriven pin RLINK:RB_LAM[1] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:199]
WARNING: [Synth 8-3295] tying undriven pin HIO:LED[15] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:285]
WARNING: [Synth 8-3295] tying undriven pin HIO:LED[14] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:285]
WARNING: [Synth 8-3295] tying undriven pin HIO:LED[13] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:285]
WARNING: [Synth 8-3295] tying undriven pin HIO:LED[12] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:285]
WARNING: [Synth 8-3295] tying undriven pin HIO:LED[11] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:285]
WARNING: [Synth 8-3295] tying undriven pin HIO:LED[10] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:285]
WARNING: [Synth 8-3295] tying undriven pin HIO:LED[9] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:285]
WARNING: [Synth 8-3295] tying undriven pin HIO:LED[8] to constant 0 [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd:285]
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:13 ; elapsed = 00:00:13 . Memory (MB): peak = 1208.137 ; gain = 116.449 ; free physical = 1433 ; free virtual = 8858
---------------------------------------------------------------------------------
INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Device 21-403] Loading part xc7a35tcpg236-1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Constraints 18-548] Could not create 'PULL' constraint because invalid IO constraint value 'NONE' specified. 'PULL' is ignored by Vivado but preserved for implementation tool. [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/c7_sram_memctl.vhd:207]

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/cmoda7_pclk.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/cmoda7_pclk.xdc]
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/cmoda7_pins.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/cmoda7_pins.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/cmoda7_pins.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/sys_tst_sram_c7_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/sys_tst_sram_c7_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/cmoda7_pins_sram.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/cmoda7_pins_sram.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/cmoda7/cmoda7_pins_sram.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/sys_tst_sram_c7_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/sys_tst_sram_c7_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RESET'
INFO: [Timing 38-2] Deriving generated clocks [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc:13]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RESET'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXERR'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXERR'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXOVR'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_RXOVR'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_ABDONE'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc] for cell 'RLINK/SERPORT/CDC_ABDONE'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_pulse.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/sys_tst_sram_c7_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/sys_tst_sram_c7_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAXON'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAXON'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAESC'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ENAESC'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXACT'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXACT'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXACT'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXACT'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ABACT'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_ABACT'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXOK'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_RXOK'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXOK'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc] for cell 'RLINK/SERPORT/CDC_TXOK'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_signal_s1.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/sys_tst_sram_c7_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/sys_tst_sram_c7_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIV'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIV'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIVF'
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc] for cell 'RLINK/SERPORT/CDC_CDIVF'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/cdclib/cdc_vector_s0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/sys_tst_sram_c7_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/sys_tst_sram_c7_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/RXFIFO'
WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:56]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/RXFIFO'
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/TXFIFO'
WARNING: [Designutils 20-1567] Use of 'set_false_path' with '-hold' is not supported by synthesis. The constraint will not be passed to synthesis. [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc:56]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc] for cell 'RLINK/SERPORT/TXFIFO'
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/vlib/memlib/fifo_2c_dram2.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/sys_tst_sram_c7_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/sys_tst_sram_c7_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc]
Completed Processing XDC Constraints

INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 2 instances were transformed.
  MMCME2_BASE => MMCME2_ADV: 2 instances

Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1493.090 ; gain = 0.000 ; free physical = 1184 ; free virtual = 8610
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 1493.090 ; gain = 401.402 ; free physical = 1274 ; free virtual = 8699
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a35tcpg236-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 1493.090 ; gain = 401.402 ; free physical = 1274 ; free virtual = 8699
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_ABDONE. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 11).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_RESET. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 11).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_RXERR. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 11).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_RXOVR. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 11).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_ABACT. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 14).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_ENAESC. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 14).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_ENAXON. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 14).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_RXACT. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 14).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_RXOK. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 14).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_TXACT. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 14).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_TXOK. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 14).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_CDIV. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 17).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/CDC_CDIVF. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 17).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/RXFIFO. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 20).
Applied set_property DONT_TOUCH = true for RLINK/SERPORT/TXFIFO. (constraint file  /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/dont_touch.xdc, line 20).
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:31 ; elapsed = 00:00:32 . Memory (MB): peak = 1493.090 ; gain = 401.402 ; free physical = 1275 ; free virtual = 8701
---------------------------------------------------------------------------------
INFO: [Synth 8-5546] ROM "n[mcnt]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[msec]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[mcnt]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[msec]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[empty]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[full]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'R_LREGS_reg[state]' in module 'rlink_core'
INFO: [Synth 8-802] inferred FSM for state register 'R_BREGS_reg[state]' in module 'rlink_core'
INFO: [Synth 8-5546] ROM "bcnt_end" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "cnt_iszero" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "bto_end" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[doretra]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "n[atocnt]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[nakcode]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "n[nakcode]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[nakcode]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[cmdseen]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "n[rtaddra_red]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[rtaddra_zero]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[rtaddrb_red]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "cnt_end" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "n[anena]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "crcreset" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[rcmd]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[addr]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[cnt]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[anact]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[dinl]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "addrb_sela" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "n[state]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "bto_go" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[rbdout]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "iesc" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'serport_uart_autobaud'
INFO: [Synth 8-5546] ROM "n[state]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "n[seen1]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iact" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'serport_uart_rx'
INFO: [Synth 8-5546] ROM "tc_ccnt" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "tc_bcnt" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[sreg]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iact" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5546] ROM "ld_ccnt" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5544] ROM "n[busy]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-4490] FSM extraction disabled for register 'R_DATA_reg' through user attribute
INFO: [Synth 8-5546] ROM "ival" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "ival" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'tst_sram'
INFO: [Synth 8-5587] ROM size for "omux_sel" is below threshold of ROM address width. It will be mapped to LUTs
INFO: [Synth 8-5544] ROM "n[srun]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'c7_sram_memctl'
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[addrb]' in module 'c7_sram_memctl'
INFO: [Synth 8-5544] ROM "iackw" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "idata_oe" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[addrb]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "imem_we" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "idata_cei" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iactw" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iactr" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ibusy" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[ackr]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[memdo]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[addrb]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iackw" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "idata_oe" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[addrb]" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "imem_we" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "idata_cei" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iactw" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "iactr" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "ibusy" won't be mapped to Block RAM because address size (3) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[ackr]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[memdo]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[addrb]" won't be mapped to Block RAM because address size (2) smaller than threshold (5)
INFO: [Synth 8-802] inferred FSM for state register 'R_REGS_reg[state]' in module 'sysmon_rbus_core'
INFO: [Synth 8-5544] ROM "irb_addr_int" won't be mapped to Block RAM because address size (4) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-5544] ROM "n[state]" won't be mapped to Block RAM because address size (1) smaller than threshold (5)
INFO: [Synth 8-3971] The signal sv_ram_reg was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 sb_idle |                    0000000000001 |                             0000
               sb_rstart |                    0000000000010 |                             0001
                sb_rreg0 |                    0000000000100 |                             0010
                sb_rreg1 |                    0000000001000 |                             0011
                 sb_rend |                    0000000010000 |                             0101
                sb_rabo1 |                    0000000100000 |                             0111
                sb_rabo0 |                    0000001000000 |                             0110
                sb_rwait |                    0000010000000 |                             0100
               sb_wstart |                    0000100000000 |                             1000
                sb_wreg0 |                    0001000000000 |                             1001
                sb_wreg1 |                    0010000000000 |                             1010
                sb_wabo0 |                    0100000000000 |                             1011
                sb_wabo1 |                    1000000000000 |                             1100
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_BREGS_reg[state]' using encoding 'one-hot' in module 'rlink_core'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                 sl_idle | 0000000000000000000000000000000000000001 |                           000000
               sl_txanot | 0000000000000000000000000000000000000010 |                           000001
                sl_txsop | 0000000000000000000000000000000000000100 |                           000010
                sl_rxcmd | 0000000000000000000000000000000000001000 |                           001000
              sl_rxaddrl | 0000000000000000000000000000000000010000 |                           001001
              sl_rxaddrh | 0000000000000000000000000000000000100000 |                           001010
               sl_rxdatl | 0000000000000000000000000000000001000000 |                           001011
               sl_rxdath | 0000000000000000000000000000000010000000 |                           001100
               sl_rxcntl | 0000000000000000000000000000000100000000 |                           001101
               sl_rxcnth | 0000000000000000000000000000001000000000 |                           001110
              sl_rxccrcl | 0000000000000000000000000000010000000000 |                           001111
              sl_rxccrch | 0000000000000000000000000000100000000000 |                           010000
                sl_txcmd | 0000000000000000000000000001000000000000 |                           010001
               sl_txlabo | 0000000000000000000000000010000000000000 |                           100011
                 sl_attn | 0000000000000000000000000100000000000000 |                           100100
               sl_txcntl | 0000000000000000000000001000000000000000 |                           010010
               sl_txcnth | 0000000000000000000000010000000000000000 |                           010011
               sl_rstart | 0000000000000000000000100000000000000000 |                           010100
                sl_txdat | 0000000000000000000001000000000000000000 |                           010101
                 sl_wblk | 0000000000000000000010000000000000000000 |                           010110
               sl_rxwblk | 0000000000000000000100000000000000000000 |                           010111
              sl_rxdcrcl | 0000000000000000001000000000000000000000 |                           011000
              sl_rxdcrch | 0000000000000000010000000000000000000000 |                           011001
                sl_wblk0 | 0000000000000000100000000000000000000000 |                           011010
                sl_wblk1 | 0000000000000001000000000000000000000000 |                           011011
                sl_wblk2 | 0000000000000010000000000000000000000000 |                           011100
                sl_wblkl | 0000000000000100000000000000000000000000 |                           011101
                sl_wblkh | 0000000000001000000000000000000000000000 |                           011110
               sl_wwait0 | 0000000000010000000000000000000000000000 |                           011111
               sl_wwait1 | 0000000000100000000000000000000000000000 |                           100000
              sl_txdcntl | 0000000001000000000000000000000000000000 |                           100001
              sl_txdcnth | 0000000010000000000000000000000000000000 |                           100010
               sl_txstat | 0000000100000000000000000000000000000000 |                           100101
               sl_txcrcl | 0000001000000000000000000000000000000000 |                           100110
               sl_txcrch | 0000010000000000000000000000000000000000 |                           100111
              sl_txrtbuf | 0000100000000000000000000000000000000000 |                           000101
                sl_txnak | 0001000000000000000000000000000000000000 |                           000011
            sl_txnakcode | 0010000000000000000000000000000000000000 |                           000100
                sl_rxeop | 0100000000000000000000000000000000000000 |                           000111
                sl_txeop | 1000000000000000000000000000000000000000 |                           000110
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_LREGS_reg[state]' using encoding 'one-hot' in module 'rlink_core'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_idle |                             0001 |                               00
                 s_break |                             0010 |                               01
                  s_wait |                             0100 |                               10
                  s_sync |                             1000 |                               11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'serport_uart_autobaud'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_idle |                          0000001 |                              000
                 s_colb0 |                          0000010 |                              001
                 s_endb0 |                          0000100 |                              010
                 s_colbx |                          0001000 |                              011
                 s_endbx |                          0010000 |                              100
                 s_colb9 |                          0100000 |                              101
                 s_endb9 |                          1000000 |                              110
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'serport_uart_rx'
INFO: [Synth 8-3971] The signal sv_ram_reg was recognized as a true dual port RAM template.
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_idle |                    0000000000001 |                             0000
                  s_mcmd |                    0000000000010 |                             0001
             s_mcmd_read |                    0000000000100 |                             0010
                s_sstart |                    0000000001000 |                             1001
                 s_sload |                    0000000010000 |                             1010
                  s_srun |                    0000000100000 |                             1011
                 s_sloop |                    0000001000000 |                             1100
              s_mblk_wr1 |                    0000010000000 |                             0011
              s_mblk_wr2 |                    0000100000000 |                             0100
              s_mblk_rd1 |                    0001000000000 |                             0101
              s_mblk_rd2 |                    0010000000000 |                             0110
                  s_sblk |                    0100000000000 |                             1000
               s_sblk_rd |                    1000000000000 |                             0111
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'tst_sram'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  iSTATE |                             0001 |                               00
                 iSTATE0 |                             0010 |                               01
                 iSTATE1 |                             0100 |                               10
                 iSTATE2 |                             1000 |                               11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[addrb]' using encoding 'one-hot' in module 'c7_sram_memctl'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_idle |                            00001 |                              000
                 s_read0 |                            00010 |                              001
                 s_read1 |                            00100 |                              010
                s_write1 |                            01000 |                              100
                s_write0 |                            10000 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'c7_sram_memctl'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  s_init |                             0001 |                               00
                  s_idle |                             0010 |                               01
                 s_twait |                             0100 |                               11
                  s_wait |                             1000 |                               10
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'R_REGS_reg[state]' using encoding 'one-hot' in module 'sysmon_rbus_core'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:37 ; elapsed = 00:00:38 . Memory (MB): peak = 1493.090 ; gain = 401.402 ; free physical = 1264 ; free virtual = 8690
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     17 Bit       Adders := 1     
	   2 Input     15 Bit       Adders := 1     
	   2 Input     12 Bit       Adders := 1     
	   2 Input     11 Bit       Adders := 3     
	   2 Input     10 Bit       Adders := 2     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      7 Bit       Adders := 3     
	   2 Input      6 Bit       Adders := 1     
	   2 Input      5 Bit       Adders := 2     
	   3 Input      5 Bit       Adders := 5     
	   2 Input      4 Bit       Adders := 3     
	   2 Input      2 Bit       Adders := 1     
+---XORs : 
	   2 Input     32 Bit         XORs := 1     
	   2 Input     17 Bit         XORs := 1     
	   2 Input      8 Bit         XORs := 2     
	   2 Input      1 Bit         XORs := 60    
	   3 Input      1 Bit         XORs := 2     
+---Registers : 
	               32 Bit    Registers := 6     
	               24 Bit    Registers := 1     
	               17 Bit    Registers := 2     
	               16 Bit    Registers := 16    
	               15 Bit    Registers := 1     
	               12 Bit    Registers := 3     
	               11 Bit    Registers := 8     
	               10 Bit    Registers := 2     
	                9 Bit    Registers := 2     
	                8 Bit    Registers := 16    
	                7 Bit    Registers := 3     
	                6 Bit    Registers := 1     
	                5 Bit    Registers := 19    
	                4 Bit    Registers := 5     
	                3 Bit    Registers := 3     
	                2 Bit    Registers := 2     
	                1 Bit    Registers := 140   
+---RAMs : 
	              32K Bit         RAMs := 5     
+---Muxes : 
	  94 Input     40 Bit        Muxes := 1     
	   2 Input     32 Bit        Muxes := 2     
	  13 Input     32 Bit        Muxes := 4     
	   4 Input     24 Bit        Muxes := 1     
	   5 Input     24 Bit        Muxes := 1     
	   2 Input     17 Bit        Muxes := 5     
	  13 Input     17 Bit        Muxes := 2     
	  40 Input     16 Bit        Muxes := 6     
	   2 Input     16 Bit        Muxes := 9     
	   4 Input     16 Bit        Muxes := 1     
	   4 Input     15 Bit        Muxes := 1     
	  24 Input     13 Bit        Muxes := 1     
	  46 Input     13 Bit        Muxes := 1     
	  40 Input     12 Bit        Muxes := 1     
	   2 Input     12 Bit        Muxes := 1     
	   2 Input     11 Bit        Muxes := 2     
	  13 Input     11 Bit        Muxes := 2     
	  40 Input      9 Bit        Muxes := 1     
	   2 Input      9 Bit        Muxes := 5     
	   4 Input      9 Bit        Muxes := 1     
	  13 Input      8 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 16    
	   6 Input      8 Bit        Muxes := 1     
	   7 Input      8 Bit        Muxes := 1     
	   4 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 3     
	  18 Input      7 Bit        Muxes := 1     
	   4 Input      7 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 3     
	   5 Input      5 Bit        Muxes := 1     
	   9 Input      5 Bit        Muxes := 1     
	   8 Input      5 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 3     
	  19 Input      4 Bit        Muxes := 1     
	  13 Input      4 Bit        Muxes := 2     
	   5 Input      4 Bit        Muxes := 2     
	   7 Input      4 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 7     
	  40 Input      3 Bit        Muxes := 1     
	   5 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 7     
	   9 Input      2 Bit        Muxes := 1     
	  40 Input      2 Bit        Muxes := 1     
	   4 Input      2 Bit        Muxes := 3     
	  13 Input      2 Bit        Muxes := 1     
	   5 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 186   
	   4 Input      1 Bit        Muxes := 28    
	  13 Input      1 Bit        Muxes := 51    
	   5 Input      1 Bit        Muxes := 17    
	   8 Input      1 Bit        Muxes := 4     
	   3 Input      1 Bit        Muxes := 1     
	  40 Input      1 Bit        Muxes := 31    
	   7 Input      1 Bit        Muxes := 14    
	  18 Input      1 Bit        Muxes := 10    
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Hierarchical Component Statistics 
---------------------------------------------------------------------------------
Hierarchical RTL Component report 
Module clkdivce 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     10 Bit       Adders := 1     
	   2 Input      7 Bit       Adders := 1     
+---Registers : 
	               10 Bit    Registers := 1     
	                7 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 3     
Module clkdivce__parameterized1 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     10 Bit       Adders := 1     
	   2 Input      7 Bit       Adders := 1     
+---Registers : 
	               10 Bit    Registers := 1     
	                7 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 3     
Module iob_reg_i_gen 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module iob_reg_o_gen 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module ram_2swsr_rfirst_gen 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 2     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module fifo_1c_dram_raw 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      5 Bit       Adders := 2     
	   3 Input      5 Bit       Adders := 1     
+---Registers : 
	                5 Bit    Registers := 2     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 4     
Module crc16 
Detailed RTL Component Info : 
+---XORs : 
	   2 Input      8 Bit         XORs := 1     
	   2 Input      1 Bit         XORs := 14    
	   3 Input      1 Bit         XORs := 1     
+---Registers : 
	               16 Bit    Registers := 1     
Module rb_sel 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rlink_core 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     11 Bit       Adders := 2     
	   2 Input      8 Bit       Adders := 1     
	   2 Input      6 Bit       Adders := 1     
+---Registers : 
	               16 Bit    Registers := 5     
	               11 Bit    Registers := 2     
	                8 Bit    Registers := 5     
	                6 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 26    
+---Muxes : 
	  94 Input     40 Bit        Muxes := 1     
	  40 Input     16 Bit        Muxes := 6     
	   2 Input     16 Bit        Muxes := 1     
	   4 Input     16 Bit        Muxes := 1     
	  24 Input     13 Bit        Muxes := 1     
	  40 Input     12 Bit        Muxes := 1     
	   2 Input     11 Bit        Muxes := 1     
	  40 Input      9 Bit        Muxes := 1     
	  13 Input      8 Bit        Muxes := 1     
	   2 Input      8 Bit        Muxes := 1     
	   4 Input      3 Bit        Muxes := 1     
	   2 Input      3 Bit        Muxes := 3     
	  40 Input      3 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 1     
	   9 Input      2 Bit        Muxes := 1     
	  40 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 41    
	   4 Input      1 Bit        Muxes := 3     
	  13 Input      1 Bit        Muxes := 22    
	   5 Input      1 Bit        Muxes := 2     
	   8 Input      1 Bit        Muxes := 2     
	   3 Input      1 Bit        Muxes := 1     
	  40 Input      1 Bit        Muxes := 31    
Module byte2cdata 
Detailed RTL Component Info : 
+---Registers : 
	                9 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input      9 Bit        Muxes := 4     
	   4 Input      9 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 5     
Module cdata2byte 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 1     
	                3 Bit    Registers := 1     
	                1 Bit    Registers := 2     
+---Muxes : 
	   2 Input      8 Bit        Muxes := 3     
	   2 Input      3 Bit        Muxes := 4     
	   5 Input      3 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 6     
	   5 Input      1 Bit        Muxes := 1     
Module cdc_pulse 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 5     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module cdc_signal_s1 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 2     
Module serport_uart_autobaud 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     15 Bit       Adders := 1     
	   2 Input      7 Bit       Adders := 1     
+---Registers : 
	               15 Bit    Registers := 1     
	                7 Bit    Registers := 1     
	                1 Bit    Registers := 1     
+---Muxes : 
	   4 Input     15 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 5     
Module serport_uart_rx 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input      4 Bit       Adders := 1     
+---Registers : 
	                8 Bit    Registers := 1     
	                4 Bit    Registers := 1     
+---Muxes : 
	  18 Input      7 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 12    
	   7 Input      1 Bit        Muxes := 8     
Module serport_uart_tx 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     12 Bit       Adders := 1     
	   2 Input      4 Bit       Adders := 1     
+---Registers : 
	               12 Bit    Registers := 1     
	                9 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                1 Bit    Registers := 1     
+---Muxes : 
	   2 Input     12 Bit        Muxes := 1     
	   2 Input      9 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 6     
Module serport_xonrx 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 4     
+---Muxes : 
	   2 Input      8 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 9     
	   5 Input      1 Bit        Muxes := 1     
	   4 Input      1 Bit        Muxes := 1     
Module serport_xontx 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 2     
	                1 Bit    Registers := 5     
+---Muxes : 
	   2 Input      8 Bit        Muxes := 6     
	   6 Input      8 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 2     
	   5 Input      5 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 20    
Module gray_cnt_5 
Detailed RTL Component Info : 
+---Registers : 
	                5 Bit    Registers := 1     
Module gray2bin_gen 
Detailed RTL Component Info : 
+---XORs : 
	   2 Input      1 Bit         XORs := 4     
Module fifo_2c_dram2 
Detailed RTL Component Info : 
+---Adders : 
	   3 Input      5 Bit       Adders := 2     
+---Registers : 
	                5 Bit    Registers := 6     
	                1 Bit    Registers := 12    
+---Muxes : 
	   2 Input      1 Bit        Muxes := 6     
Module cdc_vector_s0 
Detailed RTL Component Info : 
+---Registers : 
	               12 Bit    Registers := 1     
Module cdc_vector_s0__parameterized1 
Detailed RTL Component Info : 
+---Registers : 
	                3 Bit    Registers := 1     
Module cdc_pulse__parameterized1 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 7     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 1     
Module serport_2clock2 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
+---Muxes : 
	   2 Input      1 Bit        Muxes := 2     
Module ram_1swsr_wfirst_gen 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 1     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module ram_2swsr_wfirst_gen 
Detailed RTL Component Info : 
+---Registers : 
	               16 Bit    Registers := 2     
+---RAMs : 
	              32K Bit         RAMs := 1     
Module tst_sram 
Detailed RTL Component Info : 
+---Adders : 
	   2 Input     17 Bit       Adders := 1     
	   2 Input     11 Bit       Adders := 1     
	   2 Input      4 Bit       Adders := 1     
	   2 Input      2 Bit       Adders := 1     
+---XORs : 
	   2 Input     32 Bit         XORs := 1     
	   2 Input     17 Bit         XORs := 1     
+---Registers : 
	               32 Bit    Registers := 4     
	               17 Bit    Registers := 1     
	               16 Bit    Registers := 1     
	               11 Bit    Registers := 6     
	                4 Bit    Registers := 1     
	                2 Bit    Registers := 1     
	                1 Bit    Registers := 12    
+---Muxes : 
	   2 Input     32 Bit        Muxes := 2     
	  13 Input     32 Bit        Muxes := 4     
	   2 Input     17 Bit        Muxes := 5     
	  13 Input     17 Bit        Muxes := 2     
	   2 Input     16 Bit        Muxes := 2     
	  46 Input     13 Bit        Muxes := 1     
	   2 Input     11 Bit        Muxes := 1     
	  13 Input     11 Bit        Muxes := 2     
	  19 Input      4 Bit        Muxes := 1     
	  13 Input      4 Bit        Muxes := 2     
	   2 Input      4 Bit        Muxes := 1     
	   2 Input      2 Bit        Muxes := 2     
	   4 Input      2 Bit        Muxes := 1     
	  13 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 31    
	  18 Input      1 Bit        Muxes := 10    
	   4 Input      1 Bit        Muxes := 6     
	  13 Input      1 Bit        Muxes := 29    
Module iob_reg_o_gen__parameterized1 
Detailed RTL Component Info : 
+---Registers : 
	               17 Bit    Registers := 1     
Module iob_reg_o_gen__parameterized3 
Detailed RTL Component Info : 
+---Registers : 
	                2 Bit    Registers := 1     
Module iob_reg_io_gen 
Detailed RTL Component Info : 
+---Registers : 
	                8 Bit    Registers := 2     
	                1 Bit    Registers := 1     
+---Muxes : 
	   2 Input      8 Bit        Muxes := 1     
Module c7_sram_memctl 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 1     
	               24 Bit    Registers := 1     
	                4 Bit    Registers := 1     
	                1 Bit    Registers := 1     
+---Muxes : 
	   4 Input     24 Bit        Muxes := 1     
	   5 Input     24 Bit        Muxes := 1     
	   9 Input      5 Bit        Muxes := 1     
	   2 Input      4 Bit        Muxes := 1     
	   5 Input      4 Bit        Muxes := 2     
	   4 Input      2 Bit        Muxes := 2     
	   2 Input      2 Bit        Muxes := 4     
	   5 Input      2 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 3     
	   5 Input      1 Bit        Muxes := 13    
Module sn_humanio_emu_rbus 
Detailed RTL Component Info : 
+---Registers : 
	               32 Bit    Registers := 1     
	               16 Bit    Registers := 2     
	                8 Bit    Registers := 1     
	                5 Bit    Registers := 1     
	                1 Bit    Registers := 1     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 1     
	   8 Input      5 Bit        Muxes := 1     
	   2 Input      5 Bit        Muxes := 1     
	   8 Input      1 Bit        Muxes := 2     
	   2 Input      1 Bit        Muxes := 1     
Module sysmon_rbus_core 
Detailed RTL Component Info : 
+---Registers : 
	               12 Bit    Registers := 1     
	                8 Bit    Registers := 1     
	                1 Bit    Registers := 6     
+---Muxes : 
	   2 Input     16 Bit        Muxes := 2     
	   2 Input      8 Bit        Muxes := 4     
	   7 Input      8 Bit        Muxes := 1     
	   4 Input      8 Bit        Muxes := 1     
	   2 Input      7 Bit        Muxes := 2     
	   4 Input      7 Bit        Muxes := 1     
	   7 Input      4 Bit        Muxes := 1     
	   2 Input      1 Bit        Muxes := 23    
	   7 Input      1 Bit        Muxes := 6     
	   4 Input      1 Bit        Muxes := 13    
Module rb_sel__parameterized1 
Detailed RTL Component Info : 
+---Registers : 
	                1 Bit    Registers := 1     
Module rbd_usracc 
Detailed RTL Component Info : 
+---Muxes : 
	   2 Input     16 Bit        Muxes := 3     
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 90 (col length:60)
BRAMs: 100 (col length: RAMB18 60 RAMB36 30)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
INFO: [Synth 8-5546] ROM "n[mcnt]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[msec]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[mcnt]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "n[msec]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/RL/cnt_end" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/RL/n[rtaddra_red]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/RL/n[rtaddra_zero]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/RL/bcnt_end" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/RL/cnt_iszero" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/RL/n[atocnt]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/RL/n[rtaddrb_red]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "CORE/B2CD/iesc" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "SERPORT/UART/AB/n[state]" won't be mapped to RAM because it is too sparse
INFO: [Synth 8-5546] ROM "SERPORT/UART/RXTX/RX/tc_ccnt" won't be mapped to RAM because it is too sparse
WARNING: [Synth 8-3917] design sys_tst_sram_c7 has port O_RGBLED0_N[2] driven by constant 1
WARNING: [Synth 8-3917] design sys_tst_sram_c7 has port O_RGBLED0_N[1] driven by constant 1
WARNING: [Synth 8-3917] design sys_tst_sram_c7 has port O_RGBLED0_N[0] driven by constant 1
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][15]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][14]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][13]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][12]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][11]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][10]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][9]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][8]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][7]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][6]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][5]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][4]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][3]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][2]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][1]
WARNING: [Synth 8-3331] design rbd_usracc has unconnected port RB_MREQ[din][0]
WARNING: [Synth 8-3331] design sysmonx_rbus_base has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design sn_humanio_emu_rbus has unconnected port RB_MREQ[init]
WARNING: [Synth 8-3331] design tst_sram has unconnected port MEM_ACK_W
WARNING: [Synth 8-3331] design rlink_sp2c has unconnected port CE_USEC
WARNING: [Synth 8-3331] design rlink_sp2c has unconnected port CE_MSEC
WARNING: [Synth 8-3331] design sys_tst_sram_c7 has unconnected port I_BTN[1]
WARNING: [Synth 8-3331] design sys_tst_sram_c7 has unconnected port I_BTN[0]
INFO: [Synth 8-3971] The signal RLINK/CORE/RL/RTBUF/sv_ram_reg was recognized as a true dual port RAM template.
INFO: [Synth 8-3971] The signal TST/SMEM_B1/sv_ram_reg was recognized as a true dual port RAM template.
INFO: [Synth 8-3971] The signal TST/SMEM_B0/sv_ram_reg was recognized as a true dual port RAM template.
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\HIO/R_REGS_reg[led][12] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\HIO/R_REGS_reg[dsp_dp][4] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\HIO/R_REGS_reg[led][13] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\HIO/R_REGS_reg[led][10] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\HIO/R_REGS_reg[led][11] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\HIO/R_REGS_reg[dsp_dat][19] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\HIO/R_REGS_reg[led][8] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\HIO/R_REGS_reg[led][9] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\HIO/R_REGS_reg[led][14] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\HIO/R_REGS_reg[dsp_dp][6] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\HIO/R_REGS_reg[led][15] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\HIO/R_REGS_reg[dsp_dp][7] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\RLINK/CORE/RL/R_BREGS_reg[stat][2] )
INFO: [Synth 8-3333] propagating constant 0 across sequential element (\RLINK/CORE/RL/R_BREGS_reg[stat][3] )
WARNING: [Synth 8-3332] Sequential element (CLKDIV_CLK/R_REGS_reg[usec]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (CLKDIV_CLKS/R_REGS_reg[usec]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[attn][15]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[attn][14]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[attn][13]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[attn][12]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[attn][11]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[attn][10]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[attn][9]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[attn][8]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[attn][7]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[attn][6]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[attn][5]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[attn][4]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[attn][3]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[attn][2]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[attn][1]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_BREGS_reg[stat][3]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_BREGS_reg[stat][2]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[moneop]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (RLINK/CORE/RL/R_LREGS_reg[monattn]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (HIO/R_REGS_reg[led][15]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (HIO/R_REGS_reg[led][14]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (HIO/R_REGS_reg[led][13]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (HIO/R_REGS_reg[led][12]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (HIO/R_REGS_reg[led][11]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (HIO/R_REGS_reg[led][10]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (HIO/R_REGS_reg[led][9]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (HIO/R_REGS_reg[led][8]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (HIO/R_REGS_reg[dsp_dp][7]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (HIO/R_REGS_reg[dsp_dp][6]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (HIO/R_REGS_reg[dsp_dp][4]) is unused and will be removed from module sys_tst_sram_c7.
WARNING: [Synth 8-3332] Sequential element (HIO/R_REGS_reg[dsp_dat][19]) is unused and will be removed from module sys_tst_sram_c7.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:54 ; elapsed = 00:00:59 . Memory (MB): peak = 1493.090 ; gain = 401.402 ; free physical = 1135 ; free virtual = 8581
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

ROM:
+--------------+-----------------------+---------------+----------------+
|Module Name   | RTL Object            | Depth x Width | Implemented As | 
+--------------+-----------------------+---------------+----------------+
|gray_cnt_5    | N_DATA                | 32x5          | LUT            | 
|fifo_2c_dram2 | GCW/GRAY_5.CNT/N_DATA | 32x5          | LUT            | 
|fifo_2c_dram2 | GCR/GRAY_5.CNT/N_DATA | 32x5          | LUT            | 
|fifo_2c_dram2 | GCW/GRAY_5.CNT/N_DATA | 32x5          | LUT            | 
|fifo_2c_dram2 | GCR/GRAY_5.CNT/N_DATA | 32x5          | LUT            | 
+--------------+-----------------------+---------------+----------------+


Block RAM: Preliminary Mapping  Report (see note below)
+----------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|Module Name           | RTL Object | PORT A (Depth x Width) | W | R | PORT B (Depth x Width) | W | R | Ports driving FF | RAMB18 | RAMB36 | 
+----------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+
|ram_2swsr_rfirst_gen: | sv_ram_reg | 4 K x 8(READ_FIRST)    | W | R | 4 K x 8(READ_FIRST)    | W | R | Port A and B     | 0      | 1      | 
|ram_1swsr_wfirst_gen: | sv_ram_reg | 2 K x 16(WRITE_FIRST)  | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_1swsr_wfirst_gen: | sv_ram_reg | 2 K x 16(WRITE_FIRST)  | W | R |                        |   |   | Port A           | 0      | 1      | 
|ram_2swsr_wfirst_gen: | sv_ram_reg | 2 K x 16(WRITE_FIRST)  | W | R | 2 K x 16(WRITE_FIRST)  | W | R | Port A and B     | 0      | 1      | 
|ram_2swsr_wfirst_gen: | sv_ram_reg | 2 K x 16(WRITE_FIRST)  | W | R | 2 K x 16(WRITE_FIRST)  | W | R | Port A and B     | 0      | 1      | 
+----------------------+------------+------------------------+---+---+------------------------+---+---+------------------+--------+--------+

Note: The table above is a preliminary report that shows the Block RAMs at the current stage of the synthesis flow. Some Block RAMs may be reimplemented as non Block RAM primitives later in the synthesis flow. Multiple instantiated Block RAMs are reported only once. 

Distributed RAM: Preliminary Mapping  Report (see note below)
+----------------+---------------------------------------+----------------+----------------------+--------------+
|Module Name     | RTL Object                            | Inference      | Size (Depth x Width) | Primitives   | 
+----------------+---------------------------------------+----------------+----------------------+--------------+
|fifo_2c_dram2:  | RAM/RAM_reg                           | User Attribute | 32 x 8               | RAM32M x 2   | 
|fifo_2c_dram2:  | RAM/RAM_reg                           | User Attribute | 32 x 8               | RAM32M x 2   | 
|sys_tst_sram_c7 | RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg | User Attribute | 32 x 8               | RAM32M x 2   | 
+----------------+---------------------------------------+----------------+----------------------+--------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP and Shift Register Reporting
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:07 ; elapsed = 00:01:12 . Memory (MB): peak = 1495.090 ; gain = 403.402 ; free physical = 1018 ; free virtual = 8463
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:01:09 ; elapsed = 00:01:14 . Memory (MB): peak = 1512.105 ; gain = 420.418 ; free physical = 1011 ; free virtual = 8457
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
INFO: [Synth 8-4480] The timing for the instance RLINK/CORE/RL/RTBUF/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance TST/SMEM_B3/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance TST/SMEM_B2/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance TST/SMEM_B1/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
INFO: [Synth 8-4480] The timing for the instance TST/SMEM_B0/sv_ram_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing.
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:01:11 ; elapsed = 00:01:17 . Memory (MB): peak = 1539.707 ; gain = 448.020 ; free physical = 1005 ; free virtual = 8451
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
INFO: [Synth 8-5365] Flop SRAMCTL/IOB_MEM_DATA/R_TE_reg is being inverted and renamed to SRAMCTL/IOB_MEM_DATA/R_TE_reg_inv.
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_DI_reg[0]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_DI_reg[1]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_DI_reg[2]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_DI_reg[3]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_DI_reg[4]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_DI_reg[5]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_DI_reg[6]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_DI_reg[7]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_DO_reg[0]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_DO_reg[1]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_DO_reg[2]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_DO_reg[3]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_DO_reg[4]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_DO_reg[5]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_DO_reg[6]  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_TE_reg_inv  to handle IOB=TRUE attribute
INFO: [Synth 8-4163] Replicating register \SRAMCTL/IOB_MEM_DATA/R_DO_reg[7]  to handle IOB=TRUE attribute
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:01:12 ; elapsed = 00:01:18 . Memory (MB): peak = 1539.707 ; gain = 448.020 ; free physical = 997 ; free virtual = 8451
---------------------------------------------------------------------------------

Report Check Netlist: 
+------+------------------+-------+---------+-------+------------------+
|      |Item              |Errors |Warnings |Status |Description       |
+------+------------------+-------+---------+-------+------------------+
|1     |multi_driven_nets |      0|        0|Passed |Multi driven nets |
+------+------------------+-------+---------+-------+------------------+
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:01:12 ; elapsed = 00:01:18 . Memory (MB): peak = 1539.707 ; gain = 448.020 ; free physical = 997 ; free virtual = 8451
---------------------------------------------------------------------------------

Report RTL Partitions: 
+-+--------------+------------+----------+
| |RTL Partition |Replication |Instances |
+-+--------------+------------+----------+
+-+--------------+------------+----------+
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:12 ; elapsed = 00:01:18 . Memory (MB): peak = 1539.707 ; gain = 448.020 ; free physical = 997 ; free virtual = 8451
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:01:12 ; elapsed = 00:01:18 . Memory (MB): peak = 1539.707 ; gain = 448.020 ; free physical = 997 ; free virtual = 8451
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:01:12 ; elapsed = 00:01:18 . Memory (MB): peak = 1539.707 ; gain = 448.020 ; free physical = 997 ; free virtual = 8451
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:01:12 ; elapsed = 00:01:18 . Memory (MB): peak = 1539.707 ; gain = 448.020 ; free physical = 997 ; free virtual = 8451
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+-------------+------+
|      |Cell         |Count |
+------+-------------+------+
|1     |BUFG         |     4|
|2     |CARRY4       |    37|
|3     |LUT1         |   100|
|4     |LUT2         |   233|
|5     |LUT3         |   228|
|6     |LUT4         |   178|
|7     |LUT5         |   344|
|8     |LUT6         |   602|
|9     |MMCME2_BASE  |     2|
|10    |RAM32M       |     6|
|11    |RAMB36E1     |     1|
|12    |RAMB36E1_1   |     2|
|13    |RAMB36E1_2   |     2|
|14    |USR_ACCESSE2 |     1|
|15    |XADC         |     1|
|16    |FDRE         |  1106|
|17    |FDSE         |    29|
|18    |IBUF         |     2|
|19    |IOBUF        |     8|
|20    |OBUF         |    28|
+------+-------------+------+

Report Instance Areas: 
+------+-----------------------+------------------------------+------+
|      |Instance               |Module                        |Cells |
+------+-----------------------+------------------------------+------+
|1     |top                    |                              |  2914|
|2     |  CLKDIV_CLK           |clkdivce                      |    42|
|3     |  CLKDIV_CLKS          |clkdivce__parameterized1      |    41|
|4     |  GEN_CLKSER           |s7_cmt_sfs__parameterized1    |     3|
|5     |  GEN_CLKSYS           |s7_cmt_sfs                    |     3|
|6     |  HIO                  |sn_humanio_emu_rbus           |    92|
|7     |  IOB_RS232            |bp_rs232_2line_iob            |     2|
|8     |    IOB_RXD            |iob_reg_i                     |     1|
|9     |      IOB              |iob_reg_i_gen                 |     1|
|10    |    IOB_TXD            |iob_reg_o_15                  |     1|
|11    |      IOB              |iob_reg_o_gen_16              |     1|
|12    |  RLINK                |rlink_sp2c                    |  1701|
|13    |    CORE               |rlink_core8                   |  1032|
|14    |      B2CD             |byte2cdata                    |    40|
|15    |      CD2B             |cdata2byte                    |    23|
|16    |      RL               |rlink_core                    |   969|
|17    |        DOFIFO         |fifo_1c_dram                  |    89|
|18    |          FIFO         |fifo_1c_dram_raw              |    89|
|19    |            RAM        |ram_1swar_1ar_gen_14          |    29|
|20    |        ICRC           |crc16                         |    41|
|21    |        OCRC           |crc16_13                      |    60|
|22    |        RTBUF          |ram_2swsr_rfirst_gen          |    35|
|23    |        SEL__0         |rb_sel                        |    43|
|24    |    SERPORT            |serport_2clock2               |   669|
|25    |      CDC_RESET        |cdc_pulse                     |     6|
|26    |      CDC_ENAXON       |cdc_signal_s1__1              |     2|
|27    |      CDC_ENAESC       |cdc_signal_s1__2              |     2|
|28    |      RXFIFO           |fifo_2c_dram2__1              |   108|
|29    |        GCR            |gray_cnt_gen_8                |    12|
|30    |          \GRAY_5.CNT  |gray_cnt_5_12                 |    12|
|31    |        GCW            |gray_cnt_gen_9                |    12|
|32    |          \GRAY_5.CNT  |gray_cnt_5_11                 |    12|
|33    |        RAM            |ram_1swar_1ar_gen_10          |     2|
|34    |      TXFIFO           |fifo_2c_dram2                 |   108|
|35    |        GCR            |gray_cnt_gen                  |    12|
|36    |          \GRAY_5.CNT  |gray_cnt_5_7                  |    12|
|37    |        GCW            |gray_cnt_gen_6                |    12|
|38    |          \GRAY_5.CNT  |gray_cnt_5                    |    12|
|39    |        RAM            |ram_1swar_1ar_gen             |     2|
|40    |      CDC_RXACT        |cdc_signal_s1__3              |     2|
|41    |      CDC_TXACT        |cdc_signal_s1__4              |     2|
|42    |      CDC_ABACT        |cdc_signal_s1__5              |     2|
|43    |      CDC_RXOK         |cdc_signal_s1__6              |     2|
|44    |      CDC_TXOK         |cdc_signal_s1                 |     2|
|45    |      CDC_CDIV         |cdc_vector_s0                 |    12|
|46    |      CDC_CDIVF        |cdc_vector_s0__parameterized1 |     3|
|47    |      CDC_RXERR        |cdc_pulse__parameterized1__1  |     9|
|48    |      CDC_RXOVR        |cdc_pulse__parameterized1__2  |     9|
|49    |      CDC_ABDONE       |cdc_pulse__parameterized1     |     9|
|50    |      UART             |serport_uart_rxtx_ab          |   305|
|51    |        AB             |serport_uart_autobaud         |    81|
|52    |        RXTX           |serport_uart_rxtx             |   224|
|53    |          RX           |serport_uart_rx               |   152|
|54    |          TX           |serport_uart_tx               |    72|
|55    |      XONRX            |serport_xonrx                 |    21|
|56    |      XONTX            |serport_xontx                 |    47|
|57    |  SMRB                 |sysmonx_rbus_base             |   133|
|58    |    SMRB               |sysmon_rbus_core              |   132|
|59    |  SRAMCTL              |c7_sram_memctl                |   217|
|60    |    IOB_MEM_ADDRB      |iob_reg_o_gen__parameterized3 |    10|
|61    |    IOB_MEM_ADDRW      |iob_reg_o_gen__parameterized1 |    17|
|62    |    IOB_MEM_CE         |iob_reg_o                     |     4|
|63    |      IOB              |iob_reg_o_gen_5               |     4|
|64    |    IOB_MEM_DATA       |iob_reg_io_gen                |    52|
|65    |    IOB_MEM_OE         |iob_reg_o_2                   |     2|
|66    |      IOB              |iob_reg_o_gen_4               |     2|
|67    |    IOB_MEM_WE         |iob_reg_o_3                   |     2|
|68    |      IOB              |iob_reg_o_gen                 |     2|
|69    |  TST                  |tst_sram                      |   633|
|70    |    SMEM_B0            |ram_2swsr_wfirst_gen          |    37|
|71    |    SMEM_B1            |ram_2swsr_wfirst_gen_0        |    33|
|72    |    SMEM_B2            |ram_1swsr_wfirst_gen          |    59|
|73    |    SMEM_B3            |ram_1swsr_wfirst_gen_1        |    23|
|74    |  UARB                 |rbd_usracc                    |     8|
|75    |    RBSEL              |rb_sel__parameterized1        |     1|
|76    |    UA                 |usr_access_unisim             |     7|
+------+-----------------------+------------------------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:01:12 ; elapsed = 00:01:18 . Memory (MB): peak = 1539.707 ; gain = 448.020 ; free physical = 997 ; free virtual = 8451
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 113 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:01:02 ; elapsed = 00:01:08 . Memory (MB): peak = 1539.707 ; gain = 163.066 ; free physical = 1055 ; free virtual = 8509
Synthesis Optimization Complete : Time (s): cpu = 00:01:12 ; elapsed = 00:01:18 . Memory (MB): peak = 1539.715 ; gain = 448.020 ; free physical = 1055 ; free virtual = 8509
INFO: [Project 1-571] Translating synthesized netlist
INFO: [Netlist 29-17] Analyzing 61 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 16 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 8 instances
  MMCME2_BASE => MMCME2_ADV: 2 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 6 instances

448 Infos, 237 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:16 ; elapsed = 00:01:21 . Memory (MB): peak = 1539.715 ; gain = 460.660 ; free physical = 1053 ; free virtual = 8508
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_sram/cmoda7/project_mflow/project_mflow.runs/synth_1/sys_tst_sram_c7.dcp' has been generated.
report_utilization: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1543.715 ; gain = 0.000 ; free physical = 1052 ; free virtual = 8507
INFO: [Common 17-206] Exiting Vivado at Sun Aug 26 13:27:20 2018...
