Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017
| Date         : Sun Aug 26 13:11:55 2018
| Host         : athome running 64-bit Ubuntu 16.04.5 LTS
| Command      : report_timing_summary -warn_on_violation -max_paths 10 -file sys_tst_rlink_arty_timing_summary_routed.rpt -rpx sys_tst_rlink_arty_timing_summary_routed.rpx
| Design       : sys_tst_rlink_arty
| Device       : 7a35ti-csg324
| Speed File   : -1L  PRODUCTION 1.17 2017-05-11
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  false

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
--------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock
--------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
--------------------------
 There is 1 input port with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
 There are 17 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
--------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops
------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      1.034        0.000                      0                 2833        0.062        0.000                      0                 2833        2.917        0.000                       0                  1142  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock       Waveform(ns)         Period(ns)      Frequency(MHz)
-----       ------------         ----------      --------------
I_CLK100    {0.000 5.000}        10.000          100.000         
  CLKFBOUT  {0.000 5.000}        10.000          100.000         
  CLKOUT0   {0.000 4.167}        8.333           120.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
I_CLK100                                                                                                                                                        3.000        0.000                       0                     1  
  CLKFBOUT                                                                                                                                                      7.845        0.000                       0                     3  
  CLKOUT0           1.034        0.000                      0                 2833        0.062        0.000                      0                 2833        2.917        0.000                       0                  1138  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  I_CLK100
  To Clock:  I_CLK100

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        3.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         I_CLK100
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { I_CLK100 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     MMCME2_ADV/CLKIN1  n/a            1.249         10.000      8.751      MMCME2_ADV_X1Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
Max Period        n/a     MMCME2_ADV/CLKIN1  n/a            100.000       10.000      90.000     MMCME2_ADV_X1Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
Low Pulse Width   Fast    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
Low Pulse Width   Slow    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
High Pulse Width  Slow    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
High Pulse Width  Fast    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  CLKFBOUT
  To Clock:  CLKFBOUT

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        7.845ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         CLKFBOUT
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFG/I               n/a            2.155         10.000      7.845      BUFGCTRL_X0Y17   GEN_CLKSYS/USEMMCM.BUFG_CLKFB/I
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         10.000      8.751      MMCME2_ADV_X1Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT
Min Period  n/a     MMCME2_ADV/CLKFBIN   n/a            1.249         10.000      8.751      MMCME2_ADV_X1Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKFBIN
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       10.000      90.000     MMCME2_ADV_X1Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKFBIN
Max Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            213.360       10.000      203.360    MMCME2_ADV_X1Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT



---------------------------------------------------------------------------------------------------
From Clock:  CLKOUT0
  To Clock:  CLKOUT0

Setup :            0  Failing Endpoints,  Worst Slack        1.034ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.062ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        2.917ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             1.034ns  (required time - arrival time)
  Source:                 RBDTST/EMON/BRAM/sv_ram_reg/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/EMON/BRAM/sv_ram_reg/DIBDI[9]
                            (rising edge-triggered cell RAMB18E1 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.759ns  (logic 4.216ns (62.379%)  route 2.543ns (37.621%))
  Logic Levels:           8  (CARRY4=7 LUT2=1)
  Clock Path Skew:        -0.026ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.457ns = ( 6.877 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.853ns
    Clock Pessimism Removal (CPR):    0.578ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.489     1.489 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.722    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.946    -4.224 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.563    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.467 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.614    -0.853    RBDTST/EMON/BRAM/CLKFX
    RAMB18_X0Y16         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X0Y16         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[1])
                                                      2.454     1.601 r  RBDTST/EMON/BRAM/sv_ram_reg/DOADO[1]
                         net (fo=2, routed)           0.966     2.567    RBDTST/EMON/BRAM_n_21
    SLICE_X8Y38          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.637     3.204 r  RBDTST/EMON/plusOp_inferred__0/i__carry/CO[3]
                         net (fo=1, routed)           0.000     3.204    RBDTST/EMON/plusOp_inferred__0/i__carry_n_0
    SLICE_X8Y39          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.321 r  RBDTST/EMON/plusOp_inferred__0/i__carry__0/CO[3]
                         net (fo=1, routed)           0.000     3.321    RBDTST/EMON/plusOp_inferred__0/i__carry__0_n_0
    SLICE_X8Y40          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.438 r  RBDTST/EMON/plusOp_inferred__0/i__carry__1/CO[3]
                         net (fo=1, routed)           0.000     3.438    RBDTST/EMON/plusOp_inferred__0/i__carry__1_n_0
    SLICE_X8Y41          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.555 r  RBDTST/EMON/plusOp_inferred__0/i__carry__2/CO[3]
                         net (fo=1, routed)           0.000     3.555    RBDTST/EMON/plusOp_inferred__0/i__carry__2_n_0
    SLICE_X8Y42          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.672 r  RBDTST/EMON/plusOp_inferred__0/i__carry__3/CO[3]
                         net (fo=1, routed)           0.000     3.672    RBDTST/EMON/plusOp_inferred__0/i__carry__3_n_0
    SLICE_X8Y43          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117     3.789 r  RBDTST/EMON/plusOp_inferred__0/i__carry__4/CO[3]
                         net (fo=1, routed)           0.000     3.789    RBDTST/EMON/plusOp_inferred__0/i__carry__4_n_0
    SLICE_X8Y44          CARRY4 (Prop_carry4_CI_O[0])
                                                      0.219     4.008 r  RBDTST/EMON/plusOp_inferred__0/i__carry__5/O[0]
                         net (fo=1, routed)           0.745     4.753    RBDTST/EMON/BRAM/plusOp[24]
    SLICE_X9Y43          LUT2 (Prop_lut2_I0_O)        0.321     5.074 r  RBDTST/EMON/BRAM/sv_ram_reg_i_23__0/O
                         net (fo=1, routed)           0.832     5.906    RBDTST/EMON/BRAM/BRAM_DIB[25]
    RAMB18_X0Y16         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/DIBDI[9]
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.418     9.752 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.914    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.204     3.710 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     5.291    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.382 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.495     6.877    RBDTST/EMON/BRAM/CLKFX
    RAMB18_X0Y16         RAMB18E1                                     r  RBDTST/EMON/BRAM/sv_ram_reg/CLKBWRCLK
                         clock pessimism              0.578     7.454    
                         clock uncertainty           -0.066     7.389    
    RAMB18_X0Y16         RAMB18E1 (Setup_ramb18e1_CLKBWRCLK_DIBDI[9])
                                                     -0.449     6.940    RBDTST/EMON/BRAM/sv_ram_reg
  -------------------------------------------------------------------
                         required time                          6.940    
                         arrival time                          -5.906    
  -------------------------------------------------------------------
                         slack                                  1.034    

Slack (MET) :             1.070ns  (required time - arrival time)
  Source:                 SMRB.I0/SM/DCLK
                            (rising edge-triggered cell XADC clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[rtaddrb][4]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.910ns  (logic 1.948ns (28.192%)  route 4.962ns (71.808%))
  Logic Levels:           6  (LUT3=1 LUT6=5)
  Clock Path Skew:        -0.083ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.502ns = ( 6.831 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.935ns
    Clock Pessimism Removal (CPR):    0.485ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.489     1.489 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.722    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.946    -4.224 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.563    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.467 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.532    -0.935    SMRB.I0/CLKFX
    XADC_X0Y0            XADC                                         r  SMRB.I0/SM/DCLK
  -------------------------------------------------------------------    -------------------
    XADC_X0Y0            XADC (Prop_xadc_DCLK_DRDY)
                                                      1.204     0.269 r  SMRB.I0/SM/DRDY
                         net (fo=5, routed)           1.221     1.490    SMRB.I0/SMRB/SM_DRDY
    SLICE_X35Y72         LUT6 (Prop_lut6_I1_O)        0.124     1.614 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_6/O
                         net (fo=1, routed)           0.308     1.922    SMRB.I0/SMRB/R_REGS[rbtout]_i_6_n_0
    SLICE_X36Y72         LUT6 (Prop_lut6_I5_O)        0.124     2.046 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           1.189     3.236    RLINK/CORE/RL/RTBUF/RB_SRES_SYSMON[busy]
    SLICE_X42Y48         LUT6 (Prop_lut6_I3_O)        0.124     3.360 r  RLINK/CORE/RL/RTBUF/FSM_onehot_R_LREGS[state][29]_i_11/O
                         net (fo=3, routed)           0.759     4.119    RLINK/CORE/RL/RTBUF/iwdone
    SLICE_X47Y40         LUT6 (Prop_lut6_I4_O)        0.124     4.243 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_36/O
                         net (fo=1, routed)           0.304     4.547    RLINK/CORE/RL/RTBUF/sv_ram_reg_i_36_n_0
    SLICE_X47Y39         LUT6 (Prop_lut6_I4_O)        0.124     4.671 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_15/O
                         net (fo=4, routed)           0.687     5.357    RLINK/CORE/RL/RTBUF_n_10
    SLICE_X48Y37         LUT3 (Prop_lut3_I1_O)        0.124     5.481 r  RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2/O
                         net (fo=12, routed)          0.493     5.975    RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2_n_0
    SLICE_X48Y35         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][4]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.418     9.752 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.914    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.204     3.710 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     5.291    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.382 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.449     6.831    RLINK/CORE/RL/CLKFX
    SLICE_X48Y35         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][4]/C
                         clock pessimism              0.485     7.316    
                         clock uncertainty           -0.066     7.250    
    SLICE_X48Y35         FDRE (Setup_fdre_C_CE)      -0.205     7.045    RLINK/CORE/RL/R_LREGS_reg[rtaddrb][4]
  -------------------------------------------------------------------
                         required time                          7.045    
                         arrival time                          -5.975    
  -------------------------------------------------------------------
                         slack                                  1.070    

Slack (MET) :             1.070ns  (required time - arrival time)
  Source:                 SMRB.I0/SM/DCLK
                            (rising edge-triggered cell XADC clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[rtaddrb][5]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.910ns  (logic 1.948ns (28.192%)  route 4.962ns (71.808%))
  Logic Levels:           6  (LUT3=1 LUT6=5)
  Clock Path Skew:        -0.083ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.502ns = ( 6.831 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.935ns
    Clock Pessimism Removal (CPR):    0.485ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.489     1.489 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.722    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.946    -4.224 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.563    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.467 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.532    -0.935    SMRB.I0/CLKFX
    XADC_X0Y0            XADC                                         r  SMRB.I0/SM/DCLK
  -------------------------------------------------------------------    -------------------
    XADC_X0Y0            XADC (Prop_xadc_DCLK_DRDY)
                                                      1.204     0.269 r  SMRB.I0/SM/DRDY
                         net (fo=5, routed)           1.221     1.490    SMRB.I0/SMRB/SM_DRDY
    SLICE_X35Y72         LUT6 (Prop_lut6_I1_O)        0.124     1.614 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_6/O
                         net (fo=1, routed)           0.308     1.922    SMRB.I0/SMRB/R_REGS[rbtout]_i_6_n_0
    SLICE_X36Y72         LUT6 (Prop_lut6_I5_O)        0.124     2.046 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           1.189     3.236    RLINK/CORE/RL/RTBUF/RB_SRES_SYSMON[busy]
    SLICE_X42Y48         LUT6 (Prop_lut6_I3_O)        0.124     3.360 r  RLINK/CORE/RL/RTBUF/FSM_onehot_R_LREGS[state][29]_i_11/O
                         net (fo=3, routed)           0.759     4.119    RLINK/CORE/RL/RTBUF/iwdone
    SLICE_X47Y40         LUT6 (Prop_lut6_I4_O)        0.124     4.243 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_36/O
                         net (fo=1, routed)           0.304     4.547    RLINK/CORE/RL/RTBUF/sv_ram_reg_i_36_n_0
    SLICE_X47Y39         LUT6 (Prop_lut6_I4_O)        0.124     4.671 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_15/O
                         net (fo=4, routed)           0.687     5.357    RLINK/CORE/RL/RTBUF_n_10
    SLICE_X48Y37         LUT3 (Prop_lut3_I1_O)        0.124     5.481 r  RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2/O
                         net (fo=12, routed)          0.493     5.975    RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2_n_0
    SLICE_X48Y35         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][5]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.418     9.752 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.914    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.204     3.710 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     5.291    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.382 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.449     6.831    RLINK/CORE/RL/CLKFX
    SLICE_X48Y35         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][5]/C
                         clock pessimism              0.485     7.316    
                         clock uncertainty           -0.066     7.250    
    SLICE_X48Y35         FDRE (Setup_fdre_C_CE)      -0.205     7.045    RLINK/CORE/RL/R_LREGS_reg[rtaddrb][5]
  -------------------------------------------------------------------
                         required time                          7.045    
                         arrival time                          -5.975    
  -------------------------------------------------------------------
                         slack                                  1.070    

Slack (MET) :             1.070ns  (required time - arrival time)
  Source:                 SMRB.I0/SM/DCLK
                            (rising edge-triggered cell XADC clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[rtaddrb][6]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.910ns  (logic 1.948ns (28.192%)  route 4.962ns (71.808%))
  Logic Levels:           6  (LUT3=1 LUT6=5)
  Clock Path Skew:        -0.083ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.502ns = ( 6.831 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.935ns
    Clock Pessimism Removal (CPR):    0.485ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.489     1.489 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.722    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.946    -4.224 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.563    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.467 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.532    -0.935    SMRB.I0/CLKFX
    XADC_X0Y0            XADC                                         r  SMRB.I0/SM/DCLK
  -------------------------------------------------------------------    -------------------
    XADC_X0Y0            XADC (Prop_xadc_DCLK_DRDY)
                                                      1.204     0.269 r  SMRB.I0/SM/DRDY
                         net (fo=5, routed)           1.221     1.490    SMRB.I0/SMRB/SM_DRDY
    SLICE_X35Y72         LUT6 (Prop_lut6_I1_O)        0.124     1.614 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_6/O
                         net (fo=1, routed)           0.308     1.922    SMRB.I0/SMRB/R_REGS[rbtout]_i_6_n_0
    SLICE_X36Y72         LUT6 (Prop_lut6_I5_O)        0.124     2.046 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           1.189     3.236    RLINK/CORE/RL/RTBUF/RB_SRES_SYSMON[busy]
    SLICE_X42Y48         LUT6 (Prop_lut6_I3_O)        0.124     3.360 r  RLINK/CORE/RL/RTBUF/FSM_onehot_R_LREGS[state][29]_i_11/O
                         net (fo=3, routed)           0.759     4.119    RLINK/CORE/RL/RTBUF/iwdone
    SLICE_X47Y40         LUT6 (Prop_lut6_I4_O)        0.124     4.243 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_36/O
                         net (fo=1, routed)           0.304     4.547    RLINK/CORE/RL/RTBUF/sv_ram_reg_i_36_n_0
    SLICE_X47Y39         LUT6 (Prop_lut6_I4_O)        0.124     4.671 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_15/O
                         net (fo=4, routed)           0.687     5.357    RLINK/CORE/RL/RTBUF_n_10
    SLICE_X48Y37         LUT3 (Prop_lut3_I1_O)        0.124     5.481 r  RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2/O
                         net (fo=12, routed)          0.493     5.975    RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2_n_0
    SLICE_X48Y35         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][6]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.418     9.752 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.914    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.204     3.710 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     5.291    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.382 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.449     6.831    RLINK/CORE/RL/CLKFX
    SLICE_X48Y35         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][6]/C
                         clock pessimism              0.485     7.316    
                         clock uncertainty           -0.066     7.250    
    SLICE_X48Y35         FDRE (Setup_fdre_C_CE)      -0.205     7.045    RLINK/CORE/RL/R_LREGS_reg[rtaddrb][6]
  -------------------------------------------------------------------
                         required time                          7.045    
                         arrival time                          -5.975    
  -------------------------------------------------------------------
                         slack                                  1.070    

Slack (MET) :             1.070ns  (required time - arrival time)
  Source:                 SMRB.I0/SM/DCLK
                            (rising edge-triggered cell XADC clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[rtaddrb][7]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.910ns  (logic 1.948ns (28.192%)  route 4.962ns (71.808%))
  Logic Levels:           6  (LUT3=1 LUT6=5)
  Clock Path Skew:        -0.083ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.502ns = ( 6.831 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.935ns
    Clock Pessimism Removal (CPR):    0.485ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.489     1.489 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.722    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.946    -4.224 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.563    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.467 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.532    -0.935    SMRB.I0/CLKFX
    XADC_X0Y0            XADC                                         r  SMRB.I0/SM/DCLK
  -------------------------------------------------------------------    -------------------
    XADC_X0Y0            XADC (Prop_xadc_DCLK_DRDY)
                                                      1.204     0.269 r  SMRB.I0/SM/DRDY
                         net (fo=5, routed)           1.221     1.490    SMRB.I0/SMRB/SM_DRDY
    SLICE_X35Y72         LUT6 (Prop_lut6_I1_O)        0.124     1.614 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_6/O
                         net (fo=1, routed)           0.308     1.922    SMRB.I0/SMRB/R_REGS[rbtout]_i_6_n_0
    SLICE_X36Y72         LUT6 (Prop_lut6_I5_O)        0.124     2.046 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           1.189     3.236    RLINK/CORE/RL/RTBUF/RB_SRES_SYSMON[busy]
    SLICE_X42Y48         LUT6 (Prop_lut6_I3_O)        0.124     3.360 r  RLINK/CORE/RL/RTBUF/FSM_onehot_R_LREGS[state][29]_i_11/O
                         net (fo=3, routed)           0.759     4.119    RLINK/CORE/RL/RTBUF/iwdone
    SLICE_X47Y40         LUT6 (Prop_lut6_I4_O)        0.124     4.243 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_36/O
                         net (fo=1, routed)           0.304     4.547    RLINK/CORE/RL/RTBUF/sv_ram_reg_i_36_n_0
    SLICE_X47Y39         LUT6 (Prop_lut6_I4_O)        0.124     4.671 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_15/O
                         net (fo=4, routed)           0.687     5.357    RLINK/CORE/RL/RTBUF_n_10
    SLICE_X48Y37         LUT3 (Prop_lut3_I1_O)        0.124     5.481 r  RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2/O
                         net (fo=12, routed)          0.493     5.975    RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2_n_0
    SLICE_X48Y35         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.418     9.752 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.914    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.204     3.710 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     5.291    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.382 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.449     6.831    RLINK/CORE/RL/CLKFX
    SLICE_X48Y35         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][7]/C
                         clock pessimism              0.485     7.316    
                         clock uncertainty           -0.066     7.250    
    SLICE_X48Y35         FDRE (Setup_fdre_C_CE)      -0.205     7.045    RLINK/CORE/RL/R_LREGS_reg[rtaddrb][7]
  -------------------------------------------------------------------
                         required time                          7.045    
                         arrival time                          -5.975    
  -------------------------------------------------------------------
                         slack                                  1.070    

Slack (MET) :             1.078ns  (required time - arrival time)
  Source:                 SMRB.I0/SM/DCLK
                            (rising edge-triggered cell XADC clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[rtaddrb][0]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.901ns  (logic 1.948ns (28.227%)  route 4.953ns (71.773%))
  Logic Levels:           6  (LUT3=1 LUT6=5)
  Clock Path Skew:        -0.084ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.503ns = ( 6.830 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.935ns
    Clock Pessimism Removal (CPR):    0.485ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.489     1.489 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.722    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.946    -4.224 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.563    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.467 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.532    -0.935    SMRB.I0/CLKFX
    XADC_X0Y0            XADC                                         r  SMRB.I0/SM/DCLK
  -------------------------------------------------------------------    -------------------
    XADC_X0Y0            XADC (Prop_xadc_DCLK_DRDY)
                                                      1.204     0.269 r  SMRB.I0/SM/DRDY
                         net (fo=5, routed)           1.221     1.490    SMRB.I0/SMRB/SM_DRDY
    SLICE_X35Y72         LUT6 (Prop_lut6_I1_O)        0.124     1.614 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_6/O
                         net (fo=1, routed)           0.308     1.922    SMRB.I0/SMRB/R_REGS[rbtout]_i_6_n_0
    SLICE_X36Y72         LUT6 (Prop_lut6_I5_O)        0.124     2.046 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           1.189     3.236    RLINK/CORE/RL/RTBUF/RB_SRES_SYSMON[busy]
    SLICE_X42Y48         LUT6 (Prop_lut6_I3_O)        0.124     3.360 r  RLINK/CORE/RL/RTBUF/FSM_onehot_R_LREGS[state][29]_i_11/O
                         net (fo=3, routed)           0.759     4.119    RLINK/CORE/RL/RTBUF/iwdone
    SLICE_X47Y40         LUT6 (Prop_lut6_I4_O)        0.124     4.243 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_36/O
                         net (fo=1, routed)           0.304     4.547    RLINK/CORE/RL/RTBUF/sv_ram_reg_i_36_n_0
    SLICE_X47Y39         LUT6 (Prop_lut6_I4_O)        0.124     4.671 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_15/O
                         net (fo=4, routed)           0.687     5.357    RLINK/CORE/RL/RTBUF_n_10
    SLICE_X48Y37         LUT3 (Prop_lut3_I1_O)        0.124     5.481 r  RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2/O
                         net (fo=12, routed)          0.485     5.966    RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2_n_0
    SLICE_X48Y34         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][0]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.418     9.752 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.914    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.204     3.710 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     5.291    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.382 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.448     6.830    RLINK/CORE/RL/CLKFX
    SLICE_X48Y34         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][0]/C
                         clock pessimism              0.485     7.315    
                         clock uncertainty           -0.066     7.249    
    SLICE_X48Y34         FDRE (Setup_fdre_C_CE)      -0.205     7.044    RLINK/CORE/RL/R_LREGS_reg[rtaddrb][0]
  -------------------------------------------------------------------
                         required time                          7.044    
                         arrival time                          -5.966    
  -------------------------------------------------------------------
                         slack                                  1.078    

Slack (MET) :             1.078ns  (required time - arrival time)
  Source:                 SMRB.I0/SM/DCLK
                            (rising edge-triggered cell XADC clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[rtaddrb][1]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.901ns  (logic 1.948ns (28.227%)  route 4.953ns (71.773%))
  Logic Levels:           6  (LUT3=1 LUT6=5)
  Clock Path Skew:        -0.084ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.503ns = ( 6.830 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.935ns
    Clock Pessimism Removal (CPR):    0.485ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.489     1.489 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.722    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.946    -4.224 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.563    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.467 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.532    -0.935    SMRB.I0/CLKFX
    XADC_X0Y0            XADC                                         r  SMRB.I0/SM/DCLK
  -------------------------------------------------------------------    -------------------
    XADC_X0Y0            XADC (Prop_xadc_DCLK_DRDY)
                                                      1.204     0.269 r  SMRB.I0/SM/DRDY
                         net (fo=5, routed)           1.221     1.490    SMRB.I0/SMRB/SM_DRDY
    SLICE_X35Y72         LUT6 (Prop_lut6_I1_O)        0.124     1.614 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_6/O
                         net (fo=1, routed)           0.308     1.922    SMRB.I0/SMRB/R_REGS[rbtout]_i_6_n_0
    SLICE_X36Y72         LUT6 (Prop_lut6_I5_O)        0.124     2.046 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           1.189     3.236    RLINK/CORE/RL/RTBUF/RB_SRES_SYSMON[busy]
    SLICE_X42Y48         LUT6 (Prop_lut6_I3_O)        0.124     3.360 r  RLINK/CORE/RL/RTBUF/FSM_onehot_R_LREGS[state][29]_i_11/O
                         net (fo=3, routed)           0.759     4.119    RLINK/CORE/RL/RTBUF/iwdone
    SLICE_X47Y40         LUT6 (Prop_lut6_I4_O)        0.124     4.243 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_36/O
                         net (fo=1, routed)           0.304     4.547    RLINK/CORE/RL/RTBUF/sv_ram_reg_i_36_n_0
    SLICE_X47Y39         LUT6 (Prop_lut6_I4_O)        0.124     4.671 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_15/O
                         net (fo=4, routed)           0.687     5.357    RLINK/CORE/RL/RTBUF_n_10
    SLICE_X48Y37         LUT3 (Prop_lut3_I1_O)        0.124     5.481 r  RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2/O
                         net (fo=12, routed)          0.485     5.966    RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2_n_0
    SLICE_X48Y34         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][1]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.418     9.752 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.914    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.204     3.710 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     5.291    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.382 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.448     6.830    RLINK/CORE/RL/CLKFX
    SLICE_X48Y34         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][1]/C
                         clock pessimism              0.485     7.315    
                         clock uncertainty           -0.066     7.249    
    SLICE_X48Y34         FDRE (Setup_fdre_C_CE)      -0.205     7.044    RLINK/CORE/RL/R_LREGS_reg[rtaddrb][1]
  -------------------------------------------------------------------
                         required time                          7.044    
                         arrival time                          -5.966    
  -------------------------------------------------------------------
                         slack                                  1.078    

Slack (MET) :             1.078ns  (required time - arrival time)
  Source:                 SMRB.I0/SM/DCLK
                            (rising edge-triggered cell XADC clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[rtaddrb][2]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.901ns  (logic 1.948ns (28.227%)  route 4.953ns (71.773%))
  Logic Levels:           6  (LUT3=1 LUT6=5)
  Clock Path Skew:        -0.084ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.503ns = ( 6.830 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.935ns
    Clock Pessimism Removal (CPR):    0.485ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.489     1.489 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.722    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.946    -4.224 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.563    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.467 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.532    -0.935    SMRB.I0/CLKFX
    XADC_X0Y0            XADC                                         r  SMRB.I0/SM/DCLK
  -------------------------------------------------------------------    -------------------
    XADC_X0Y0            XADC (Prop_xadc_DCLK_DRDY)
                                                      1.204     0.269 r  SMRB.I0/SM/DRDY
                         net (fo=5, routed)           1.221     1.490    SMRB.I0/SMRB/SM_DRDY
    SLICE_X35Y72         LUT6 (Prop_lut6_I1_O)        0.124     1.614 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_6/O
                         net (fo=1, routed)           0.308     1.922    SMRB.I0/SMRB/R_REGS[rbtout]_i_6_n_0
    SLICE_X36Y72         LUT6 (Prop_lut6_I5_O)        0.124     2.046 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           1.189     3.236    RLINK/CORE/RL/RTBUF/RB_SRES_SYSMON[busy]
    SLICE_X42Y48         LUT6 (Prop_lut6_I3_O)        0.124     3.360 r  RLINK/CORE/RL/RTBUF/FSM_onehot_R_LREGS[state][29]_i_11/O
                         net (fo=3, routed)           0.759     4.119    RLINK/CORE/RL/RTBUF/iwdone
    SLICE_X47Y40         LUT6 (Prop_lut6_I4_O)        0.124     4.243 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_36/O
                         net (fo=1, routed)           0.304     4.547    RLINK/CORE/RL/RTBUF/sv_ram_reg_i_36_n_0
    SLICE_X47Y39         LUT6 (Prop_lut6_I4_O)        0.124     4.671 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_15/O
                         net (fo=4, routed)           0.687     5.357    RLINK/CORE/RL/RTBUF_n_10
    SLICE_X48Y37         LUT3 (Prop_lut3_I1_O)        0.124     5.481 r  RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2/O
                         net (fo=12, routed)          0.485     5.966    RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2_n_0
    SLICE_X48Y34         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][2]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.418     9.752 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.914    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.204     3.710 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     5.291    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.382 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.448     6.830    RLINK/CORE/RL/CLKFX
    SLICE_X48Y34         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][2]/C
                         clock pessimism              0.485     7.315    
                         clock uncertainty           -0.066     7.249    
    SLICE_X48Y34         FDRE (Setup_fdre_C_CE)      -0.205     7.044    RLINK/CORE/RL/R_LREGS_reg[rtaddrb][2]
  -------------------------------------------------------------------
                         required time                          7.044    
                         arrival time                          -5.966    
  -------------------------------------------------------------------
                         slack                                  1.078    

Slack (MET) :             1.078ns  (required time - arrival time)
  Source:                 SMRB.I0/SM/DCLK
                            (rising edge-triggered cell XADC clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[rtaddrb][3]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.901ns  (logic 1.948ns (28.227%)  route 4.953ns (71.773%))
  Logic Levels:           6  (LUT3=1 LUT6=5)
  Clock Path Skew:        -0.084ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.503ns = ( 6.830 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.935ns
    Clock Pessimism Removal (CPR):    0.485ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.489     1.489 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.722    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.946    -4.224 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.563    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.467 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.532    -0.935    SMRB.I0/CLKFX
    XADC_X0Y0            XADC                                         r  SMRB.I0/SM/DCLK
  -------------------------------------------------------------------    -------------------
    XADC_X0Y0            XADC (Prop_xadc_DCLK_DRDY)
                                                      1.204     0.269 r  SMRB.I0/SM/DRDY
                         net (fo=5, routed)           1.221     1.490    SMRB.I0/SMRB/SM_DRDY
    SLICE_X35Y72         LUT6 (Prop_lut6_I1_O)        0.124     1.614 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_6/O
                         net (fo=1, routed)           0.308     1.922    SMRB.I0/SMRB/R_REGS[rbtout]_i_6_n_0
    SLICE_X36Y72         LUT6 (Prop_lut6_I5_O)        0.124     2.046 f  SMRB.I0/SMRB/R_REGS[rbtout]_i_2/O
                         net (fo=3, routed)           1.189     3.236    RLINK/CORE/RL/RTBUF/RB_SRES_SYSMON[busy]
    SLICE_X42Y48         LUT6 (Prop_lut6_I3_O)        0.124     3.360 r  RLINK/CORE/RL/RTBUF/FSM_onehot_R_LREGS[state][29]_i_11/O
                         net (fo=3, routed)           0.759     4.119    RLINK/CORE/RL/RTBUF/iwdone
    SLICE_X47Y40         LUT6 (Prop_lut6_I4_O)        0.124     4.243 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_36/O
                         net (fo=1, routed)           0.304     4.547    RLINK/CORE/RL/RTBUF/sv_ram_reg_i_36_n_0
    SLICE_X47Y39         LUT6 (Prop_lut6_I4_O)        0.124     4.671 r  RLINK/CORE/RL/RTBUF/sv_ram_reg_i_15/O
                         net (fo=4, routed)           0.687     5.357    RLINK/CORE/RL/RTBUF_n_10
    SLICE_X48Y37         LUT3 (Prop_lut3_I1_O)        0.124     5.481 r  RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2/O
                         net (fo=12, routed)          0.485     5.966    RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2_n_0
    SLICE_X48Y34         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][3]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.418     9.752 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.914    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.204     3.710 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     5.291    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.382 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.448     6.830    RLINK/CORE/RL/CLKFX
    SLICE_X48Y34         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[rtaddrb][3]/C
                         clock pessimism              0.485     7.315    
                         clock uncertainty           -0.066     7.249    
    SLICE_X48Y34         FDRE (Setup_fdre_C_CE)      -0.205     7.044    RLINK/CORE/RL/R_LREGS_reg[rtaddrb][3]
  -------------------------------------------------------------------
                         required time                          7.044    
                         arrival time                          -5.966    
  -------------------------------------------------------------------
                         slack                                  1.078    

Slack (MET) :             1.092ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/EMON/R_REGS_reg[laddr][7]/CE
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            8.333ns  (CLKOUT0 rise@8.333ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        6.584ns  (logic 0.821ns (12.469%)  route 5.763ns (87.531%))
  Logic Levels:           2  (LUT6=2)
  Clock Path Skew:        -0.386ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.503ns = ( 6.830 - 8.333 ) 
    Source Clock Delay      (SCD):    -0.632ns
    Clock Pessimism Removal (CPR):    0.485ns
  Clock Uncertainty:      0.066ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.110ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.489     1.489 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.722    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.946    -4.224 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.661    -2.563    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.467 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.835    -0.632    IOB_RS232/IOB_RXD/IOB/CLKFX
    ILOGIC_X0Y121        FDRE                                         r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y121        FDRE (Prop_fdre_C_Q)         0.517    -0.115 f  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=24, routed)          4.663     4.548    RBDTST/EMON/RXD
    SLICE_X30Y42         LUT6 (Prop_lut6_I4_O)        0.180     4.728 r  RBDTST/EMON//i___2/O
                         net (fo=10, routed)          0.494     5.222    RLINK/CORE/RL/laddr_clr
    SLICE_X29Y40         LUT6 (Prop_lut6_I4_O)        0.124     5.346 r  RLINK/CORE/RL/R_REGS[laddr][8]_i_1/O
                         net (fo=9, routed)           0.606     5.952    RBDTST/EMON/R_LREGS_reg[addr][1]
    SLICE_X29Y40         FDRE                                         r  RBDTST/EMON/R_REGS_reg[laddr][7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    8.333     8.333 r  
    E3                                                0.000     8.333 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     8.333    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.418     9.752 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    10.914    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.204     3.710 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.581     5.291    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     5.382 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        1.448     6.830    RBDTST/EMON/CLKFX
    SLICE_X29Y40         FDRE                                         r  RBDTST/EMON/R_REGS_reg[laddr][7]/C
                         clock pessimism              0.485     7.315    
                         clock uncertainty           -0.066     7.249    
    SLICE_X29Y40         FDRE (Setup_fdre_C_CE)      -0.205     7.044    RBDTST/EMON/R_REGS_reg[laddr][7]
  -------------------------------------------------------------------
                         required time                          7.044    
                         arrival time                          -5.952    
  -------------------------------------------------------------------
                         slack                                  1.092    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.062ns  (arrival time - required time)
  Source:                 RBDTST/TEST/R_REGS_reg[cntcyc][3]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/TEST/R_REGS_reg[ncyc][3]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.409ns  (logic 0.141ns (34.513%)  route 0.268ns (65.487%))
  Logic Levels:           0  
  Clock Path Skew:        0.277ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.819ns
    Source Clock Delay      (SCD):    -0.588ns
    Clock Pessimism Removal (CPR):    -0.508ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.257     0.257 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.697    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.356    -1.659 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.173    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.147 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.559    -0.588    RBDTST/TEST/CLKFX
    SLICE_X39Y54         FDRE                                         r  RBDTST/TEST/R_REGS_reg[cntcyc][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y54         FDRE (Prop_fdre_C_Q)         0.141    -0.447 r  RBDTST/TEST/R_REGS_reg[cntcyc][3]/Q
                         net (fo=5, routed)           0.268    -0.180    RBDTST/TEST/R_REGS_reg[cntcyc][3]
    SLICE_X40Y49         FDRE                                         r  RBDTST/TEST/R_REGS_reg[ncyc][3]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.445     0.445 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.925    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.138    -2.213 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.684    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.655 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.836    -0.819    RBDTST/TEST/CLKFX
    SLICE_X40Y49         FDRE                                         r  RBDTST/TEST/R_REGS_reg[ncyc][3]/C
                         clock pessimism              0.508    -0.311    
    SLICE_X40Y49         FDRE (Hold_fdre_C_D)         0.070    -0.241    RBDTST/TEST/R_REGS_reg[ncyc][3]
  -------------------------------------------------------------------
                         required time                          0.241    
                         arrival time                          -0.180    
  -------------------------------------------------------------------
                         slack                                  0.062    

Slack (MET) :             0.076ns  (arrival time - required time)
  Source:                 RBDTST/TEST/R_REGS_reg[cntcyc][2]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RBDTST/TEST/R_REGS_reg[ncyc][2]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.418ns  (logic 0.141ns (33.696%)  route 0.277ns (66.304%))
  Logic Levels:           0  
  Clock Path Skew:        0.277ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.819ns
    Source Clock Delay      (SCD):    -0.588ns
    Clock Pessimism Removal (CPR):    -0.508ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.257     0.257 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.697    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.356    -1.659 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.173    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.147 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.559    -0.588    RBDTST/TEST/CLKFX
    SLICE_X39Y54         FDRE                                         r  RBDTST/TEST/R_REGS_reg[cntcyc][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y54         FDRE (Prop_fdre_C_Q)         0.141    -0.447 r  RBDTST/TEST/R_REGS_reg[cntcyc][2]/Q
                         net (fo=6, routed)           0.277    -0.170    RBDTST/TEST/R_REGS_reg[cntcyc][2]
    SLICE_X40Y49         FDRE                                         r  RBDTST/TEST/R_REGS_reg[ncyc][2]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.445     0.445 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.925    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.138    -2.213 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.684    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.655 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.836    -0.819    RBDTST/TEST/CLKFX
    SLICE_X40Y49         FDRE                                         r  RBDTST/TEST/R_REGS_reg[ncyc][2]/C
                         clock pessimism              0.508    -0.311    
    SLICE_X40Y49         FDRE (Hold_fdre_C_D)         0.066    -0.245    RBDTST/TEST/R_REGS_reg[ncyc][2]
  -------------------------------------------------------------------
                         required time                          0.245    
                         arrival time                          -0.170    
  -------------------------------------------------------------------
                         slack                                  0.076    

Slack (MET) :             0.083ns  (arrival time - required time)
  Source:                 RLINK/CORE/B2CD/R_REGS_reg[data][5]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[addr][5]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.418ns  (logic 0.141ns (33.701%)  route 0.277ns (66.299%))
  Logic Levels:           0  
  Clock Path Skew:        0.276ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.820ns
    Source Clock Delay      (SCD):    -0.588ns
    Clock Pessimism Removal (CPR):    -0.508ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.257     0.257 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.697    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.356    -1.659 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.173    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.147 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.559    -0.588    RLINK/CORE/B2CD/CLKFX
    SLICE_X43Y56         FDRE                                         r  RLINK/CORE/B2CD/R_REGS_reg[data][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X43Y56         FDRE (Prop_fdre_C_Q)         0.141    -0.447 r  RLINK/CORE/B2CD/R_REGS_reg[data][5]/Q
                         net (fo=17, routed)          0.277    -0.170    RLINK/CORE/RL/Q[5]
    SLICE_X38Y49         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[addr][5]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.445     0.445 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.925    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.138    -2.213 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.684    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.655 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.835    -0.820    RLINK/CORE/RL/CLKFX
    SLICE_X38Y49         FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[addr][5]/C
                         clock pessimism              0.508    -0.312    
    SLICE_X38Y49         FDRE (Hold_fdre_C_D)         0.059    -0.253    RLINK/CORE/RL/R_LREGS_reg[addr][5]
  -------------------------------------------------------------------
                         required time                          0.253    
                         arrival time                          -0.170    
  -------------------------------------------------------------------
                         slack                                  0.083    

Slack (MET) :             0.088ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/FSM_onehot_R_BREGS_reg[state][7]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/FSM_onehot_R_BREGS_reg[state][0]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.444ns  (logic 0.209ns (47.040%)  route 0.235ns (52.960%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.264ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.825ns
    Source Clock Delay      (SCD):    -0.581ns
    Clock Pessimism Removal (CPR):    -0.508ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.257     0.257 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.697    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.356    -1.659 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.173    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.147 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.566    -0.581    RLINK/CORE/RL/CLKFX
    SLICE_X42Y49         FDRE                                         r  RLINK/CORE/RL/FSM_onehot_R_BREGS_reg[state][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X42Y49         FDRE (Prop_fdre_C_Q)         0.164    -0.417 f  RLINK/CORE/RL/FSM_onehot_R_BREGS_reg[state][7]/Q
                         net (fo=7, routed)           0.235    -0.182    RLINK/CORE/RL/FSM_onehot_R_BREGS_reg[state_n_0_][7]
    SLICE_X43Y50         LUT6 (Prop_lut6_I1_O)        0.045    -0.137 r  RLINK/CORE/RL/FSM_onehot_R_BREGS[state][0]_i_1/O
                         net (fo=1, routed)           0.000    -0.137    RLINK/CORE/RL/FSM_onehot_R_BREGS[state][0]_i_1_n_0
    SLICE_X43Y50         FDRE                                         r  RLINK/CORE/RL/FSM_onehot_R_BREGS_reg[state][0]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.445     0.445 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.925    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.138    -2.213 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.684    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.655 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.830    -0.825    RLINK/CORE/RL/CLKFX
    SLICE_X43Y50         FDRE                                         r  RLINK/CORE/RL/FSM_onehot_R_BREGS_reg[state][0]/C
                         clock pessimism              0.508    -0.317    
    SLICE_X43Y50         FDRE (Hold_fdre_C_D)         0.092    -0.225    RLINK/CORE/RL/FSM_onehot_R_BREGS_reg[state][0]
  -------------------------------------------------------------------
                         required time                          0.225    
                         arrival time                          -0.137    
  -------------------------------------------------------------------
                         slack                                  0.088    

Slack (MET) :             0.090ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/FSM_onehot_R_BREGS_reg[state][7]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/CORE/RL/FSM_onehot_R_BREGS_reg[state][6]/D
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.445ns  (logic 0.209ns (46.935%)  route 0.236ns (53.065%))
  Logic Levels:           1  (LUT6=1)
  Clock Path Skew:        0.264ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.825ns
    Source Clock Delay      (SCD):    -0.581ns
    Clock Pessimism Removal (CPR):    -0.508ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.257     0.257 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.697    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.356    -1.659 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.173    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.147 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.566    -0.581    RLINK/CORE/RL/CLKFX
    SLICE_X42Y49         FDRE                                         r  RLINK/CORE/RL/FSM_onehot_R_BREGS_reg[state][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X42Y49         FDRE (Prop_fdre_C_Q)         0.164    -0.417 f  RLINK/CORE/RL/FSM_onehot_R_BREGS_reg[state][7]/Q
                         net (fo=7, routed)           0.236    -0.181    RLINK/CORE/RL/FSM_onehot_R_BREGS_reg[state_n_0_][7]
    SLICE_X43Y50         LUT6 (Prop_lut6_I1_O)        0.045    -0.136 r  RLINK/CORE/RL/FSM_onehot_R_BREGS[state][6]_i_1/O
                         net (fo=1, routed)           0.000    -0.136    RLINK/CORE/RL/FSM_onehot_R_BREGS[state][6]_i_1_n_0
    SLICE_X43Y50         FDRE                                         r  RLINK/CORE/RL/FSM_onehot_R_BREGS_reg[state][6]/D
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.445     0.445 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.925    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.138    -2.213 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.684    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.655 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.830    -0.825    RLINK/CORE/RL/CLKFX
    SLICE_X43Y50         FDRE                                         r  RLINK/CORE/RL/FSM_onehot_R_BREGS_reg[state][6]/C
                         clock pessimism              0.508    -0.317    
    SLICE_X43Y50         FDRE (Hold_fdre_C_D)         0.091    -0.226    RLINK/CORE/RL/FSM_onehot_R_BREGS_reg[state][6]
  -------------------------------------------------------------------
                         required time                          0.226    
                         arrival time                          -0.136    
  -------------------------------------------------------------------
                         slack                                  0.090    

Slack (MET) :             0.094ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/RXFIFO/FIFO/R_REGS_reg[waddr][3]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA/WADR3
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.350ns  (logic 0.141ns (40.276%)  route 0.209ns (59.724%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.827ns
    Source Clock Delay      (SCD):    -0.589ns
    Clock Pessimism Removal (CPR):    -0.254ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.257     0.257 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.697    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.356    -1.659 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.173    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.147 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.558    -0.589    RLINK/SERPORT/RXFIFO/FIFO/CLKFX
    SLICE_X41Y59         FDRE                                         r  RLINK/SERPORT/RXFIFO/FIFO/R_REGS_reg[waddr][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y59         FDRE (Prop_fdre_C_Q)         0.141    -0.448 r  RLINK/SERPORT/RXFIFO/FIFO/R_REGS_reg[waddr][3]/Q
                         net (fo=22, routed)          0.209    -0.239    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/ADDRD3
    SLICE_X42Y59         RAMD32                                       r  RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA/WADR3
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.445     0.445 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.925    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.138    -2.213 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.684    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.655 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.828    -0.827    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/WCLK
    SLICE_X42Y59         RAMD32                                       r  RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA/CLK
                         clock pessimism              0.254    -0.573    
    SLICE_X42Y59         RAMD32 (Hold_ramd32_CLK_WADR3)
                                                      0.240    -0.333    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA
  -------------------------------------------------------------------
                         required time                          0.333    
                         arrival time                          -0.239    
  -------------------------------------------------------------------
                         slack                                  0.094    

Slack (MET) :             0.094ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/RXFIFO/FIFO/R_REGS_reg[waddr][3]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA_D1/WADR3
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.350ns  (logic 0.141ns (40.276%)  route 0.209ns (59.724%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.827ns
    Source Clock Delay      (SCD):    -0.589ns
    Clock Pessimism Removal (CPR):    -0.254ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.257     0.257 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.697    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.356    -1.659 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.173    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.147 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.558    -0.589    RLINK/SERPORT/RXFIFO/FIFO/CLKFX
    SLICE_X41Y59         FDRE                                         r  RLINK/SERPORT/RXFIFO/FIFO/R_REGS_reg[waddr][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y59         FDRE (Prop_fdre_C_Q)         0.141    -0.448 r  RLINK/SERPORT/RXFIFO/FIFO/R_REGS_reg[waddr][3]/Q
                         net (fo=22, routed)          0.209    -0.239    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/ADDRD3
    SLICE_X42Y59         RAMD32                                       r  RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA_D1/WADR3
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.445     0.445 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.925    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.138    -2.213 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.684    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.655 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.828    -0.827    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/WCLK
    SLICE_X42Y59         RAMD32                                       r  RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA_D1/CLK
                         clock pessimism              0.254    -0.573    
    SLICE_X42Y59         RAMD32 (Hold_ramd32_CLK_WADR3)
                                                      0.240    -0.333    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA_D1
  -------------------------------------------------------------------
                         required time                          0.333    
                         arrival time                          -0.239    
  -------------------------------------------------------------------
                         slack                                  0.094    

Slack (MET) :             0.094ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/RXFIFO/FIFO/R_REGS_reg[waddr][3]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMB/WADR3
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.350ns  (logic 0.141ns (40.276%)  route 0.209ns (59.724%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.827ns
    Source Clock Delay      (SCD):    -0.589ns
    Clock Pessimism Removal (CPR):    -0.254ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.257     0.257 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.697    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.356    -1.659 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.173    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.147 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.558    -0.589    RLINK/SERPORT/RXFIFO/FIFO/CLKFX
    SLICE_X41Y59         FDRE                                         r  RLINK/SERPORT/RXFIFO/FIFO/R_REGS_reg[waddr][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y59         FDRE (Prop_fdre_C_Q)         0.141    -0.448 r  RLINK/SERPORT/RXFIFO/FIFO/R_REGS_reg[waddr][3]/Q
                         net (fo=22, routed)          0.209    -0.239    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/ADDRD3
    SLICE_X42Y59         RAMD32                                       r  RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMB/WADR3
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.445     0.445 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.925    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.138    -2.213 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.684    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.655 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.828    -0.827    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/WCLK
    SLICE_X42Y59         RAMD32                                       r  RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMB/CLK
                         clock pessimism              0.254    -0.573    
    SLICE_X42Y59         RAMD32 (Hold_ramd32_CLK_WADR3)
                                                      0.240    -0.333    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMB
  -------------------------------------------------------------------
                         required time                          0.333    
                         arrival time                          -0.239    
  -------------------------------------------------------------------
                         slack                                  0.094    

Slack (MET) :             0.094ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/RXFIFO/FIFO/R_REGS_reg[waddr][3]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMB_D1/WADR3
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.350ns  (logic 0.141ns (40.276%)  route 0.209ns (59.724%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.827ns
    Source Clock Delay      (SCD):    -0.589ns
    Clock Pessimism Removal (CPR):    -0.254ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.257     0.257 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.697    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.356    -1.659 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.173    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.147 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.558    -0.589    RLINK/SERPORT/RXFIFO/FIFO/CLKFX
    SLICE_X41Y59         FDRE                                         r  RLINK/SERPORT/RXFIFO/FIFO/R_REGS_reg[waddr][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y59         FDRE (Prop_fdre_C_Q)         0.141    -0.448 r  RLINK/SERPORT/RXFIFO/FIFO/R_REGS_reg[waddr][3]/Q
                         net (fo=22, routed)          0.209    -0.239    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/ADDRD3
    SLICE_X42Y59         RAMD32                                       r  RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMB_D1/WADR3
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.445     0.445 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.925    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.138    -2.213 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.684    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.655 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.828    -0.827    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/WCLK
    SLICE_X42Y59         RAMD32                                       r  RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMB_D1/CLK
                         clock pessimism              0.254    -0.573    
    SLICE_X42Y59         RAMD32 (Hold_ramd32_CLK_WADR3)
                                                      0.240    -0.333    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMB_D1
  -------------------------------------------------------------------
                         required time                          0.333    
                         arrival time                          -0.239    
  -------------------------------------------------------------------
                         slack                                  0.094    

Slack (MET) :             0.094ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/RXFIFO/FIFO/R_REGS_reg[waddr][3]/C
                            (rising edge-triggered cell FDRE clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Destination:            RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMC/WADR3
                            (rising edge-triggered cell RAMD32 clocked by CLKOUT0  {rise@0.000ns fall@4.167ns period=8.333ns})
  Path Group:             CLKOUT0
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (CLKOUT0 rise@0.000ns - CLKOUT0 rise@0.000ns)
  Data Path Delay:        0.350ns  (logic 0.141ns (40.276%)  route 0.209ns (59.724%))
  Logic Levels:           0  
  Clock Path Skew:        0.016ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.827ns
    Source Clock Delay      (SCD):    -0.589ns
    Clock Pessimism Removal (CPR):    -0.254ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.257     0.257 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.697    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.356    -1.659 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.486    -1.173    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.147 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.558    -0.589    RLINK/SERPORT/RXFIFO/FIFO/CLKFX
    SLICE_X41Y59         FDRE                                         r  RLINK/SERPORT/RXFIFO/FIFO/R_REGS_reg[waddr][3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X41Y59         FDRE (Prop_fdre_C_Q)         0.141    -0.448 r  RLINK/SERPORT/RXFIFO/FIFO/R_REGS_reg[waddr][3]/Q
                         net (fo=22, routed)          0.209    -0.239    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/ADDRD3
    SLICE_X42Y59         RAMD32                                       r  RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMC/WADR3
  -------------------------------------------------------------------    -------------------

                         (clock CLKOUT0 rise edge)    0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.445     0.445 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.925    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y1      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.138    -2.213 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.530    -1.684    GEN_CLKSYS/CLKOUT0
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.655 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=1136, routed)        0.828    -0.827    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/WCLK
    SLICE_X42Y59         RAMD32                                       r  RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMC/CLK
                         clock pessimism              0.254    -0.573    
    SLICE_X42Y59         RAMD32 (Hold_ramd32_CLK_WADR3)
                                                      0.240    -0.333    RLINK/SERPORT/RXFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMC
  -------------------------------------------------------------------
                         required time                          0.333    
                         arrival time                          -0.239    
  -------------------------------------------------------------------
                         slack                                  0.094    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         CLKOUT0
Waveform(ns):       { 0.000 4.167 }
Period(ns):         8.333
Sources:            { GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     XADC/DCLK           n/a            4.000         8.333       4.333      XADC_X0Y0        SMRB.I0/SM/DCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.944         8.333       5.389      RAMB18_X0Y16     RBDTST/EMON/BRAM/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.944         8.333       5.389      RAMB18_X0Y16     RBDTST/EMON/BRAM/sv_ram_reg/CLKBWRCLK
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.944         8.333       5.389      RAMB36_X1Y7      RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.944         8.333       5.389      RAMB36_X1Y7      RLINK/CORE/RL/RTBUF/sv_ram_reg/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         8.333       5.757      RAMB18_X1Y16     RBDTST/MON/BRAM0/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.576         8.333       5.757      RAMB18_X1Y16     RBDTST/MON/BRAM0/sv_ram_reg/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         8.333       5.757      RAMB18_X1Y17     RBDTST/MON/BRAM1/sv_ram_reg/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.576         8.333       5.757      RAMB18_X1Y17     RBDTST/MON/BRAM1/sv_ram_reg/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576         8.333       5.757      RAMB18_X1Y18     RBDTST/BRAM/BRAM/sv_ram_reg/CLKARDCLK
Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       8.333       205.027    MMCME2_ADV_X1Y1  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X38Y47     TEST/FIFO/RAM/RAM_reg_0_15_0_5/RAMA/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X38Y47     TEST/FIFO/RAM/RAM_reg_0_15_0_5/RAMA_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X38Y47     TEST/FIFO/RAM/RAM_reg_0_15_0_5/RAMB/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X38Y47     TEST/FIFO/RAM/RAM_reg_0_15_0_5/RAMB_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X38Y47     TEST/FIFO/RAM/RAM_reg_0_15_0_5/RAMC/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X38Y47     TEST/FIFO/RAM/RAM_reg_0_15_0_5/RAMC_D1/CLK
Low Pulse Width   Slow    RAMS32/CLK          n/a            1.250         4.167       2.917      SLICE_X38Y47     TEST/FIFO/RAM/RAM_reg_0_15_0_5/RAMD/CLK
Low Pulse Width   Slow    RAMS32/CLK          n/a            1.250         4.167       2.917      SLICE_X38Y47     TEST/FIFO/RAM/RAM_reg_0_15_0_5/RAMD_D1/CLK
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X34Y47     TEST/FIFO/RAM/RAM_reg_0_15_12_15/RAMA/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X34Y47     TEST/FIFO/RAM/RAM_reg_0_15_12_15/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X46Y47     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X46Y47     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMA_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X46Y47     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X46Y47     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMB_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X46Y47     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X46Y47     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMC_D1/CLK
High Pulse Width  Fast    RAMS32/CLK          n/a            1.250         4.167       2.917      SLICE_X46Y47     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMD/CLK
High Pulse Width  Fast    RAMS32/CLK          n/a            1.250         4.167       2.917      SLICE_X46Y47     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_0_5/RAMD_D1/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X46Y48     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA/CLK
High Pulse Width  Fast    RAMD32/CLK          n/a            1.250         4.167       2.917      SLICE_X46Y48     RLINK/CORE/RL/DOFIFO/FIFO/RAM/RAM_reg_0_31_6_7/RAMA_D1/CLK



