
*** Running vivado
    with args -log sys_tst_rlink_arty.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source sys_tst_rlink_arty.tcl -notrace


****** Vivado v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source sys_tst_rlink_arty.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 114 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.2
INFO: [Device 21-403] Loading part xc7a35ticsg324-1L
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/arty/arty_pclk.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/arty/arty_pclk.xdc]
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/arty/arty_pins.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/bplib/arty/arty_pins.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 9 instances were transformed.
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 9 instances

link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1305.680 ; gain = 226.629 ; free physical = 1303 ; free virtual = 8728
Command: opt_design -directive Explore
INFO: [Vivado_Tcl 4-136] Directive used for opt_design is: Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
Running DRC as a precondition to command opt_design

Starting DRC Task
Command: report_drc (run_mandatory_drcs) for: opt_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1319.688 ; gain = 14.008 ; free physical = 1307 ; free virtual = 8723
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-2] Deriving generated clocks

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 2 inverter(s) to 2 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1d3a44132

Time (s): cpu = 00:00:00.26 ; elapsed = 00:00:00.53 . Memory (MB): peak = 1778.117 ; gain = 0.000 ; free physical = 904 ; free virtual = 8346
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 115 cells

Phase 2 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 2 Constant propagation | Checksum: 15862220c

Time (s): cpu = 00:00:00.34 ; elapsed = 00:00:01 . Memory (MB): peak = 1778.117 ; gain = 0.000 ; free physical = 886 ; free virtual = 8337
INFO: [Opt 31-389] Phase Constant propagation created 1 cells and removed 1 cells

Phase 3 Sweep
Phase 3 Sweep | Checksum: 12164f319

Time (s): cpu = 00:00:00.40 ; elapsed = 00:00:02 . Memory (MB): peak = 1778.117 ; gain = 0.000 ; free physical = 881 ; free virtual = 8335
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 4 BUFG optimization
Phase 4 BUFG optimization | Checksum: 12164f319

Time (s): cpu = 00:00:00.48 ; elapsed = 00:00:02 . Memory (MB): peak = 1778.117 ; gain = 0.000 ; free physical = 876 ; free virtual = 8330
INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells

Phase 5 Shift Register Optimization
Phase 5 Shift Register Optimization | Checksum: 12164f319

Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:02 . Memory (MB): peak = 1778.117 ; gain = 0.000 ; free physical = 876 ; free virtual = 8330
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1778.117 ; gain = 0.000 ; free physical = 875 ; free virtual = 8329
Ending Logic Optimization Task | Checksum: 12164f319

Time (s): cpu = 00:00:00.50 ; elapsed = 00:00:02 . Memory (MB): peak = 1778.117 ; gain = 0.000 ; free physical = 875 ; free virtual = 8330

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Power 33-23] Power model is not available for UA
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 5 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 1 Total Ports: 10
Ending PowerOpt Patch Enables Task | Checksum: 14e6163ec

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.04 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 813 ; free virtual = 8289
Ending Power Optimization Task | Checksum: 14e6163ec

Time (s): cpu = 00:00:02 ; elapsed = 00:00:03 . Memory (MB): peak = 1939.539 ; gain = 161.422 ; free physical = 819 ; free virtual = 8295
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1939.539 ; gain = 633.859 ; free physical = 819 ; free virtual = 8295
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.15 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 802 ; free virtual = 8280
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_rlink/arty/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_arty_opt.dcp' has been generated.
Command: report_drc -file sys_tst_rlink_arty_drc_opted.rpt
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_rlink/arty/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_arty_drc_opted.rpt.
report_drc completed successfully
INFO: [Chipscope 16-241] No debug cores found in the current design.
Before running the implement_debug_core command, either use the Set Up Debug wizard (GUI mode)
or use the create_debug_core and connect_debug_core Tcl commands to insert debug cores into the design.
Command: place_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
Command: report_drc (run_mandatory_drcs) for: incr_eco_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
Command: report_drc (run_mandatory_drcs) for: placer_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 46-5] The placer was invoked with the 'Explore' directive.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 759 ; free virtual = 8255
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 124c26cef

Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.14 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 759 ; free virtual = 8255
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 759 ; free virtual = 8255

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 14318e62e

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 754 ; free virtual = 8253

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 1df02c011

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 750 ; free virtual = 8251

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 1df02c011

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 750 ; free virtual = 8251
Phase 1 Placer Initialization | Checksum: 1df02c011

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 750 ; free virtual = 8251

Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 1ad3c64be

Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 722 ; free virtual = 8225

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1ad3c64be

Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 722 ; free virtual = 8225

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 19bd81551

Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 722 ; free virtual = 8225

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1597826a7

Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 722 ; free virtual = 8225

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 1597826a7

Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 722 ; free virtual = 8225

Phase 3.5 Timing Path Optimizer
Phase 3.5 Timing Path Optimizer | Checksum: 1650dc212

Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 722 ; free virtual = 8225

Phase 3.6 Small Shape Detail Placement
Phase 3.6 Small Shape Detail Placement | Checksum: 1628056b1

Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 720 ; free virtual = 8224

Phase 3.7 Re-assign LUT pins
Phase 3.7 Re-assign LUT pins | Checksum: 15f4c7f6c

Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 722 ; free virtual = 8226

Phase 3.8 Pipeline Register Optimization
Phase 3.8 Pipeline Register Optimization | Checksum: 15f4c7f6c

Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 722 ; free virtual = 8226
Phase 3 Detail Placement | Checksum: 15f4c7f6c

Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 722 ; free virtual = 8226

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1104c973b

Phase 4.1.1.1 BUFG Insertion
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 2 CPUs
INFO: [Place 46-41] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason.
Phase 4.1.1.1 BUFG Insertion | Checksum: 1104c973b

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 735 ; free virtual = 8239
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.822. For the most accurate timing information please run report_timing.
Phase 4.1.1 Post Placement Optimization | Checksum: c7a8ef23

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 727 ; free virtual = 8239
Phase 4.1 Post Commit Optimization | Checksum: c7a8ef23

Time (s): cpu = 00:00:10 ; elapsed = 00:00:09 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 727 ; free virtual = 8239

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: c7a8ef23

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 728 ; free virtual = 8241

Phase 4.3 Placer Reporting
Phase 4.3 Placer Reporting | Checksum: c7a8ef23

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 728 ; free virtual = 8241

Phase 4.4 Final Placement Cleanup
Phase 4.4 Final Placement Cleanup | Checksum: 11cdd34a7

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 728 ; free virtual = 8241
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 11cdd34a7

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 728 ; free virtual = 8241
Ending Placer Task | Checksum: 1102e2485

Time (s): cpu = 00:00:10 ; elapsed = 00:00:10 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 731 ; free virtual = 8244
49 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:11 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 731 ; free virtual = 8244
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 728 ; free virtual = 8245
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_rlink/arty/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_arty_placed.dcp' has been generated.
report_io: Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 733 ; free virtual = 8247
report_utilization: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.21 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 738 ; free virtual = 8252
report_control_sets: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.23 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 737 ; free virtual = 8251
Command: phys_opt_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
INFO: [Vivado_Tcl 4-137] Directive used for phys_opt_design is: Explore
INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.500 ns. Skipping all physical synthesis optimizations.
INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
54 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
phys_opt_design completed successfully
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 728 ; free virtual = 8255
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_rlink/arty/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_arty_physopt.dcp' has been generated.
Command: route_design -directive Explore
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
Running DRC as a precondition to command route_design
Command: report_drc (run_mandatory_drcs) for: router_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-270] Using Router directive 'Explore'.
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 207ab500 ConstDB: 0 ShapeSum: efb36f85 RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 16ea24357

Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 691 ; free virtual = 8184

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 16ea24357

Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 691 ; free virtual = 8184

Phase 2.2 Fix Topology Constraints
Phase 2.2 Fix Topology Constraints | Checksum: 16ea24357

Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 683 ; free virtual = 8177

Phase 2.3 Pre Route Cleanup
Phase 2.3 Pre Route Cleanup | Checksum: 16ea24357

Time (s): cpu = 00:00:26 ; elapsed = 00:00:23 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 683 ; free virtual = 8177
 Number of Nodes with overlaps = 0

Phase 2.4 Update Timing
Phase 2.4 Update Timing | Checksum: 1a1c800f8

Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 673 ; free virtual = 8168
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.933  | TNS=0.000  | WHS=-0.326 | THS=-79.375|

Phase 2 Router Initialization | Checksum: 1b358e505

Time (s): cpu = 00:00:28 ; elapsed = 00:00:25 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 672 ; free virtual = 8167

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: c5fb8f9b

Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 675 ; free virtual = 8169

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 361
 Number of Nodes with overlaps = 34
 Number of Nodes with overlaps = 11
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.937  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 137b02654

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 675 ; free virtual = 8170
Phase 4 Rip-up And Reroute | Checksum: 137b02654

Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 675 ; free virtual = 8170

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 190380475

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 675 ; free virtual = 8170
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.030  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 5.1 Delay CleanUp | Checksum: 190380475

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 675 ; free virtual = 8170

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 190380475

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 675 ; free virtual = 8170
Phase 5 Delay and Skew Optimization | Checksum: 190380475

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 675 ; free virtual = 8170

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 107d801da

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 677 ; free virtual = 8171
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.030  | TNS=0.000  | WHS=0.060  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 133b3e16a

Time (s): cpu = 00:00:33 ; elapsed = 00:00:28 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 677 ; free virtual = 8171
Phase 6 Post Hold Fix | Checksum: 133b3e16a

Time (s): cpu = 00:00:33 ; elapsed = 00:00:28 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 677 ; free virtual = 8171

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.905206 %
  Global Horizontal Routing Utilization  = 0.998048 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 13d085d55

Time (s): cpu = 00:00:33 ; elapsed = 00:00:28 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 677 ; free virtual = 8171

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 13d085d55

Time (s): cpu = 00:00:33 ; elapsed = 00:00:28 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 676 ; free virtual = 8171

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 19f3e43a4

Time (s): cpu = 00:00:33 ; elapsed = 00:00:28 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 676 ; free virtual = 8171

Phase 10 Post Router Timing
INFO: [Route 35-20] Post Routing Timing Summary | WNS=1.034  | TNS=0.000  | WHS=0.062  | THS=0.000  |

INFO: [Route 35-61] The design met the timing requirement.
Phase 10 Post Router Timing | Checksum: 1fc9ea0b4

Time (s): cpu = 00:00:34 ; elapsed = 00:00:29 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 676 ; free virtual = 8171
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:34 ; elapsed = 00:00:29 . Memory (MB): peak = 1939.539 ; gain = 0.000 ; free physical = 742 ; free virtual = 8237

Routing Is Done.
68 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:37 ; elapsed = 00:00:31 . Memory (MB): peak = 1973.492 ; gain = 33.953 ; free physical = 742 ; free virtual = 8237
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.41 . Memory (MB): peak = 1973.492 ; gain = 0.000 ; free physical = 737 ; free virtual = 8236
INFO: [Common 17-1381] The checkpoint '/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_rlink/arty/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_arty_routed.dcp' has been generated.
Command: report_drc -file sys_tst_rlink_arty_drc_routed.rpt -pb sys_tst_rlink_arty_drc_routed.pb -rpx sys_tst_rlink_arty_drc_routed.rpx
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_rlink/arty/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_arty_drc_routed.rpt.
report_drc completed successfully
Command: report_methodology -file sys_tst_rlink_arty_methodology_drc_routed.rpt -rpx sys_tst_rlink_arty_methodology_drc_routed.rpx
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [DRC 23-133] Running Methodology with 2 threads
INFO: [Coretcl 2-1520] The results of Report Methodology are in file /mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_rlink/arty/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_arty_methodology_drc_routed.rpt.
report_methodology completed successfully
Command: report_power -file sys_tst_rlink_arty_power_routed.rpt -pb sys_tst_rlink_arty_power_summary_routed.pb -rpx sys_tst_rlink_arty_power_routed.rpx
INFO: [Power 33-23] Power model is not available for UA
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
76 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1L, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Common 17-206] Exiting Vivado at Sun Aug 26 13:11:55 2018...

*** Running vivado
    with args -log sys_tst_rlink_arty.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source sys_tst_rlink_arty.tcl -notrace


****** Vivado v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source sys_tst_rlink_arty.tcl -notrace
Command: open_checkpoint sys_tst_rlink_arty_routed.dcp

Starting open_checkpoint Task

Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1077.035 ; gain = 0.000 ; free physical = 844 ; free virtual = 8331
INFO: [Netlist 29-17] Analyzing 114 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.2
INFO: [Device 21-403] Loading part xc7a35ticsg324-1L
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_rlink/arty/project_mflow/project_mflow.runs/impl_1/.Xil/Vivado-3783-athome/dcp3/sys_tst_rlink_arty_early.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_rlink/arty/project_mflow/project_mflow.runs/impl_1/.Xil/Vivado-3783-athome/dcp3/sys_tst_rlink_arty_early.xdc]
Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_rlink/arty/project_mflow/project_mflow.runs/impl_1/.Xil/Vivado-3783-athome/dcp3/sys_tst_rlink_arty.xdc]
Finished Parsing XDC File [/mnt/dataold/tmp/tmp/w11-test/v0.752/w11/rtl/sys_gen/tst_rlink/arty/project_mflow/project_mflow.runs/impl_1/.Xil/Vivado-3783-athome/dcp3/sys_tst_rlink_arty.xdc]
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1305.945 ; gain = 2.000 ; free physical = 570 ; free virtual = 8074
Restored from archive | CPU: 0.220000 secs | Memory: 2.955276 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.22 . Memory (MB): peak = 1305.945 ; gain = 2.000 ; free physical = 570 ; free virtual = 8074
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 9 instances were transformed.
  RAM32M => RAM32M (RAMS32, RAMS32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32): 9 instances

INFO: [Project 1-604] Checkpoint was created with Vivado v2017.2 (64-bit) build 1909853
open_checkpoint: Time (s): cpu = 00:00:08 ; elapsed = 00:00:09 . Memory (MB): peak = 1305.945 ; gain = 228.910 ; free physical = 575 ; free virtual = 8073
Command: write_bitstream -force sys_tst_rlink_arty.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35ti-csg324'
Running DRC as a precondition to command write_bitstream
Command: report_drc (run_mandatory_drcs) for: bitstream_checks
INFO: [DRC 23-27] Running DRC with 2 threads
report_drc (run_mandatory_drcs) completed successfully
INFO: [Vivado 12-3199] DRC finished with 0 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Project 1-821] Please set project.enableDesignId to be 'true'.
INFO: [Designutils 20-2272] Running write_bitstream with 2 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Overwriting "TIMESTAMP" with "D424D34B" for option USR_ACCESS
Creating bitmap...
Creating bitstream...
Writing bitstream ./sys_tst_rlink_arty.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
14 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:29 ; elapsed = 00:00:27 . Memory (MB): peak = 1796.301 ; gain = 490.355 ; free physical = 387 ; free virtual = 7967
INFO: [Common 17-206] Exiting Vivado at Sun Aug 26 13:13:18 2018...
