Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-----------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017
| Date         : Sun Aug 26 13:11:14 2018
| Host         : athome running 64-bit Ubuntu 16.04.5 LTS
| Command      : report_control_sets -verbose -file sys_tst_rlink_arty_control_sets_placed.rpt
| Design       : sys_tst_rlink_arty
| Device       : xc7a35ti
-----------------------------------------------------------------------------------------------

Control Set Information

Table of Contents
-----------------
1. Summary
2. Flip-Flop Distribution
3. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Number of unique control sets                            |    95 |
| Unused register locations in slices containing registers |   276 |
+----------------------------------------------------------+-------+


2. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |             161 |           87 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |              28 |           19 |
| Yes          | No                    | No                     |             654 |          257 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |             193 |           71 |
+--------------+-----------------------+------------------------+-----------------+--------------+


3. Detailed Control Set Information
-----------------------------------

+-------------------+----------------------------------------------------------------+-------------------------------------------------------+------------------+----------------+
|    Clock Signal   |                          Enable Signal                         |                    Set/Reset Signal                   | Slice Load Count | Bel Load Count |
+-------------------+----------------------------------------------------------------+-------------------------------------------------------+------------------+----------------+
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/out[0]                                           |                                                       |                1 |              1 |
|  GEN_CLKSYS/CLKFX |                                                                | RGBMSTR/R_RGB_reg[0]                                  |                4 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/TX/E[0]                                | RLINK/SERPORT/UART/RXTX/TX/R_REGS[bcnt][3]_i_1__0_n_0 |                2 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/RX/R_REGS[bcnt][3]_i_1_n_0             |                                                       |                2 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_2_n_0            | RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_1_n_0   |                2 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/N_REGS[rbtake_1]                                 |                                                       |                1 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/AB/FSM_onehot_R_REGS[state][3]_i_1_n_0      |                                                       |                1 |              4 |
|  GEN_CLKSYS/CLKFX | SMRB.I0/SMRB/FSM_onehot_R_REGS[state][3]_i_1__1_n_0            |                                                       |                1 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[waddr][0]_0[0]                        | RLINK/CORE/RL/SR[0]                                   |                2 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[stat][0][0]                           | RLINK/CORE/RL/R_REGS_reg[stat][0]_0[0]                |                1 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/E[0]                                             | RLINK/CORE/RL/SR[0]                                   |                1 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[stat]                                          |                                                       |                1 |              4 |
|  GEN_CLKSYS/CLKFX |                                                                | RLINK/CORE/RL/R_REGS_reg[rbsel]_0                     |                2 |              4 |
|  GEN_CLKSYS/CLKFX |                                                                | RGBMSTR/R_RGB_reg[2]                                  |                4 |              4 |
|  GEN_CLKSYS/CLKFX |                                                                | RGBMSTR/R_RGB_reg[1]                                  |                4 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[addrsame]11_out                                |                                                       |                2 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/N_REGS[empty]                                    | RLINK/SERPORT/UART/AB/in1                             |                2 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/N_REGS[empty]                        |                                                       |                3 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/XONRX/E[0]                                       | RLINK/SERPORT/UART/AB/in1                             |                2 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/XONTX/n[oval]12_out                              | RLINK/SERPORT/UART/AB/SR[0]                           |                2 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/CD2B/N_REGS[full]                                   | RLINK/SERPORT/UART/AB/in1                             |                3 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[nbusy][5]_0                           |                                                       |                2 |              6 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[cntbusy][0]                           |                                                       |                3 |              6 |
|  GEN_CLKSYS/CLKFX |                                                                | RLINK/SERPORT/UART/AB/in1                             |                3 |              6 |
|  GEN_CLKSYS/CLKFX |                                                                | RLINK/CORE/RL/R_BREGS[btocnt][5]_i_1_n_0              |                2 |              6 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/RX/FSM_onehot_R_REGS[state][6]_i_2_n_0 | RLINK/SERPORT/UART/AB/in1                             |                4 |              7 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/AB/n[mcnt]                                  |                                                       |                3 |              7 |
|  GEN_CLKSYS/CLKFX | RBDTST/EMON/n[rdivcnt]                                         |                                                       |                6 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[rdiv]                                          |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[cntcyc][0]_1                          | RLINK/CORE/RL/R_REGS_reg[cntcyc][0]_0                 |                3 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/out[1]                                           |                                                       |                4 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/RX/E[0]                                | RLINK/SERPORT/UART/AB/in1                             |                2 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[lcmd][7]_i_1_n_0                         |                                                       |                1 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[din][7]_i_1_n_0                          |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[din][15]_i_1_n_0                         |                                                       |                3 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[cnt][15]_i_1_n_0                         |                                                       |                5 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[atocnt][7]_i_1_n_0                       |                                                       |                3 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[cnt][7]_i_1_n_0                          |                                                       |                3 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/TX/R_REGS[sreg][7]_i_1_n_0             |                                                       |                4 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/RX/n[sreg]                             |                                                       |                3 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/n[dinl]                              |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state_n_0_][5]            |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[laddr][0]_2                           |                                                       |                4 |              9 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[laddr][0]                             |                                                       |                6 |              9 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/CD2B/n[ecodeval]3_out                               |                                                       |                4 |              9 |
|  GEN_CLKSYS/CLKFX | CLKDIV/n[mcnt]                                                 |                                                       |                4 |             10 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[nbusy][0][0]                          | RLINK/CORE/RL/R_REGS_reg[stat][0]_0[0]                |                5 |             10 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dataval][0]                           |                                                       |                3 |             10 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/SEL/n[anena]                                     |                                                       |                3 |             10 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[cntbusy][0]_0                         |                                                       |                5 |             10 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[addr]                                          |                                                       |                7 |             10 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[ncyc]0                                |                                                       |                6 |             10 |
|  GEN_CLKSYS/CLKFX | RBDTST/MON/R_REGS[rbnbusy][9]_i_2_n_0                          | RBDTST/MON/R_REGS[rbnbusy][9]_i_1_n_0                 |                3 |             10 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/FSM_onehot_R_LREGS_reg[state_n_0_][4]            |                                                       |                7 |             11 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_BREGS[cnt][10]_i_1_n_0                         |                                                       |                6 |             11 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_BREGS[dcnt][10]_i_2_n_0                        | RLINK/CORE/RL/dcnt_clear                              |                4 |             11 |
|  GEN_CLKSYS/CLKFX | SMRB.I0/SMRB/n[temp]                                           |                                                       |                7 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dimb][0]_2                            |                                                       |                4 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dimr][0]_2                            |                                                       |                4 |             12 |
|  GEN_CLKSYS/CLKFX | CLKDIV/CE_USEC                                                 |                                                       |                3 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS_reg[bcnt][11]                |                                                       |                3 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS_reg[rtaddra][0]              | RLINK/CORE/RL/addra_clear                             |                3 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[rtaddrb][0]_i_2_n_0                      | RLINK/CORE/B2CD/n[rtaddrb_red]17_out                  |                3 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dimb][0]                              |                                                       |                4 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dimb][0]_0                            |                                                       |                3 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dimb][0]_1                            |                                                       |                5 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dimg][0]                              |                                                       |                5 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dimg][0]_0                            |                                                       |                3 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dimg][0]_2                            |                                                       |                3 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dimr][0]_1                            |                                                       |                4 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dimg][0]_1                            |                                                       |                4 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dimr][0]                              |                                                       |                3 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dimr][0]_0                            |                                                       |                3 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/XONTX/E[0]                                       | RLINK/SERPORT/UART/AB/in1                             |                4 |             13 |
|  GEN_CLKSYS/CLKFX | IOB_RS232/IOB_RXD/IOB/R_REGS_reg[dcnt][12]                     |                                                       |                4 |             13 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/FSM_onehot_R_BREGS[state][12]_i_1_n_0            |                                                       |                6 |             13 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[rbndly]                                        | RLINK/CORE/RL/R_REGS_reg[rbndly][13]                  |                4 |             14 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/AB/n[ccnt]                                  |                                                       |                5 |             15 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[rbdout]                                        |                                                       |                7 |             16 |
|  GEN_CLKSYS/CLKFX | SMRB.I0/SM_EOS                                                 |                                                       |                4 |             16 |
|  GEN_CLKSYS/CLKFX | RBDTST/TIM0/R_REGS[timer][15]_i_1_n_0                          |                                                       |                7 |             16 |
|  GEN_CLKSYS/CLKFX | RBDTST/TIM1/R_REGS[timer][15]_i_1__0_n_0                       |                                                       |                6 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[data][0][0]                           | RLINK/CORE/RL/R_REGS_reg[data][15]_0[0]               |                5 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[lolim]_15__s_net_1                    |                                                       |                8 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/ICRC/icrcena                                     | RLINK/CORE/RL/out[0]                                  |                7 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[rbdata]0                              |                                                       |                7 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/E[0]                                 | RLINK/CORE/RL/out[0]                                  |                7 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[hilim]                                         |                                                       |                5 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/AB/iram_we_0                                |                                                       |                2 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/AB/iram_we                                  |                                                       |                2 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[addrsame]0                            |                                                       |                3 |             17 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/RAM/N_REGS[full]                     |                                                       |                5 |             21 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[waddr][0]_0[0]                        |                                                       |                3 |             24 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/FSM_onehot_R_LREGS[state][29]_i_2_n_0            |                                                       |               19 |             36 |
|  GEN_CLKSYS/CLKFX |                                                                |                                                       |               87 |            161 |
+-------------------+----------------------------------------------------------------+-------------------------------------------------------+------------------+----------------+


+--------+-----------------------+
| Fanout | Number of ControlSets |
+--------+-----------------------+
| 1      |                     1 |
| 4      |                    14 |
| 5      |                     6 |
| 6      |                     4 |
| 7      |                     2 |
| 8      |                    15 |
| 9      |                     3 |
| 10     |                     8 |
| 11     |                     3 |
| 12     |                    17 |
| 13     |                     3 |
| 14     |                     1 |
| 15     |                     1 |
| 16+    |                    17 |
+--------+-----------------------+


