Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> 

Reading constraint file sys_tst_sram_s3.xcf.
XCF parsing done.
Reading design: /home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/sys_tst_sram_s3.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/sys_tst_sram_s3.prj"
Input Format                       : VHDL
Synthesis Constraint File          : sys_tst_sram_s3.xcf

---- Target Parameters
Output File Name                   : "sys_tst_sram_s3"
Output Format                      : ngc
Target Device                      : xc3s1000-ft256-4

---- Source Options
Shift Register Extraction          : NO

---- General Options
Optimization Goal                  : SPEED
Optimization Effort                : 2

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/slvtypes.vhd" in Library work.
Package <slvtypes> compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/memlib.vhd" in Library work.
Package <memlib> compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/ram_1swar_1ar_gen_unisim.vhd" in Library work.
Entity <ram_1swar_1ar_gen> compiled.
Entity <ram_1swar_1ar_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serportlib.vhd" in Library work.
Package <serportlib> compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_uart_rx.vhd" in Library work.
Entity <serport_uart_rx> compiled.
Entity <serport_uart_rx> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_uart_tx.vhd" in Library work.
Entity <serport_uart_tx> compiled.
Entity <serport_uart_tx> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/rbus/rblib.vhd" in Library work.
Package <rblib> compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/comlib/comlib.vhd" in Library work.
Package <comlib> compiled.
Package body <comlib> compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/fifo_1c_dram_raw.vhd" in Library work.
Entity <fifo_1c_dram_raw> compiled.
Entity <fifo_1c_dram_raw> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd" in Library work.
Entity <ram_2swsr_xfirst_gen_unisim> compiled.
Entity <ram_2swsr_xfirst_gen_unisim> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/xlib.vhd" in Library work.
Package <xlib> compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd" in Library work.
Entity <ram_1swsr_xfirst_gen_unisim> compiled.
Entity <ram_1swsr_xfirst_gen_unisim> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_uart_autobaud.vhd" in Library work.
Entity <serport_uart_autobaud> compiled.
Entity <serport_uart_autobaud> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_uart_rxtx.vhd" in Library work.
Entity <serport_uart_rxtx> compiled.
Entity <serport_uart_rxtx> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/rlink/rlinklib.vhd" in Library work.
Package <rlinklib> compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd" in Library work.
Entity <ram_2swsr_rfirst_gen> compiled.
Entity <ram_2swsr_rfirst_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/fifo_1c_dram.vhd" in Library work.
Entity <fifo_1c_dram> compiled.
Entity <fifo_1c_dram> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/comlib/crc16.vhd" in Library work.
Entity <crc16> compiled.
Entity <crc16> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/rbus/rb_sel.vhd" in Library work.
Entity <rb_sel> compiled.
Entity <rb_sel> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/rbus/rb_sres_or_2.vhd" in Library work.
Entity <rb_sres_or_2> compiled.
Entity <rb_sres_or_2> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd" in Library work.
Entity <iob_reg_o_gen> compiled.
Entity <iob_reg_o_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd" in Library work.
Entity <ram_1swsr_wfirst_gen> compiled.
Entity <ram_1swsr_wfirst_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_uart_rxtx_ab.vhd" in Library work.
Entity <serport_uart_rxtx_ab> compiled.
Entity <serport_uart_rxtx_ab> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_xonrx.vhd" in Library work.
Entity <serport_xonrx> compiled.
Entity <serport_xonrx> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_xontx.vhd" in Library work.
Entity <serport_xontx> compiled.
Entity <serport_xontx> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/rlink/rlink_core.vhd" in Library work.
Entity <rlink_core> compiled.
Entity <rlink_core> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/comlib/byte2cdata.vhd" in Library work.
Entity <byte2cdata> compiled.
Entity <byte2cdata> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/comlib/cdata2byte.vhd" in Library work.
Entity <cdata2byte> compiled.
Entity <cdata2byte> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/genlib/genlib.vhd" in Library work.
Package <genlib> compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../bplib/bpgen/bpgenlib.vhd" in Library work.
Package <bpgenlib> compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_i_gen.vhd" in Library work.
Entity <iob_reg_i_gen> compiled.
Entity <iob_reg_i_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/genlib/debounce_gen.vhd" in Library work.
Entity <debounce_gen> compiled.
Entity <debounce_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_o.vhd" in Library work.
Entity <iob_reg_o> compiled.
Entity <iob_reg_o> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_io_gen.vhd" in Library work.
Entity <iob_reg_io_gen> compiled.
Entity <iob_reg_io_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/ram_2swsr_wfirst_gen_unisim.vhd" in Library work.
Entity <ram_2swsr_wfirst_gen> compiled.
Entity <ram_2swsr_wfirst_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/rbus/rbdlib.vhd" in Library work.
Package <rbdlib> compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/rlink/rlink_core8.vhd" in Library work.
Entity <rlink_core8> compiled.
Entity <rlink_core8> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_1clock.vhd" in Library work.
Entity <serport_1clock> compiled.
Entity <serport_1clock> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/rbus/rbd_rbmon.vhd" in Library work.
Entity <rbd_rbmon> compiled.
Entity <rbd_rbmon> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../bplib/bpgen/bp_swibtnled.vhd" in Library work.
Entity <bp_swibtnled> compiled.
Entity <bp_swibtnled> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../bplib/bpgen/sn_7segctl.vhd" in Library work.
Entity <sn_7segctl> compiled.
Entity <sn_7segctl> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_i.vhd" in Library work.
Entity <iob_reg_i> compiled.
Entity <iob_reg_i> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../bplib/s3board/s3boardlib.vhd" in Library work.
Package <s3boardlib> compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../sys_conf.vhd" in Library work.
Package <sys_conf> compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/genlib/clkdivce.vhd" in Library work.
Entity <clkdivce> compiled.
Entity <clkdivce> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../bplib/bpgen/bp_rs232_2line_iob.vhd" in Library work.
Entity <bp_rs232_2line_iob> compiled.
Entity <bp_rs232_2line_iob> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../bplib/bpgen/sn_humanio.vhd" in Library work.
Entity <sn_humanio> compiled.
Entity <sn_humanio> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/rlink/rlink_sp1c.vhd" in Library work.
Entity <rlink_sp1c> compiled.
Entity <rlink_sp1c> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../tst_sram.vhd" in Library work.
Entity <tst_sram> compiled.
Entity <tst_sram> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../bplib/s3board/s3_sram_memctl.vhd" in Library work.
Entity <s3_sram_memctl> compiled.
Entity <s3_sram_memctl> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../sys_tst_sram_s3.vhd" in Library work.
Entity <sys_tst_sram_s3> compiled.
Entity <sys_tst_sram_s3> (Architecture <syn>) compiled.

Reading constraint file sys_tst_sram_s3.xcf.
XCF parsing done.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <sys_tst_sram_s3> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <clkdivce> in library <work> (architecture <syn>) with generics.
	CDUWIDTH = 6
	MSECDIV = 1000
	USECDIV = 50

Analyzing hierarchy for entity <bp_rs232_2line_iob> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <sn_humanio> in library <work> (architecture <syn>) with generics.
	BWIDTH = 4
	DCWIDTH = 2
	DEBOUNCE = true
	LWIDTH = 8
	SWIDTH = 8

Analyzing hierarchy for entity <rlink_sp1c> in library <work> (architecture <syn>) with generics.
	BTOWIDTH = 6
	CDINIT = 433
	CDWIDTH = 13
	ENAPIN_RBMON = 13
	ENAPIN_RLBMON = -1
	ENAPIN_RLMON = 15
	IFAWIDTH = 5
	OFAWIDTH = 5
	RBMON_AWIDTH = 0
	RBMON_RBADDR = "1111111111101000"
	RTAWIDTH = 12
	SYSID = "00000000000000000000000000000000"

Analyzing hierarchy for entity <tst_sram> in library <work> (architecture <syn>) with generics.
	AWIDTH = 18
	RB_ADDR = "0000000000000000"

Analyzing hierarchy for entity <s3_sram_memctl> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <iob_reg_i> in library <work> (architecture <syn>) with generics.
	INIT = '1'

Analyzing hierarchy for entity <iob_reg_o> in library <work> (architecture <syn>) with generics.
	INIT = '1'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 4
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 8
	INIT = '0'

Analyzing hierarchy for entity <bp_swibtnled> in library <work> (architecture <syn>) with generics.
	BWIDTH = 4
	DEBOUNCE = true
	LWIDTH = 8
	SWIDTH = 8

Analyzing hierarchy for entity <sn_7segctl> in library <work> (architecture <syn>) with generics.
	CDWIDTH = 7
	DCWIDTH = 2

Analyzing hierarchy for entity <rlink_core8> in library <work> (architecture <syn>) with generics.
	BTOWIDTH = 6
	ENAPIN_RBMON = 13
	ENAPIN_RLBMON = -1
	ENAPIN_RLMON = 15
	RTAWIDTH = 12
	SYSID = "00000000000000000000000000000000"

Analyzing hierarchy for entity <serport_1clock> in library <work> (architecture <syn>) with generics.
	CDINIT = 433
	CDWIDTH = 13
	RXFAWIDTH = 5
	TXFAWIDTH = 5

Analyzing hierarchy for entity <rb_sres_or_2> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ram_1swsr_wfirst_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 11
	DWIDTH = 16

Analyzing hierarchy for entity <ram_2swsr_wfirst_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 11
	DWIDTH = 16

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 2
	INIT = '1'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 4
	INIT = '1'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 18
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_io_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 32
	INITE = '0'
	INITI = '0'
	INITO = '0'
	PULL = "NONE"

Analyzing hierarchy for entity <iob_reg_i_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 1
	INIT = '1'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 1
	INIT = '1'

Analyzing hierarchy for entity <iob_reg_i_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 8
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_i_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 4
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 8
	INIT = '0'

Analyzing hierarchy for entity <debounce_gen> in library <work> (architecture <syn>) with generics.
	CEDIV = 3
	CWIDTH = 2
	DWIDTH = 8

Analyzing hierarchy for entity <debounce_gen> in library <work> (architecture <syn>) with generics.
	CEDIV = 3
	CWIDTH = 2
	DWIDTH = 4

Analyzing hierarchy for entity <rlink_core> in library <work> (architecture <syn>) with generics.
	BTOWIDTH = 6
	ENAPIN_RBMON = 13
	ENAPIN_RLMON = 15
	RTAWIDTH = 12
	SYSID = "00000000000000000000000000000000"

Analyzing hierarchy for entity <byte2cdata> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <cdata2byte> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <serport_uart_rxtx_ab> in library <work> (architecture <syn>) with generics.
	CDINIT = 433
	CDWIDTH = 13

Analyzing hierarchy for entity <serport_xonrx> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <serport_xontx> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <fifo_1c_dram> in library <work> (architecture <syn>) with generics.
	AWIDTH = 5
	DWIDTH = 8

Analyzing hierarchy for entity <ram_1swsr_xfirst_gen_unisim> in library <work> (architecture <syn>) with generics.
	AWIDTH = 11
	DWIDTH = 16
	WRITE_MODE = "WRITE_FIRST"

Analyzing hierarchy for entity <ram_2swsr_xfirst_gen_unisim> in library <work> (architecture <syn>) with generics.
	AWIDTH = 11
	DWIDTH = 16
	WRITE_MODE = "WRITE_FIRST"

Analyzing hierarchy for entity <ram_2swsr_rfirst_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 12
	DWIDTH = 8

Analyzing hierarchy for entity <crc16> in library <work> (architecture <syn>) with generics.
	INIT = "0000000000000000"

Analyzing hierarchy for entity <rb_sel> in library <work> (architecture <syn>) with generics.
	RB_ADDR = "1111111111111100"
	SAWIDTH = 2

Analyzing hierarchy for entity <rb_sres_or_2> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <serport_uart_autobaud> in library <work> (architecture <syn>) with generics.
	CDINIT = 433
	CDWIDTH = 13

Analyzing hierarchy for entity <serport_uart_rxtx> in library <work> (architecture <syn>) with generics.
	CDWIDTH = 13

Analyzing hierarchy for entity <fifo_1c_dram_raw> in library <work> (architecture <syn>) with generics.
	AWIDTH = 5
	DWIDTH = 8

Analyzing hierarchy for entity <ram_2swsr_xfirst_gen_unisim> in library <work> (architecture <syn>) with generics.
	AWIDTH = 12
	DWIDTH = 8
	WRITE_MODE = "READ_FIRST"

Analyzing hierarchy for entity <serport_uart_rx> in library <work> (architecture <syn>) with generics.
	CDWIDTH = 13

Analyzing hierarchy for entity <serport_uart_tx> in library <work> (architecture <syn>) with generics.
	CDWIDTH = 13

Analyzing hierarchy for entity <ram_1swar_1ar_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 5
	DWIDTH = 8


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sys_tst_sram_s3> in library <work> (Architecture <syn>).
WARNING:Xst:753 - "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../sys_tst_sram_s3.vhd" line 203: Unconnected output port 'RL_MONI' of component 'rlink_sp1c'.
Entity <sys_tst_sram_s3> analyzed. Unit <sys_tst_sram_s3> generated.

Analyzing generic Entity <clkdivce> in library <work> (Architecture <syn>).
	CDUWIDTH = 6
	MSECDIV = 1000
	USECDIV = 50
Entity <clkdivce> analyzed. Unit <clkdivce> generated.

Analyzing Entity <bp_rs232_2line_iob> in library <work> (Architecture <syn>).
Entity <bp_rs232_2line_iob> analyzed. Unit <bp_rs232_2line_iob> generated.

Analyzing generic Entity <iob_reg_i> in library <work> (Architecture <syn>).
	INIT = '1'
Entity <iob_reg_i> analyzed. Unit <iob_reg_i> generated.

Analyzing generic Entity <iob_reg_i_gen.1> in library <work> (Architecture <syn>).
	DWIDTH = 1
	INIT = '1'
    Set user-defined property "IOB =  true" for signal <R_DI>.
Entity <iob_reg_i_gen.1> analyzed. Unit <iob_reg_i_gen.1> generated.

Analyzing generic Entity <iob_reg_o> in library <work> (Architecture <syn>).
	INIT = '1'
Entity <iob_reg_o> analyzed. Unit <iob_reg_o> generated.

Analyzing generic Entity <iob_reg_o_gen.6> in library <work> (Architecture <syn>).
	DWIDTH = 1
	INIT = '1'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.6> analyzed. Unit <iob_reg_o_gen.6> generated.

Analyzing generic Entity <sn_humanio> in library <work> (Architecture <syn>).
	BWIDTH = 4
	DCWIDTH = 2
	DEBOUNCE = true
	LWIDTH = 8
	SWIDTH = 8
Entity <sn_humanio> analyzed. Unit <sn_humanio> generated.

Analyzing generic Entity <iob_reg_o_gen.1> in library <work> (Architecture <syn>).
	DWIDTH = 4
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.1> analyzed. Unit <iob_reg_o_gen.1> generated.

Analyzing generic Entity <iob_reg_o_gen.2> in library <work> (Architecture <syn>).
	DWIDTH = 8
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.2> analyzed. Unit <iob_reg_o_gen.2> generated.

Analyzing generic Entity <bp_swibtnled> in library <work> (Architecture <syn>).
	BWIDTH = 4
	DEBOUNCE = true
	LWIDTH = 8
	SWIDTH = 8
Entity <bp_swibtnled> analyzed. Unit <bp_swibtnled> generated.

Analyzing generic Entity <iob_reg_i_gen.2> in library <work> (Architecture <syn>).
	DWIDTH = 8
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DI>.
Entity <iob_reg_i_gen.2> analyzed. Unit <iob_reg_i_gen.2> generated.

Analyzing generic Entity <iob_reg_i_gen.3> in library <work> (Architecture <syn>).
	DWIDTH = 4
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DI>.
Entity <iob_reg_i_gen.3> analyzed. Unit <iob_reg_i_gen.3> generated.

Analyzing generic Entity <debounce_gen.1> in library <work> (Architecture <syn>).
	CEDIV = 3
	CWIDTH = 2
	DWIDTH = 8
Entity <debounce_gen.1> analyzed. Unit <debounce_gen.1> generated.

Analyzing generic Entity <debounce_gen.2> in library <work> (Architecture <syn>).
	CEDIV = 3
	CWIDTH = 2
	DWIDTH = 4
Entity <debounce_gen.2> analyzed. Unit <debounce_gen.2> generated.

Analyzing generic Entity <sn_7segctl> in library <work> (Architecture <syn>).
	CDWIDTH = 7
	DCWIDTH = 2
Entity <sn_7segctl> analyzed. Unit <sn_7segctl> generated.

Analyzing generic Entity <rlink_sp1c> in library <work> (Architecture <syn>).
	BTOWIDTH = 6
	CDINIT = 433
	CDWIDTH = 13
	ENAPIN_RBMON = 13
	ENAPIN_RLBMON = -1
	ENAPIN_RLMON = 15
	IFAWIDTH = 5
	OFAWIDTH = 5
	RBMON_AWIDTH = 0
	RBMON_RBADDR = "1111111111101000"
	RTAWIDTH = 12
	SYSID = "00000000000000000000000000000000"
Entity <rlink_sp1c> analyzed. Unit <rlink_sp1c> generated.

Analyzing generic Entity <rlink_core8> in library <work> (Architecture <syn>).
	BTOWIDTH = 6
	ENAPIN_RBMON = 13
	ENAPIN_RLBMON = -1
	ENAPIN_RLMON = 15
	RTAWIDTH = 12
	SYSID = "00000000000000000000000000000000"
    Set property "fsm_encoding = one-hot" for unit <rlink_core>.
Entity <rlink_core8> analyzed. Unit <rlink_core8> generated.

Analyzing generic Entity <rlink_core> in library <work> (Architecture <syn>).
	BTOWIDTH = 6
	ENAPIN_RBMON = 13
	ENAPIN_RLMON = 15
	RTAWIDTH = 12
	SYSID = "00000000000000000000000000000000"
WARNING:Xst:753 - "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/rlink/rlink_core.vhd" line 447: Unconnected output port 'DOA' of component 'ram_2swsr_rfirst_gen'.
WARNING:Xst:753 - "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/rlink/rlink_core.vhd" line 466: Unconnected output port 'BUSY' of component 'fifo_1c_dram'.
Entity <rlink_core> analyzed. Unit <rlink_core> generated.

Analyzing generic Entity <ram_2swsr_rfirst_gen> in library <work> (Architecture <syn>).
	AWIDTH = 12
	DWIDTH = 8
Entity <ram_2swsr_rfirst_gen> analyzed. Unit <ram_2swsr_rfirst_gen> generated.

Analyzing generic Entity <ram_2swsr_xfirst_gen_unisim.2> in library <work> (Architecture <syn>).
	AWIDTH = 12
	DWIDTH = 8
	WRITE_MODE = "READ_FIRST"
    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_A =  000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_B =  000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "SRVAL_A =  000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "SRVAL_B =  000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "WRITE_MODE_A =  READ_FIRST" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "WRITE_MODE_B =  READ_FIRST" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_A =  000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_B =  000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "SRVAL_A =  000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "SRVAL_B =  000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "WRITE_MODE_A =  READ_FIRST" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "WRITE_MODE_B =  READ_FIRST" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
Entity <ram_2swsr_xfirst_gen_unisim.2> analyzed. Unit <ram_2swsr_xfirst_gen_unisim.2> generated.

Analyzing generic Entity <fifo_1c_dram> in library <work> (Architecture <syn>).
	AWIDTH = 5
	DWIDTH = 8
Entity <fifo_1c_dram> analyzed. Unit <fifo_1c_dram> generated.

Analyzing generic Entity <fifo_1c_dram_raw> in library <work> (Architecture <syn>).
	AWIDTH = 5
	DWIDTH = 8
WARNING:Xst:753 - "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/fifo_1c_dram_raw.vhd" line 79: Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'.
Entity <fifo_1c_dram_raw> analyzed. Unit <fifo_1c_dram_raw> generated.

Analyzing generic Entity <ram_1swar_1ar_gen> in library <work> (Architecture <syn>).
	AWIDTH = 5
	DWIDTH = 8
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[7].MEM0> in unit <ram_1swar_1ar_gen>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[7].MEM1> in unit <ram_1swar_1ar_gen>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[6].MEM0> in unit <ram_1swar_1ar_gen>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[6].MEM1> in unit <ram_1swar_1ar_gen>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[5].MEM0> in unit <ram_1swar_1ar_gen>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[5].MEM1> in unit <ram_1swar_1ar_gen>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[4].MEM0> in unit <ram_1swar_1ar_gen>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[4].MEM1> in unit <ram_1swar_1ar_gen>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[3].MEM0> in unit <ram_1swar_1ar_gen>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[3].MEM1> in unit <ram_1swar_1ar_gen>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[2].MEM0> in unit <ram_1swar_1ar_gen>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[2].MEM1> in unit <ram_1swar_1ar_gen>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[1].MEM0> in unit <ram_1swar_1ar_gen>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[1].MEM1> in unit <ram_1swar_1ar_gen>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[0].MEM0> in unit <ram_1swar_1ar_gen>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[0].MEM1> in unit <ram_1swar_1ar_gen>.
Entity <ram_1swar_1ar_gen> analyzed. Unit <ram_1swar_1ar_gen> generated.

Analyzing generic Entity <crc16> in library <work> (Architecture <syn>).
	INIT = "0000000000000000"
Entity <crc16> analyzed. Unit <crc16> generated.

Analyzing generic Entity <rb_sel> in library <work> (Architecture <syn>).
	RB_ADDR = "1111111111111100"
	SAWIDTH = 2
Entity <rb_sel> analyzed. Unit <rb_sel> generated.

Analyzing Entity <byte2cdata> in library <work> (Architecture <syn>).
Entity <byte2cdata> analyzed. Unit <byte2cdata> generated.

Analyzing Entity <cdata2byte> in library <work> (Architecture <syn>).
Entity <cdata2byte> analyzed. Unit <cdata2byte> generated.

Analyzing generic Entity <serport_1clock> in library <work> (Architecture <syn>).
	CDINIT = 433
	CDWIDTH = 13
	RXFAWIDTH = 5
	TXFAWIDTH = 5
WARNING:Xst:753 - "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_1clock.vhd" line 188: Unconnected output port 'SIZE' of component 'fifo_1c_dram'.
Entity <serport_1clock> analyzed. Unit <serport_1clock> generated.

Analyzing generic Entity <serport_uart_rxtx_ab> in library <work> (Architecture <syn>).
	CDINIT = 433
	CDWIDTH = 13
Entity <serport_uart_rxtx_ab> analyzed. Unit <serport_uart_rxtx_ab> generated.

Analyzing generic Entity <serport_uart_autobaud> in library <work> (Architecture <syn>).
	CDINIT = 433
	CDWIDTH = 13
Entity <serport_uart_autobaud> analyzed. Unit <serport_uart_autobaud> generated.

Analyzing generic Entity <serport_uart_rxtx> in library <work> (Architecture <syn>).
	CDWIDTH = 13
Entity <serport_uart_rxtx> analyzed. Unit <serport_uart_rxtx> generated.

Analyzing generic Entity <serport_uart_rx> in library <work> (Architecture <syn>).
	CDWIDTH = 13
Entity <serport_uart_rx> analyzed. Unit <serport_uart_rx> generated.

Analyzing generic Entity <serport_uart_tx> in library <work> (Architecture <syn>).
	CDWIDTH = 13
Entity <serport_uart_tx> analyzed. Unit <serport_uart_tx> generated.

Analyzing Entity <serport_xonrx> in library <work> (Architecture <syn>).
Entity <serport_xonrx> analyzed. Unit <serport_xonrx> generated.

Analyzing Entity <serport_xontx> in library <work> (Architecture <syn>).
Entity <serport_xontx> analyzed. Unit <serport_xontx> generated.

Analyzing Entity <rb_sres_or_2> in library <work> (Architecture <syn>).
Entity <rb_sres_or_2> analyzed. Unit <rb_sres_or_2> generated.

Analyzing generic Entity <tst_sram> in library <work> (Architecture <syn>).
	AWIDTH = 18
	RB_ADDR = "0000000000000000"
WARNING:Xst:753 - "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../tst_sram.vhd" line 387: Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen'.
WARNING:Xst:753 - "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../tst_sram.vhd" line 406: Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen'.
Entity <tst_sram> analyzed. Unit <tst_sram> generated.

Analyzing generic Entity <ram_1swsr_wfirst_gen> in library <work> (Architecture <syn>).
	AWIDTH = 11
	DWIDTH = 16
Entity <ram_1swsr_wfirst_gen> analyzed. Unit <ram_1swsr_wfirst_gen> generated.

Analyzing generic Entity <ram_1swsr_xfirst_gen_unisim> in library <work> (Architecture <syn>).
	AWIDTH = 11
	DWIDTH = 16
	WRITE_MODE = "WRITE_FIRST"
    Set user-defined property "INIT =  000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "SRVAL =  000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "WRITE_MODE =  WRITE_FIRST" for instance <AW_11_S9.GL[1].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT =  000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "SRVAL =  000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "WRITE_MODE =  WRITE_FIRST" for instance <AW_11_S9.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
Entity <ram_1swsr_xfirst_gen_unisim> analyzed. Unit <ram_1swsr_xfirst_gen_unisim> generated.

Analyzing generic Entity <ram_2swsr_wfirst_gen> in library <work> (Architecture <syn>).
	AWIDTH = 11
	DWIDTH = 16
Entity <ram_2swsr_wfirst_gen> analyzed. Unit <ram_2swsr_wfirst_gen> generated.

Analyzing generic Entity <ram_2swsr_xfirst_gen_unisim.1> in library <work> (Architecture <syn>).
	AWIDTH = 11
	DWIDTH = 16
	WRITE_MODE = "WRITE_FIRST"
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_A =  000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_B =  000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "SRVAL_A =  000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "SRVAL_B =  000000000" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <AW_11_S9.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_A =  000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_B =  000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "SRVAL_A =  000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "SRVAL_B =  000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
Entity <ram_2swsr_xfirst_gen_unisim.1> analyzed. Unit <ram_2swsr_xfirst_gen_unisim.1> generated.

Analyzing Entity <s3_sram_memctl> in library <work> (Architecture <syn>).
Entity <s3_sram_memctl> analyzed. Unit <s3_sram_memctl> generated.

Analyzing generic Entity <iob_reg_o_gen.3> in library <work> (Architecture <syn>).
	DWIDTH = 2
	INIT = '1'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.3> analyzed. Unit <iob_reg_o_gen.3> generated.

Analyzing generic Entity <iob_reg_o_gen.4> in library <work> (Architecture <syn>).
	DWIDTH = 4
	INIT = '1'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.4> analyzed. Unit <iob_reg_o_gen.4> generated.

Analyzing generic Entity <iob_reg_o_gen.5> in library <work> (Architecture <syn>).
	DWIDTH = 18
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.5> analyzed. Unit <iob_reg_o_gen.5> generated.

Analyzing generic Entity <iob_reg_io_gen> in library <work> (Architecture <syn>).
	DWIDTH = 32
	INITE = '0'
	INITI = '0'
	INITO = '0'
	PULL = "NONE"
    Set user-defined property "IOB =  true" for signal <R_TE>.
    Set user-defined property "IOB =  true" for signal <R_DI>.
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_io_gen> analyzed. Unit <iob_reg_io_gen> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <clkdivce>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/genlib/clkdivce.vhd".
    Found 6-bit subtractor for signal <N_REGS.ucnt$addsub0000> created at line 99.
    Found 10-bit down counter for signal <R_REGS.mcnt>.
    Found 1-bit register for signal <R_REGS.msec>.
    Found 6-bit register for signal <R_REGS.ucnt>.
    Found 1-bit register for signal <R_REGS.usec>.
    Summary:
	inferred   1 Counter(s).
	inferred   8 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <clkdivce> synthesized.


Synthesizing Unit <iob_reg_i_gen_1>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_i_gen.vhd".
    Found 1-bit register for signal <R_DI<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <iob_reg_i_gen_1> synthesized.


Synthesizing Unit <iob_reg_o_gen_6>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 1-bit register for signal <R_DO<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <iob_reg_o_gen_6> synthesized.


Synthesizing Unit <iob_reg_o_gen_1>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 4-bit register for signal <R_DO>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <iob_reg_o_gen_1> synthesized.


Synthesizing Unit <iob_reg_o_gen_2>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 8-bit register for signal <R_DO>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <iob_reg_o_gen_2> synthesized.


Synthesizing Unit <sn_7segctl>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../bplib/bpgen/sn_7segctl.vhd".
    Found 16x7-bit ROM for signal <SEG_N$rom0000> created at line 154.
    Found 1-bit 4-to-1 multiplexer for signal <CDP>.
    Found 4-bit 4-to-1 multiplexer for signal <CHEX>.
    Found 7-bit down counter for signal <R_REGS.cdiv>.
    Found 2-bit up counter for signal <R_REGS.dcnt>.
    Summary:
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred   5 Multiplexer(s).
Unit <sn_7segctl> synthesized.


Synthesizing Unit <iob_reg_i_gen_2>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_i_gen.vhd".
    Found 8-bit register for signal <R_DI>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <iob_reg_i_gen_2> synthesized.


Synthesizing Unit <iob_reg_i_gen_3>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_i_gen.vhd".
    Found 4-bit register for signal <R_DI>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <iob_reg_i_gen_3> synthesized.


Synthesizing Unit <debounce_gen_1>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/genlib/debounce_gen.vhd".
    Found 1-bit xor2 for signal <n.dchange_0$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_1$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_2$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_3$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_4$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_5$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_6$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_7$xor0000> created at line 104.
    Found 2-bit down counter for signal <R_REGS.cecnt>.
    Found 8-bit register for signal <R_REGS.dchange>.
    Found 8-bit register for signal <R_REGS.dout>.
    Found 8-bit register for signal <R_REGS.dref>.
    Summary:
	inferred   1 Counter(s).
	inferred  24 D-type flip-flop(s).
Unit <debounce_gen_1> synthesized.


Synthesizing Unit <debounce_gen_2>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/genlib/debounce_gen.vhd".
    Found 1-bit xor2 for signal <n.dchange_0$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_1$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_2$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_3$xor0000> created at line 104.
    Found 2-bit down counter for signal <R_REGS.cecnt>.
    Found 4-bit register for signal <R_REGS.dchange>.
    Found 4-bit register for signal <R_REGS.dout>.
    Found 4-bit register for signal <R_REGS.dref>.
    Summary:
	inferred   1 Counter(s).
	inferred  12 D-type flip-flop(s).
Unit <debounce_gen_2> synthesized.


Synthesizing Unit <rb_sres_or_2>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/rbus/rb_sres_or_2.vhd".
Unit <rb_sres_or_2> synthesized.


Synthesizing Unit <byte2cdata>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/comlib/byte2cdata.vhd".
    Found 9-bit register for signal <R_REGS.data>.
    Found 3-bit comparator equal for signal <R_REGS.data$cmp_eq0001> created at line 103.
    Found 1-bit register for signal <R_REGS.dataval>.
    Found 1-bit register for signal <R_REGS.edpend>.
    Summary:
	inferred  11 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <byte2cdata> synthesized.


Synthesizing Unit <cdata2byte>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/comlib/cdata2byte.vhd".
    Found 8-bit register for signal <R_REGS.data>.
    Found 1-bit register for signal <R_REGS.dataval>.
    Found 3-bit register for signal <R_REGS.ecode>.
    Found 1-bit register for signal <R_REGS.ecodeval>.
    Summary:
	inferred  13 D-type flip-flop(s).
Unit <cdata2byte> synthesized.


Synthesizing Unit <crc16>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/comlib/crc16.vhd".
    Found 16-bit register for signal <R_CRC>.
    Found 1-bit xor3 for signal <R_CRC$xor0000> created at line 252.
    Found 1-bit xor3 for signal <R_CRC$xor0001> created at line 251.
    Found 1-bit xor3 for signal <R_CRC$xor0002> created at line 250.
    Found 1-bit xor3 for signal <R_CRC$xor0003> created at line 249.
    Found 1-bit xor2 for signal <R_CRC$xor0004> created at line 248.
    Found 1-bit xor2 for signal <R_CRC$xor0005> created at line 247.
    Found 1-bit xor2 for signal <R_CRC$xor0006> created at line 246.
    Found 1-bit xor3 for signal <R_CRC$xor0007> created at line 245.
    Found 1-bit xor3 for signal <R_CRC$xor0008> created at line 243.
    Found 1-bit xor3 for signal <R_CRC$xor0009> created at line 242.
    Found 1-bit xor2 for signal <R_CRC$xor0010> created at line 241.
    Found 1-bit xor2 for signal <R_CRC$xor0011> created at line 234.
    Found 1-bit xor2 for signal <R_CRC$xor0012> created at line 239.
    Found 1-bit xor2 for signal <R_CRC$xor0013> created at line 238.
    Found 1-bit xor2 for signal <R_CRC$xor0014> created at line 237.
    Found 1-bit xor3 for signal <R_CRC$xor0015> created at line 236.
    Found 1-bit xor2 for signal <R_CRC$xor0016> created at line 252.
    Found 1-bit xor2 for signal <R_CRC$xor0017> created at line 252.
    Found 1-bit xor2 for signal <R_CRC$xor0018> created at line 251.
    Found 1-bit xor2 for signal <R_CRC$xor0019> created at line 251.
    Found 1-bit xor2 for signal <R_CRC$xor0020> created at line 250.
    Found 1-bit xor2 for signal <R_CRC$xor0021> created at line 250.
    Summary:
	inferred  16 D-type flip-flop(s).
	inferred   8 Xor(s).
Unit <crc16> synthesized.


Synthesizing Unit <rb_sel>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/rbus/rb_sel.vhd".
WARNING:Xst:647 - Input <RB_MREQ.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.addr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <rb_sel> synthesized.


Synthesizing Unit <serport_xonrx>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_xonrx.vhd".
    Found 1-bit register for signal <R_REGS.escseen>.
    Found 8-bit register for signal <R_REGS.rxdata>.
    Found 1-bit register for signal <R_REGS.rxovr>.
    Found 1-bit register for signal <R_REGS.rxval>.
    Found 1-bit register for signal <R_REGS.txok>.
    Summary:
	inferred  12 D-type flip-flop(s).
Unit <serport_xonrx> synthesized.


Synthesizing Unit <serport_xontx>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_xontx.vhd".
    Found 1-bit register for signal <R_REGS.enaxon_1>.
    Found 1-bit register for signal <R_REGS.escpend>.
    Found 8-bit register for signal <R_REGS.ibuf>.
    Found 1-bit register for signal <R_REGS.ival>.
    Found 8-bit register for signal <R_REGS.obuf>.
    Found 1-bit xor2 for signal <R_REGS.obuf$xor0000> created at line 111.
    Found 1-bit register for signal <R_REGS.oval>.
    Found 1-bit register for signal <R_REGS.rxok>.
    Summary:
	inferred  21 D-type flip-flop(s).
Unit <serport_xontx> synthesized.


Synthesizing Unit <serport_uart_autobaud>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_uart_autobaud.vhd".
    Found finite state machine <FSM_0> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 4                                              |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | RESET                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 00                                             |
    | Power Up State     | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 16-bit adder for signal <N_REGS.ccnt$addsub0000> created at line 166.
    Found 16-bit register for signal <R_REGS.ccnt>.
    Found 7-bit up counter for signal <R_REGS.mcnt>.
    Found 1-bit register for signal <R_REGS.seen1>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  17 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <serport_uart_autobaud> synthesized.


Synthesizing Unit <serport_uart_rx>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_uart_rx.vhd".
    Found finite state machine <FSM_1> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 23                                             |
    | Inputs             | 4                                              |
    | Outputs            | 8                                              |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | RESET                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Power Up State     | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 14-bit comparator greater for signal <dbit$cmp_gt0000> created at line 154.
    Found 14-bit adder for signal <n.dcnt$add0000> created at line 291.
    Found 13-bit subtractor for signal <N_REGS.ccnt$addsub0000> created at line 283.
    Found 4-bit up counter for signal <R_REGS.bcnt>.
    Found 13-bit register for signal <R_REGS.ccnt>.
    Found 14-bit register for signal <R_REGS.dcnt>.
    Found 8-bit register for signal <R_REGS.sreg>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  35 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <serport_uart_rx> synthesized.


Synthesizing Unit <serport_uart_tx>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_uart_tx.vhd".
    Found 13-bit subtractor for signal <N_REGS.ccnt$addsub0000> created at line 126.
    Found 4-bit up counter for signal <R_REGS.bcnt>.
    Found 1-bit register for signal <R_REGS.busy>.
    Found 13-bit register for signal <R_REGS.ccnt>.
    Found 9-bit register for signal <R_REGS.sreg>.
    Summary:
	inferred   1 Counter(s).
	inferred  23 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <serport_uart_tx> synthesized.


Synthesizing Unit <iob_reg_o_gen_3>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 2-bit register for signal <R_DO>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <iob_reg_o_gen_3> synthesized.


Synthesizing Unit <iob_reg_o_gen_4>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 4-bit register for signal <R_DO>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <iob_reg_o_gen_4> synthesized.


Synthesizing Unit <iob_reg_o_gen_5>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 18-bit register for signal <R_DO>.
    Summary:
	inferred  18 D-type flip-flop(s).
Unit <iob_reg_o_gen_5> synthesized.


Synthesizing Unit <iob_reg_io_gen>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_io_gen.vhd".
    Found 32-bit tristate buffer for signal <PAD>.
    Found 32-bit register for signal <R_DI>.
    Found 32-bit register for signal <R_DO>.
    Found 1-bit register for signal <R_TE>.
    Summary:
	inferred  65 D-type flip-flop(s).
	inferred  32 Tristate(s).
Unit <iob_reg_io_gen> synthesized.


Synthesizing Unit <iob_reg_i>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_i.vhd".
Unit <iob_reg_i> synthesized.


Synthesizing Unit <iob_reg_o>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/xlib/iob_reg_o.vhd".
Unit <iob_reg_o> synthesized.


Synthesizing Unit <bp_swibtnled>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../bplib/bpgen/bp_swibtnled.vhd".
Unit <bp_swibtnled> synthesized.


Synthesizing Unit <ram_2swsr_xfirst_gen_unisim_2>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd".
Unit <ram_2swsr_xfirst_gen_unisim_2> synthesized.


Synthesizing Unit <ram_1swar_1ar_gen>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/ram_1swar_1ar_gen_unisim.vhd".
Unit <ram_1swar_1ar_gen> synthesized.


Synthesizing Unit <serport_uart_rxtx>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_uart_rxtx.vhd".
Unit <serport_uart_rxtx> synthesized.


Synthesizing Unit <ram_1swsr_xfirst_gen_unisim>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd".
WARNING:Xst:646 - Signal <L_DO<17:16>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <ram_1swsr_xfirst_gen_unisim> synthesized.


Synthesizing Unit <ram_2swsr_xfirst_gen_unisim_1>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd".
WARNING:Xst:646 - Signal <L_DOB<17:16>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <L_DOA<17:16>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <ram_2swsr_xfirst_gen_unisim_1> synthesized.


Synthesizing Unit <bp_rs232_2line_iob>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../bplib/bpgen/bp_rs232_2line_iob.vhd".
Unit <bp_rs232_2line_iob> synthesized.


Synthesizing Unit <sn_humanio>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../bplib/bpgen/sn_humanio.vhd".
Unit <sn_humanio> synthesized.


Synthesizing Unit <s3_sram_memctl>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../bplib/s3board/s3_sram_memctl.vhd".
    Found finite state machine <FSM_2> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 12                                             |
    | Inputs             | 2                                              |
    | Outputs            | 10                                             |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | RESET                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Power Up State     | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <R_REGS.ackr>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 D-type flip-flop(s).
Unit <s3_sram_memctl> synthesized.


Synthesizing Unit <ram_2swsr_rfirst_gen>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd".
Unit <ram_2swsr_rfirst_gen> synthesized.


Synthesizing Unit <fifo_1c_dram_raw>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/fifo_1c_dram_raw.vhd".
    Found 1-bit register for signal <R_REGS.empty>.
    Found 1-bit register for signal <R_REGS.full>.
    Found 5-bit up counter for signal <R_REGS.raddr>.
    Found 5-bit up counter for signal <R_REGS.waddr>.
    Found 5-bit subtractor for signal <SIZE$sub0000> created at line 120.
    Summary:
	inferred   2 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <fifo_1c_dram_raw> synthesized.


Synthesizing Unit <serport_uart_rxtx_ab>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_uart_rxtx_ab.vhd".
Unit <serport_uart_rxtx_ab> synthesized.


Synthesizing Unit <ram_1swsr_wfirst_gen>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd".
Unit <ram_1swsr_wfirst_gen> synthesized.


Synthesizing Unit <ram_2swsr_wfirst_gen>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/ram_2swsr_wfirst_gen_unisim.vhd".
Unit <ram_2swsr_wfirst_gen> synthesized.


Synthesizing Unit <tst_sram>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../tst_sram.vhd".
WARNING:Xst:647 - Input <MEM_ACK_W> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found finite state machine <FSM_3> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 61                                             |
    | Inputs             | 22                                             |
    | Outputs            | 15                                             |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | SEQ_RESET                 (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Power Up State     | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 18-bit xor2 for signal <ixor_addr$xor0000> created at line 915.
    Found 32-bit xor2 for signal <ixor_data$xor0000> created at line 927.
    Found 18-bit adder for signal <n.maddr_17$add0000> created at line 987.
    Found 32-bit 4-to-1 multiplexer for signal <n.se_data$mux0001> created at line 543.
    Found 32-bit comparator not equal for signal <n.srun$cmp_ne0000> created at line 544.
    Found 4-bit adder for signal <N_REGS.swcnt$addsub0000> created at line 995.
    Found 1-bit 16-to-1 multiplexer for signal <omux_dat_0$mux0000> created at line 1004.
    Found 1-bit 16-to-1 multiplexer for signal <omux_dat_1$mux0000> created at line 1004.
    Found 1-bit 16-to-1 multiplexer for signal <omux_dat_10$mux0000> created at line 1004.
    Found 1-bit 16-to-1 multiplexer for signal <omux_dat_11$mux0000> created at line 1004.
    Found 1-bit 16-to-1 multiplexer for signal <omux_dat_12$mux0000> created at line 1004.
    Found 1-bit 16-to-1 multiplexer for signal <omux_dat_13$mux0000> created at line 1004.
    Found 1-bit 16-to-1 multiplexer for signal <omux_dat_14$mux0000> created at line 1004.
    Found 1-bit 16-to-1 multiplexer for signal <omux_dat_15$mux0000> created at line 1004.
    Found 1-bit 16-to-1 multiplexer for signal <omux_dat_2$mux0000> created at line 1004.
    Found 1-bit 16-to-1 multiplexer for signal <omux_dat_3$mux0000> created at line 1004.
    Found 1-bit 16-to-1 multiplexer for signal <omux_dat_4$mux0000> created at line 1004.
    Found 1-bit 16-to-1 multiplexer for signal <omux_dat_5$mux0000> created at line 1004.
    Found 1-bit 16-to-1 multiplexer for signal <omux_dat_6$mux0000> created at line 1004.
    Found 1-bit 16-to-1 multiplexer for signal <omux_dat_7$mux0000> created at line 1004.
    Found 1-bit 16-to-1 multiplexer for signal <omux_dat_8$mux0000> created at line 1004.
    Found 1-bit 16-to-1 multiplexer for signal <omux_dat_9$mux0000> created at line 1004.
    Found 16-bit register for signal <R_REGS.dispval>.
    Found 18-bit register for signal <R_REGS.maddr>.
    Found 32-bit register for signal <R_REGS.mdi>.
    Found 11-bit register for signal <R_REGS.mrp_adr_al>.
    Found 11-bit register for signal <R_REGS.mrp_adr_dl>.
    Found 32-bit register for signal <R_REGS.mrp_dat_al>.
    Found 32-bit register for signal <R_REGS.mrp_dat_dl>.
    Found 1-bit register for signal <R_REGS.mrp_val_al>.
    Found 1-bit register for signal <R_REGS.mrp_val_dl>.
    Found 1-bit register for signal <R_REGS.rbsel>.
    Found 11-bit register for signal <R_REGS.saddr>.
    Found 11-bit adder for signal <R_REGS.saddr$addsub0000> created at line 991.
    Found 2-bit register for signal <R_REGS.sbank>.
    Found 2-bit subtractor for signal <R_REGS.sbank$addsub0000> created at line 876.
    Found 11-bit register for signal <R_REGS.scaddr>.
    Found 11-bit register for signal <R_REGS.se_addr>.
    Found 32-bit register for signal <R_REGS.se_data>.
    Found 1-bit register for signal <R_REGS.sfail>.
    Found 32-bit comparator equal for signal <R_REGS.sfail$cmp_eq0000> created at line 544.
    Found 1-bit register for signal <R_REGS.slast>.
    Found 11-bit register for signal <R_REGS.slim>.
    Found 1-bit register for signal <R_REGS.sloop>.
    Found 1-bit register for signal <R_REGS.srun>.
    Found 4-bit comparator not equal for signal <R_REGS.state$cmp_ne0000> created at line 933.
    Found 1-bit register for signal <R_REGS.sveri>.
    Found 4-bit register for signal <R_REGS.swcnt>.
    Found 1-bit register for signal <R_REGS.swloop>.
    Found 1-bit register for signal <R_REGS.swswap>.
    Found 1-bit register for signal <R_REGS.sxora>.
    Found 1-bit register for signal <R_REGS.sxord>.
    Found 11-bit comparator equal for signal <saddr_last$cmp_eq0000> created at line 537.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred 246 D-type flip-flop(s).
	inferred   4 Adder/Subtractor(s).
	inferred   4 Comparator(s).
	inferred  48 Multiplexer(s).
Unit <tst_sram> synthesized.


Synthesizing Unit <fifo_1c_dram>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/memlib/fifo_1c_dram.vhd".
Unit <fifo_1c_dram> synthesized.


Synthesizing Unit <serport_1clock>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/serport/serport_1clock.vhd".
WARNING:Xst:646 - Signal <RXFIFO_SIZE<2:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <R_RXOK>.
    Found 3-bit comparator greatequal for signal <R_RXOK$cmp_ge0000> created at line 217.
    Found 3-bit comparator lessequal for signal <R_RXOK$cmp_le0000> created at line 218.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <serport_1clock> synthesized.


Synthesizing Unit <rlink_core>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/rlink/rlink_core.vhd".
    Found finite state machine <FSM_4> for signal <R_BREGS.state>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 30                                             |
    | Inputs             | 10                                             |
    | Outputs            | 13                                             |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | RESET                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Power Up State     | 0000                                           |
    | Encoding           | one-hot                                        |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_5> for signal <R_LREGS.state>.
    -----------------------------------------------------------------------
    | States             | 40                                             |
    | Transitions        | 137                                            |
    | Inputs             | 32                                             |
    | Outputs            | 41                                             |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | RESET                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 000000                                         |
    | Power Up State     | 000000                                         |
    | Encoding           | one-hot                                        |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <L2B_CMD>.
    Found 6-bit subtractor for signal <N_BREGS.btocnt$addsub0000> created at line 1562.
    Found 1-bit register for signal <R_BREGS.blkabo>.
    Found 6-bit register for signal <R_BREGS.btocnt>.
    Found 11-bit down counter for signal <R_BREGS.cnt>.
    Found 1-bit register for signal <R_BREGS.dathpend>.
    Found 11-bit up counter for signal <R_BREGS.dcnt>.
    Found 1-bit register for signal <R_BREGS.rbaval>.
    Found 16-bit register for signal <R_BREGS.rbdout>.
    Found 1-bit register for signal <R_BREGS.rberr>.
    Found 1-bit register for signal <R_BREGS.rbinit>.
    Found 1-bit register for signal <R_BREGS.rbnak>.
    Found 1-bit register for signal <R_BREGS.rbre>.
    Found 1-bit register for signal <R_BREGS.rbtout>.
    Found 1-bit register for signal <R_BREGS.rbwe>.
    Found 4-bit register for signal <R_BREGS.stat>.
    Found 1-bit register for signal <R_BREGS.wfifo>.
    Found 6-bit comparator greatequal for signal <R_BREGS.wfifo$cmp_ge0000> created at line 1379.
    Found 6-bit comparator lessequal for signal <R_BREGS.wfifo$cmp_le0000> created at line 1380.
    Found 1-bit register for signal <R_CREGS.anena>.
    Found 1-bit register for signal <R_CREGS.atoena>.
    Found 8-bit register for signal <R_CREGS.atoval>.
    Found 16-bit register for signal <R_LREGS.addr>.
    Found 1-bit register for signal <R_LREGS.anact>.
    Found 1-bit register for signal <R_LREGS.anreq>.
    Found 1-bit register for signal <R_LREGS.arpend>.
    Found 8-bit down counter for signal <R_LREGS.atocnt>.
    Found 16-bit register for signal <R_LREGS.attn>.
    Found 1-bit register for signal <R_LREGS.babo>.
    Found 12-bit down counter for signal <R_LREGS.bcnt>.
    Found 1-bit register for signal <R_LREGS.cmdseen>.
    Found 16-bit register for signal <R_LREGS.cnt>.
    Found 16-bit register for signal <R_LREGS.din>.
    Found 8-bit register for signal <R_LREGS.dinl>.
    Found 1-bit register for signal <R_LREGS.doretra>.
    Found 8-bit register for signal <R_LREGS.lcmd>.
    Found 1-bit register for signal <R_LREGS.monattn>.
    Found 1-bit register for signal <R_LREGS.moneop>.
    Found 3-bit register for signal <R_LREGS.nakcode>.
    Found 1-bit register for signal <R_LREGS.nakdone>.
    Found 8-bit register for signal <R_LREGS.rcmd>.
    Found 12-bit up counter for signal <R_LREGS.rtaddra>.
    Found 1-bit register for signal <R_LREGS.rtaddra_bad>.
    Found 1-bit register for signal <R_LREGS.rtaddra_red>.
    Found 1-bit register for signal <R_LREGS.rtaddra_zero>.
    Found 12-bit up counter for signal <R_LREGS.rtaddrb>.
    Found 1-bit register for signal <R_LREGS.rtaddrb_bad>.
    Found 1-bit register for signal <R_LREGS.rtaddrb_red>.
    Found 8-bit comparator not equal for signal <R_LREGS.state$cmp_ne0000> created at line 919.
    Found 8-bit comparator not equal for signal <R_LREGS.state$cmp_ne0001> created at line 935.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred   6 Counter(s).
	inferred 151 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   4 Comparator(s).
Unit <rlink_core> synthesized.


Synthesizing Unit <rlink_core8>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/rlink/rlink_core8.vhd".
Unit <rlink_core8> synthesized.


Synthesizing Unit <rlink_sp1c>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../../../../vlib/rlink/rlink_sp1c.vhd".
WARNING:Xst:647 - Input <CE_USEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <RB_SRES_RBMON.err> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <RB_SRES_RBMON.dout> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <RB_SRES_RBMON.busy> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <RB_SRES_RBMON.ack> is used but never assigned. This sourceless signal will be automatically connected to value 0.
Unit <rlink_sp1c> synthesized.


Synthesizing Unit <sys_tst_sram_s3>.
    Related source file is "/home/walter/tmp/w11-test/v0.75/w11/rtl/sys_gen/tst_sram/s3board/ise/../sys_tst_sram_s3.vhd".
WARNING:Xst:646 - Signal <SER_MONI.rxovr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SER_MONI.rxerr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SER_MONI.abdone> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SER_MONI.abclkdiv_f> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SER_MONI.abclkdiv> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SER_MONI.abact> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <RTS_N> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <RB_LAM<15:1>> is used but never assigned. This sourceless signal will be automatically connected to value 000000000000000.
WARNING:Xst:653 - Signal <GBL_RESET> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <CTS_N> is used but never assigned. This sourceless signal will be automatically connected to value 0.
Unit <sys_tst_sram_s3> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 16x7-bit ROM                                          : 1
# Adders/Subtractors                                   : 13
 11-bit adder                                          : 1
 13-bit subtractor                                     : 2
 14-bit adder                                          : 1
 16-bit adder                                          : 1
 18-bit adder                                          : 1
 2-bit subtractor                                      : 1
 4-bit adder                                           : 1
 5-bit subtractor                                      : 3
 6-bit subtractor                                      : 2
# Counters                                             : 20
 10-bit down counter                                   : 1
 11-bit down counter                                   : 1
 11-bit up counter                                     : 1
 12-bit down counter                                   : 1
 12-bit up counter                                     : 2
 2-bit down counter                                    : 2
 2-bit up counter                                      : 1
 4-bit up counter                                      : 2
 5-bit up counter                                      : 6
 7-bit down counter                                    : 1
 7-bit up counter                                      : 1
 8-bit down counter                                    : 1
# Registers                                            : 126
 1-bit register                                        : 69
 11-bit register                                       : 6
 13-bit register                                       : 2
 14-bit register                                       : 1
 16-bit register                                       : 9
 18-bit register                                       : 2
 2-bit register                                        : 2
 3-bit register                                        : 2
 32-bit register                                       : 6
 4-bit register                                        : 8
 6-bit register                                        : 2
 8-bit register                                        : 15
 9-bit register                                        : 2
# Comparators                                          : 12
 11-bit comparator equal                               : 1
 14-bit comparator greater                             : 1
 3-bit comparator equal                                : 1
 3-bit comparator greatequal                           : 1
 3-bit comparator lessequal                            : 1
 32-bit comparator equal                               : 1
 32-bit comparator not equal                           : 1
 4-bit comparator not equal                            : 1
 6-bit comparator greatequal                           : 1
 6-bit comparator lessequal                            : 1
 8-bit comparator not equal                            : 2
# Multiplexers                                         : 22
 1-bit 16-to-1 multiplexer                             : 16
 1-bit 4-to-1 multiplexer                              : 5
 32-bit 4-to-1 multiplexer                             : 1
# Tristates                                            : 1
 32-bit tristate buffer                                : 1
# Xors                                                 : 59
 1-bit xor2                                            : 41
 1-bit xor3                                            : 16
 18-bit xor2                                           : 1
 32-bit xor2                                           : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Optimizing FSM <RLINK/CORE/RL/R_LREGS.state/FSM> on signal <R_LREGS.state[1:40]> with one-hot encoding.
----------------------------------------------------
 State  | Encoding
----------------------------------------------------
 000000 | 0000000000000000000000000000000000000001
 000001 | 0000000000000000000000000000000000000010
 000010 | 0000000000000000000000000000000000000100
 000011 | 0000000000000000000000000000000000100000
 000100 | 0000000000000000000000000000000100000000
 000101 | 0000000000000000000000000000000001000000
 000110 | 0000000000000000000000000000000000010000
 000111 | 0000000000000000000000000000001000000000
 001000 | 0000000000000000000000000000000010000000
 001001 | 0000000000000000000000000000010000000000
 001010 | 0000000000000000000000000001000000000000
 001011 | 0000000000000000000000000010000000000000
 001100 | 0000000000000000000000001000000000000000
 001101 | 0000000000000000000000000100000000000000
 001110 | 0000000000000000000000010000000000000000
 001111 | 0000000000000000000000000000100000000000
 010000 | 0000000000000000000000100000000000000000
 010001 | 0000000000000000000001000000000000000000
 010010 | 0000000000000000000000000000000000001000
 010011 | 0000000000000100000000000000000000000000
 010100 | 0000000000000000000010000000000000000000
 010101 | 0000000000100000000000000000000000000000
 010110 | 0000000000000000001000000000000000000000
 010111 | 0000000001000000000000000000000000000000
 011000 | 0000000000000000010000000000000000000000
 011001 | 0000000010000000000000000000000000000000
 011010 | 0000000100000000000000000000000000000000
 011011 | 0000001000000000000000000000000000000000
 011100 | 0000010000000000000000000000000000000000
 011101 | 0000100000000000000000000000000000000000
 011110 | 0001000000000000000000000000000000000000
 011111 | 0000000000000000000100000000000000000000
 100000 | 0010000000000000000000000000000000000000
 100001 | 0000000000010000000000000000000000000000
 100010 | 0100000000000000000000000000000000000000
 100011 | 0000000000000000100000000000000000000000
 100100 | 0000000000000001000000000000000000000000
 100101 | 0000000000000010000000000000000000000000
 100110 | 0000000000001000000000000000000000000000
 100111 | 1000000000000000000000000000000000000000
----------------------------------------------------
Optimizing FSM <RLINK/CORE/RL/R_BREGS.state/FSM> on signal <R_BREGS.state[1:13]> with one-hot encoding.
------------------------
 State | Encoding
------------------------
 0000  | 0000000000001
 0001  | 0000000000010
 0010  | 0000000001000
 0011  | 0000000010000
 0100  | 0000000100000
 0101  | 0000010000000
 0110  | 0000100000000
 0111  | 0000001000000
 1000  | 0000000000100
 1001  | 0001000000000
 1010  | 0010000000000
 1011  | 0100000000000
 1100  | 1000000000000
------------------------
Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <TST/R_REGS.state/FSM> on signal <R_REGS.state[1:13]> with one-hot encoding.
------------------------
 State | Encoding
------------------------
 0000  | 0000000000001
 0001  | 0000000000010
 0010  | 0000100000000
 0011  | 0000000001000
 0100  | 0001000000000
 0101  | 0000000000100
 0110  | 0010000000000
 0111  | 0000000010000
 1000  | 0000000100000
 1001  | 0000001000000
 1010  | 0100000000000
 1011  | 0000010000000
 1100  | 1000000000000
------------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <SRAMCTL/R_REGS.state/FSM> on signal <R_REGS.state[1:6]> with one-hot encoding.
-------------------
 State | Encoding
-------------------
 000   | 000001
 001   | 000010
 010   | 000100
 011   | 010000
 100   | 001000
 101   | 100000
-------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <RLINK/SERPORT/UART/RXTX/RX/R_REGS.state/FSM> on signal <R_REGS.state[1:7]> with one-hot encoding.
-------------------
 State | Encoding
-------------------
 000   | 0000001
 001   | 0000100
 010   | 0000010
 011   | 0010000
 100   | 0001000
 101   | 1000000
 110   | 0100000
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <RLINK/SERPORT/UART/AB/R_REGS.state/FSM> on signal <R_REGS.state[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 11
 11    | 10
-------------------

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 6
# ROMs                                                 : 1
 16x7-bit ROM                                          : 1
# Adders/Subtractors                                   : 13
 11-bit adder                                          : 1
 13-bit subtractor                                     : 2
 14-bit adder                                          : 1
 16-bit adder                                          : 1
 18-bit adder                                          : 1
 2-bit subtractor                                      : 1
 4-bit adder                                           : 1
 5-bit subtractor                                      : 3
 6-bit subtractor                                      : 2
# Counters                                             : 20
 10-bit down counter                                   : 1
 11-bit down counter                                   : 1
 11-bit up counter                                     : 1
 12-bit down counter                                   : 1
 12-bit up counter                                     : 2
 2-bit down counter                                    : 2
 2-bit up counter                                      : 1
 4-bit up counter                                      : 2
 5-bit up counter                                      : 6
 7-bit down counter                                    : 1
 7-bit up counter                                      : 1
 8-bit down counter                                    : 1
# Registers                                            : 739
 Flip-Flops                                            : 739
# Comparators                                          : 12
 11-bit comparator equal                               : 1
 14-bit comparator greater                             : 1
 3-bit comparator equal                                : 1
 3-bit comparator greatequal                           : 1
 3-bit comparator lessequal                            : 1
 32-bit comparator equal                               : 1
 32-bit comparator not equal                           : 1
 4-bit comparator not equal                            : 1
 6-bit comparator greatequal                           : 1
 6-bit comparator lessequal                            : 1
 8-bit comparator not equal                            : 2
# Multiplexers                                         : 22
 1-bit 16-to-1 multiplexer                             : 16
 1-bit 4-to-1 multiplexer                              : 5
 32-bit 4-to-1 multiplexer                             : 1
# Xors                                                 : 59
 1-bit xor2                                            : 41
 1-bit xor3                                            : 16
 18-bit xor2                                           : 1
 32-bit xor2                                           : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch <R_REGS.escseen> has a constant value of 0 in block <serport_xonrx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <R_REGS.escpend> has a constant value of 0 in block <serport_xontx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <R_LREGS.attn_1> has a constant value of 0 in block <rlink_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_LREGS.attn_2> has a constant value of 0 in block <rlink_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_LREGS.attn_3> has a constant value of 0 in block <rlink_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_LREGS.attn_4> has a constant value of 0 in block <rlink_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_LREGS.attn_5> has a constant value of 0 in block <rlink_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_LREGS.attn_6> has a constant value of 0 in block <rlink_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_LREGS.attn_7> has a constant value of 0 in block <rlink_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_LREGS.attn_8> has a constant value of 0 in block <rlink_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_LREGS.attn_9> has a constant value of 0 in block <rlink_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_LREGS.attn_10> has a constant value of 0 in block <rlink_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_LREGS.attn_11> has a constant value of 0 in block <rlink_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_LREGS.attn_12> has a constant value of 0 in block <rlink_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_LREGS.attn_13> has a constant value of 0 in block <rlink_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_LREGS.attn_14> has a constant value of 0 in block <rlink_core>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_LREGS.attn_15> has a constant value of 0 in block <rlink_core>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:1901 - Instance SMEM_B2/UMEM/AW_11_S9.GL[1].MEM in unit SMEM_B2/UMEM/AW_11_S9.GL[1].MEM of type RAMB16_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance SMEM_B2/UMEM/AW_11_S9.GL[0].MEM in unit SMEM_B2/UMEM/AW_11_S9.GL[0].MEM of type RAMB16_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance SMEM_B3/UMEM/AW_11_S9.GL[1].MEM in unit SMEM_B3/UMEM/AW_11_S9.GL[1].MEM of type RAMB16_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance SMEM_B3/UMEM/AW_11_S9.GL[0].MEM in unit SMEM_B3/UMEM/AW_11_S9.GL[0].MEM of type RAMB16_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance SMEM_B0/UMEM/AW_11_S9.GL[1].MEM in unit SMEM_B0/UMEM/AW_11_S9.GL[1].MEM of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance SMEM_B0/UMEM/AW_11_S9.GL[0].MEM in unit SMEM_B0/UMEM/AW_11_S9.GL[0].MEM of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance SMEM_B1/UMEM/AW_11_S9.GL[1].MEM in unit SMEM_B1/UMEM/AW_11_S9.GL[1].MEM of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance SMEM_B1/UMEM/AW_11_S9.GL[0].MEM in unit SMEM_B1/UMEM/AW_11_S9.GL[0].MEM of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance RTBUF/UMEM/AW_12_S4.GL[1].MEM in unit RTBUF/UMEM/AW_12_S4.GL[1].MEM of type RAMB16_S4_S4 has been replaced by RAMB16
INFO:Xst:1901 - Instance RTBUF/UMEM/AW_12_S4.GL[0].MEM in unit RTBUF/UMEM/AW_12_S4.GL[0].MEM of type RAMB16_S4_S4 has been replaced by RAMB16
INFO:Xst:2261 - The FF/Latch <R_BREGS.rbwe> in Unit <rlink_core> is equivalent to the following FF/Latch, which will be removed : <R_BREGS.state_FSM_FFd4> 

Optimizing unit <sys_tst_sram_s3> ...

Optimizing unit <clkdivce> ...

Optimizing unit <iob_reg_o_gen_2> ...

Optimizing unit <sn_7segctl> ...

Optimizing unit <iob_reg_i_gen_2> ...

Optimizing unit <debounce_gen_1> ...

Optimizing unit <debounce_gen_2> ...

Optimizing unit <byte2cdata> ...

Optimizing unit <cdata2byte> ...

Optimizing unit <crc16> ...

Optimizing unit <serport_xonrx> ...

Optimizing unit <serport_xontx> ...

Optimizing unit <serport_uart_autobaud> ...

Optimizing unit <serport_uart_rx> ...

Optimizing unit <serport_uart_tx> ...

Optimizing unit <iob_reg_o_gen_5> ...

Optimizing unit <ram_1swar_1ar_gen> ...

Optimizing unit <fifo_1c_dram_raw> ...

Optimizing unit <tst_sram> ...

Optimizing unit <serport_1clock> ...

Optimizing unit <rlink_core> ...
INFO:Xst:2261 - The FF/Latch <R_BREGS.rbre> in Unit <rlink_core> is equivalent to the following FF/Latch, which will be removed : <R_BREGS.state_FSM_FFd10> 
INFO:Xst:2261 - The FF/Latch <R_BREGS.rbre> in Unit <rlink_core> is equivalent to the following FF/Latch, which will be removed : <R_BREGS.state_FSM_FFd10> 
INFO:Xst:2261 - The FF/Latch <R_BREGS.rbre> in Unit <rlink_core> is equivalent to the following FF/Latch, which will be removed : <R_BREGS.state_FSM_FFd10> 
INFO:Xst:2261 - The FF/Latch <R_BREGS.rbre> in Unit <rlink_core> is equivalent to the following FF/Latch, which will be removed : <R_BREGS.state_FSM_FFd10> 
WARNING:Xst:1293 - FF/Latch <RLINK/CORE/RL/R_BREGS.stat_3> has a constant value of 0 in block <sys_tst_sram_s3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/CORE/RL/R_BREGS.stat_2> has a constant value of 0 in block <sys_tst_sram_s3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <CLKDIV/R_REGS.usec> of sequential type is unconnected in block <sys_tst_sram_s3>.
WARNING:Xst:2677 - Node <RLINK/SERPORT/XONRX/R_REGS.rxovr> of sequential type is unconnected in block <sys_tst_sram_s3>.
WARNING:Xst:2677 - Node <RLINK/CORE/RL/R_LREGS.monattn> of sequential type is unconnected in block <sys_tst_sram_s3>.
WARNING:Xst:2677 - Node <RLINK/CORE/RL/R_LREGS.moneop> of sequential type is unconnected in block <sys_tst_sram_s3>.

Mapping all equations...
Annotating constraints using XCF file 'sys_tst_sram_s3.xcf'
XCF parsing done.
Building and optimizing final netlist ...
Replicating register SRAMCTL/IOB_MEM_DATA/R_TE to handle IOB=TRUE attribute

FlipFlop RLINK/CORE/B2CD/R_REGS.data_0 has been replicated 1 time(s)
FlipFlop RLINK/CORE/B2CD/R_REGS.data_1 has been replicated 1 time(s)
FlipFlop RLINK/CORE/B2CD/R_REGS.data_2 has been replicated 1 time(s)
FlipFlop RLINK/CORE/B2CD/R_REGS.data_8 has been replicated 1 time(s)
FlipFlop RLINK/CORE/B2CD/R_REGS.dataval has been replicated 1 time(s)
FlipFlop RLINK/CORE/CD2B/R_REGS.ecodeval has been replicated 1 time(s)
FlipFlop RLINK/CORE/RL/R_BREGS.rbwe has been replicated 1 time(s)
FlipFlop RLINK/CORE/RL/R_LREGS.addr_0 has been replicated 2 time(s)
FlipFlop RLINK/CORE/RL/R_LREGS.addr_1 has been replicated 3 time(s)
FlipFlop RLINK/CORE/RL/R_LREGS.addr_2 has been replicated 3 time(s)
FlipFlop RLINK/CORE/RL/R_LREGS.addr_3 has been replicated 2 time(s)
FlipFlop RLINK/CORE/RL/R_LREGS.addr_4 has been replicated 2 time(s)
FlipFlop SRAMCTL/R_REGS.ackr has been replicated 1 time(s)
FlipFlop TST/R_REGS.rbsel has been replicated 2 time(s)
FlipFlop TST/R_REGS.state_FSM_FFd13 has been replicated 1 time(s)
FlipFlop TST/R_REGS.state_FSM_FFd6 has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 984
 Flip-Flops                                            : 984

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : sys_tst_sram_s3
Output Format                      : ngc
Optimization Goal                  : SPEED
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 93

Cell Usage :
# BELS                             : 2456
#      GND                         : 11
#      INV                         : 65
#      LUT1                        : 81
#      LUT2                        : 197
#      LUT2_D                      : 8
#      LUT2_L                      : 9
#      LUT3                        : 417
#      LUT3_D                      : 26
#      LUT3_L                      : 39
#      LUT4                        : 932
#      LUT4_D                      : 69
#      LUT4_L                      : 114
#      MUXCY                       : 185
#      MUXF5                       : 104
#      MUXF6                       : 22
#      MUXF7                       : 11
#      VCC                         : 1
#      XORCY                       : 165
# FlipFlops/Latches                : 984
#      FD                          : 91
#      FDE                         : 150
#      FDR                         : 213
#      FDRE                        : 393
#      FDRS                        : 89
#      FDRSE                       : 3
#      FDS                         : 31
#      FDSE                        : 14
# RAMS                             : 58
#      RAM16X1D                    : 48
#      RAMB16                      : 10
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 92
#      IBUF                        : 13
#      IOBUF                       : 32
#      OBUF                        : 47
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1000ft256-4 

 Number of Slices:                     1071  out of   7680    13%  
 Number of Slice Flip Flops:            828  out of  15360     5%  
 Number of 4 input LUTs:               2053  out of  15360    13%  
    Number used as logic:              1957
    Number used as RAMs:                 96
 Number of IOs:                          93
 Number of bonded IOBs:                  93  out of    173    53%  
    IOB Flip Flops:                     156
 Number of BRAMs:                        10  out of     24    41%  
 Number of GCLKs:                         1  out of      8    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
I_CLK50                            | BUFGP                  | 1042  |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 11.978ns (Maximum Frequency: 83.486MHz)
   Minimum input arrival time before clock: 1.825ns
   Maximum output required time after clock: 7.408ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'I_CLK50'
  Clock period: 11.978ns (frequency: 83.486MHz)
  Total number of paths / destination ports: 57865 / 2824
-------------------------------------------------------------------------
Delay:               11.978ns (Levels of Logic = 6)
  Source:            SRAMCTL/R_REGS.state_FSM_FFd3 (FF)
  Destination:       RLINK/CORE/RL/R_LREGS.rtaddrb_11 (FF)
  Source Clock:      I_CLK50 rising
  Destination Clock: I_CLK50 rising

  Data Path: SRAMCTL/R_REGS.state_FSM_FFd3 to RLINK/CORE/RL/R_LREGS.rtaddrb_11
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              6   0.720   1.342  SRAMCTL/R_REGS.state_FSM_FFd3 (SRAMCTL/R_REGS.state_FSM_FFd3)
     LUT3:I0->O           12   0.551   1.186  SRAMCTL/R_REGS.state_FSM_Out81 (MEM_BUSY)
     LUT3:I2->O            1   0.551   0.869  TST/RB_SRES_busy27 (TST/RB_SRES_busy27)
     LUT4:I2->O            4   0.551   0.943  TST/RB_SRES_busy46 (TST/RB_SRES_busy46)
     LUT4:I3->O            2   0.551   0.903  TST/RB_SRES_busy142_1 (TST/RB_SRES_busy142)
     LUT4:I3->O            5   0.551   0.989  RLINK/CORE/RL/RTBUF_ENB52 (RLINK/CORE/RL/RTBUF_ENB)
     LUT3:I2->O           12   0.551   1.118  RLINK/CORE/RL/R_LREGS_rtaddrb_not00011 (RLINK/CORE/RL/R_LREGS_rtaddrb_not0001)
     FDRE:CE                   0.602          RLINK/CORE/RL/R_LREGS.rtaddrb_0
    ----------------------------------------
    Total                     11.978ns (4.628ns logic, 7.350ns route)
                                       (38.6% logic, 61.4% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'I_CLK50'
  Total number of paths / destination ports: 45 / 45
-------------------------------------------------------------------------
Offset:              1.825ns (Levels of Logic = 1)
  Source:            I_RXD (PAD)
  Destination:       IOB_RS232/IOB_RXD/IOB/R_DI_0 (FF)
  Destination Clock: I_CLK50 rising

  Data Path: I_RXD to IOB_RS232/IOB_RXD/IOB/R_DI_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.821   0.801  I_RXD_IBUF (I_RXD_IBUF)
     FD:D                      0.203          IOB_RS232/IOB_RXD/IOB/R_DI_0
    ----------------------------------------
    Total                      1.825ns (1.024ns logic, 0.801ns route)
                                       (56.1% logic, 43.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'I_CLK50'
  Total number of paths / destination ports: 111 / 79
-------------------------------------------------------------------------
Offset:              7.408ns (Levels of Logic = 1)
  Source:            SRAMCTL/IOB_MEM_DATA/R_TE_1 (FF)
  Destination:       IO_MEM_DATA<31> (PAD)
  Source Clock:      I_CLK50 rising

  Data Path: SRAMCTL/IOB_MEM_DATA/R_TE_1 to IO_MEM_DATA<31>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.720   0.801  SRAMCTL/IOB_MEM_DATA/R_TE_1 (SRAMCTL/IOB_MEM_DATA/R_TE_1)
     IOBUF:T->IO               5.887          IO_MEM_DATA_31_IOBUF (IO_MEM_DATA<31>)
    ----------------------------------------
    Total                      7.408ns (6.607ns logic, 0.801ns route)
                                       (89.2% logic, 10.8% route)

=========================================================================


Total REAL time to Xst completion: 45.00 secs
Total CPU time to Xst completion: 37.19 secs
 
--> 


Total memory usage is 597436 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   55 (   0 filtered)
Number of infos    :   15 (   0 filtered)

