Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
| Date         : Sat Mar 19 15:31:39 2016
| Host         : athome running 64-bit Ubuntu 14.04.4 LTS
| Command      : report_timing_summary -warn_on_violation -max_paths 10 -file sys_w11a_n4_timing_summary_routed.rpt -rpx sys_w11a_n4_timing_summary_routed.rpx
| Design       : sys_w11a_n4
| Device       : 7a100t-csg324
| Speed File   : -1  PRODUCTION 1.14 2014-09-11
---------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  false

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking latch_loops

1. checking no_clock
--------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock
--------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
--------------------------
 There are 39 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
 There are 76 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
--------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops
------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.244        0.000                      0                 7854        0.055        0.000                      0                 7854        3.000        0.000                       0                  2956  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock               Waveform(ns)       Period(ns)      Frequency(MHz)
-----               ------------       ----------      --------------
I_CLK100            {0.000 5.000}      10.000          100.000         
  I                 {0.000 5.000}      10.000          100.000         
  USEMMCM.MMCM_n_2  {0.000 6.250}      12.500          80.000          


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock                   WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----                   -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
I_CLK100                                                                                                                                                              3.000        0.000                       0                     1  
  I                                                                                                                                                                   7.845        0.000                       0                     3  
  USEMMCM.MMCM_n_2        0.244        0.000                      0                 7854        0.055        0.000                      0                 7854        5.000        0.000                       0                  2952  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  I_CLK100
  To Clock:  I_CLK100

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        3.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         I_CLK100
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { I_CLK100 }

Check Type        Corner  Lib Pin            Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     MMCME2_ADV/CLKIN1  n/a            1.249         10.000      8.751      MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
Max Period        n/a     MMCME2_ADV/CLKIN1  n/a            100.000       10.000      90.000     MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
Low Pulse Width   Slow    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
Low Pulse Width   Fast    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
High Pulse Width  Fast    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1
High Pulse Width  Slow    MMCME2_ADV/CLKIN1  n/a            2.000         5.000       3.000      MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKIN1



---------------------------------------------------------------------------------------------------
From Clock:  I
  To Clock:  I

Setup :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
Hold  :           NA  Failing Endpoints,  Worst Slack           NA  ,  Total Violation           NA
PW    :            0  Failing Endpoints,  Worst Slack        7.845ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         I
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT }

Check Type  Corner  Lib Pin              Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period  n/a     BUFG/I               n/a            2.155         10.000      7.845      BUFGCTRL_X0Y17   GEN_CLKSYS/USEMMCM.BUFG_CLKFB/I
Min Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            1.249         10.000      8.751      MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT
Min Period  n/a     MMCME2_ADV/CLKFBIN   n/a            1.249         10.000      8.751      MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKFBIN
Max Period  n/a     MMCME2_ADV/CLKFBIN   n/a            100.000       10.000      90.000     MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKFBIN
Max Period  n/a     MMCME2_ADV/CLKFBOUT  n/a            213.360       10.000      203.360    MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKFBOUT



---------------------------------------------------------------------------------------------------
From Clock:  USEMMCM.MMCM_n_2
  To Clock:  USEMMCM.MMCM_n_2

Setup :            0  Failing Endpoints,  Worst Slack        0.244ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.055ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        5.000ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.244ns  (required time - arrival time)
  Source:                 SYS70/W11A/SEQ/R_STATE_reg[5]_rep/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/W11A/SEQ/R_STATE_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (USEMMCM.MMCM_n_2 rise@12.500ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        12.085ns  (logic 3.457ns (28.607%)  route 8.628ns (71.393%))
  Logic Levels:           16  (CARRY4=3 LUT2=1 LUT3=1 LUT4=2 LUT5=1 LUT6=8)
  Clock Path Skew:        -0.022ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.423ns = ( 11.077 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.826ns
    Clock Pessimism Removal (CPR):    0.575ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.826    -4.111 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.475    -2.636    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.714    -0.826    SYS70/W11A/SEQ/CLKFX
    SLICE_X3Y81          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg[5]_rep/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y81          FDRE (Prop_fdre_C_Q)         0.456    -0.370 f  SYS70/W11A/SEQ/R_STATE_reg[5]_rep/Q
                         net (fo=100, routed)         0.982     0.612    SYS70/W11A/SEQ/R_STATUS_reg[do_gprwe]_0
    SLICE_X8Y84          LUT2 (Prop_lut2_I1_O)        0.124     0.736 r  SYS70/W11A/SEQ/R_DD_L[15]_i_5/O
                         net (fo=3, routed)           0.702     1.438    SYS70/W11A/SEQ/R_DD_L[15]_i_5_n_0
    SLICE_X8Y84          LUT6 (Prop_lut6_I0_O)        0.124     1.562 r  SYS70/W11A/SEQ/R_REGS[mdin][0]_i_20/O
                         net (fo=31, routed)          0.653     2.215    SYS70/W11A/DPATH/MUNIT/DP_CNTL[munit_s_div_cr]
    SLICE_X9Y84          LUT5 (Prop_lut5_I0_O)        0.124     2.339 r  SYS70/W11A/DPATH/MUNIT/R_REGS[mdin][0]_i_19/O
                         net (fo=1, routed)           0.000     2.339    SYS70/W11A/DPATH/MUNIT/R_REGS[mdin][0]_i_19_n_0
    SLICE_X9Y84          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     2.871 r  SYS70/W11A/DPATH/MUNIT/R_REGS_reg[mdin][0]_i_7/CO[3]
                         net (fo=1, routed)           0.000     2.871    SYS70/W11A/DPATH/MUNIT/R_REGS_reg[mdin][0]_i_7_n_0
    SLICE_X9Y85          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     2.985 r  SYS70/W11A/DPATH/MUNIT/R_REGS_reg[mdin][7]_i_43/CO[3]
                         net (fo=1, routed)           0.000     2.985    SYS70/W11A/DPATH/MUNIT/R_REGS_reg[mdin][7]_i_43_n_0
    SLICE_X9Y86          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334     3.319 r  SYS70/W11A/DPATH/MUNIT/AW_4.GL[3].MEM_i_28/O[1]
                         net (fo=4, routed)           0.864     4.183    SYS70/W11A/SEQ/DOUT_DIV[9]
    SLICE_X10Y87         LUT6 (Prop_lut6_I3_O)        0.303     4.486 r  SYS70/W11A/SEQ/R_DIV_V_i_54/O
                         net (fo=1, routed)           0.404     4.891    SYS70/W11A/SEQ/R_DIV_V_i_54_n_0
    SLICE_X11Y87         LUT6 (Prop_lut6_I0_O)        0.124     5.015 r  SYS70/W11A/SEQ/R_DIV_V_i_35/O
                         net (fo=1, routed)           0.578     5.593    SYS70/W11A/SEQ/R_DIV_V_i_35_n_0
    SLICE_X15Y88         LUT4 (Prop_lut4_I3_O)        0.124     5.717 r  SYS70/W11A/SEQ/R_DIV_V_i_16/O
                         net (fo=2, routed)           0.416     6.133    SYS70/W11A/SEQ/div_ovfl1
    SLICE_X15Y89         LUT6 (Prop_lut6_I1_O)        0.124     6.257 r  SYS70/W11A/SEQ/R_DIV_V_i_5/O
                         net (fo=1, routed)           0.292     6.550    SYS70/W11A/DPATH/R_DDO_LT_reg
    SLICE_X15Y88         LUT4 (Prop_lut4_I3_O)        0.124     6.674 f  SYS70/W11A/DPATH/R_DIV_V_i_2/O
                         net (fo=2, routed)           0.313     6.987    SYS70/W11A/DPATH/MUNIT/R_DSRC_reg[14]
    SLICE_X12Y88         LUT6 (Prop_lut6_I1_O)        0.124     7.111 f  SYS70/W11A/DPATH/MUNIT/R_REGS[se_idone]_i_6/O
                         net (fo=8, routed)           1.201     8.312    SYS70/W11A/DPATH/PSR/STAT[div_quit]
    SLICE_X2Y87          LUT3 (Prop_lut3_I2_O)        0.150     8.462 r  SYS70/W11A/DPATH/PSR/R_STATE[1]_i_22/O
                         net (fo=1, routed)           0.452     8.914    SYS70/W11A/SEQ/R_STATE_reg[0]_6
    SLICE_X2Y87          LUT6 (Prop_lut6_I1_O)        0.328     9.242 r  SYS70/W11A/SEQ/R_STATE[1]_i_12/O
                         net (fo=1, routed)           0.659     9.901    SYS70/W11A/SEQ/R_STATE[1]_i_12_n_0
    SLICE_X2Y88          LUT6 (Prop_lut6_I5_O)        0.124    10.025 r  SYS70/W11A/SEQ/R_STATE[1]_i_3/O
                         net (fo=1, routed)           0.780    10.805    SYS70/W11A/SEQ/R_STATE[1]_i_3_n_0
    SLICE_X3Y83          LUT6 (Prop_lut6_I1_O)        0.124    10.929 r  SYS70/W11A/SEQ/R_STATE[1]_i_1/O
                         net (fo=2, routed)           0.330    11.259    SYS70/W11A/SEQ/R_STATE[1]_i_1_n_0
    SLICE_X3Y82          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                     12.500    12.500 r  
    E3                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411    13.911 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    15.073    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.087     7.986 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.402     9.388    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.479 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.597    11.077    SYS70/W11A/SEQ/CLKFX
    SLICE_X3Y82          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg[1]/C
                         clock pessimism              0.575    11.652    
                         clock uncertainty           -0.082    11.570    
    SLICE_X3Y82          FDRE (Setup_fdre_C_D)       -0.067    11.503    SYS70/W11A/SEQ/R_STATE_reg[1]
  -------------------------------------------------------------------
                         required time                         11.503    
                         arrival time                         -11.259    
  -------------------------------------------------------------------
                         slack                                  0.244    

Slack (MET) :             0.299ns  (required time - arrival time)
  Source:                 SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/W11A/SEQ/R_STATE_reg_rep[5]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (USEMMCM.MMCM_n_2 rise@12.500ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        11.874ns  (logic 5.367ns (45.201%)  route 6.507ns (54.799%))
  Logic Levels:           15  (CARRY4=1 LUT3=2 LUT4=1 LUT5=2 LUT6=7 MUXF7=2)
  Clock Path Skew:        -0.009ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.423ns = ( 11.077 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.854ns
    Clock Pessimism Removal (CPR):    0.559ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.826    -4.111 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.475    -2.636    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.686    -0.854    SYS70/CACHE/CMEM_DAT3/UMEM/CLKFX
    RAMB18_X0Y34         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X0Y34         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[1])
                                                      2.454     1.600 r  SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/DOADO[1]
                         net (fo=2, routed)           0.899     2.499    SYS70/CACHE/CMEM_DAT3/UMEM/CMEM_DOA_3[1]
    SLICE_X4Y85          LUT5 (Prop_lut5_I2_O)        0.124     2.623 r  SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_3/O
                         net (fo=1, routed)           0.294     2.917    SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_3_n_0
    SLICE_X5Y86          LUT6 (Prop_lut6_I0_O)        0.124     3.041 r  SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_2/O
                         net (fo=2, routed)           0.651     3.692    SYS70/W11A/VMBOX/EM_SRES[dout][9]
    SLICE_X6Y79          LUT6 (Prop_lut6_I3_O)        0.124     3.816 r  SYS70/W11A/VMBOX/R_IREG[1]_i_1/O
                         net (fo=4, routed)           0.306     4.122    SYS70/W11A/SEQ/R_REGS_reg[ibdout][15][1]
    SLICE_X6Y79          LUT6 (Prop_lut6_I5_O)        0.124     4.246 r  SYS70/W11A/SEQ/R_REGS[mdin][3]_i_33/O
                         net (fo=2, routed)           0.315     4.561    SYS70/W11A/SEQ/R_REGS[mdin][3]_i_24_n_0
    SLICE_X6Y80          LUT3 (Prop_lut3_I0_O)        0.124     4.685 r  SYS70/W11A/SEQ/R_REGS[mdin][3]_i_28/O
                         net (fo=1, routed)           0.000     4.685    SYS70/W11A/SEQ/R_REGS[mdin][3]_i_28_n_0
    SLICE_X6Y80          CARRY4 (Prop_carry4_S[1]_O[3])
                                                      0.643     5.328 r  SYS70/W11A/SEQ/R_REGS_reg[mdin][3]_i_7/O[3]
                         net (fo=2, routed)           0.658     5.986    SYS70/W11A/SEQ/R_REGS_reg[mdin][3]_i_7_n_4
    SLICE_X7Y81          LUT4 (Prop_lut4_I1_O)        0.307     6.293 r  SYS70/W11A/SEQ/R_PSW[cc][2]_i_24/O
                         net (fo=1, routed)           0.296     6.589    SYS70/W11A/SEQ/R_PSW[cc][2]_i_24_n_0
    SLICE_X7Y82          LUT5 (Prop_lut5_I4_O)        0.124     6.713 r  SYS70/W11A/SEQ/R_PSW[cc][2]_i_16/O
                         net (fo=1, routed)           0.652     7.365    SYS70/W11A/SEQ/R_PSW[cc][2]_i_16_n_0
    SLICE_X4Y83          LUT6 (Prop_lut6_I5_O)        0.124     7.489 f  SYS70/W11A/SEQ/R_PSW[cc][2]_i_7/O
                         net (fo=1, routed)           0.159     7.647    SYS70/W11A/SEQ/DPATH/OUNIT/nzo
    SLICE_X4Y83          LUT3 (Prop_lut3_I2_O)        0.124     7.771 f  SYS70/W11A/SEQ/R_PSW[cc][2]_i_4/O
                         net (fo=1, routed)           0.000     7.771    SYS70/W11A/SEQ/R_PSW[cc][2]_i_4_n_0
    SLICE_X4Y83          MUXF7 (Prop_muxf7_I0_O)      0.212     7.983 f  SYS70/W11A/SEQ/R_PSW_reg[cc][2]_i_3/O
                         net (fo=7, routed)           0.692     8.675    SYS70/W11A/SEQ/STAT[ccout_z]
    SLICE_X5Y83          LUT6 (Prop_lut6_I2_O)        0.299     8.974 r  SYS70/W11A/SEQ/R_STATE[5]_i_11/O
                         net (fo=1, routed)           0.596     9.570    SYS70/W11A/SEQ/R_STATE[5]_i_11_n_0
    SLICE_X4Y83          LUT6 (Prop_lut6_I0_O)        0.124     9.694 r  SYS70/W11A/SEQ/R_STATE[5]_i_4/O
                         net (fo=1, routed)           0.442    10.136    SYS70/W11A/SEQ/R_STATE[5]_i_4_n_0
    SLICE_X4Y82          LUT6 (Prop_lut6_I0_O)        0.124    10.260 r  SYS70/W11A/SEQ/R_STATE[5]_i_2/O
                         net (fo=1, routed)           0.000    10.260    SYS70/W11A/SEQ/R_STATE[5]_i_2_n_0
    SLICE_X4Y82          MUXF7 (Prop_muxf7_I0_O)      0.212    10.472 r  SYS70/W11A/SEQ/R_STATE_reg[5]_i_1/O
                         net (fo=3, routed)           0.547    11.019    SYS70/W11A/SEQ/R_STATE_reg[5]_i_1_n_0
    SLICE_X3Y82          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg_rep[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                     12.500    12.500 r  
    E3                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411    13.911 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    15.073    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.087     7.986 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.402     9.388    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.479 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.597    11.077    SYS70/W11A/SEQ/CLKFX
    SLICE_X3Y82          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg_rep[5]/C
                         clock pessimism              0.559    11.636    
                         clock uncertainty           -0.082    11.554    
    SLICE_X3Y82          FDRE (Setup_fdre_C_D)       -0.236    11.318    SYS70/W11A/SEQ/R_STATE_reg_rep[5]
  -------------------------------------------------------------------
                         required time                         11.318    
                         arrival time                         -11.019    
  -------------------------------------------------------------------
                         slack                                  0.299    

Slack (MET) :             0.350ns  (required time - arrival time)
  Source:                 SYS70/CACHE/CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            CRAM_CTL/IOB_MEM_BE/R_DO_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (USEMMCM.MMCM_n_2 rise@12.500ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        11.121ns  (logic 4.684ns (42.120%)  route 6.437ns (57.880%))
  Logic Levels:           9  (CARRY4=1 LUT2=1 LUT3=2 LUT4=1 LUT6=4)
  Clock Path Skew:        -0.113ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.458ns = ( 11.042 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.865ns
    Clock Pessimism Removal (CPR):    0.480ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.826    -4.111 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.475    -2.636    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.675    -0.865    SYS70/CACHE/CMEM_TAG/UMEM/CLKFX
    RAMB18_X0Y30         RAMB18E1                                     r  SYS70/CACHE/CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X0Y30         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[3])
                                                      2.454     1.589 r  SYS70/CACHE/CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM/DOADO[3]
                         net (fo=2, routed)           0.876     2.465    SYS70/CACHE/CMEM_TAG/UMEM/DOA[3]
    SLICE_X8Y76          LUT6 (Prop_lut6_I0_O)        0.124     2.589 r  SYS70/CACHE/CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM_i_16__0/O
                         net (fo=1, routed)           0.000     2.589    SYS70/CACHE/CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM_i_16__0_n_0
    SLICE_X8Y76          CARRY4 (Prop_carry4_S[1]_CO[2])
                                                      0.574     3.163 f  SYS70/CACHE/CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM_i_14__0/CO[2]
                         net (fo=6, routed)           0.332     3.495    SYS70/MEM70/CO[0]
    SLICE_X8Y75          LUT4 (Prop_lut4_I0_O)        0.310     3.805 r  SYS70/MEM70/R_REGS[state][0]_i_5__0/O
                         net (fo=1, routed)           0.561     4.366    SYS70/CACHE/CMEM_DAT0/UMEM/R_REGS_reg[cr_fmiss][0]
    SLICE_X2Y76          LUT6 (Prop_lut6_I5_O)        0.124     4.490 f  SYS70/CACHE/CMEM_DAT0/UMEM/R_REGS[state][0]_i_2__2/O
                         net (fo=7, routed)           1.012     5.502    SYS70/CACHE/CMEM_DAT0/UMEM/R_REGS_reg[state][0]
    SLICE_X4Y87          LUT3 (Prop_lut3_I0_O)        0.150     5.652 r  SYS70/CACHE/CMEM_DAT0/UMEM/R_REGS[state][3]_i_4__2/O
                         net (fo=9, routed)           1.000     6.652    SYS70/CACHE/CMEM_DAT0/UMEM/R_REGS_reg[state][0]_0
    SLICE_X2Y96          LUT2 (Prop_lut2_I0_O)        0.352     7.004 f  SYS70/CACHE/CMEM_DAT0/UMEM/R_REGS[state][2]_i_4__2/O
                         net (fo=10, routed)          0.493     7.496    SYS70/CACHE/CMEM_DAT0/UMEM/R_DO_reg[0]_2
    SLICE_X3Y97          LUT6 (Prop_lut6_I5_O)        0.348     7.844 r  SYS70/CACHE/CMEM_DAT0/UMEM/R_DO[1]_i_9/O
                         net (fo=1, routed)           0.403     8.247    CRAM_CTL/IOB_MEM_BE/R_REGS_reg[fidle]_1
    SLICE_X3Y96          LUT6 (Prop_lut6_I2_O)        0.124     8.371 r  CRAM_CTL/IOB_MEM_BE/R_DO[1]_i_8/O
                         net (fo=1, routed)           0.640     9.011    CRAM_CTL/IOB_MEM_BE/R_DO[1]_i_8_n_0
    SLICE_X0Y97          LUT3 (Prop_lut3_I2_O)        0.124     9.135 r  CRAM_CTL/IOB_MEM_BE/R_DO[1]_i_2/O
                         net (fo=1, routed)           1.120    10.255    CRAM_CTL/IOB_MEM_BE/MEM_BE_N[1]
    OLOGIC_X0Y115        FDRE                                         r  CRAM_CTL/IOB_MEM_BE/R_DO_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                     12.500    12.500 r  
    E3                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411    13.911 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    15.073    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.087     7.986 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.402     9.388    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.479 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.562    11.042    CRAM_CTL/IOB_MEM_BE/CLKFX
    OLOGIC_X0Y115        FDRE                                         r  CRAM_CTL/IOB_MEM_BE/R_DO_reg[1]/C
                         clock pessimism              0.480    11.522    
                         clock uncertainty           -0.082    11.440    
    OLOGIC_X0Y115        FDRE (Setup_fdre_C_D)       -0.834    10.606    CRAM_CTL/IOB_MEM_BE/R_DO_reg[1]
  -------------------------------------------------------------------
                         required time                         10.606    
                         arrival time                         -10.255    
  -------------------------------------------------------------------
                         slack                                  0.350    

Slack (MET) :             0.373ns  (required time - arrival time)
  Source:                 SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/W11A/SEQ/R_STATE_reg[3]_rep__0/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (USEMMCM.MMCM_n_2 rise@12.500ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        11.997ns  (logic 5.671ns (47.270%)  route 6.326ns (52.730%))
  Logic Levels:           16  (CARRY4=1 LUT3=4 LUT4=1 LUT5=3 LUT6=5 MUXF7=2)
  Clock Path Skew:        -0.011ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.425ns = ( 11.075 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.854ns
    Clock Pessimism Removal (CPR):    0.559ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.826    -4.111 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.475    -2.636    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.686    -0.854    SYS70/CACHE/CMEM_DAT3/UMEM/CLKFX
    RAMB18_X0Y34         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X0Y34         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[1])
                                                      2.454     1.600 r  SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/DOADO[1]
                         net (fo=2, routed)           0.899     2.499    SYS70/CACHE/CMEM_DAT3/UMEM/CMEM_DOA_3[1]
    SLICE_X4Y85          LUT5 (Prop_lut5_I2_O)        0.124     2.623 r  SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_3/O
                         net (fo=1, routed)           0.294     2.917    SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_3_n_0
    SLICE_X5Y86          LUT6 (Prop_lut6_I0_O)        0.124     3.041 r  SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_2/O
                         net (fo=2, routed)           0.651     3.692    SYS70/W11A/VMBOX/EM_SRES[dout][9]
    SLICE_X6Y79          LUT6 (Prop_lut6_I3_O)        0.124     3.816 r  SYS70/W11A/VMBOX/R_IREG[1]_i_1/O
                         net (fo=4, routed)           0.306     4.122    SYS70/W11A/SEQ/R_REGS_reg[ibdout][15][1]
    SLICE_X6Y79          LUT6 (Prop_lut6_I5_O)        0.124     4.246 r  SYS70/W11A/SEQ/R_REGS[mdin][3]_i_33/O
                         net (fo=2, routed)           0.315     4.561    SYS70/W11A/SEQ/R_REGS[mdin][3]_i_24_n_0
    SLICE_X6Y80          LUT3 (Prop_lut3_I0_O)        0.124     4.685 r  SYS70/W11A/SEQ/R_REGS[mdin][3]_i_28/O
                         net (fo=1, routed)           0.000     4.685    SYS70/W11A/SEQ/R_REGS[mdin][3]_i_28_n_0
    SLICE_X6Y80          CARRY4 (Prop_carry4_S[1]_O[3])
                                                      0.643     5.328 r  SYS70/W11A/SEQ/R_REGS_reg[mdin][3]_i_7/O[3]
                         net (fo=2, routed)           0.658     5.986    SYS70/W11A/SEQ/R_REGS_reg[mdin][3]_i_7_n_4
    SLICE_X7Y81          LUT4 (Prop_lut4_I1_O)        0.307     6.293 r  SYS70/W11A/SEQ/R_PSW[cc][2]_i_24/O
                         net (fo=1, routed)           0.296     6.589    SYS70/W11A/SEQ/R_PSW[cc][2]_i_24_n_0
    SLICE_X7Y82          LUT5 (Prop_lut5_I4_O)        0.124     6.713 r  SYS70/W11A/SEQ/R_PSW[cc][2]_i_16/O
                         net (fo=1, routed)           0.652     7.365    SYS70/W11A/SEQ/R_PSW[cc][2]_i_16_n_0
    SLICE_X4Y83          LUT6 (Prop_lut6_I5_O)        0.124     7.489 f  SYS70/W11A/SEQ/R_PSW[cc][2]_i_7/O
                         net (fo=1, routed)           0.159     7.647    SYS70/W11A/SEQ/DPATH/OUNIT/nzo
    SLICE_X4Y83          LUT3 (Prop_lut3_I2_O)        0.124     7.771 f  SYS70/W11A/SEQ/R_PSW[cc][2]_i_4/O
                         net (fo=1, routed)           0.000     7.771    SYS70/W11A/SEQ/R_PSW[cc][2]_i_4_n_0
    SLICE_X4Y83          MUXF7 (Prop_muxf7_I0_O)      0.212     7.983 f  SYS70/W11A/SEQ/R_PSW_reg[cc][2]_i_3/O
                         net (fo=7, routed)           0.561     8.544    SYS70/W11A/SEQ/STAT[ccout_z]
    SLICE_X0Y80          LUT3 (Prop_lut3_I2_O)        0.299     8.843 r  SYS70/W11A/SEQ/R_STATE[1]_i_25/O
                         net (fo=3, routed)           0.326     9.169    SYS70/W11A/SEQ/R_STATE[1]_i_25_n_0
    SLICE_X3Y81          LUT5 (Prop_lut5_I2_O)        0.124     9.293 r  SYS70/W11A/SEQ/R_STATE[3]_i_23/O
                         net (fo=1, routed)           0.000     9.293    SYS70/W11A/SEQ/R_STATE[3]_i_23_n_0
    SLICE_X3Y81          MUXF7 (Prop_muxf7_I1_O)      0.217     9.510 r  SYS70/W11A/SEQ/R_STATE_reg[3]_i_11/O
                         net (fo=1, routed)           0.291     9.801    SYS70/W11A/SEQ/R_STATE_reg[3]_i_11_n_0
    SLICE_X1Y81          LUT3 (Prop_lut3_I2_O)        0.299    10.100 r  SYS70/W11A/SEQ/R_STATE[3]_i_4/O
                         net (fo=1, routed)           0.294    10.394    SYS70/W11A/SEQ/R_STATE[3]_i_4_n_0
    SLICE_X2Y81          LUT6 (Prop_lut6_I3_O)        0.124    10.518 r  SYS70/W11A/SEQ/R_STATE[3]_i_1/O
                         net (fo=4, routed)           0.625    11.143    SYS70/W11A/SEQ/R_STATE[3]_i_1_n_0
    SLICE_X2Y81          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg[3]_rep__0/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                     12.500    12.500 r  
    E3                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411    13.911 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    15.073    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.087     7.986 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.402     9.388    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.479 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.595    11.075    SYS70/W11A/SEQ/CLKFX
    SLICE_X2Y81          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg[3]_rep__0/C
                         clock pessimism              0.559    11.634    
                         clock uncertainty           -0.082    11.552    
    SLICE_X2Y81          FDRE (Setup_fdre_C_D)       -0.036    11.516    SYS70/W11A/SEQ/R_STATE_reg[3]_rep__0
  -------------------------------------------------------------------
                         required time                         11.516    
                         arrival time                         -11.143    
  -------------------------------------------------------------------
                         slack                                  0.373    

Slack (MET) :             0.396ns  (required time - arrival time)
  Source:                 SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/W11A/SEQ/R_STATE_reg[3]_rep/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (USEMMCM.MMCM_n_2 rise@12.500ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        11.997ns  (logic 5.671ns (47.270%)  route 6.326ns (52.730%))
  Logic Levels:           16  (CARRY4=1 LUT3=4 LUT4=1 LUT5=3 LUT6=5 MUXF7=2)
  Clock Path Skew:        -0.011ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.425ns = ( 11.075 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.854ns
    Clock Pessimism Removal (CPR):    0.559ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.826    -4.111 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.475    -2.636    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.686    -0.854    SYS70/CACHE/CMEM_DAT3/UMEM/CLKFX
    RAMB18_X0Y34         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X0Y34         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[1])
                                                      2.454     1.600 r  SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/DOADO[1]
                         net (fo=2, routed)           0.899     2.499    SYS70/CACHE/CMEM_DAT3/UMEM/CMEM_DOA_3[1]
    SLICE_X4Y85          LUT5 (Prop_lut5_I2_O)        0.124     2.623 r  SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_3/O
                         net (fo=1, routed)           0.294     2.917    SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_3_n_0
    SLICE_X5Y86          LUT6 (Prop_lut6_I0_O)        0.124     3.041 r  SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_2/O
                         net (fo=2, routed)           0.651     3.692    SYS70/W11A/VMBOX/EM_SRES[dout][9]
    SLICE_X6Y79          LUT6 (Prop_lut6_I3_O)        0.124     3.816 r  SYS70/W11A/VMBOX/R_IREG[1]_i_1/O
                         net (fo=4, routed)           0.306     4.122    SYS70/W11A/SEQ/R_REGS_reg[ibdout][15][1]
    SLICE_X6Y79          LUT6 (Prop_lut6_I5_O)        0.124     4.246 r  SYS70/W11A/SEQ/R_REGS[mdin][3]_i_33/O
                         net (fo=2, routed)           0.315     4.561    SYS70/W11A/SEQ/R_REGS[mdin][3]_i_24_n_0
    SLICE_X6Y80          LUT3 (Prop_lut3_I0_O)        0.124     4.685 r  SYS70/W11A/SEQ/R_REGS[mdin][3]_i_28/O
                         net (fo=1, routed)           0.000     4.685    SYS70/W11A/SEQ/R_REGS[mdin][3]_i_28_n_0
    SLICE_X6Y80          CARRY4 (Prop_carry4_S[1]_O[3])
                                                      0.643     5.328 r  SYS70/W11A/SEQ/R_REGS_reg[mdin][3]_i_7/O[3]
                         net (fo=2, routed)           0.658     5.986    SYS70/W11A/SEQ/R_REGS_reg[mdin][3]_i_7_n_4
    SLICE_X7Y81          LUT4 (Prop_lut4_I1_O)        0.307     6.293 r  SYS70/W11A/SEQ/R_PSW[cc][2]_i_24/O
                         net (fo=1, routed)           0.296     6.589    SYS70/W11A/SEQ/R_PSW[cc][2]_i_24_n_0
    SLICE_X7Y82          LUT5 (Prop_lut5_I4_O)        0.124     6.713 r  SYS70/W11A/SEQ/R_PSW[cc][2]_i_16/O
                         net (fo=1, routed)           0.652     7.365    SYS70/W11A/SEQ/R_PSW[cc][2]_i_16_n_0
    SLICE_X4Y83          LUT6 (Prop_lut6_I5_O)        0.124     7.489 f  SYS70/W11A/SEQ/R_PSW[cc][2]_i_7/O
                         net (fo=1, routed)           0.159     7.647    SYS70/W11A/SEQ/DPATH/OUNIT/nzo
    SLICE_X4Y83          LUT3 (Prop_lut3_I2_O)        0.124     7.771 f  SYS70/W11A/SEQ/R_PSW[cc][2]_i_4/O
                         net (fo=1, routed)           0.000     7.771    SYS70/W11A/SEQ/R_PSW[cc][2]_i_4_n_0
    SLICE_X4Y83          MUXF7 (Prop_muxf7_I0_O)      0.212     7.983 f  SYS70/W11A/SEQ/R_PSW_reg[cc][2]_i_3/O
                         net (fo=7, routed)           0.561     8.544    SYS70/W11A/SEQ/STAT[ccout_z]
    SLICE_X0Y80          LUT3 (Prop_lut3_I2_O)        0.299     8.843 r  SYS70/W11A/SEQ/R_STATE[1]_i_25/O
                         net (fo=3, routed)           0.326     9.169    SYS70/W11A/SEQ/R_STATE[1]_i_25_n_0
    SLICE_X3Y81          LUT5 (Prop_lut5_I2_O)        0.124     9.293 r  SYS70/W11A/SEQ/R_STATE[3]_i_23/O
                         net (fo=1, routed)           0.000     9.293    SYS70/W11A/SEQ/R_STATE[3]_i_23_n_0
    SLICE_X3Y81          MUXF7 (Prop_muxf7_I1_O)      0.217     9.510 r  SYS70/W11A/SEQ/R_STATE_reg[3]_i_11/O
                         net (fo=1, routed)           0.291     9.801    SYS70/W11A/SEQ/R_STATE_reg[3]_i_11_n_0
    SLICE_X1Y81          LUT3 (Prop_lut3_I2_O)        0.299    10.100 r  SYS70/W11A/SEQ/R_STATE[3]_i_4/O
                         net (fo=1, routed)           0.294    10.394    SYS70/W11A/SEQ/R_STATE[3]_i_4_n_0
    SLICE_X2Y81          LUT6 (Prop_lut6_I3_O)        0.124    10.518 r  SYS70/W11A/SEQ/R_STATE[3]_i_1/O
                         net (fo=4, routed)           0.625    11.143    SYS70/W11A/SEQ/R_STATE[3]_i_1_n_0
    SLICE_X2Y81          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg[3]_rep/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                     12.500    12.500 r  
    E3                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411    13.911 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    15.073    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.087     7.986 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.402     9.388    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.479 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.595    11.075    SYS70/W11A/SEQ/CLKFX
    SLICE_X2Y81          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg[3]_rep/C
                         clock pessimism              0.559    11.634    
                         clock uncertainty           -0.082    11.552    
    SLICE_X2Y81          FDRE (Setup_fdre_C_D)       -0.013    11.539    SYS70/W11A/SEQ/R_STATE_reg[3]_rep
  -------------------------------------------------------------------
                         required time                         11.539    
                         arrival time                         -11.143    
  -------------------------------------------------------------------
                         slack                                  0.396    

Slack (MET) :             0.413ns  (required time - arrival time)
  Source:                 SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/W11A/SEQ/R_STATE_reg_rep[0]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (USEMMCM.MMCM_n_2 rise@12.500ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        11.935ns  (logic 5.666ns (47.474%)  route 6.269ns (52.526%))
  Logic Levels:           16  (CARRY4=1 LUT3=3 LUT4=1 LUT5=2 LUT6=7 MUXF7=2)
  Clock Path Skew:        -0.011ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.425ns = ( 11.075 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.854ns
    Clock Pessimism Removal (CPR):    0.559ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.826    -4.111 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.475    -2.636    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.686    -0.854    SYS70/CACHE/CMEM_DAT3/UMEM/CLKFX
    RAMB18_X0Y34         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X0Y34         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[1])
                                                      2.454     1.600 r  SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/DOADO[1]
                         net (fo=2, routed)           0.899     2.499    SYS70/CACHE/CMEM_DAT3/UMEM/CMEM_DOA_3[1]
    SLICE_X4Y85          LUT5 (Prop_lut5_I2_O)        0.124     2.623 r  SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_3/O
                         net (fo=1, routed)           0.294     2.917    SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_3_n_0
    SLICE_X5Y86          LUT6 (Prop_lut6_I0_O)        0.124     3.041 r  SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_2/O
                         net (fo=2, routed)           0.651     3.692    SYS70/W11A/VMBOX/EM_SRES[dout][9]
    SLICE_X6Y79          LUT6 (Prop_lut6_I3_O)        0.124     3.816 r  SYS70/W11A/VMBOX/R_IREG[1]_i_1/O
                         net (fo=4, routed)           0.306     4.122    SYS70/W11A/SEQ/R_REGS_reg[ibdout][15][1]
    SLICE_X6Y79          LUT6 (Prop_lut6_I5_O)        0.124     4.246 r  SYS70/W11A/SEQ/R_REGS[mdin][3]_i_33/O
                         net (fo=2, routed)           0.315     4.561    SYS70/W11A/SEQ/R_REGS[mdin][3]_i_24_n_0
    SLICE_X6Y80          LUT3 (Prop_lut3_I0_O)        0.124     4.685 r  SYS70/W11A/SEQ/R_REGS[mdin][3]_i_28/O
                         net (fo=1, routed)           0.000     4.685    SYS70/W11A/SEQ/R_REGS[mdin][3]_i_28_n_0
    SLICE_X6Y80          CARRY4 (Prop_carry4_S[1]_O[3])
                                                      0.643     5.328 r  SYS70/W11A/SEQ/R_REGS_reg[mdin][3]_i_7/O[3]
                         net (fo=2, routed)           0.658     5.986    SYS70/W11A/SEQ/R_REGS_reg[mdin][3]_i_7_n_4
    SLICE_X7Y81          LUT4 (Prop_lut4_I1_O)        0.307     6.293 r  SYS70/W11A/SEQ/R_PSW[cc][2]_i_24/O
                         net (fo=1, routed)           0.296     6.589    SYS70/W11A/SEQ/R_PSW[cc][2]_i_24_n_0
    SLICE_X7Y82          LUT5 (Prop_lut5_I4_O)        0.124     6.713 r  SYS70/W11A/SEQ/R_PSW[cc][2]_i_16/O
                         net (fo=1, routed)           0.652     7.365    SYS70/W11A/SEQ/R_PSW[cc][2]_i_16_n_0
    SLICE_X4Y83          LUT6 (Prop_lut6_I5_O)        0.124     7.489 f  SYS70/W11A/SEQ/R_PSW[cc][2]_i_7/O
                         net (fo=1, routed)           0.159     7.647    SYS70/W11A/SEQ/DPATH/OUNIT/nzo
    SLICE_X4Y83          LUT3 (Prop_lut3_I2_O)        0.124     7.771 f  SYS70/W11A/SEQ/R_PSW[cc][2]_i_4/O
                         net (fo=1, routed)           0.000     7.771    SYS70/W11A/SEQ/R_PSW[cc][2]_i_4_n_0
    SLICE_X4Y83          MUXF7 (Prop_muxf7_I0_O)      0.212     7.983 f  SYS70/W11A/SEQ/R_PSW_reg[cc][2]_i_3/O
                         net (fo=7, routed)           0.503     8.487    SYS70/W11A/SEQ/STAT[ccout_z]
    SLICE_X1Y83          LUT6 (Prop_lut6_I1_O)        0.299     8.786 r  SYS70/W11A/SEQ/R_STATE[0]_i_39/O
                         net (fo=1, routed)           0.298     9.084    SYS70/W11A/SEQ/R_STATE[0]_i_39_n_0
    SLICE_X2Y83          LUT6 (Prop_lut6_I5_O)        0.124     9.208 r  SYS70/W11A/SEQ/R_STATE[0]_i_27/O
                         net (fo=1, routed)           0.000     9.208    SYS70/W11A/SEQ/R_STATE[0]_i_27_n_0
    SLICE_X2Y83          MUXF7 (Prop_muxf7_I1_O)      0.214     9.422 r  SYS70/W11A/SEQ/R_STATE_reg[0]_i_14/O
                         net (fo=1, routed)           0.450     9.872    SYS70/W11A/SEQ/R_STATE_reg[0]_i_14_n_0
    SLICE_X0Y81          LUT3 (Prop_lut3_I2_O)        0.297    10.169 r  SYS70/W11A/SEQ/R_STATE[0]_i_4/O
                         net (fo=1, routed)           0.598    10.767    SYS70/W11A/SEQ/R_STATE[0]_i_4_n_0
    SLICE_X2Y81          LUT6 (Prop_lut6_I3_O)        0.124    10.891 r  SYS70/W11A/SEQ/R_STATE[0]_i_1/O
                         net (fo=2, routed)           0.190    11.081    SYS70/W11A/SEQ/R_STATE[0]_i_1_n_0
    SLICE_X3Y81          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg_rep[0]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                     12.500    12.500 r  
    E3                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411    13.911 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    15.073    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.087     7.986 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.402     9.388    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.479 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.595    11.075    SYS70/W11A/SEQ/CLKFX
    SLICE_X3Y81          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg_rep[0]/C
                         clock pessimism              0.559    11.634    
                         clock uncertainty           -0.082    11.552    
    SLICE_X3Y81          FDRE (Setup_fdre_C_D)       -0.058    11.494    SYS70/W11A/SEQ/R_STATE_reg_rep[0]
  -------------------------------------------------------------------
                         required time                         11.494    
                         arrival time                         -11.081    
  -------------------------------------------------------------------
                         slack                                  0.413    

Slack (MET) :             0.424ns  (required time - arrival time)
  Source:                 SYS70/W11A/SEQ/R_STATE_reg[5]_rep/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/DMCMON.I0/R_REGS_reg[dp_dres][13]/CE
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (USEMMCM.MMCM_n_2 rise@12.500ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        11.675ns  (logic 3.814ns (32.668%)  route 7.861ns (67.332%))
  Logic Levels:           17  (CARRY4=3 LUT2=1 LUT4=2 LUT5=3 LUT6=7 MUXF7=1)
  Clock Path Skew:        -0.113ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.498ns = ( 11.002 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.826ns
    Clock Pessimism Removal (CPR):    0.559ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.826    -4.111 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.475    -2.636    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.714    -0.826    SYS70/W11A/SEQ/CLKFX
    SLICE_X3Y81          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg[5]_rep/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y81          FDRE (Prop_fdre_C_Q)         0.456    -0.370 f  SYS70/W11A/SEQ/R_STATE_reg[5]_rep/Q
                         net (fo=100, routed)         0.982     0.612    SYS70/W11A/SEQ/R_STATUS_reg[do_gprwe]_0
    SLICE_X8Y84          LUT2 (Prop_lut2_I1_O)        0.124     0.736 r  SYS70/W11A/SEQ/R_DD_L[15]_i_5/O
                         net (fo=3, routed)           0.702     1.438    SYS70/W11A/SEQ/R_DD_L[15]_i_5_n_0
    SLICE_X8Y84          LUT6 (Prop_lut6_I0_O)        0.124     1.562 r  SYS70/W11A/SEQ/R_REGS[mdin][0]_i_20/O
                         net (fo=31, routed)          0.653     2.215    SYS70/W11A/DPATH/MUNIT/DP_CNTL[munit_s_div_cr]
    SLICE_X9Y84          LUT5 (Prop_lut5_I0_O)        0.124     2.339 r  SYS70/W11A/DPATH/MUNIT/R_REGS[mdin][0]_i_19/O
                         net (fo=1, routed)           0.000     2.339    SYS70/W11A/DPATH/MUNIT/R_REGS[mdin][0]_i_19_n_0
    SLICE_X9Y84          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     2.871 r  SYS70/W11A/DPATH/MUNIT/R_REGS_reg[mdin][0]_i_7/CO[3]
                         net (fo=1, routed)           0.000     2.871    SYS70/W11A/DPATH/MUNIT/R_REGS_reg[mdin][0]_i_7_n_0
    SLICE_X9Y85          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     2.985 r  SYS70/W11A/DPATH/MUNIT/R_REGS_reg[mdin][7]_i_43/CO[3]
                         net (fo=1, routed)           0.000     2.985    SYS70/W11A/DPATH/MUNIT/R_REGS_reg[mdin][7]_i_43_n_0
    SLICE_X9Y86          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334     3.319 r  SYS70/W11A/DPATH/MUNIT/AW_4.GL[3].MEM_i_28/O[1]
                         net (fo=4, routed)           0.864     4.183    SYS70/W11A/SEQ/DOUT_DIV[9]
    SLICE_X10Y87         LUT6 (Prop_lut6_I3_O)        0.303     4.486 r  SYS70/W11A/SEQ/R_DIV_V_i_54/O
                         net (fo=1, routed)           0.404     4.891    SYS70/W11A/SEQ/R_DIV_V_i_54_n_0
    SLICE_X11Y87         LUT6 (Prop_lut6_I0_O)        0.124     5.015 r  SYS70/W11A/SEQ/R_DIV_V_i_35/O
                         net (fo=1, routed)           0.578     5.593    SYS70/W11A/SEQ/R_DIV_V_i_35_n_0
    SLICE_X15Y88         LUT4 (Prop_lut4_I3_O)        0.124     5.717 r  SYS70/W11A/SEQ/R_DIV_V_i_16/O
                         net (fo=2, routed)           0.416     6.133    SYS70/W11A/SEQ/div_ovfl1
    SLICE_X15Y89         LUT6 (Prop_lut6_I1_O)        0.124     6.257 r  SYS70/W11A/SEQ/R_DIV_V_i_5/O
                         net (fo=1, routed)           0.292     6.550    SYS70/W11A/DPATH/R_DDO_LT_reg
    SLICE_X15Y88         LUT4 (Prop_lut4_I3_O)        0.124     6.674 f  SYS70/W11A/DPATH/R_DIV_V_i_2/O
                         net (fo=2, routed)           0.313     6.987    SYS70/W11A/DPATH/MUNIT/R_DSRC_reg[14]
    SLICE_X12Y88         LUT6 (Prop_lut6_I1_O)        0.124     7.111 f  SYS70/W11A/DPATH/MUNIT/R_REGS[se_idone]_i_6/O
                         net (fo=8, routed)           0.538     7.648    SYS70/W11A/SEQ/STAT[div_quit]
    SLICE_X13Y88         LUT5 (Prop_lut5_I2_O)        0.124     7.772 r  SYS70/W11A/SEQ/R_DTMP[15]_i_17/O
                         net (fo=1, routed)           0.151     7.923    SYS70/W11A/SEQ/R_DTMP[15]_i_17_n_0
    SLICE_X13Y88         LUT6 (Prop_lut6_I1_O)        0.124     8.047 f  SYS70/W11A/SEQ/R_DTMP[15]_i_10/O
                         net (fo=1, routed)           0.000     8.047    SYS70/W11A/SEQ/R_DTMP[15]_i_10_n_0
    SLICE_X13Y88         MUXF7 (Prop_muxf7_I0_O)      0.212     8.259 f  SYS70/W11A/SEQ/R_DTMP_reg[15]_i_4/O
                         net (fo=1, routed)           0.475     8.734    SYS70/W11A/SEQ/R_DTMP_reg[15]_i_4_n_0
    SLICE_X12Y88         LUT5 (Prop_lut5_I4_O)        0.292     9.026 r  SYS70/W11A/SEQ/R_DTMP[15]_i_1/O
                         net (fo=17, routed)          0.841     9.867    SYS70/W11A/SEQ/R_DTMP_reg[15][0]
    SLICE_X15Y85         LUT6 (Prop_lut6_I0_O)        0.331    10.198 r  SYS70/W11A/SEQ/R_REGS[dp_dres][15]_i_1/O
                         net (fo=17, routed)          0.652    10.849    SYS70/DMCMON.I0/N_REGS[dp_dres_val]
    SLICE_X15Y89         FDRE                                         r  SYS70/DMCMON.I0/R_REGS_reg[dp_dres][13]/CE
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                     12.500    12.500 r  
    E3                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411    13.911 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    15.073    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.087     7.986 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.402     9.388    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.479 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.522    11.002    SYS70/DMCMON.I0/CLKFX
    SLICE_X15Y89         FDRE                                         r  SYS70/DMCMON.I0/R_REGS_reg[dp_dres][13]/C
                         clock pessimism              0.559    11.561    
                         clock uncertainty           -0.082    11.479    
    SLICE_X15Y89         FDRE (Setup_fdre_C_CE)      -0.205    11.274    SYS70/DMCMON.I0/R_REGS_reg[dp_dres][13]
  -------------------------------------------------------------------
                         required time                         11.274    
                         arrival time                         -10.850    
  -------------------------------------------------------------------
                         slack                                  0.424    

Slack (MET) :             0.424ns  (required time - arrival time)
  Source:                 SYS70/W11A/SEQ/R_STATE_reg[5]_rep/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/DMCMON.I0/R_REGS_reg[dp_dres][7]/CE
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (USEMMCM.MMCM_n_2 rise@12.500ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        11.675ns  (logic 3.814ns (32.668%)  route 7.861ns (67.332%))
  Logic Levels:           17  (CARRY4=3 LUT2=1 LUT4=2 LUT5=3 LUT6=7 MUXF7=1)
  Clock Path Skew:        -0.113ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.498ns = ( 11.002 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.826ns
    Clock Pessimism Removal (CPR):    0.559ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.826    -4.111 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.475    -2.636    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.714    -0.826    SYS70/W11A/SEQ/CLKFX
    SLICE_X3Y81          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg[5]_rep/C
  -------------------------------------------------------------------    -------------------
    SLICE_X3Y81          FDRE (Prop_fdre_C_Q)         0.456    -0.370 f  SYS70/W11A/SEQ/R_STATE_reg[5]_rep/Q
                         net (fo=100, routed)         0.982     0.612    SYS70/W11A/SEQ/R_STATUS_reg[do_gprwe]_0
    SLICE_X8Y84          LUT2 (Prop_lut2_I1_O)        0.124     0.736 r  SYS70/W11A/SEQ/R_DD_L[15]_i_5/O
                         net (fo=3, routed)           0.702     1.438    SYS70/W11A/SEQ/R_DD_L[15]_i_5_n_0
    SLICE_X8Y84          LUT6 (Prop_lut6_I0_O)        0.124     1.562 r  SYS70/W11A/SEQ/R_REGS[mdin][0]_i_20/O
                         net (fo=31, routed)          0.653     2.215    SYS70/W11A/DPATH/MUNIT/DP_CNTL[munit_s_div_cr]
    SLICE_X9Y84          LUT5 (Prop_lut5_I0_O)        0.124     2.339 r  SYS70/W11A/DPATH/MUNIT/R_REGS[mdin][0]_i_19/O
                         net (fo=1, routed)           0.000     2.339    SYS70/W11A/DPATH/MUNIT/R_REGS[mdin][0]_i_19_n_0
    SLICE_X9Y84          CARRY4 (Prop_carry4_S[0]_CO[3])
                                                      0.532     2.871 r  SYS70/W11A/DPATH/MUNIT/R_REGS_reg[mdin][0]_i_7/CO[3]
                         net (fo=1, routed)           0.000     2.871    SYS70/W11A/DPATH/MUNIT/R_REGS_reg[mdin][0]_i_7_n_0
    SLICE_X9Y85          CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     2.985 r  SYS70/W11A/DPATH/MUNIT/R_REGS_reg[mdin][7]_i_43/CO[3]
                         net (fo=1, routed)           0.000     2.985    SYS70/W11A/DPATH/MUNIT/R_REGS_reg[mdin][7]_i_43_n_0
    SLICE_X9Y86          CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334     3.319 r  SYS70/W11A/DPATH/MUNIT/AW_4.GL[3].MEM_i_28/O[1]
                         net (fo=4, routed)           0.864     4.183    SYS70/W11A/SEQ/DOUT_DIV[9]
    SLICE_X10Y87         LUT6 (Prop_lut6_I3_O)        0.303     4.486 r  SYS70/W11A/SEQ/R_DIV_V_i_54/O
                         net (fo=1, routed)           0.404     4.891    SYS70/W11A/SEQ/R_DIV_V_i_54_n_0
    SLICE_X11Y87         LUT6 (Prop_lut6_I0_O)        0.124     5.015 r  SYS70/W11A/SEQ/R_DIV_V_i_35/O
                         net (fo=1, routed)           0.578     5.593    SYS70/W11A/SEQ/R_DIV_V_i_35_n_0
    SLICE_X15Y88         LUT4 (Prop_lut4_I3_O)        0.124     5.717 r  SYS70/W11A/SEQ/R_DIV_V_i_16/O
                         net (fo=2, routed)           0.416     6.133    SYS70/W11A/SEQ/div_ovfl1
    SLICE_X15Y89         LUT6 (Prop_lut6_I1_O)        0.124     6.257 r  SYS70/W11A/SEQ/R_DIV_V_i_5/O
                         net (fo=1, routed)           0.292     6.550    SYS70/W11A/DPATH/R_DDO_LT_reg
    SLICE_X15Y88         LUT4 (Prop_lut4_I3_O)        0.124     6.674 f  SYS70/W11A/DPATH/R_DIV_V_i_2/O
                         net (fo=2, routed)           0.313     6.987    SYS70/W11A/DPATH/MUNIT/R_DSRC_reg[14]
    SLICE_X12Y88         LUT6 (Prop_lut6_I1_O)        0.124     7.111 f  SYS70/W11A/DPATH/MUNIT/R_REGS[se_idone]_i_6/O
                         net (fo=8, routed)           0.538     7.648    SYS70/W11A/SEQ/STAT[div_quit]
    SLICE_X13Y88         LUT5 (Prop_lut5_I2_O)        0.124     7.772 r  SYS70/W11A/SEQ/R_DTMP[15]_i_17/O
                         net (fo=1, routed)           0.151     7.923    SYS70/W11A/SEQ/R_DTMP[15]_i_17_n_0
    SLICE_X13Y88         LUT6 (Prop_lut6_I1_O)        0.124     8.047 f  SYS70/W11A/SEQ/R_DTMP[15]_i_10/O
                         net (fo=1, routed)           0.000     8.047    SYS70/W11A/SEQ/R_DTMP[15]_i_10_n_0
    SLICE_X13Y88         MUXF7 (Prop_muxf7_I0_O)      0.212     8.259 f  SYS70/W11A/SEQ/R_DTMP_reg[15]_i_4/O
                         net (fo=1, routed)           0.475     8.734    SYS70/W11A/SEQ/R_DTMP_reg[15]_i_4_n_0
    SLICE_X12Y88         LUT5 (Prop_lut5_I4_O)        0.292     9.026 r  SYS70/W11A/SEQ/R_DTMP[15]_i_1/O
                         net (fo=17, routed)          0.841     9.867    SYS70/W11A/SEQ/R_DTMP_reg[15][0]
    SLICE_X15Y85         LUT6 (Prop_lut6_I0_O)        0.331    10.198 r  SYS70/W11A/SEQ/R_REGS[dp_dres][15]_i_1/O
                         net (fo=17, routed)          0.652    10.849    SYS70/DMCMON.I0/N_REGS[dp_dres_val]
    SLICE_X15Y89         FDRE                                         r  SYS70/DMCMON.I0/R_REGS_reg[dp_dres][7]/CE
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                     12.500    12.500 r  
    E3                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411    13.911 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    15.073    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.087     7.986 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.402     9.388    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.479 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.522    11.002    SYS70/DMCMON.I0/CLKFX
    SLICE_X15Y89         FDRE                                         r  SYS70/DMCMON.I0/R_REGS_reg[dp_dres][7]/C
                         clock pessimism              0.559    11.561    
                         clock uncertainty           -0.082    11.479    
    SLICE_X15Y89         FDRE (Setup_fdre_C_CE)      -0.205    11.274    SYS70/DMCMON.I0/R_REGS_reg[dp_dres][7]
  -------------------------------------------------------------------
                         required time                         11.274    
                         arrival time                         -10.850    
  -------------------------------------------------------------------
                         slack                                  0.424    

Slack (MET) :             0.458ns  (required time - arrival time)
  Source:                 SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/W11A/SEQ/R_STATE_reg[4]_rep/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (USEMMCM.MMCM_n_2 rise@12.500ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        11.906ns  (logic 5.671ns (47.631%)  route 6.235ns (52.369%))
  Logic Levels:           16  (CARRY4=1 LUT3=4 LUT4=1 LUT5=2 LUT6=6 MUXF7=2)
  Clock Path Skew:        -0.013ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.427ns = ( 11.073 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.854ns
    Clock Pessimism Removal (CPR):    0.559ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.826    -4.111 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.475    -2.636    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.686    -0.854    SYS70/CACHE/CMEM_DAT3/UMEM/CLKFX
    RAMB18_X0Y34         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X0Y34         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[1])
                                                      2.454     1.600 r  SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/DOADO[1]
                         net (fo=2, routed)           0.899     2.499    SYS70/CACHE/CMEM_DAT3/UMEM/CMEM_DOA_3[1]
    SLICE_X4Y85          LUT5 (Prop_lut5_I2_O)        0.124     2.623 r  SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_3/O
                         net (fo=1, routed)           0.294     2.917    SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_3_n_0
    SLICE_X5Y86          LUT6 (Prop_lut6_I0_O)        0.124     3.041 r  SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_2/O
                         net (fo=2, routed)           0.651     3.692    SYS70/W11A/VMBOX/EM_SRES[dout][9]
    SLICE_X6Y79          LUT6 (Prop_lut6_I3_O)        0.124     3.816 r  SYS70/W11A/VMBOX/R_IREG[1]_i_1/O
                         net (fo=4, routed)           0.306     4.122    SYS70/W11A/SEQ/R_REGS_reg[ibdout][15][1]
    SLICE_X6Y79          LUT6 (Prop_lut6_I5_O)        0.124     4.246 r  SYS70/W11A/SEQ/R_REGS[mdin][3]_i_33/O
                         net (fo=2, routed)           0.315     4.561    SYS70/W11A/SEQ/R_REGS[mdin][3]_i_24_n_0
    SLICE_X6Y80          LUT3 (Prop_lut3_I0_O)        0.124     4.685 r  SYS70/W11A/SEQ/R_REGS[mdin][3]_i_28/O
                         net (fo=1, routed)           0.000     4.685    SYS70/W11A/SEQ/R_REGS[mdin][3]_i_28_n_0
    SLICE_X6Y80          CARRY4 (Prop_carry4_S[1]_O[3])
                                                      0.643     5.328 r  SYS70/W11A/SEQ/R_REGS_reg[mdin][3]_i_7/O[3]
                         net (fo=2, routed)           0.658     5.986    SYS70/W11A/SEQ/R_REGS_reg[mdin][3]_i_7_n_4
    SLICE_X7Y81          LUT4 (Prop_lut4_I1_O)        0.307     6.293 r  SYS70/W11A/SEQ/R_PSW[cc][2]_i_24/O
                         net (fo=1, routed)           0.296     6.589    SYS70/W11A/SEQ/R_PSW[cc][2]_i_24_n_0
    SLICE_X7Y82          LUT5 (Prop_lut5_I4_O)        0.124     6.713 r  SYS70/W11A/SEQ/R_PSW[cc][2]_i_16/O
                         net (fo=1, routed)           0.652     7.365    SYS70/W11A/SEQ/R_PSW[cc][2]_i_16_n_0
    SLICE_X4Y83          LUT6 (Prop_lut6_I5_O)        0.124     7.489 f  SYS70/W11A/SEQ/R_PSW[cc][2]_i_7/O
                         net (fo=1, routed)           0.159     7.647    SYS70/W11A/SEQ/DPATH/OUNIT/nzo
    SLICE_X4Y83          LUT3 (Prop_lut3_I2_O)        0.124     7.771 f  SYS70/W11A/SEQ/R_PSW[cc][2]_i_4/O
                         net (fo=1, routed)           0.000     7.771    SYS70/W11A/SEQ/R_PSW[cc][2]_i_4_n_0
    SLICE_X4Y83          MUXF7 (Prop_muxf7_I0_O)      0.212     7.983 f  SYS70/W11A/SEQ/R_PSW_reg[cc][2]_i_3/O
                         net (fo=7, routed)           0.561     8.544    SYS70/W11A/SEQ/STAT[ccout_z]
    SLICE_X0Y80          LUT3 (Prop_lut3_I2_O)        0.299     8.843 r  SYS70/W11A/SEQ/R_STATE[1]_i_25/O
                         net (fo=3, routed)           0.308     9.151    SYS70/W11A/SEQ/R_STATE[1]_i_25_n_0
    SLICE_X1Y79          LUT6 (Prop_lut6_I3_O)        0.124     9.275 r  SYS70/W11A/SEQ/R_STATE[4]_i_24/O
                         net (fo=1, routed)           0.000     9.275    SYS70/W11A/SEQ/R_STATE[4]_i_24_n_0
    SLICE_X1Y79          MUXF7 (Prop_muxf7_I1_O)      0.217     9.492 r  SYS70/W11A/SEQ/R_STATE_reg[4]_i_11/O
                         net (fo=1, routed)           0.399     9.891    SYS70/W11A/SEQ/R_STATE_reg[4]_i_11_n_0
    SLICE_X3Y79          LUT3 (Prop_lut3_I2_O)        0.299    10.190 r  SYS70/W11A/SEQ/R_STATE[4]_i_4/O
                         net (fo=1, routed)           0.395    10.585    SYS70/W11A/SEQ/R_STATE[4]_i_4_n_0
    SLICE_X1Y79          LUT6 (Prop_lut6_I3_O)        0.124    10.709 r  SYS70/W11A/SEQ/R_STATE[4]_i_1/O
                         net (fo=3, routed)           0.343    11.052    SYS70/W11A/SEQ/R_STATE[4]_i_1_n_0
    SLICE_X0Y78          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg[4]_rep/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                     12.500    12.500 r  
    E3                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411    13.911 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    15.073    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.087     7.986 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.402     9.388    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.479 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.593    11.073    SYS70/W11A/SEQ/CLKFX
    SLICE_X0Y78          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg[4]_rep/C
                         clock pessimism              0.559    11.632    
                         clock uncertainty           -0.082    11.550    
    SLICE_X0Y78          FDRE (Setup_fdre_C_D)       -0.040    11.510    SYS70/W11A/SEQ/R_STATE_reg[4]_rep
  -------------------------------------------------------------------
                         required time                         11.510    
                         arrival time                         -11.052    
  -------------------------------------------------------------------
                         slack                                  0.458    

Slack (MET) :             0.461ns  (required time - arrival time)
  Source:                 SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
                            (rising edge-triggered cell RAMB18E1 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/W11A/SEQ/R_STATE_reg_rep[4]/D
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            12.500ns  (USEMMCM.MMCM_n_2 rise@12.500ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        11.903ns  (logic 5.671ns (47.642%)  route 6.232ns (52.358%))
  Logic Levels:           16  (CARRY4=1 LUT3=4 LUT4=1 LUT5=2 LUT6=6 MUXF7=2)
  Clock Path Skew:        -0.013ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    -1.427ns = ( 11.073 - 12.500 ) 
    Source Clock Delay      (SCD):    -0.854ns
    Clock Pessimism Removal (CPR):    0.559ns
  Clock Uncertainty:      0.082ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Discrete Jitter          (DJ):    0.149ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.482     1.482 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.233     2.715    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -6.826    -4.111 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.475    -2.636    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.096    -2.540 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.686    -0.854    SYS70/CACHE/CMEM_DAT3/UMEM/CLKFX
    RAMB18_X0Y34         RAMB18E1                                     r  SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
  -------------------------------------------------------------------    -------------------
    RAMB18_X0Y34         RAMB18E1 (Prop_ramb18e1_CLKARDCLK_DOADO[1])
                                                      2.454     1.600 r  SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/DOADO[1]
                         net (fo=2, routed)           0.899     2.499    SYS70/CACHE/CMEM_DAT3/UMEM/CMEM_DOA_3[1]
    SLICE_X4Y85          LUT5 (Prop_lut5_I2_O)        0.124     2.623 r  SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_3/O
                         net (fo=1, routed)           0.294     2.917    SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_3_n_0
    SLICE_X5Y86          LUT6 (Prop_lut6_I0_O)        0.124     3.041 r  SYS70/CACHE/CMEM_DAT3/UMEM/R_IREG[9]_i_2/O
                         net (fo=2, routed)           0.651     3.692    SYS70/W11A/VMBOX/EM_SRES[dout][9]
    SLICE_X6Y79          LUT6 (Prop_lut6_I3_O)        0.124     3.816 r  SYS70/W11A/VMBOX/R_IREG[1]_i_1/O
                         net (fo=4, routed)           0.306     4.122    SYS70/W11A/SEQ/R_REGS_reg[ibdout][15][1]
    SLICE_X6Y79          LUT6 (Prop_lut6_I5_O)        0.124     4.246 r  SYS70/W11A/SEQ/R_REGS[mdin][3]_i_33/O
                         net (fo=2, routed)           0.315     4.561    SYS70/W11A/SEQ/R_REGS[mdin][3]_i_24_n_0
    SLICE_X6Y80          LUT3 (Prop_lut3_I0_O)        0.124     4.685 r  SYS70/W11A/SEQ/R_REGS[mdin][3]_i_28/O
                         net (fo=1, routed)           0.000     4.685    SYS70/W11A/SEQ/R_REGS[mdin][3]_i_28_n_0
    SLICE_X6Y80          CARRY4 (Prop_carry4_S[1]_O[3])
                                                      0.643     5.328 r  SYS70/W11A/SEQ/R_REGS_reg[mdin][3]_i_7/O[3]
                         net (fo=2, routed)           0.658     5.986    SYS70/W11A/SEQ/R_REGS_reg[mdin][3]_i_7_n_4
    SLICE_X7Y81          LUT4 (Prop_lut4_I1_O)        0.307     6.293 r  SYS70/W11A/SEQ/R_PSW[cc][2]_i_24/O
                         net (fo=1, routed)           0.296     6.589    SYS70/W11A/SEQ/R_PSW[cc][2]_i_24_n_0
    SLICE_X7Y82          LUT5 (Prop_lut5_I4_O)        0.124     6.713 r  SYS70/W11A/SEQ/R_PSW[cc][2]_i_16/O
                         net (fo=1, routed)           0.652     7.365    SYS70/W11A/SEQ/R_PSW[cc][2]_i_16_n_0
    SLICE_X4Y83          LUT6 (Prop_lut6_I5_O)        0.124     7.489 f  SYS70/W11A/SEQ/R_PSW[cc][2]_i_7/O
                         net (fo=1, routed)           0.159     7.647    SYS70/W11A/SEQ/DPATH/OUNIT/nzo
    SLICE_X4Y83          LUT3 (Prop_lut3_I2_O)        0.124     7.771 f  SYS70/W11A/SEQ/R_PSW[cc][2]_i_4/O
                         net (fo=1, routed)           0.000     7.771    SYS70/W11A/SEQ/R_PSW[cc][2]_i_4_n_0
    SLICE_X4Y83          MUXF7 (Prop_muxf7_I0_O)      0.212     7.983 f  SYS70/W11A/SEQ/R_PSW_reg[cc][2]_i_3/O
                         net (fo=7, routed)           0.561     8.544    SYS70/W11A/SEQ/STAT[ccout_z]
    SLICE_X0Y80          LUT3 (Prop_lut3_I2_O)        0.299     8.843 r  SYS70/W11A/SEQ/R_STATE[1]_i_25/O
                         net (fo=3, routed)           0.308     9.151    SYS70/W11A/SEQ/R_STATE[1]_i_25_n_0
    SLICE_X1Y79          LUT6 (Prop_lut6_I3_O)        0.124     9.275 r  SYS70/W11A/SEQ/R_STATE[4]_i_24/O
                         net (fo=1, routed)           0.000     9.275    SYS70/W11A/SEQ/R_STATE[4]_i_24_n_0
    SLICE_X1Y79          MUXF7 (Prop_muxf7_I1_O)      0.217     9.492 r  SYS70/W11A/SEQ/R_STATE_reg[4]_i_11/O
                         net (fo=1, routed)           0.399     9.891    SYS70/W11A/SEQ/R_STATE_reg[4]_i_11_n_0
    SLICE_X3Y79          LUT3 (Prop_lut3_I2_O)        0.299    10.190 r  SYS70/W11A/SEQ/R_STATE[4]_i_4/O
                         net (fo=1, routed)           0.395    10.585    SYS70/W11A/SEQ/R_STATE[4]_i_4_n_0
    SLICE_X1Y79          LUT6 (Prop_lut6_I3_O)        0.124    10.709 r  SYS70/W11A/SEQ/R_STATE[4]_i_1/O
                         net (fo=3, routed)           0.340    11.049    SYS70/W11A/SEQ/R_STATE[4]_i_1_n_0
    SLICE_X1Y78          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg_rep[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                     12.500    12.500 r  
    E3                                                0.000    12.500 r  I_CLK100 (IN)
                         net (fo=0)                   0.000    12.500    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         1.411    13.911 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.162    15.073    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -7.087     7.986 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           1.402     9.388    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.091     9.479 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        1.593    11.073    SYS70/W11A/SEQ/CLKFX
    SLICE_X1Y78          FDRE                                         r  SYS70/W11A/SEQ/R_STATE_reg_rep[4]/C
                         clock pessimism              0.559    11.632    
                         clock uncertainty           -0.082    11.550    
    SLICE_X1Y78          FDRE (Setup_fdre_C_D)       -0.040    11.510    SYS70/W11A/SEQ/R_STATE_reg_rep[4]
  -------------------------------------------------------------------
                         required time                         11.510    
                         arrival time                         -11.049    
  -------------------------------------------------------------------
                         slack                                  0.461    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.055ns  (arrival time - required time)
  Source:                 SYS70/IBMON.I0/R_REGS_reg[ibaddr][7]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM/DIADI[7]
                            (rising edge-triggered cell RAMB36E1 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.MMCM_n_2 rise@0.000ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        0.411ns  (logic 0.164ns (39.950%)  route 0.247ns (60.050%))
  Logic Levels:           0  
  Clock Path Skew:        0.059ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.785ns
    Source Clock Delay      (SCD):    -0.590ns
    Clock Pessimism Removal (CPR):    -0.254ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.293    -1.603 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.413    -1.190    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.574    -0.590    SYS70/IBMON.I0/CLKFX
    SLICE_X8Y58          FDRE                                         r  SYS70/IBMON.I0/R_REGS_reg[ibaddr][7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y58          FDRE (Prop_fdre_C_Q)         0.164    -0.426 r  SYS70/IBMON.I0/R_REGS_reg[ibaddr][7]/Q
                         net (fo=1, routed)           0.247    -0.180    SYS70/IBMON.I0/BRAM0/UMEM/DI[7]
    RAMB36_X0Y10         RAMB36E1                                     r  SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM/DIADI[7]
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.067    -2.149 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.448    -1.702    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.888    -0.785    SYS70/IBMON.I0/BRAM0/UMEM/CLKFX
    RAMB36_X0Y10         RAMB36E1                                     r  SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM/CLKARDCLK
                         clock pessimism              0.254    -0.531    
    RAMB36_X0Y10         RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[7])
                                                      0.296    -0.235    SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
  -------------------------------------------------------------------
                         required time                          0.235    
                         arrival time                          -0.180    
  -------------------------------------------------------------------
                         slack                                  0.055    

Slack (MET) :             0.059ns  (arrival time - required time)
  Source:                 SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/DMCMON.I0/MAL/AW_4.GL[2].MEM/DP/WADR0
                            (rising edge-triggered cell RAMD32 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.MMCM_n_2 rise@0.000ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        0.382ns  (logic 0.141ns (36.939%)  route 0.241ns (63.061%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.834ns
    Source Clock Delay      (SCD):    -0.597ns
    Clock Pessimism Removal (CPR):    -0.250ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.293    -1.603 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.413    -1.190    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.567    -0.597    SYS70/DMCMON.I0/CLKFX
    SLICE_X39Y90         FDRE                                         r  SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y90         FDRE (Prop_fdre_C_Q)         0.141    -0.456 r  SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/Q
                         net (fo=53, routed)          0.241    -0.216    SYS70/DMCMON.I0/MAL/AW_4.GL[2].MEM/A0
    SLICE_X38Y90         RAMD32                                       r  SYS70/DMCMON.I0/MAL/AW_4.GL[2].MEM/DP/WADR0
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.067    -2.149 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.448    -1.702    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.839    -0.834    SYS70/DMCMON.I0/MAL/AW_4.GL[2].MEM/WCLK
    SLICE_X38Y90         RAMD32                                       r  SYS70/DMCMON.I0/MAL/AW_4.GL[2].MEM/DP/CLK
                         clock pessimism              0.250    -0.584    
    SLICE_X38Y90         RAMD32 (Hold_ramd32_CLK_WADR0)
                                                      0.310    -0.274    SYS70/DMCMON.I0/MAL/AW_4.GL[2].MEM/DP
  -------------------------------------------------------------------
                         required time                          0.274    
                         arrival time                          -0.216    
  -------------------------------------------------------------------
                         slack                                  0.059    

Slack (MET) :             0.059ns  (arrival time - required time)
  Source:                 SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/DMCMON.I0/MAL/AW_4.GL[2].MEM/SP/WADR0
                            (rising edge-triggered cell RAMD32 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.MMCM_n_2 rise@0.000ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        0.382ns  (logic 0.141ns (36.939%)  route 0.241ns (63.061%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.834ns
    Source Clock Delay      (SCD):    -0.597ns
    Clock Pessimism Removal (CPR):    -0.250ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.293    -1.603 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.413    -1.190    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.567    -0.597    SYS70/DMCMON.I0/CLKFX
    SLICE_X39Y90         FDRE                                         r  SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y90         FDRE (Prop_fdre_C_Q)         0.141    -0.456 r  SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/Q
                         net (fo=53, routed)          0.241    -0.216    SYS70/DMCMON.I0/MAL/AW_4.GL[2].MEM/A0
    SLICE_X38Y90         RAMD32                                       r  SYS70/DMCMON.I0/MAL/AW_4.GL[2].MEM/SP/WADR0
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.067    -2.149 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.448    -1.702    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.839    -0.834    SYS70/DMCMON.I0/MAL/AW_4.GL[2].MEM/WCLK
    SLICE_X38Y90         RAMD32                                       r  SYS70/DMCMON.I0/MAL/AW_4.GL[2].MEM/SP/CLK
                         clock pessimism              0.250    -0.584    
    SLICE_X38Y90         RAMD32 (Hold_ramd32_CLK_WADR0)
                                                      0.310    -0.274    SYS70/DMCMON.I0/MAL/AW_4.GL[2].MEM/SP
  -------------------------------------------------------------------
                         required time                          0.274    
                         arrival time                          -0.216    
  -------------------------------------------------------------------
                         slack                                  0.059    

Slack (MET) :             0.059ns  (arrival time - required time)
  Source:                 SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/DMCMON.I0/MAL/AW_4.GL[3].MEM/DP/WADR0
                            (rising edge-triggered cell RAMD32 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.MMCM_n_2 rise@0.000ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        0.382ns  (logic 0.141ns (36.939%)  route 0.241ns (63.061%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.834ns
    Source Clock Delay      (SCD):    -0.597ns
    Clock Pessimism Removal (CPR):    -0.250ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.293    -1.603 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.413    -1.190    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.567    -0.597    SYS70/DMCMON.I0/CLKFX
    SLICE_X39Y90         FDRE                                         r  SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y90         FDRE (Prop_fdre_C_Q)         0.141    -0.456 r  SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/Q
                         net (fo=53, routed)          0.241    -0.216    SYS70/DMCMON.I0/MAL/AW_4.GL[3].MEM/A0
    SLICE_X38Y90         RAMD32                                       r  SYS70/DMCMON.I0/MAL/AW_4.GL[3].MEM/DP/WADR0
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.067    -2.149 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.448    -1.702    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.839    -0.834    SYS70/DMCMON.I0/MAL/AW_4.GL[3].MEM/WCLK
    SLICE_X38Y90         RAMD32                                       r  SYS70/DMCMON.I0/MAL/AW_4.GL[3].MEM/DP/CLK
                         clock pessimism              0.250    -0.584    
    SLICE_X38Y90         RAMD32 (Hold_ramd32_CLK_WADR0)
                                                      0.310    -0.274    SYS70/DMCMON.I0/MAL/AW_4.GL[3].MEM/DP
  -------------------------------------------------------------------
                         required time                          0.274    
                         arrival time                          -0.216    
  -------------------------------------------------------------------
                         slack                                  0.059    

Slack (MET) :             0.059ns  (arrival time - required time)
  Source:                 SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/DMCMON.I0/MAL/AW_4.GL[3].MEM/SP/WADR0
                            (rising edge-triggered cell RAMD32 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.MMCM_n_2 rise@0.000ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        0.382ns  (logic 0.141ns (36.939%)  route 0.241ns (63.061%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.834ns
    Source Clock Delay      (SCD):    -0.597ns
    Clock Pessimism Removal (CPR):    -0.250ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.293    -1.603 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.413    -1.190    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.567    -0.597    SYS70/DMCMON.I0/CLKFX
    SLICE_X39Y90         FDRE                                         r  SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y90         FDRE (Prop_fdre_C_Q)         0.141    -0.456 r  SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/Q
                         net (fo=53, routed)          0.241    -0.216    SYS70/DMCMON.I0/MAL/AW_4.GL[3].MEM/A0
    SLICE_X38Y90         RAMD32                                       r  SYS70/DMCMON.I0/MAL/AW_4.GL[3].MEM/SP/WADR0
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.067    -2.149 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.448    -1.702    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.839    -0.834    SYS70/DMCMON.I0/MAL/AW_4.GL[3].MEM/WCLK
    SLICE_X38Y90         RAMD32                                       r  SYS70/DMCMON.I0/MAL/AW_4.GL[3].MEM/SP/CLK
                         clock pessimism              0.250    -0.584    
    SLICE_X38Y90         RAMD32 (Hold_ramd32_CLK_WADR0)
                                                      0.310    -0.274    SYS70/DMCMON.I0/MAL/AW_4.GL[3].MEM/SP
  -------------------------------------------------------------------
                         required time                          0.274    
                         arrival time                          -0.216    
  -------------------------------------------------------------------
                         slack                                  0.059    

Slack (MET) :             0.059ns  (arrival time - required time)
  Source:                 SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/DMCMON.I0/MAL/AW_4.GL[4].MEM/DP/WADR0
                            (rising edge-triggered cell RAMD32 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.MMCM_n_2 rise@0.000ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        0.382ns  (logic 0.141ns (36.939%)  route 0.241ns (63.061%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.834ns
    Source Clock Delay      (SCD):    -0.597ns
    Clock Pessimism Removal (CPR):    -0.250ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.293    -1.603 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.413    -1.190    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.567    -0.597    SYS70/DMCMON.I0/CLKFX
    SLICE_X39Y90         FDRE                                         r  SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y90         FDRE (Prop_fdre_C_Q)         0.141    -0.456 r  SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/Q
                         net (fo=53, routed)          0.241    -0.216    SYS70/DMCMON.I0/MAL/AW_4.GL[4].MEM/A0
    SLICE_X38Y90         RAMD32                                       r  SYS70/DMCMON.I0/MAL/AW_4.GL[4].MEM/DP/WADR0
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.067    -2.149 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.448    -1.702    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.839    -0.834    SYS70/DMCMON.I0/MAL/AW_4.GL[4].MEM/WCLK
    SLICE_X38Y90         RAMD32                                       r  SYS70/DMCMON.I0/MAL/AW_4.GL[4].MEM/DP/CLK
                         clock pessimism              0.250    -0.584    
    SLICE_X38Y90         RAMD32 (Hold_ramd32_CLK_WADR0)
                                                      0.310    -0.274    SYS70/DMCMON.I0/MAL/AW_4.GL[4].MEM/DP
  -------------------------------------------------------------------
                         required time                          0.274    
                         arrival time                          -0.216    
  -------------------------------------------------------------------
                         slack                                  0.059    

Slack (MET) :             0.059ns  (arrival time - required time)
  Source:                 SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/DMCMON.I0/MAL/AW_4.GL[4].MEM/SP/WADR0
                            (rising edge-triggered cell RAMD32 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.MMCM_n_2 rise@0.000ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        0.382ns  (logic 0.141ns (36.939%)  route 0.241ns (63.061%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.834ns
    Source Clock Delay      (SCD):    -0.597ns
    Clock Pessimism Removal (CPR):    -0.250ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.293    -1.603 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.413    -1.190    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.567    -0.597    SYS70/DMCMON.I0/CLKFX
    SLICE_X39Y90         FDRE                                         r  SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y90         FDRE (Prop_fdre_C_Q)         0.141    -0.456 r  SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/Q
                         net (fo=53, routed)          0.241    -0.216    SYS70/DMCMON.I0/MAL/AW_4.GL[4].MEM/A0
    SLICE_X38Y90         RAMD32                                       r  SYS70/DMCMON.I0/MAL/AW_4.GL[4].MEM/SP/WADR0
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.067    -2.149 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.448    -1.702    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.839    -0.834    SYS70/DMCMON.I0/MAL/AW_4.GL[4].MEM/WCLK
    SLICE_X38Y90         RAMD32                                       r  SYS70/DMCMON.I0/MAL/AW_4.GL[4].MEM/SP/CLK
                         clock pessimism              0.250    -0.584    
    SLICE_X38Y90         RAMD32 (Hold_ramd32_CLK_WADR0)
                                                      0.310    -0.274    SYS70/DMCMON.I0/MAL/AW_4.GL[4].MEM/SP
  -------------------------------------------------------------------
                         required time                          0.274    
                         arrival time                          -0.216    
  -------------------------------------------------------------------
                         slack                                  0.059    

Slack (MET) :             0.059ns  (arrival time - required time)
  Source:                 SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/DMCMON.I0/MAL/AW_4.GL[5].MEM/DP/WADR0
                            (rising edge-triggered cell RAMD32 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.MMCM_n_2 rise@0.000ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        0.382ns  (logic 0.141ns (36.939%)  route 0.241ns (63.061%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.834ns
    Source Clock Delay      (SCD):    -0.597ns
    Clock Pessimism Removal (CPR):    -0.250ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.293    -1.603 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.413    -1.190    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.567    -0.597    SYS70/DMCMON.I0/CLKFX
    SLICE_X39Y90         FDRE                                         r  SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y90         FDRE (Prop_fdre_C_Q)         0.141    -0.456 r  SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/Q
                         net (fo=53, routed)          0.241    -0.216    SYS70/DMCMON.I0/MAL/AW_4.GL[5].MEM/A0
    SLICE_X38Y90         RAMD32                                       r  SYS70/DMCMON.I0/MAL/AW_4.GL[5].MEM/DP/WADR0
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.067    -2.149 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.448    -1.702    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.839    -0.834    SYS70/DMCMON.I0/MAL/AW_4.GL[5].MEM/WCLK
    SLICE_X38Y90         RAMD32                                       r  SYS70/DMCMON.I0/MAL/AW_4.GL[5].MEM/DP/CLK
                         clock pessimism              0.250    -0.584    
    SLICE_X38Y90         RAMD32 (Hold_ramd32_CLK_WADR0)
                                                      0.310    -0.274    SYS70/DMCMON.I0/MAL/AW_4.GL[5].MEM/DP
  -------------------------------------------------------------------
                         required time                          0.274    
                         arrival time                          -0.216    
  -------------------------------------------------------------------
                         slack                                  0.059    

Slack (MET) :             0.059ns  (arrival time - required time)
  Source:                 SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/DMCMON.I0/MAL/AW_4.GL[5].MEM/SP/WADR0
                            (rising edge-triggered cell RAMD32 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.MMCM_n_2 rise@0.000ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        0.382ns  (logic 0.141ns (36.939%)  route 0.241ns (63.061%))
  Logic Levels:           0  
  Clock Path Skew:        0.013ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.834ns
    Source Clock Delay      (SCD):    -0.597ns
    Clock Pessimism Removal (CPR):    -0.250ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.293    -1.603 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.413    -1.190    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.567    -0.597    SYS70/DMCMON.I0/CLKFX
    SLICE_X39Y90         FDRE                                         r  SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X39Y90         FDRE (Prop_fdre_C_Q)         0.141    -0.456 r  SYS70/DMCMON.I0/R_REGS_reg[mal_waddr][0]/Q
                         net (fo=53, routed)          0.241    -0.216    SYS70/DMCMON.I0/MAL/AW_4.GL[5].MEM/A0
    SLICE_X38Y90         RAMD32                                       r  SYS70/DMCMON.I0/MAL/AW_4.GL[5].MEM/SP/WADR0
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.067    -2.149 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.448    -1.702    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.839    -0.834    SYS70/DMCMON.I0/MAL/AW_4.GL[5].MEM/WCLK
    SLICE_X38Y90         RAMD32                                       r  SYS70/DMCMON.I0/MAL/AW_4.GL[5].MEM/SP/CLK
                         clock pessimism              0.250    -0.584    
    SLICE_X38Y90         RAMD32 (Hold_ramd32_CLK_WADR0)
                                                      0.310    -0.274    SYS70/DMCMON.I0/MAL/AW_4.GL[5].MEM/SP
  -------------------------------------------------------------------
                         required time                          0.274    
                         arrival time                          -0.216    
  -------------------------------------------------------------------
                         slack                                  0.059    

Slack (MET) :             0.061ns  (arrival time - required time)
  Source:                 SYS70/IBMON.I0/R_REGS_reg[ibaddr][12]/C
                            (rising edge-triggered cell FDRE clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Destination:            SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM/DIADI[12]
                            (rising edge-triggered cell RAMB36E1 clocked by USEMMCM.MMCM_n_2  {rise@0.000ns fall@6.250ns period=12.500ns})
  Path Group:             USEMMCM.MMCM_n_2
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (USEMMCM.MMCM_n_2 rise@0.000ns - USEMMCM.MMCM_n_2 rise@0.000ns)
  Data Path Delay:        0.416ns  (logic 0.164ns (39.417%)  route 0.252ns (60.583%))
  Logic Levels:           0  
  Clock Path Skew:        0.059ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    -0.785ns
    Source Clock Delay      (SCD):    -0.590ns
    Clock Pessimism Removal (CPR):    -0.254ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.250     0.250 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.440     0.690    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -2.293    -1.603 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.413    -1.190    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.026    -1.164 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.574    -0.590    SYS70/IBMON.I0/CLKFX
    SLICE_X8Y58          FDRE                                         r  SYS70/IBMON.I0/R_REGS_reg[ibaddr][12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X8Y58          FDRE (Prop_fdre_C_Q)         0.164    -0.426 r  SYS70/IBMON.I0/R_REGS_reg[ibaddr][12]/Q
                         net (fo=1, routed)           0.252    -0.174    SYS70/IBMON.I0/BRAM0/UMEM/DI[12]
    RAMB36_X0Y10         RAMB36E1                                     r  SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM/DIADI[12]
  -------------------------------------------------------------------    -------------------

                         (clock USEMMCM.MMCM_n_2 rise edge)
                                                      0.000     0.000 r  
    E3                                                0.000     0.000 r  I_CLK100 (IN)
                         net (fo=0)                   0.000     0.000    I_CLK100
    E3                   IBUF (Prop_ibuf_I_O)         0.438     0.438 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.480     0.918    GEN_CLKSYS/CLKIN
    MMCME2_ADV_X1Y2      MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
                                                     -3.067    -2.149 r  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
                         net (fo=1, routed)           0.448    -1.702    GEN_CLKSYS/USEMMCM.MMCM_n_2
    BUFGCTRL_X0Y16       BUFG (Prop_bufg_I_O)         0.029    -1.673 r  GEN_CLKSYS/USEMMCM.BUFG_CLKOUT/O
                         net (fo=2951, routed)        0.888    -0.785    SYS70/IBMON.I0/BRAM0/UMEM/CLKFX
    RAMB36_X0Y10         RAMB36E1                                     r  SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM/CLKARDCLK
                         clock pessimism              0.254    -0.531    
    RAMB36_X0Y10         RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[12])
                                                      0.296    -0.235    SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
  -------------------------------------------------------------------
                         required time                          0.235    
                         arrival time                          -0.174    
  -------------------------------------------------------------------
                         slack                                  0.061    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         USEMMCM.MMCM_n_2
Waveform(ns):       { 0.000 6.250 }
Period(ns):         12.500
Sources:            { GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0 }

Check Type        Corner  Lib Pin             Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location         Pin
Min Period        n/a     XADC/DCLK           n/a            4.000         12.500      8.500      XADC_X0Y0        SMRB.I0/SM/DCLK
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.944         12.500      9.556      RAMB36_X1Y18     SYS70/DMCMON.I0/BRAM1/UMEM/AW_09_S36.GL[0].MEM/CLKARDCLK
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.944         12.500      9.556      RAMB36_X1Y18     SYS70/DMCMON.I0/BRAM1/UMEM/AW_09_S36.GL[0].MEM/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.944         12.500      9.556      RAMB18_X0Y32     SYS70/CACHE/CMEM_DAT0/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.944         12.500      9.556      RAMB18_X0Y32     SYS70/CACHE/CMEM_DAT0/UMEM/AW_11_S9.GL[0].MEM/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.944         12.500      9.556      RAMB18_X0Y33     SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.944         12.500      9.556      RAMB18_X0Y33     SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM/CLKBWRCLK
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.944         12.500      9.556      RAMB18_X0Y31     SYS70/CACHE/CMEM_DAT2/UMEM/AW_11_S9.GL[0].MEM/CLKARDCLK
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.944         12.500      9.556      RAMB18_X0Y31     SYS70/CACHE/CMEM_DAT2/UMEM/AW_11_S9.GL[0].MEM/CLKBWRCLK
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.944         12.500      9.556      RAMB36_X1Y15     SYS70/DMSCNT.I0/CMEM/UMEM/AW_09_S36.GL[0].MEM/CLKARDCLK
Max Period        n/a     MMCME2_ADV/CLKOUT0  n/a            213.360       12.500      200.860    MMCME2_ADV_X1Y2  GEN_CLKSYS/USEMMCM.MMCM/CLKOUT0
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X38Y89     SYS70/DMCMON.I0/MAL/AW_4.GL[0].MEM/DP/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X38Y89     SYS70/DMCMON.I0/MAL/AW_4.GL[0].MEM/SP/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X38Y89     SYS70/DMCMON.I0/MAL/AW_4.GL[10].MEM/DP/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X38Y89     SYS70/DMCMON.I0/MAL/AW_4.GL[10].MEM/SP/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X38Y89     SYS70/DMCMON.I0/MAL/AW_4.GL[11].MEM/DP/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X38Y89     SYS70/DMCMON.I0/MAL/AW_4.GL[11].MEM/SP/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X38Y89     SYS70/DMCMON.I0/MAL/AW_4.GL[12].MEM/DP/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X38Y89     SYS70/DMCMON.I0/MAL/AW_4.GL[12].MEM/SP/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X38Y88     SYS70/DMCMON.I0/MAL/AW_4.GL[13].MEM/DP/CLK
Low Pulse Width   Fast    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X38Y88     SYS70/DMCMON.I0/MAL/AW_4.GL[13].MEM/SP/CLK
High Pulse Width  Slow    RAMS64E/CLK         n/a            1.250         6.250       5.000      SLICE_X12Y75     SYS70/W11A/VMBOX/MMU/SADR/SDR_LOW/AW_6.GL[0].MEM/SP/CLK
High Pulse Width  Slow    RAMS64E/CLK         n/a            1.250         6.250       5.000      SLICE_X12Y75     SYS70/W11A/VMBOX/MMU/SADR/SDR_LOW/AW_6.GL[1].MEM/SP/CLK
High Pulse Width  Slow    RAMS64E/CLK         n/a            1.250         6.250       5.000      SLICE_X12Y75     SYS70/W11A/VMBOX/MMU/SADR/SDR_LOW/AW_6.GL[2].MEM/SP/CLK
High Pulse Width  Slow    RAMS64E/CLK         n/a            1.250         6.250       5.000      SLICE_X12Y75     SYS70/W11A/VMBOX/MMU/SADR/SDR_LOW/AW_6.GL[3].MEM/SP/CLK
High Pulse Width  Slow    RAMS64E/CLK         n/a            1.250         6.250       5.000      SLICE_X14Y75     SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[0].MEM/SP/CLK
High Pulse Width  Slow    RAMS64E/CLK         n/a            1.250         6.250       5.000      SLICE_X14Y75     SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[1].MEM/SP/CLK
High Pulse Width  Slow    RAMS64E/CLK         n/a            1.250         6.250       5.000      SLICE_X14Y75     SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[2].MEM/SP/CLK
High Pulse Width  Slow    RAMS64E/CLK         n/a            1.250         6.250       5.000      SLICE_X14Y75     SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[3].MEM/SP/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X38Y89     SYS70/DMCMON.I0/MAL/AW_4.GL[0].MEM/DP/CLK
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250         6.250       5.000      SLICE_X38Y89     SYS70/DMCMON.I0/MAL/AW_4.GL[0].MEM/SP/CLK



