Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.4 (lin64) Build 1412921 Wed Nov 18 09:44:32 MST 2015
| Date         : Sat Mar 19 15:30:38 2016
| Host         : athome running 64-bit Ubuntu 14.04.4 LTS
| Command      : report_control_sets -verbose -file sys_w11a_n4_control_sets_placed.rpt
| Design       : sys_w11a_n4
| Device       : xc7a100t
----------------------------------------------------------------------------------------

Control Set Information

Table of Contents
-----------------
1. Summary
2. Flip-Flop Distribution
3. Detailed Control Set Information

1. Summary
----------

+-------------------------------------------------------------------+-------+
|                               Status                              | Count |
+-------------------------------------------------------------------+-------+
| Number of unique control sets                                     |   207 |
| Minimum Number of register sites lost to control set restrictions |   448 |
+-------------------------------------------------------------------+-------+


2. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |             574 |          296 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |             222 |          133 |
| Yes          | No                    | No                     |             987 |          389 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |             753 |          302 |
+--------------+-----------------------+------------------------+-----------------+--------------+


3. Detailed Control Set Information
-----------------------------------

+-------------------+--------------------------------------------------------------+-------------------------------------------------------+------------------+----------------+
|    Clock Signal   |                         Enable Signal                        |                    Set/Reset Signal                   | Slice Load Count | Bel Load Count |
+-------------------+--------------------------------------------------------------+-------------------------------------------------------+------------------+----------------+
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RL11.I0/R_REGS[seekdt]_i_1_n_0                      | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                1 |              1 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RL11.I0/R_REGS[gshs]_i_1_n_0                        | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                1 |              1 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/SDR_AIB_WE                 |                                                       |                1 |              2 |
|  GEN_CLKSYS/CLKFX | CLKDIV/CE_MSEC                                               | SYS70/W11A/SEQ/R_REGS_reg[ibsel]0_4                   |                1 |              4 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/n[ibracc]                                   | SYS70/RB2CP/SR[0]                                     |                1 |              4 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/n[conena]                                   |                                                       |                1 |              4 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RHRP.I0/n[cs2unit]                                  | IBDR_SYS/RHRP.I0/R_REGS[cs2unit][0]_i_1_n_0           |                1 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/TX/n[sreg]                           | RLINK/SERPORT/UART/RXTX/TX/R_REGS[bcnt][3]_i_1_n_0    |                1 |              4 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[cse][0][0]                       | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                2 |              4 |
|  GEN_CLKSYS/CLKFX | CRAM_CTL/R_REGS[state][3]_i_1__2_n_0                         | SYS70/RB2CP/SR[0]                                     |                3 |              4 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/MMU/SADR/SDR_LOW/SDR_LOW_WE                 |                                                       |                1 |              4 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RHRP.I0/n[bae][5]                                   | IBDR_SYS/RHRP.I0/R_REGS[bae][5]_i_1_n_0               |                1 |              4 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[msk_bm][0][0]                    | SYS70/W11A/SEQ/R_REGS_reg[stc_count][7]               |                1 |              4 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/IIST.I0/n[ste_sie]                                  | SYS70/W11A/SEQ/R_REGS_reg[stc_count][7]               |                2 |              4 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/IIST.I0/n[ste_sbe]                                  | SYS70/W11A/SEQ/R_REGS_reg[stc_count][7]               |                1 |              4 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/IIST.I0/n[pge_pie]                                  | SYS70/W11A/SEQ/R_REGS_reg[stc_count][7]               |                1 |              4 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/IIST.I0/n[pge_pbe]                                  | SYS70/W11A/SEQ/R_REGS_reg[stc_count][7]               |                3 |              4 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[msk_im][0][0]                    | SYS70/W11A/SEQ/R_REGS_reg[stc_count][7]               |                2 |              4 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[mtc_mid][1][0]                   | SYS70/W11A/SEQ/R_REGS_reg[stc_count][7]               |                2 |              4 |
|  GEN_CLKSYS/CLKFX | CLKDIV/CE_MSEC                                               |                                                       |                1 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[swi]                                         |                                                       |                1 |              4 |
|  GEN_CLKSYS/CLKFX | SYS70/DMCMON.I0/MAL/E[0]                                     | SYS70/DMCMON.I0/R_REGS_reg[dp_ireg_we_n_0_]           |                1 |              4 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RL11.I0/R_REGS_reg[state]0                          | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                2 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[mal_raddr][0]_0                     | RLINK/CORE/RL/R_REGS_reg[mal_raddr][3]                |                1 |              4 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[crden][0][0]                     | IBDR_SYS/TM11.I0/SR[0]                                |                2 |              4 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/R_PSW_reg[cc][0]_1[0]                         |                                                       |                3 |              4 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RL11.I0/R_REGS[iaddr][3]_i_1_n_0                    | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                1 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[waddr]                                       |                                                       |                3 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[state]                                       |                                                       |                2 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/RX/R_REGS[bcnt][3]_i_2_n_0           | RLINK/SERPORT/UART/RXTX/RX/R_REGS[bcnt][3]_i_1__0_n_0 |                1 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_BREGS[stat][3]_i_1_n_0                       |                                                       |                2 |              4 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/n[mtc_dsbt]                                 | SYS70/W11A/SEQ/R_REGS_reg[stc_count][7]               |                2 |              4 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[acr_ac][0][0]                    | SYS70/W11A/SEQ/R_REGS_reg[stc_count][7]               |                2 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/AB/R_REGS[mcnt][6]_i_2_n_0                | RLINK/SERPORT/UART/AB/R_REGS[mcnt][6]_i_1_n_0         |                2 |              4 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[mode][1]                            |                                                       |                2 |              5 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[mprem][0][0]                     | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                2 |              5 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/R_REGS_reg[tcnt][0][0]                        |                                                       |                2 |              5 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/R_PSW_reg[rset][0]                            |                                                       |                2 |              5 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/MMU/SEL_SSR0/nssr0[seg_mode]                | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                2 |              5 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/MMU/SEL_SSR3/R_SSR3[ena_ubmap]              | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                1 |              5 |
|  GEN_CLKSYS/CLKFX |                                                              | HIO/HIO/HIO/DEB.DEB_BTN/n[dref]                       |                2 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/N_REGS[empty]                      |                                                       |                2 |              5 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/n[srpae]20_out                              | IBDR_SYS/TM11.I0/SR[0]                                |                3 |              5 |
|  GEN_CLKSYS/CLKFX | HIO/HIO/HIO/DEB.DEB_BTN/n[dref]                              |                                                       |                2 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/N_REGS[empty]                                  | RLINK/SERPORT/UART/AB/R_REGS_reg[busy]                |                1 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/XONTX/n[oval]12_out                            | RLINK/SERPORT/XONTX/R_REGS[obuf][7]_i_1_n_0           |                1 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[drena]                              |                                                       |                2 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/RAM/N_REGS[full]                   |                                                       |                2 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/CD2B/E[0]                                         | RLINK/SERPORT/UART/AB/R_REGS_reg[busy]                |                2 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[swi_en]                                      |                                                       |                1 |              5 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RHRP.I0/n[state]                                    |                                                       |                4 |              5 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_VMSTAT_reg[err]                           |                                                       |                2 |              5 |
|  GEN_CLKSYS/CLKFX | SYS70/RB2CP/R_REGS[cpfunc][4]_i_1_n_0                        |                                                       |                3 |              5 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/XONRX/E[0]                                     | RLINK/SERPORT/UART/AB/R_REGS_reg[busy]                |                2 |              5 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/MMU/MMU_CNTL[req]                           | SYS70/RB2CP/SR[0]                                     |                3 |              5 |
|  GEN_CLKSYS/CLKFX | SYS70/CACHE/CMEM_DAT0/UMEM/R_REGS_reg[hm_data][0]_0[0]       | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                2 |              6 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/R_SHC_reg[0][0]                               | SYS70/W11A/SEQ/SS[0]                                  |                3 |              6 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[cr_distrap][0]                   | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                2 |              6 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/UBMAP/SEL/iwe2                              |                                                       |                2 |              6 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/nstatus[intack]                               | SYS70/RB2CP/SR[0]                                     |                3 |              6 |
|  GEN_CLKSYS/CLKFX | SYS70/RB2CP/R_REGS[addr][21]_i_1_n_0                         |                                                       |                3 |              6 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS_reg[state][0]              |                                                       |                5 |              6 |
|  GEN_CLKSYS/CLKFX |                                                              | SYS70/W11A/VMBOX/R_REGS[atocnt][5]_i_1_n_0            |                2 |              6 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RHRP.I0/iscinc11_out                                | IBDR_SYS/RHRP.I0/n[sc]                                |                2 |              6 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/AB/R_REGS[ccnt][12]_i_2__0_n_0            | RLINK/SERPORT/UART/AB/R_REGS[ccnt][12]_i_1_n_0        |                3 |              6 |
|  GEN_CLKSYS/CLKFX | CLKDIV/CE_USEC                                               |                                                       |                2 |              7 |
|  GEN_CLKSYS/CLKFX | CRAM_CTL/R_REGS[cntce][6]_i_2_n_0                            | SYS70/RB2CP/R_REGS_reg[cntce][0][0]                   |                2 |              7 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/SDR_SLF_WE                 |                                                       |                2 |              7 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/UBMAP/SEL/iwe0                              |                                                       |                2 |              7 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/E[0]                                        | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                2 |              7 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RHRP.I0/E[0]                                        |                                                       |                6 |              7 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/R_PC_reg[3]_0                                 |                                                       |                3 |              7 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[buf][6][0]                       | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                3 |              7 |
|  GEN_CLKSYS/CLKFX |                                                              | RLINK/CORE/RL/R_BREGS[btocnt][6]_i_1_n_0              |                3 |              7 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[ba][15][0]                       | IBDR_SYS/TM11.I0/SR[0]                                |                3 |              7 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[pbuf][0][0]                      | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                2 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[mbrk][7][0]                      | SYS70/W11A/SEQ/R_SSR1_reg[rb_delta][0]                |                4 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[dreg][11][1]                     | SYS70/RB2CP/SR[0]                                     |                2 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[dreg][11][0]                     | SYS70/RB2CP/SR[0]                                     |                3 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/RB2CP/E[0]                                             | SYS70/RB2CP/SR[0]                                     |                2 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[da][15][1]                       | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                2 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[da][15][0]                       | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                2 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[xbuf][0]_0[0]                    | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                1 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[rbuf][0][0]                      | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                4 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[addr][15]_i_1_n_0                      |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[rbuf][0]_0[0]                    | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                4 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[rbuf][0]_1[0]                    | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                4 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[tcnt256][0][0]                   |                                                       |                3 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[xbuf][0][0]                      | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                3 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[bc][15]_0[1]                     | IBDR_SYS/TM11.I0/SR[0]                                |                3 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[bc][15]_0[0]                     | IBDR_SYS/TM11.I0/SR[0]                                |                2 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[ba][15][1]                       | IBDR_SYS/TM11.I0/SR[0]                                |                3 |              8 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RL11.I0/MEM_0/MEM_0_WE                              |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[dsp_dp]                                      |                                                       |                3 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[din][15]                                     |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[din][7]                                      |                                                       |                3 |              8 |
|  GEN_CLKSYS/CLKFX |                                                              | HIO/HIO/R_REGS_reg[ledin][8]                          |                5 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/R_PC_reg[11]_0                                |                                                       |                4 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/RX/E[0]                              | RLINK/SERPORT/UART/AB/R_REGS_reg[busy]                |                1 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/RX/R_REGS[sreg][7]_i_1__0_n_0        |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/RXTX/TX/R_REGS[sreg][7]_i_1_n_0           |                                                       |                3 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[atocnt][7]_i_1_n_0                     |                                                       |                3 |              8 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/IIST.I0/R_REGS[stc_count][7]_i_1_n_0                | SYS70/W11A/SEQ/R_REGS_reg[stc_count][7]               |                4 |              8 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RL11.I0/MEM_0/MEM_1_WE                              |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RHRP.I0/MEM_1/imem_we1                              |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RHRP.I0/MEM_0/imem_we0                              |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RHRP.I0/R_REGS[idlyval][7]_i_1_n_0                  |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RHRP.I0/R_REGS[idlycnt][7]_i_1_n_0                  |                                                       |                3 |              8 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RK11.I0/MEM_1/MEM_1_WE                              |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/SEL__0/E[0]                                 | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                3 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/MMU/SADR/SAR_HIGH/SAR_HIGH_WE               |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[cnt][15]_i_1_n_0                       |                                                       |                3 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/MMU/SADR/SAR_LOW/SAR_LOW_WE                 |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/MEM_0_WE                                    |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/MMU/SSR12/SEL_SSR1/R_SSR1_reg[rb_num][0][0] | SYS70/W11A/SEQ/R_SSR1_reg[rb_delta][0]                |                4 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[laddr][0]_1                         |                                                       |                3 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/MMU/SSR12/SEL_SSR1/R_SSR1_reg[ra_num][0][0] | SYS70/W11A/SEQ/R_SSR1_reg[rb_delta][0]                |                3 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[rcmd][7]_i_1_n_0                       |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[dinl][7]_i_1_n_0                       |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[cnt][7]_i_1_n_0                        |                                                       |                3 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[lcmd]                                        |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/UBMAP/SEL/iwe1                              |                                                       |                2 |              8 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[laddr][0]_0                         |                                                       |                5 |              9 |
|  GEN_CLKSYS/CLKFX |                                                              | RLINK/SERPORT/UART/AB/R_REGS_reg[busy]                |                4 |              9 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[laddr][8]                        |                                                       |                4 |              9 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RL11.I0/R_REGS[seekcac][8]_i_1_n_0                  | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                4 |              9 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/CD2B/n[ecodeval]3_out                             |                                                       |                2 |              9 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[laddr][8]                           |                                                       |                5 |              9 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/E[0]                                           |                                                       |                4 |             10 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RL11.I0/R_REGS[seekcan][9]_i_1_n_0                  | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |                3 |             10 |
|  GEN_CLKSYS/CLKFX | RLINK/RBMON.I0/n[rbnbusy]                                    | RLINK/CORE/RL/SR[0]                                   |                2 |             10 |
|  GEN_CLKSYS/CLKFX | SYS70/IBMON.I0/n[ibnbusy]                                    | SYS70/W11A/VMBOX/R_REGS_reg[ibnbusy][9][0]            |                3 |             10 |
|  GEN_CLKSYS/CLKFX | CLKDIV/n[mcnt]                                               |                                                       |                3 |             10 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/SEL/n[anena]                                   |                                                       |                4 |             10 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[rdlycnt][0]_0[0]                 |                                                       |                5 |             10 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[rdlycnt][0]_1[0]                 |                                                       |                4 |             10 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/UART/AB/R_REGS[ccnt][12]_i_2__0_n_0            |                                                       |                3 |             10 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_BREGS[dcnt][10]_i_2_n_0                      | RLINK/CORE/RL/cnt_load                                |                5 |             11 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_BREGS[cnt][10]_i_1_n_0                       |                                                       |                5 |             11 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_LREGS[addr][7]_i_1_n_0                       |                                                       |                4 |             12 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/n[lolim]                                    |                                                       |                5 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/ICRC/R_LREGS_reg[rtaddrb][0]                   | RLINK/CORE/RL/ICRC/n[rtaddrb_red]15_out               |                3 |             12 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/n[hilim]                                    |                                                       |                4 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/R_LREGS_reg[bcnt][0]               |                                                       |                3 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/n[rtaddra]                         | RLINK/CORE/RL/addra_clear                             |                3 |             12 |
|  GEN_CLKSYS/CLKFX | SMRB.I0/SMRB/R_REGS[temp][11]_i_1_n_0                        |                                                       |                4 |             12 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/XONTX/E[0]                                     | RLINK/SERPORT/UART/AB/R_REGS_reg[busy]                |                4 |             13 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[rbndly]                                      | RLINK/RBMON.I0/R_REGS[rbndly][0]_i_1_n_0              |                4 |             14 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/n[ibndly]                                   | SYS70/IBMON.I0/R_REGS[ibndly][0]_i_1_n_0              |                4 |             14 |
|  GEN_CLKSYS/CLKFX | IOB_RS232/IOB_RXD/IOB/R_REGS_reg[dcnt][0]                    |                                                       |                4 |             14 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[lolim]_15__s_net_1                  |                                                       |                5 |             15 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[hilim]_15__s_net_1                  |                                                       |                3 |             15 |
|  GEN_CLKSYS/CLKFX | SYS70/DMCMON.I0/R_REGS_reg[dp_ireg_we_n_0_]                  |                                                       |                8 |             15 |
|  GEN_CLKSYS/CLKFX | SYS70/RB2CP/R_REGS[addr][15]_i_1_n_0                         |                                                       |                4 |             15 |
|  GEN_CLKSYS/CLKFX |                                                              | IBDR_SYS/TM11.I0/SR[0]                                |                8 |             15 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[lolim]                                       |                                                       |                7 |             15 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[hilim]                                       |                                                       |                5 |             15 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/R_REGS_reg[dp_pc_fet][15]_0                   |                                                       |                4 |             15 |
|  GEN_CLKSYS/CLKFX | SMRB.I0/SM_EOS                                               |                                                       |                4 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dsp_dat][12]                        |                                                       |                4 |             16 |
|  GEN_CLKSYS/CLKFX | HIO/HIO/HIO/DEB.DEB_SWI/n[dref]                              |                                                       |                7 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/TXFIFO/FIFO/RAM/WE0                            |                                                       |                2 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/TXFIFO/FIFO/RAM/WE1                            |                                                       |                2 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[7].MEM0_i_1__1_n_0     |                                                       |                2 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/SERPORT/RXFIFO/FIFO/RAM/WE1                            |                                                       |                2 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[hilim]_1                                     |                                                       |                5 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[led]                                         |                                                       |                3 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/n[lolim]_0                                     |                                                       |                6 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[dsp_dat][28]                        |                                                       |                4 |             16 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS[ibdout][15]_i_1_n_0                  | SYS70/RB2CP/SR[0]                                     |                4 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_BREGS[rbdout][15]_i_1_n_0                    |                                                       |                9 |             16 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/DOUT0                                         |                                                       |                7 |             16 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/R_IREG_reg[0]_0[0]                            |                                                       |                9 |             16 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/DOUT0_0                                       |                                                       |                8 |             16 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/R_DTMP_reg[15][0]                             |                                                       |               12 |             16 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/R_DD_L_reg[0]_0[0]                            |                                                       |                4 |             16 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/MMU/SSR12/SEL_SSR1/E[0]                     | SYS70/W11A/SEQ/R_SSR1_reg[rb_delta][0]                |                3 |             16 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/N_REGS[dp_dres_val]                           |                                                       |                4 |             16 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/R_STATUS_reg[cmdack]_0                        | SYS70/W11A/SEQ/R_SSR1_reg[rb_delta][0]                |                8 |             16 |
|  GEN_CLKSYS/CLKFX | CRAM_CTL/N_REGS[ackr]                                        | SYS70/RB2CP/SR[0]                                     |               10 |             16 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/R_REGS_reg[dp_dres_val]                       |                                                       |                2 |             16 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[sreg][0][0]                      | SYS70/RB2CP/SR[0]                                     |                6 |             16 |
|  GEN_CLKSYS/CLKFX |                                                              | HIO/HIO/HIO/DEB.DEB_SWI/n[dref]                       |                8 |             16 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/R_DD_L_reg[8]                                 |                                                       |                2 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/ICRC/icrcena                                   | RLINK/CORE/RL/ICRC/R_CRC_reg[0]_0                     |                5 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/RAM/WE0                            |                                                       |                2 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/RAM/AW_5.GL[7].MEM1_i_1__1_n_0     |                                                       |                2 |             16 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/DOFIFO/FIFO/E[0]                               | RLINK/CORE/RL/ICRC/R_CRC_reg[0]_0                     |                6 |             16 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS[macc]_i_1_n_0                        | SYS70/RB2CP/SR[0]                                     |               11 |             18 |
|  GEN_CLKSYS/CLKFX | CRAM_CTL/IOB_MEM_ADDRH/E[0]                                  | SYS70/RB2CP/SR[0]                                     |                9 |             18 |
|  GEN_CLKSYS/CLKFX | SYS70/DMSCNT.I0/R_REGS_reg[mbuf][0]_0                        |                                                       |                7 |             20 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/nstate                                        | SYS70/RB2CP/SR[0]                                     |               12 |             21 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS[paddr][21]_i_1_n_0                   | SYS70/RB2CP/SR[0]                                     |               10 |             24 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/R_REGS_reg[vm_req]                            |                                                       |               12 |             26 |
|  GEN_CLKSYS/CLKFX |                                                              | SYS70/W11A/SEQ/R_REGS_reg[stc_count][7]               |               12 |             27 |
|  GEN_CLKSYS/CLKFX |                                                              | SYS70/W11A/SEQ/R_REGS_reg[ibsel]0_4                   |               19 |             31 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/R_REGS_reg[vm_addr_1][0]_0                    |                                                       |               11 |             32 |
|  GEN_CLKSYS/CLKFX | SYS70/DMCMON.I0/MAL/E[0]                                     |                                                       |                4 |             32 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[vm_ack]_0                        |                                                       |               15 |             34 |
|  GEN_CLKSYS/CLKFX | RLINK/CORE/RL/R_REGS_reg[rbtake_1]_0                         |                                                       |               18 |             36 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/VMBOX/R_REGS_reg[ibtake_1]_0                      |                                                       |               14 |             36 |
|  GEN_CLKSYS/CLKFX | SYS70/W11A/SEQ/nidstat[is_dstmode0]                          | SYS70/RB2CP/SR[0]                                     |               25 |             41 |
|  GEN_CLKSYS/CLKFX | SYS70/CACHE/CMEM_DAT3/UMEM/R_REGS_reg[addr_l][10]            | SYS70/RB2CP/SR[0]                                     |               22 |             41 |
|  GEN_CLKSYS/CLKFX | IBDR_SYS/RHRP.I0/R_REGS[camax][9]_i_1_n_0                    |                                                       |               21 |             41 |
|  GEN_CLKSYS/CLKFX |                                                              | SYS70/W11A/SEQ/R_SSR0_reg[seg_mode][0]                |               35 |             47 |
|  GEN_CLKSYS/CLKFX |                                                              | SYS70/RB2CP/SR[0]                                     |               35 |             51 |
|  GEN_CLKSYS/CLKFX |                                                              |                                                       |              296 |            574 |
+-------------------+--------------------------------------------------------------+-------------------------------------------------------+------------------+----------------+


