
*** Running vivado
    with args -log sys_w11a_n4.vdi -applog -m64 -messageDb vivado.pb -mode batch -source sys_w11a_n4.tcl -notrace


****** Vivado v2015.4 (64-bit)
  **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015
  **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015
    ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.

source sys_w11a_n4.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 359 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2015.4
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/walter/tmp/octest/trunk/rtl/bplib/nexys4/nexys4_pclk.xdc]
Finished Parsing XDC File [/home/walter/tmp/octest/trunk/rtl/bplib/nexys4/nexys4_pclk.xdc]
Parsing XDC File [/home/walter/tmp/octest/trunk/rtl/bplib/nexys4/nexys4_pins.xdc]
Finished Parsing XDC File [/home/walter/tmp/octest/trunk/rtl/bplib/nexys4/nexys4_pins.xdc]
Parsing XDC File [/home/walter/tmp/octest/trunk/rtl/bplib/nexys4/nexys4_pins_cram.xdc]
Finished Parsing XDC File [/home/walter/tmp/octest/trunk/rtl/bplib/nexys4/nexys4_pins_cram.xdc]
INFO: [Opt 31-140] Inserted 1 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 194 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 16 instances
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 80 instances
  RAM16X1S => RAM32X1S (RAMS32): 32 instances
  RAM32X1S => RAM32X1S (RAMS32): 37 instances
  RAM64X1S => RAM64X1S (RAMS64E): 29 instances

link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1186.332 ; gain = 280.953 ; free physical = 1062 ; free virtual = 8913
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00.22 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1192.344 ; gain = 4.008 ; free physical = 1059 ; free virtual = 8911
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Timing 38-2] Deriving generated clocks

Starting Logic Optimization Task
Implement Debug Cores | Checksum: aff16cfa

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: beda9416

Time (s): cpu = 00:00:00.75 ; elapsed = 00:00:00.74 . Memory (MB): peak = 1574.773 ; gain = 0.000 ; free physical = 715 ; free virtual = 8588

Phase 2 Constant Propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-10] Eliminated 0 cells.
Phase 2 Constant Propagation | Checksum: beda9416

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 1574.773 ; gain = 0.000 ; free physical = 712 ; free virtual = 8585

Phase 3 Sweep
INFO: [Opt 31-12] Eliminated 462 unconnected nets.
INFO: [Opt 31-140] Inserted 1 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-11] Eliminated 1 unconnected cells.
Phase 3 Sweep | Checksum: 18b7bb95c

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1574.773 ; gain = 0.000 ; free physical = 712 ; free virtual = 8584

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1574.773 ; gain = 0.000 ; free physical = 712 ; free virtual = 8584
Ending Logic Optimization Task | Checksum: 18b7bb95c

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1574.773 ; gain = 0.000 ; free physical = 712 ; free virtual = 8584

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...
INFO: [Timing 38-35] Done setting XDC timing constraints.
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 14 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 5 newly gated: 0 Total Ports: 28
Ending PowerOpt Patch Enables Task | Checksum: 4acf304e

Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1761.828 ; gain = 0.000 ; free physical = 585 ; free virtual = 8464
Ending Power Optimization Task | Checksum: 4acf304e

Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 1761.828 ; gain = 187.055 ; free physical = 585 ; free virtual = 8463
INFO: [Common 17-83] Releasing license: Implementation
28 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:21 ; elapsed = 00:00:20 . Memory (MB): peak = 1761.828 ; gain = 575.496 ; free physical = 585 ; free virtual = 8463
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1763.832 ; gain = 0.000 ; free physical = 583 ; free virtual = 8463
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys4/project_mflow/project_mflow.runs/impl_1/sys_w11a_n4_drc_opted.rpt.
INFO: [Vivado_Tcl 4-424] Cannot write hardware definition file as there are no IPI block design hardware handoff files present
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Initialization
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 578 ; free virtual = 8460
INFO: [Timing 38-35] Done setting XDC timing constraints.
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 577 ; free virtual = 8459

Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device

Phase 1.1.1 Pre-Place Cells
Phase 1.1.1 Pre-Place Cells | Checksum: 353c9512

Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:00.86 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 577 ; free virtual = 8459
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 1.1.2 IO and Clk Clean Up
Phase 1.1.2 IO and Clk Clean Up | Checksum: 353c9512

Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 577 ; free virtual = 8459

Phase 1.1.3 Implementation Feasibility check On IDelay
Phase 1.1.3 Implementation Feasibility check On IDelay | Checksum: 353c9512

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 577 ; free virtual = 8459

Phase 1.1.4 Commit IO Placement
Phase 1.1.4 Commit IO Placement | Checksum: 39865cf7

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 577 ; free virtual = 8459
Phase 1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 7274d618

Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 577 ; free virtual = 8459

Phase 1.2 Build Placer Netlist Model

Phase 1.2.1 Place Init Design

Phase 1.2.1.1 Init Lut Pin Assignment
Phase 1.2.1.1 Init Lut Pin Assignment | Checksum: 16750574c

Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 575 ; free virtual = 8457
Phase 1.2.1 Place Init Design | Checksum: 129105b85

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 575 ; free virtual = 8457
Phase 1.2 Build Placer Netlist Model | Checksum: 129105b85

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 575 ; free virtual = 8457

Phase 1.3 Constrain Clocks/Macros

Phase 1.3.1 Constrain Global/Regional Clocks
Phase 1.3.1 Constrain Global/Regional Clocks | Checksum: 129105b85

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 575 ; free virtual = 8457
Phase 1.3 Constrain Clocks/Macros | Checksum: 129105b85

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 575 ; free virtual = 8457
Phase 1 Placer Initialization | Checksum: 129105b85

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 575 ; free virtual = 8457

Phase 2 Global Placement
Phase 2 Global Placement | Checksum: 5281b058

Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 5281b058

Time (s): cpu = 00:00:19 ; elapsed = 00:00:15 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 131426c7b

Time (s): cpu = 00:00:23 ; elapsed = 00:00:17 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 17ef727f4

Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 3.4 updateClock Trees: DP
Phase 3.4 updateClock Trees: DP | Checksum: 17ef727f4

Time (s): cpu = 00:00:23 ; elapsed = 00:00:18 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 3.5 Timing Path Optimizer
Phase 3.5 Timing Path Optimizer | Checksum: 188c4491e

Time (s): cpu = 00:00:24 ; elapsed = 00:00:18 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 3.6 Fast Optimization
Phase 3.6 Fast Optimization | Checksum: 1bd46d3b1

Time (s): cpu = 00:00:24 ; elapsed = 00:00:19 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 3.7 Small Shape Detail Placement

Phase 3.7.1 Commit Small Macros and Core Logic

Phase 3.7.1.1 Commit Slice Clusters
Phase 3.7.1.1 Commit Slice Clusters | Checksum: 105dafd50

Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454
Phase 3.7.1 Commit Small Macros and Core Logic | Checksum: 105dafd50

Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 3.7.2 Clock Restriction Legalization for Leaf Columns
Phase 3.7.2 Clock Restriction Legalization for Leaf Columns | Checksum: 105dafd50

Time (s): cpu = 00:00:29 ; elapsed = 00:00:23 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 3.7.3 Clock Restriction Legalization for Non-Clock Pins
Phase 3.7.3 Clock Restriction Legalization for Non-Clock Pins | Checksum: 105dafd50

Time (s): cpu = 00:00:29 ; elapsed = 00:00:23 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454
Phase 3.7 Small Shape Detail Placement | Checksum: 105dafd50

Time (s): cpu = 00:00:29 ; elapsed = 00:00:23 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 3.8 Re-assign LUT pins
Phase 3.8 Re-assign LUT pins | Checksum: 122502654

Time (s): cpu = 00:00:29 ; elapsed = 00:00:24 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454
Phase 3 Detail Placement | Checksum: 122502654

Time (s): cpu = 00:00:29 ; elapsed = 00:00:24 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization

Phase 4.1.1 callUpdateTimingBeforePCO
Phase 4.1.1 callUpdateTimingBeforePCO | Checksum: 1309d63e1

Time (s): cpu = 00:00:32 ; elapsed = 00:00:25 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 4.1.2 updateClock Trees: PCOPT
Phase 4.1.2 updateClock Trees: PCOPT | Checksum: 1309d63e1

Time (s): cpu = 00:00:32 ; elapsed = 00:00:25 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 4.1.3 Post Placement Optimization

Phase 4.1.3.1 PCOPT Shape updates

Phase 4.1.3.1.1 removeOptionalFFsFromShapes
Phase 4.1.3.1.1 removeOptionalFFsFromShapes | Checksum: 1309d63e1

Time (s): cpu = 00:00:32 ; elapsed = 00:00:25 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 4.1.3.1.2 deleteLutnmShapes

Phase 4.1.3.1.2.1 deleteShapes
Phase 4.1.3.1.2.1 deleteShapes | Checksum: 1349cfce4

Time (s): cpu = 00:00:32 ; elapsed = 00:00:25 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454
Phase 4.1.3.1.2 deleteLutnmShapes | Checksum: 1349cfce4

Time (s): cpu = 00:00:32 ; elapsed = 00:00:25 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454
Phase 4.1.3.1 PCOPT Shape updates | Checksum: 1349cfce4

Time (s): cpu = 00:00:32 ; elapsed = 00:00:25 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 4.1.3.2 Post Placement Timing Optimization

Phase 4.1.3.2.1 Restore Best Placement
Phase 4.1.3.2.1 Restore Best Placement | Checksum: 166ddd19b

Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.197. For the most accurate timing information please run report_timing.
Phase 4.1.3.2 Post Placement Timing Optimization | Checksum: 166ddd19b

Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454
Phase 4.1.3 Post Placement Optimization | Checksum: 166ddd19b

Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454
Phase 4.1 Post Commit Optimization | Checksum: 166ddd19b

Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 4.2 Sweep Clock Roots: Post-Placement
Phase 4.2 Sweep Clock Roots: Post-Placement | Checksum: 166ddd19b

Time (s): cpu = 00:00:39 ; elapsed = 00:00:32 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 4.3 Post Placement Cleanup
Phase 4.3 Post Placement Cleanup | Checksum: 166ddd19b

Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 4.4 Placer Reporting

Phase 4.4.1 Restore STA
Phase 4.4.1 Restore STA | Checksum: 166ddd19b

Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454
Phase 4.4 Placer Reporting | Checksum: 166ddd19b

Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454

Phase 4.5 Final Placement Cleanup
Phase 4.5 Final Placement Cleanup | Checksum: 1505a0612

Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1505a0612

Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454
Ending Placer Task | Checksum: 5c6f3d43

Time (s): cpu = 00:00:39 ; elapsed = 00:00:33 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454
INFO: [Common 17-83] Releasing license: Implementation
44 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:41 ; elapsed = 00:00:34 . Memory (MB): peak = 1763.836 ; gain = 0.000 ; free physical = 598 ; free virtual = 8454
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 1765.836 ; gain = 0.000 ; free physical = 589 ; free virtual = 8453
report_io: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1765.840 ; gain = 0.000 ; free physical = 594 ; free virtual = 8452
report_utilization: Time (s): cpu = 00:00:00.18 ; elapsed = 00:00:00.25 . Memory (MB): peak = 1765.840 ; gain = 0.000 ; free physical = 593 ; free virtual = 8452
report_control_sets: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.19 . Memory (MB): peak = 1765.840 ; gain = 0.000 ; free physical = 593 ; free virtual = 8452
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs
Checksum: PlaceDB: 24897c40 ConstDB: 0 ShapeSum: 37e5c103 RouteDB: 0

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 9148124b

Time (s): cpu = 00:00:38 ; elapsed = 00:00:31 . Memory (MB): peak = 1765.840 ; gain = 0.000 ; free physical = 544 ; free virtual = 8402

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: 9148124b

Time (s): cpu = 00:00:38 ; elapsed = 00:00:32 . Memory (MB): peak = 1765.840 ; gain = 0.000 ; free physical = 542 ; free virtual = 8401

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 9148124b

Time (s): cpu = 00:00:38 ; elapsed = 00:00:32 . Memory (MB): peak = 1765.840 ; gain = 0.000 ; free physical = 535 ; free virtual = 8394
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 1ecf3f280

Time (s): cpu = 00:00:43 ; elapsed = 00:00:35 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 499 ; free virtual = 8358
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.232  | TNS=0.000  | WHS=-0.430 | THS=-119.809|

Phase 2 Router Initialization | Checksum: 26ccd96ca

Time (s): cpu = 00:00:45 ; elapsed = 00:00:36 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 499 ; free virtual = 8358

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 31a07e0c

Time (s): cpu = 00:00:48 ; elapsed = 00:00:38 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 499 ; free virtual = 8358

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 2098
 Number of Nodes with overlaps = 410
 Number of Nodes with overlaps = 84
 Number of Nodes with overlaps = 36
 Number of Nodes with overlaps = 4
 Number of Nodes with overlaps = 0

Phase 4.1.1 Update Timing
Phase 4.1.1 Update Timing | Checksum: 16b7f85f2

Time (s): cpu = 00:01:03 ; elapsed = 00:00:46 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342
INFO: [Route 35-416] Intermediate Timing Summary | WNS=-0.159 | TNS=-0.667 | WHS=N/A    | THS=N/A    |


Phase 4.1.2 GlobIterForTiming

Phase 4.1.2.1 Update Timing
Phase 4.1.2.1 Update Timing | Checksum: e3ec9c55

Time (s): cpu = 00:01:03 ; elapsed = 00:00:47 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342

Phase 4.1.2.2 Fast Budgeting
Phase 4.1.2.2 Fast Budgeting | Checksum: 10d3071ef

Time (s): cpu = 00:01:03 ; elapsed = 00:00:47 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342
Phase 4.1.2 GlobIterForTiming | Checksum: 15070801b

Time (s): cpu = 00:01:04 ; elapsed = 00:00:47 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342
Phase 4.1 Global Iteration 0 | Checksum: 15070801b

Time (s): cpu = 00:01:04 ; elapsed = 00:00:47 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342

Phase 4.2 Global Iteration 1
 Number of Nodes with overlaps = 357
 Number of Nodes with overlaps = 67
 Number of Nodes with overlaps = 13
 Number of Nodes with overlaps = 5
 Number of Nodes with overlaps = 9
 Number of Nodes with overlaps = 3
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0

Phase 4.2.1 Update Timing
Phase 4.2.1 Update Timing | Checksum: 10eeebca6

Time (s): cpu = 00:01:08 ; elapsed = 00:00:51 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.143  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.2 Global Iteration 1 | Checksum: 17749bf74

Time (s): cpu = 00:01:08 ; elapsed = 00:00:51 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342
Phase 4 Rip-up And Reroute | Checksum: 17749bf74

Time (s): cpu = 00:01:08 ; elapsed = 00:00:51 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 1d5927d82

Time (s): cpu = 00:01:09 ; elapsed = 00:00:52 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.238  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 5.1 Delay CleanUp | Checksum: 1d5927d82

Time (s): cpu = 00:01:09 ; elapsed = 00:00:52 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 1d5927d82

Time (s): cpu = 00:01:09 ; elapsed = 00:00:52 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342
Phase 5 Delay and Skew Optimization | Checksum: 1d5927d82

Time (s): cpu = 00:01:09 ; elapsed = 00:00:52 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342

Phase 6 Post Hold Fix

Phase 6.1 Update Timing
Phase 6.1 Update Timing | Checksum: 1625a63c3

Time (s): cpu = 00:01:10 ; elapsed = 00:00:52 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342
INFO: [Route 35-416] Intermediate Timing Summary | WNS=0.238  | TNS=0.000  | WHS=0.053  | THS=0.000  |

Phase 6 Post Hold Fix | Checksum: 1625a63c3

Time (s): cpu = 00:01:10 ; elapsed = 00:00:52 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342
WARNING: [Route 35-446] The router encountered 4 pins that are both setup-critical and hold-critical and tried to fix hold violations at the expense of setup slack.
Resolution: Run report_timing on the design before routing to identify timing paths with higher hold violations and low or negative setup margin.

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 1.95665 %
  Global Horizontal Routing Utilization  = 2.42157 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 10bab6124

Time (s): cpu = 00:01:10 ; elapsed = 00:00:52 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 10bab6124

Time (s): cpu = 00:01:10 ; elapsed = 00:00:52 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 740aece2

Time (s): cpu = 00:01:11 ; elapsed = 00:00:53 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.238  | TNS=0.000  | WHS=0.053  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 740aece2

Time (s): cpu = 00:01:11 ; elapsed = 00:00:53 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:01:11 ; elapsed = 00:00:53 . Memory (MB): peak = 1784.836 ; gain = 18.996 ; free physical = 483 ; free virtual = 8342

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
58 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:13 ; elapsed = 00:00:54 . Memory (MB): peak = 1784.965 ; gain = 19.125 ; free physical = 483 ; free virtual = 8342
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.98 . Memory (MB): peak = 1784.965 ; gain = 0.000 ; free physical = 472 ; free virtual = 8342
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys4/project_mflow/project_mflow.runs/impl_1/sys_w11a_n4_drc_routed.rpt.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
INFO: [Common 17-206] Exiting Vivado at Sat Mar 19 15:31:43 2016...
