Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
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Reading constraint file sys_w11a_s3.xcf.
XCF parsing done.
Reading design: /home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/sys_w11a_s3.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/sys_w11a_s3.prj"
Input Format                       : VHDL
Synthesis Constraint File          : sys_w11a_s3.xcf

---- Target Parameters
Output File Name                   : "sys_w11a_s3"
Output Format                      : ngc
Target Device                      : xc3s1000-ft256-4

---- Source Options
Shift Register Extraction          : NO

---- General Options
Optimization Goal                  : SPEED
Optimization Effort                : 2

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/slvtypes.vhd" in Library work.
Package <slvtypes> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/iblib.vhd" in Library work.
Package <iblib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rbus/rblib.vhd" in Library work.
Package <rblib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11.vhd" in Library work.
Package <pdp11> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_sel.vhd" in Library work.
Entity <ib_sel> compiled.
Entity <ib_sel> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/memlib.vhd" in Library work.
Package <memlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swar_gen_unisim.vhd" in Library work.
Entity <ram_1swar_gen> compiled.
Entity <ram_1swar_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swar_1ar_gen_unisim.vhd" in Library work.
Entity <ram_1swar_1ar_gen> compiled.
Entity <ram_1swar_1ar_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/xlib.vhd" in Library work.
Package <xlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_mmu_sadr.vhd" in Library work.
Entity <pdp11_mmu_sadr> compiled.
Entity <pdp11_mmu_sadr> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_mmu_ssr12.vhd" in Library work.
Entity <pdp11_mmu_ssr12> compiled.
Entity <pdp11_mmu_ssr12> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_sres_or_3.vhd" in Library work.
Entity <ib_sres_or_3> compiled.
Entity <ib_sres_or_3> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serportlib.vhd" in Library work.
Package <serportlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_uart_rx.vhd" in Library work.
Entity <serport_uart_rx> compiled.
Entity <serport_uart_rx> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_uart_tx.vhd" in Library work.
Entity <serport_uart_tx> compiled.
Entity <serport_uart_tx> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/comlib/comlib.vhd" in Library work.
Package <comlib> compiled.
Package body <comlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/fifo_1c_dram_raw.vhd" in Library work.
Entity <fifo_1c_dram_raw> compiled.
Entity <fifo_1c_dram_raw> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd" in Library work.
Entity <ram_2swsr_xfirst_gen_unisim> compiled.
Entity <ram_2swsr_xfirst_gen_unisim> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/genlib/genlib.vhd" in Library work.
Package <genlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/bpgen/bpgenlib.vhd" in Library work.
Package <bpgenlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_i_gen.vhd" in Library work.
Entity <iob_reg_i_gen> compiled.
Entity <iob_reg_i_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd" in Library work.
Entity <iob_reg_o_gen> compiled.
Entity <iob_reg_o_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/genlib/debounce_gen.vhd" in Library work.
Entity <debounce_gen> compiled.
Entity <debounce_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd" in Library work.
Entity <ram_1swsr_xfirst_gen_unisim> compiled.
Entity <ram_1swsr_xfirst_gen_unisim> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../sys_conf.vhd" in Library work.
Package <sys_conf> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_gpr.vhd" in Library work.
Entity <pdp11_gpr> compiled.
Entity <pdp11_gpr> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_psr.vhd" in Library work.
Entity <pdp11_psr> compiled.
Entity <pdp11_psr> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_ounit.vhd" in Library work.
Entity <pdp11_ounit> compiled.
Entity <pdp11_ounit> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_aunit.vhd" in Library work.
Entity <pdp11_aunit> compiled.
Entity <pdp11_aunit> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_lunit.vhd" in Library work.
Entity <pdp11_lunit> compiled.
Entity <pdp11_lunit> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_munit.vhd" in Library work.
Entity <pdp11_munit> compiled.
Entity <pdp11_munit> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_mmu.vhd" in Library work.
Entity <pdp11_mmu> compiled.
Entity <pdp11_mmu> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_ubmap.vhd" in Library work.
Entity <pdp11_ubmap> compiled.
Entity <pdp11_ubmap> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_sres_or_4.vhd" in Library work.
Entity <ib_sres_or_4> compiled.
Entity <ib_sres_or_4> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_sres_or_2.vhd" in Library work.
Entity <ib_sres_or_2> compiled.
Entity <ib_sres_or_2> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_uart_autobaud.vhd" in Library work.
Entity <serport_uart_autobaud> compiled.
Entity <serport_uart_autobaud> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_uart_rxtx.vhd" in Library work.
Entity <serport_uart_rxtx> compiled.
Entity <serport_uart_rxtx> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rlink/rlinklib.vhd" in Library work.
Package <rlinklib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd" in Library work.
Entity <ram_2swsr_rfirst_gen> compiled.
Entity <ram_2swsr_rfirst_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/fifo_1c_dram.vhd" in Library work.
Entity <fifo_1c_dram> compiled.
Entity <fifo_1c_dram> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/comlib/crc16.vhd" in Library work.
Entity <crc16> compiled.
Entity <crc16> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rbus/rb_sel.vhd" in Library work.
Entity <rb_sel> compiled.
Entity <rb_sel> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rbus/rb_sres_or_2.vhd" in Library work.
Entity <rb_sres_or_2> compiled.
Entity <rb_sres_or_2> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/bpgen/bp_swibtnled.vhd" in Library work.
Entity <bp_swibtnled> compiled.
Entity <bp_swibtnled> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/bpgen/sn_7segctl.vhd" in Library work.
Entity <sn_7segctl> compiled.
Entity <sn_7segctl> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdlib.vhd" in Library work.
Package <ibdlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_dmhbpt_unit.vhd" in Library work.
Entity <pdp11_dmhbpt_unit> compiled.
Entity <pdp11_dmhbpt_unit> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rbus/rb_sres_or_4.vhd" in Library work.
Entity <rb_sres_or_4> compiled.
Entity <rb_sres_or_4> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd" in Library work.
Entity <ram_1swsr_wfirst_gen> compiled.
Entity <ram_1swsr_wfirst_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_vmbox.vhd" in Library work.
Entity <pdp11_vmbox> compiled.
Entity <pdp11_vmbox> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_dpath.vhd" in Library work.
Entity <pdp11_dpath> compiled.
Entity <pdp11_dpath> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_decode.vhd" in Library work.
Entity <pdp11_decode> compiled.
Entity <pdp11_decode> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_sequencer.vhd" in Library work.
Entity <pdp11_sequencer> compiled.
Entity <pdp11_sequencer> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_irq.vhd" in Library work.
Entity <pdp11_irq> compiled.
Entity <pdp11_irq> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_reg70.vhd" in Library work.
Entity <pdp11_reg70> compiled.
Entity <pdp11_reg70> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_uart_rxtx_ab.vhd" in Library work.
Entity <serport_uart_rxtx_ab> compiled.
Entity <serport_uart_rxtx_ab> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_xonrx.vhd" in Library work.
Entity <serport_xonrx> compiled.
Entity <serport_xonrx> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_xontx.vhd" in Library work.
Entity <serport_xontx> compiled.
Entity <serport_xontx> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rlink/rlink_core.vhd" in Library work.
Entity <rlink_core> compiled.
Entity <rlink_core> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/comlib/byte2cdata.vhd" in Library work.
Entity <byte2cdata> compiled.
Entity <byte2cdata> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/comlib/cdata2byte.vhd" in Library work.
Entity <cdata2byte> compiled.
Entity <cdata2byte> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_i.vhd" in Library work.
Entity <iob_reg_i> compiled.
Entity <iob_reg_i> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_o.vhd" in Library work.
Entity <iob_reg_o> compiled.
Entity <iob_reg_o> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/bpgen/sn_humanio.vhd" in Library work.
Entity <sn_humanio> compiled.
Entity <sn_humanio> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_statleds.vhd" in Library work.
Entity <pdp11_statleds> compiled.
Entity <pdp11_statleds> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_ledmux.vhd" in Library work.
Entity <pdp11_ledmux> compiled.
Entity <pdp11_ledmux> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_dspmux.vhd" in Library work.
Entity <pdp11_dspmux> compiled.
Entity <pdp11_dspmux> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_io_gen.vhd" in Library work.
Entity <iob_reg_io_gen> compiled.
Entity <iob_reg_io_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibd_iist.vhd" in Library work.
Entity <ibd_iist> compiled.
Entity <ibd_iist> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibd_kw11l.vhd" in Library work.
Entity <ibd_kw11l> compiled.
Entity <ibd_kw11l> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_rhrp.vhd" in Library work.
Entity <ibdr_rhrp> compiled.
Entity <ibdr_rhrp> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_rl11.vhd" in Library work.
Entity <ibdr_rl11> compiled.
Entity <ibdr_rl11> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_rk11.vhd" in Library work.
Entity <ibdr_rk11> compiled.
Entity <ibdr_rk11> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_tm11.vhd" in Library work.
Entity <ibdr_tm11> compiled.
Entity <ibdr_tm11> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_dl11.vhd" in Library work.
Entity <ibdr_dl11> compiled.
Entity <ibdr_dl11> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_pc11.vhd" in Library work.
Entity <ibdr_pc11> compiled.
Entity <ibdr_pc11> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_lp11.vhd" in Library work.
Entity <ibdr_lp11> compiled.
Entity <ibdr_lp11> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_sdreg.vhd" in Library work.
Entity <ibdr_sdreg> compiled.
Entity <ibdr_sdreg> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_intmap.vhd" in Library work.
Entity <ib_intmap> compiled.
Entity <ib_intmap> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_core_rbus.vhd" in Library work.
Entity <pdp11_core_rbus> compiled.
Entity <pdp11_core_rbus> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_core.vhd" in Library work.
Entity <pdp11_core> compiled.
Entity <pdp11_core> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_cache.vhd" in Library work.
Entity <pdp11_cache> compiled.
Entity <pdp11_cache> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_mem70.vhd" in Library work.
Entity <pdp11_mem70> compiled.
Entity <pdp11_mem70> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibd_ibmon.vhd" in Library work.
Entity <ibd_ibmon> compiled.
Entity <ibd_ibmon> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_dmscnt.vhd" in Library work.
Entity <pdp11_dmscnt> compiled.
Entity <pdp11_dmscnt> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_dmcmon.vhd" in Library work.
Entity <pdp11_dmcmon> compiled.
Entity <pdp11_dmcmon> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_dmhbpt.vhd" in Library work.
Entity <pdp11_dmhbpt> compiled.
Entity <pdp11_dmhbpt> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rbus/rbdlib.vhd" in Library work.
Package <rbdlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rlink/rlink_core8.vhd" in Library work.
Entity <rlink_core8> compiled.
Entity <rlink_core8> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_1clock.vhd" in Library work.
Entity <serport_1clock> compiled.
Entity <serport_1clock> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rbus/rbd_rbmon.vhd" in Library work.
Entity <rbd_rbmon> compiled.
Entity <rbd_rbmon> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/bpgen/bp_rs232_2line_iob.vhd" in Library work.
Entity <bp_rs232_2line_iob> compiled.
Entity <bp_rs232_2line_iob> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/bpgen/bp_rs232_4line_iob.vhd" in Library work.
Entity <bp_rs232_4line_iob> compiled.
Entity <bp_rs232_4line_iob> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/bpgen/bpgenrbuslib.vhd" in Library work.
Package <bpgenrbuslib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/s3board/s3boardlib.vhd" in Library work.
Package <s3boardlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/genlib/clkdivce.vhd" in Library work.
Entity <clkdivce> compiled.
Entity <clkdivce> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/bpgen/bp_rs232_2l4l_iob.vhd" in Library work.
Entity <bp_rs232_2l4l_iob> compiled.
Entity <bp_rs232_2l4l_iob> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rlink/rlink_sp1c.vhd" in Library work.
Entity <rlink_sp1c> compiled.
Entity <rlink_sp1c> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_sys70.vhd" in Library work.
Entity <pdp11_sys70> compiled.
Entity <pdp11_sys70> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_maxisys.vhd" in Library work.
Entity <ibdr_maxisys> compiled.
Entity <ibdr_maxisys> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/s3board/s3_sram_memctl.vhd" in Library work.
Entity <s3_sram_memctl> compiled.
Entity <s3_sram_memctl> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rlink/ioleds_sp1c.vhd" in Library work.
Entity <ioleds_sp1c> compiled.
Entity <ioleds_sp1c> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_hio70.vhd" in Library work.
Entity <pdp11_hio70> compiled.
Entity <pdp11_hio70> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/bpgen/sn_humanio_rbus.vhd" in Library work.
Entity <sn_humanio_rbus> compiled.
Entity <sn_humanio_rbus> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../sys_w11a_s3.vhd" in Library work.
Entity <sys_w11a_s3> compiled.
Entity <sys_w11a_s3> (Architecture <syn>) compiled.

Reading constraint file sys_w11a_s3.xcf.
XCF parsing done.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <sys_w11a_s3> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <clkdivce> in library <work> (architecture <syn>) with generics.
	CDUWIDTH = 6
	MSECDIV = 1000
	USECDIV = 50

Analyzing hierarchy for entity <bp_rs232_2l4l_iob> in library <work> (architecture <syn>) with generics.
	RELAY = false

Analyzing hierarchy for entity <rlink_sp1c> in library <work> (architecture <syn>) with generics.
	BTOWIDTH = 6
	CDINIT = 433
	CDWIDTH = 13
	ENAPIN_RBMON = 13
	ENAPIN_RLBMON = -1
	ENAPIN_RLMON = 15
	IFAWIDTH = 5
	OFAWIDTH = 5
	RBMON_AWIDTH = 9
	RBMON_RBADDR = "1111111111101000"
	RTAWIDTH = 12
	SYSID = "00000000000000000000000000000000"

Analyzing hierarchy for entity <pdp11_sys70> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ibdr_maxisys> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <s3_sram_memctl> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ioleds_sp1c> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_hio70> in library <work> (architecture <syn>) with generics.
	DCWIDTH = 2
	LWIDTH = 8

Analyzing hierarchy for entity <sn_humanio_rbus> in library <work> (architecture <syn>) with generics.
	BWIDTH = 4
	DCWIDTH = 2
	DEBOUNCE = true
	LWIDTH = 8
	RB_ADDR = "1111111011110000"
	SWIDTH = 8

Analyzing hierarchy for entity <rb_sres_or_2> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <bp_rs232_2line_iob> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <bp_rs232_4line_iob> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <rlink_core8> in library <work> (architecture <syn>) with generics.
	BTOWIDTH = 6
	ENAPIN_RBMON = 13
	ENAPIN_RLBMON = -1
	ENAPIN_RLMON = 15
	RTAWIDTH = 12
	SYSID = "00000000000000000000000000000000"

Analyzing hierarchy for entity <serport_1clock> in library <work> (architecture <syn>) with generics.
	CDINIT = 433
	CDWIDTH = 13
	RXFAWIDTH = 5
	TXFAWIDTH = 5

Analyzing hierarchy for entity <rbd_rbmon> in library <work> (architecture <syn>) with generics.
	AWIDTH = 9
	RB_ADDR = "1111111111101000"

Analyzing hierarchy for entity <pdp11_core_rbus> in library <work> (architecture <syn>) with generics.
	RB_ADDR_CORE = "0000000000000000"
	RB_ADDR_IBUS = "0100000000000000"

Analyzing hierarchy for entity <pdp11_core> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_cache> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_mem70> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ibd_ibmon> in library <work> (architecture <syn>) with generics.
	AWIDTH = 9
	IB_ADDR = "1110000000000000"

Analyzing hierarchy for entity <ib_sres_or_3> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_dmscnt> in library <work> (architecture <syn>) with generics.
	RB_ADDR = "0000000001000000"

Analyzing hierarchy for entity <pdp11_dmcmon> in library <work> (architecture <syn>) with generics.
	AWIDTH = 8
	RB_ADDR = "0000000001001000"

Analyzing hierarchy for entity <pdp11_dmhbpt> in library <work> (architecture <syn>) with generics.
	NUNIT = 2
	RB_ADDR = "0000000001010000"

Analyzing hierarchy for entity <rb_sres_or_4> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ibd_iist> in library <work> (architecture <syn>) with generics.
	SID = "00"

Analyzing hierarchy for entity <ibd_kw11l> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ibdr_rhrp> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ibdr_rl11> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ibdr_rk11> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ibdr_tm11> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ibdr_dl11> in library <work> (architecture <syn>) with generics.
	IB_ADDR = "1111111101110000"

Analyzing hierarchy for entity <ibdr_dl11> in library <work> (architecture <syn>) with generics.
	IB_ADDR = "1111110101000000"

Analyzing hierarchy for entity <ibdr_pc11> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ibdr_lp11> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ibdr_sdreg> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ib_sres_or_4> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ib_intmap> in library <work> (architecture <syn>) with generics.
	INTMAP = ((vec => 176
	           pri => 6),
	          (vec => 64
	           pri => 6),
	          (vec => 172
	           pri => 5),
	          (vec => 112
	           pri => 5),
	          (vec => 144
	           pri => 5),
	          (vec => 148
	           pri => 5),
	          (vec => 200
	           pri => 5),
	          (vec => 204
	           pri => 5),
	          (vec => 48
	           pri => 4),
	          (vec => 52
	           pri => 4),
	          (vec => 192
	           pri => 4),
	          (vec => 196
	           pri => 4),
	          (vec => 56
	           pri => 4),
	          (vec => 60
	           pri => 4),
	          (vec => 128
	           pri => 4),
	          (vec => 0
	           pri => 0))

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 2
	INIT = '1'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 4
	INIT = '1'

Analyzing hierarchy for entity <iob_reg_o> in library <work> (architecture <syn>) with generics.
	INIT = '1'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 18
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_io_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 32
	INITE = '0'
	INITI = '0'
	INITO = '0'
	PULL = "KEEP"

Analyzing hierarchy for entity <pdp11_statleds> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_ledmux> in library <work> (architecture <syn>) with generics.
	LWIDTH = 8

Analyzing hierarchy for entity <pdp11_dspmux> in library <work> (architecture <syn>) with generics.
	DCWIDTH = 2

Analyzing hierarchy for entity <sn_humanio> in library <work> (architecture <syn>) with generics.
	BWIDTH = 4
	DCWIDTH = 2
	DEBOUNCE = true
	LWIDTH = 8
	SWIDTH = 8

Analyzing hierarchy for entity <iob_reg_i> in library <work> (architecture <syn>) with generics.
	INIT = '1'

Analyzing hierarchy for entity <iob_reg_i> in library <work> (architecture <syn>) with generics.
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_o> in library <work> (architecture <syn>) with generics.
	INIT = '0'

Analyzing hierarchy for entity <rlink_core> in library <work> (architecture <syn>) with generics.
	BTOWIDTH = 6
	ENAPIN_RBMON = 13
	ENAPIN_RLMON = 15
	RTAWIDTH = 12
	SYSID = "00000000000000000000000000000000"

Analyzing hierarchy for entity <byte2cdata> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <cdata2byte> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <serport_uart_rxtx_ab> in library <work> (architecture <syn>) with generics.
	CDINIT = 433
	CDWIDTH = 13

Analyzing hierarchy for entity <serport_xonrx> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <serport_xontx> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <fifo_1c_dram> in library <work> (architecture <syn>) with generics.
	AWIDTH = 5
	DWIDTH = 8

Analyzing hierarchy for entity <ram_1swsr_wfirst_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 9
	DWIDTH = 32

Analyzing hierarchy for entity <pdp11_vmbox> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_dpath> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_decode> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_sequencer> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_irq> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_reg70> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ram_2swsr_rfirst_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 11
	DWIDTH = 9

Analyzing hierarchy for entity <ram_2swsr_rfirst_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 9
	DWIDTH = 36

Analyzing hierarchy for entity <ram_1swar_1ar_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 4
	DWIDTH = 16

Analyzing hierarchy for entity <pdp11_dmhbpt_unit> in library <work> (architecture <syn>) with generics.
	INDEX = 1
	RB_ADDR = "0000000001010000"

Analyzing hierarchy for entity <pdp11_dmhbpt_unit> in library <work> (architecture <syn>) with generics.
	INDEX = 0
	RB_ADDR = "0000000001010000"

Analyzing hierarchy for entity <ram_1swar_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 5
	DWIDTH = 8

Analyzing hierarchy for entity <ram_1swar_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 4
	DWIDTH = 8

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 1
	INIT = '1'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 4
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 8
	INIT = '0'

Analyzing hierarchy for entity <bp_swibtnled> in library <work> (architecture <syn>) with generics.
	BWIDTH = 4
	DEBOUNCE = true
	LWIDTH = 8
	SWIDTH = 8

Analyzing hierarchy for entity <sn_7segctl> in library <work> (architecture <syn>) with generics.
	CDWIDTH = 7
	DCWIDTH = 2

Analyzing hierarchy for entity <iob_reg_i_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 1
	INIT = '1'

Analyzing hierarchy for entity <iob_reg_i_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 1
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 1
	INIT = '0'

Analyzing hierarchy for entity <ram_2swsr_rfirst_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 12
	DWIDTH = 8

Analyzing hierarchy for entity <crc16> in library <work> (architecture <syn>) with generics.
	INIT = "0000000000000000"

Analyzing hierarchy for entity <rb_sel> in library <work> (architecture <syn>) with generics.
	RB_ADDR = "1111111111111100"
	SAWIDTH = 2

Analyzing hierarchy for entity <rb_sres_or_2> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <serport_uart_autobaud> in library <work> (architecture <syn>) with generics.
	CDINIT = 433
	CDWIDTH = 13

Analyzing hierarchy for entity <serport_uart_rxtx> in library <work> (architecture <syn>) with generics.
	CDWIDTH = 13

Analyzing hierarchy for entity <fifo_1c_dram_raw> in library <work> (architecture <syn>) with generics.
	AWIDTH = 5
	DWIDTH = 8

Analyzing hierarchy for entity <ram_1swsr_xfirst_gen_unisim> in library <work> (architecture <syn>) with generics.
	AWIDTH = 9
	DWIDTH = 32
	WRITE_MODE = "WRITE_FIRST"

Analyzing hierarchy for entity <pdp11_mmu> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_ubmap> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ib_sres_or_4> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ib_sres_or_2> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ib_sel> in library <work> (architecture <syn>) with generics.
	IB_ADDR = "1111111111111100"
	SAWIDTH = 0

Analyzing hierarchy for entity <pdp11_gpr> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_psr> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_ounit> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_aunit> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_lunit> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_munit> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ib_sel> in library <work> (architecture <syn>) with generics.
	IB_ADDR = "1111111111110110"
	SAWIDTH = 0

Analyzing hierarchy for entity <ib_sel> in library <work> (architecture <syn>) with generics.
	IB_ADDR = "1111111111111010"
	SAWIDTH = 0

Analyzing hierarchy for entity <ram_2swsr_xfirst_gen_unisim> in library <work> (architecture <syn>) with generics.
	AWIDTH = 11
	DWIDTH = 9
	WRITE_MODE = "READ_FIRST"

Analyzing hierarchy for entity <ram_2swsr_xfirst_gen_unisim> in library <work> (architecture <syn>) with generics.
	AWIDTH = 9
	DWIDTH = 36
	WRITE_MODE = "READ_FIRST"

Analyzing hierarchy for entity <iob_reg_i_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 8
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_i_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 4
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 8
	INIT = '0'

Analyzing hierarchy for entity <debounce_gen> in library <work> (architecture <syn>) with generics.
	CEDIV = 3
	CWIDTH = 2
	DWIDTH = 8

Analyzing hierarchy for entity <debounce_gen> in library <work> (architecture <syn>) with generics.
	CEDIV = 3
	CWIDTH = 2
	DWIDTH = 4

Analyzing hierarchy for entity <ram_2swsr_xfirst_gen_unisim> in library <work> (architecture <syn>) with generics.
	AWIDTH = 12
	DWIDTH = 8
	WRITE_MODE = "READ_FIRST"

Analyzing hierarchy for entity <serport_uart_rx> in library <work> (architecture <syn>) with generics.
	CDWIDTH = 13

Analyzing hierarchy for entity <serport_uart_tx> in library <work> (architecture <syn>) with generics.
	CDWIDTH = 13

Analyzing hierarchy for entity <ram_1swar_1ar_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 5
	DWIDTH = 8

Analyzing hierarchy for entity <pdp11_mmu_sadr> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <pdp11_mmu_ssr12> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ib_sres_or_3> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <ib_sel> in library <work> (architecture <syn>) with generics.
	IB_ADDR = "1111111101111010"
	SAWIDTH = 0

Analyzing hierarchy for entity <ib_sel> in library <work> (architecture <syn>) with generics.
	IB_ADDR = "1111010101001110"
	SAWIDTH = 0

Analyzing hierarchy for entity <ram_1swar_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 5
	DWIDTH = 6

Analyzing hierarchy for entity <ram_1swar_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 5
	DWIDTH = 8

Analyzing hierarchy for entity <ram_1swar_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 5
	DWIDTH = 7

Analyzing hierarchy for entity <ib_sel> in library <work> (architecture <syn>) with generics.
	IB_ADDR = "1111000010000000"
	SAWIDTH = 6

Analyzing hierarchy for entity <ram_1swar_1ar_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 4
	DWIDTH = 8

Analyzing hierarchy for entity <ib_sel> in library <work> (architecture <syn>) with generics.
	IB_ADDR = "1111111111111110"
	SAWIDTH = 0

Analyzing hierarchy for entity <ram_1swar_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 6
	DWIDTH = 8

Analyzing hierarchy for entity <ram_1swar_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 6
	DWIDTH = 7

Analyzing hierarchy for entity <ram_1swar_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 6
	DWIDTH = 2

Analyzing hierarchy for entity <ram_1swar_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 6
	DWIDTH = 4

Analyzing hierarchy for entity <ib_sel> in library <work> (architecture <syn>) with generics.
	IB_ADDR = "1111111101111100"
	SAWIDTH = 0

Analyzing hierarchy for entity <ib_sel> in library <work> (architecture <syn>) with generics.
	IB_ADDR = "1111111101111110"
	SAWIDTH = 0


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sys_w11a_s3> in library <work> (Architecture <syn>).
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../sys_w11a_s3.vhd" line 312: Unconnected output port 'RL_MONI' of component 'rlink_sp1c'.
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../sys_w11a_s3.vhd" line 391: Unconnected output port 'ACK_W' of component 's3_sram_memctl'.
Entity <sys_w11a_s3> analyzed. Unit <sys_w11a_s3> generated.

Analyzing generic Entity <clkdivce> in library <work> (Architecture <syn>).
	CDUWIDTH = 6
	MSECDIV = 1000
	USECDIV = 50
Entity <clkdivce> analyzed. Unit <clkdivce> generated.

Analyzing generic Entity <bp_rs232_2l4l_iob> in library <work> (Architecture <syn>).
	RELAY = false
Entity <bp_rs232_2l4l_iob> analyzed. Unit <bp_rs232_2l4l_iob> generated.

Analyzing Entity <bp_rs232_2line_iob> in library <work> (Architecture <syn>).
Entity <bp_rs232_2line_iob> analyzed. Unit <bp_rs232_2line_iob> generated.

Analyzing generic Entity <iob_reg_i.1> in library <work> (Architecture <syn>).
	INIT = '1'
Entity <iob_reg_i.1> analyzed. Unit <iob_reg_i.1> generated.

Analyzing generic Entity <iob_reg_i_gen.1> in library <work> (Architecture <syn>).
	DWIDTH = 1
	INIT = '1'
    Set user-defined property "IOB =  true" for signal <R_DI>.
Entity <iob_reg_i_gen.1> analyzed. Unit <iob_reg_i_gen.1> generated.

Analyzing generic Entity <iob_reg_o.1> in library <work> (Architecture <syn>).
	INIT = '1'
Entity <iob_reg_o.1> analyzed. Unit <iob_reg_o.1> generated.

Analyzing generic Entity <iob_reg_o_gen.4> in library <work> (Architecture <syn>).
	DWIDTH = 1
	INIT = '1'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.4> analyzed. Unit <iob_reg_o_gen.4> generated.

Analyzing Entity <bp_rs232_4line_iob> in library <work> (Architecture <syn>).
Entity <bp_rs232_4line_iob> analyzed. Unit <bp_rs232_4line_iob> generated.

Analyzing generic Entity <iob_reg_i.2> in library <work> (Architecture <syn>).
	INIT = '0'
Entity <iob_reg_i.2> analyzed. Unit <iob_reg_i.2> generated.

Analyzing generic Entity <iob_reg_i_gen.2> in library <work> (Architecture <syn>).
	DWIDTH = 1
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DI>.
Entity <iob_reg_i_gen.2> analyzed. Unit <iob_reg_i_gen.2> generated.

Analyzing generic Entity <iob_reg_o.2> in library <work> (Architecture <syn>).
	INIT = '0'
Entity <iob_reg_o.2> analyzed. Unit <iob_reg_o.2> generated.

Analyzing generic Entity <iob_reg_o_gen.7> in library <work> (Architecture <syn>).
	DWIDTH = 1
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.7> analyzed. Unit <iob_reg_o_gen.7> generated.

Analyzing generic Entity <rlink_sp1c> in library <work> (Architecture <syn>).
	BTOWIDTH = 6
	CDINIT = 433
	CDWIDTH = 13
	ENAPIN_RBMON = 13
	ENAPIN_RLBMON = -1
	ENAPIN_RLMON = 15
	IFAWIDTH = 5
	OFAWIDTH = 5
	RBMON_AWIDTH = 9
	RBMON_RBADDR = "1111111111101000"
	RTAWIDTH = 12
	SYSID = "00000000000000000000000000000000"
Entity <rlink_sp1c> analyzed. Unit <rlink_sp1c> generated.

Analyzing generic Entity <rlink_core8> in library <work> (Architecture <syn>).
	BTOWIDTH = 6
	ENAPIN_RBMON = 13
	ENAPIN_RLBMON = -1
	ENAPIN_RLMON = 15
	RTAWIDTH = 12
	SYSID = "00000000000000000000000000000000"
    Set property "fsm_encoding = one-hot" for unit <rlink_core>.
Entity <rlink_core8> analyzed. Unit <rlink_core8> generated.

Analyzing generic Entity <rlink_core> in library <work> (Architecture <syn>).
	BTOWIDTH = 6
	ENAPIN_RBMON = 13
	ENAPIN_RLMON = 15
	RTAWIDTH = 12
	SYSID = "00000000000000000000000000000000"
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rlink/rlink_core.vhd" line 441: Unconnected output port 'DOA' of component 'ram_2swsr_rfirst_gen'.
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rlink/rlink_core.vhd" line 460: Unconnected output port 'BUSY' of component 'fifo_1c_dram'.
Entity <rlink_core> analyzed. Unit <rlink_core> generated.

Analyzing generic Entity <ram_2swsr_rfirst_gen.3> in library <work> (Architecture <syn>).
	AWIDTH = 12
	DWIDTH = 8
Entity <ram_2swsr_rfirst_gen.3> analyzed. Unit <ram_2swsr_rfirst_gen.3> generated.

Analyzing generic Entity <ram_2swsr_xfirst_gen_unisim.3> in library <work> (Architecture <syn>).
	AWIDTH = 12
	DWIDTH = 8
	WRITE_MODE = "READ_FIRST"
    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_A =  000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_B =  000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "SRVAL_A =  000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "SRVAL_B =  000000000" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "WRITE_MODE_A =  READ_FIRST" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "WRITE_MODE_B =  READ_FIRST" for instance <AW_12_S4.GL[1].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_A =  000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "INIT_B =  000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "SRVAL_A =  000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "SRVAL_B =  000000000" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "WRITE_MODE_A =  READ_FIRST" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
    Set user-defined property "WRITE_MODE_B =  READ_FIRST" for instance <AW_12_S4.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.3>.
Entity <ram_2swsr_xfirst_gen_unisim.3> analyzed. Unit <ram_2swsr_xfirst_gen_unisim.3> generated.

Analyzing generic Entity <fifo_1c_dram> in library <work> (Architecture <syn>).
	AWIDTH = 5
	DWIDTH = 8
Entity <fifo_1c_dram> analyzed. Unit <fifo_1c_dram> generated.

Analyzing generic Entity <fifo_1c_dram_raw> in library <work> (Architecture <syn>).
	AWIDTH = 5
	DWIDTH = 8
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/fifo_1c_dram_raw.vhd" line 79: Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'.
Entity <fifo_1c_dram_raw> analyzed. Unit <fifo_1c_dram_raw> generated.

Analyzing generic Entity <ram_1swar_1ar_gen.2> in library <work> (Architecture <syn>).
	AWIDTH = 5
	DWIDTH = 8
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[7].MEM0> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[7].MEM1> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[6].MEM0> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[6].MEM1> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[5].MEM0> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[5].MEM1> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[4].MEM0> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[4].MEM1> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[3].MEM0> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[3].MEM1> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[2].MEM0> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[2].MEM1> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[1].MEM0> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[1].MEM1> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[0].MEM0> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[0].MEM1> in unit <ram_1swar_1ar_gen.2>.
Entity <ram_1swar_1ar_gen.2> analyzed. Unit <ram_1swar_1ar_gen.2> generated.

Analyzing generic Entity <crc16> in library <work> (Architecture <syn>).
	INIT = "0000000000000000"
Entity <crc16> analyzed. Unit <crc16> generated.

Analyzing generic Entity <rb_sel> in library <work> (Architecture <syn>).
	RB_ADDR = "1111111111111100"
	SAWIDTH = 2
Entity <rb_sel> analyzed. Unit <rb_sel> generated.

Analyzing Entity <byte2cdata> in library <work> (Architecture <syn>).
Entity <byte2cdata> analyzed. Unit <byte2cdata> generated.

Analyzing Entity <cdata2byte> in library <work> (Architecture <syn>).
Entity <cdata2byte> analyzed. Unit <cdata2byte> generated.

Analyzing generic Entity <serport_1clock> in library <work> (Architecture <syn>).
	CDINIT = 433
	CDWIDTH = 13
	RXFAWIDTH = 5
	TXFAWIDTH = 5
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_1clock.vhd" line 188: Unconnected output port 'SIZE' of component 'fifo_1c_dram'.
Entity <serport_1clock> analyzed. Unit <serport_1clock> generated.

Analyzing generic Entity <serport_uart_rxtx_ab> in library <work> (Architecture <syn>).
	CDINIT = 433
	CDWIDTH = 13
Entity <serport_uart_rxtx_ab> analyzed. Unit <serport_uart_rxtx_ab> generated.

Analyzing generic Entity <serport_uart_autobaud> in library <work> (Architecture <syn>).
	CDINIT = 433
	CDWIDTH = 13
Entity <serport_uart_autobaud> analyzed. Unit <serport_uart_autobaud> generated.

Analyzing generic Entity <serport_uart_rxtx> in library <work> (Architecture <syn>).
	CDWIDTH = 13
Entity <serport_uart_rxtx> analyzed. Unit <serport_uart_rxtx> generated.

Analyzing generic Entity <serport_uart_rx> in library <work> (Architecture <syn>).
	CDWIDTH = 13
Entity <serport_uart_rx> analyzed. Unit <serport_uart_rx> generated.

Analyzing generic Entity <serport_uart_tx> in library <work> (Architecture <syn>).
	CDWIDTH = 13
Entity <serport_uart_tx> analyzed. Unit <serport_uart_tx> generated.

Analyzing Entity <serport_xonrx> in library <work> (Architecture <syn>).
Entity <serport_xonrx> analyzed. Unit <serport_xonrx> generated.

Analyzing Entity <serport_xontx> in library <work> (Architecture <syn>).
Entity <serport_xontx> analyzed. Unit <serport_xontx> generated.

Analyzing generic Entity <rbd_rbmon> in library <work> (Architecture <syn>).
	AWIDTH = 9
	RB_ADDR = "1111111111101000"
Entity <rbd_rbmon> analyzed. Unit <rbd_rbmon> generated.

Analyzing generic Entity <ram_1swsr_wfirst_gen> in library <work> (Architecture <syn>).
	AWIDTH = 9
	DWIDTH = 32
Entity <ram_1swsr_wfirst_gen> analyzed. Unit <ram_1swsr_wfirst_gen> generated.

Analyzing generic Entity <ram_1swsr_xfirst_gen_unisim> in library <work> (Architecture <syn>).
	AWIDTH = 9
	DWIDTH = 32
	WRITE_MODE = "WRITE_FIRST"
    Set user-defined property "INIT =  000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "SRVAL =  000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
    Set user-defined property "WRITE_MODE =  WRITE_FIRST" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim>.
Entity <ram_1swsr_xfirst_gen_unisim> analyzed. Unit <ram_1swsr_xfirst_gen_unisim> generated.

Analyzing Entity <pdp11_sys70> in library <work> (Architecture <syn>).
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_sys70.vhd" line 146: Unconnected output port 'ESUSP_O' of component 'pdp11_core'.
Entity <pdp11_sys70> analyzed. Unit <pdp11_sys70> generated.

Analyzing generic Entity <pdp11_core_rbus> in library <work> (Architecture <syn>).
	RB_ADDR_CORE = "0000000000000000"
	RB_ADDR_IBUS = "0100000000000000"
Entity <pdp11_core_rbus> analyzed. Unit <pdp11_core_rbus> generated.

Analyzing Entity <pdp11_core> in library <work> (Architecture <syn>).
Entity <pdp11_core> analyzed. Unit <pdp11_core> generated.

Analyzing Entity <pdp11_vmbox> in library <work> (Architecture <syn>).
Entity <pdp11_vmbox> analyzed. Unit <pdp11_vmbox> generated.

Analyzing Entity <pdp11_mmu> in library <work> (Architecture <syn>).
Entity <pdp11_mmu> analyzed. Unit <pdp11_mmu> generated.

Analyzing Entity <pdp11_mmu_sadr> in library <work> (Architecture <syn>).
Entity <pdp11_mmu_sadr> analyzed. Unit <pdp11_mmu_sadr> generated.

Analyzing generic Entity <ram_1swar_gen.5> in library <work> (Architecture <syn>).
	AWIDTH = 6
	DWIDTH = 8
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[7].MEM> in unit <ram_1swar_gen.5>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[6].MEM> in unit <ram_1swar_gen.5>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[5].MEM> in unit <ram_1swar_gen.5>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[4].MEM> in unit <ram_1swar_gen.5>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[3].MEM> in unit <ram_1swar_gen.5>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[2].MEM> in unit <ram_1swar_gen.5>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[1].MEM> in unit <ram_1swar_gen.5>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[0].MEM> in unit <ram_1swar_gen.5>.
Entity <ram_1swar_gen.5> analyzed. Unit <ram_1swar_gen.5> generated.

Analyzing generic Entity <ram_1swar_gen.6> in library <work> (Architecture <syn>).
	AWIDTH = 6
	DWIDTH = 7
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[6].MEM> in unit <ram_1swar_gen.6>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[5].MEM> in unit <ram_1swar_gen.6>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[4].MEM> in unit <ram_1swar_gen.6>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[3].MEM> in unit <ram_1swar_gen.6>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[2].MEM> in unit <ram_1swar_gen.6>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[1].MEM> in unit <ram_1swar_gen.6>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[0].MEM> in unit <ram_1swar_gen.6>.
Entity <ram_1swar_gen.6> analyzed. Unit <ram_1swar_gen.6> generated.

Analyzing generic Entity <ram_1swar_gen.7> in library <work> (Architecture <syn>).
	AWIDTH = 6
	DWIDTH = 2
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[1].MEM> in unit <ram_1swar_gen.7>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[0].MEM> in unit <ram_1swar_gen.7>.
Entity <ram_1swar_gen.7> analyzed. Unit <ram_1swar_gen.7> generated.

Analyzing generic Entity <ram_1swar_gen.8> in library <work> (Architecture <syn>).
	AWIDTH = 6
	DWIDTH = 4
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[3].MEM> in unit <ram_1swar_gen.8>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[2].MEM> in unit <ram_1swar_gen.8>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[1].MEM> in unit <ram_1swar_gen.8>.
    Set user-defined property "INIT =  0000000000000000" for instance <AW_6.GL[0].MEM> in unit <ram_1swar_gen.8>.
Entity <ram_1swar_gen.8> analyzed. Unit <ram_1swar_gen.8> generated.

Analyzing Entity <pdp11_mmu_ssr12> in library <work> (Architecture <syn>).
Entity <pdp11_mmu_ssr12> analyzed. Unit <pdp11_mmu_ssr12> generated.

Analyzing generic Entity <ib_sel.8> in library <work> (Architecture <syn>).
	IB_ADDR = "1111111101111100"
	SAWIDTH = 0
Entity <ib_sel.8> analyzed. Unit <ib_sel.8> generated.

Analyzing generic Entity <ib_sel.9> in library <work> (Architecture <syn>).
	IB_ADDR = "1111111101111110"
	SAWIDTH = 0
Entity <ib_sel.9> analyzed. Unit <ib_sel.9> generated.

Analyzing generic Entity <ib_sel.4> in library <work> (Architecture <syn>).
	IB_ADDR = "1111111101111010"
	SAWIDTH = 0
Entity <ib_sel.4> analyzed. Unit <ib_sel.4> generated.

Analyzing generic Entity <ib_sel.5> in library <work> (Architecture <syn>).
	IB_ADDR = "1111010101001110"
	SAWIDTH = 0
Entity <ib_sel.5> analyzed. Unit <ib_sel.5> generated.

Analyzing Entity <pdp11_ubmap> in library <work> (Architecture <syn>).
Entity <pdp11_ubmap> analyzed. Unit <pdp11_ubmap> generated.

Analyzing generic Entity <ram_1swar_gen.3> in library <work> (Architecture <syn>).
	AWIDTH = 5
	DWIDTH = 6
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[5].MEM> in unit <ram_1swar_gen.3>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[4].MEM> in unit <ram_1swar_gen.3>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[3].MEM> in unit <ram_1swar_gen.3>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[2].MEM> in unit <ram_1swar_gen.3>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[1].MEM> in unit <ram_1swar_gen.3>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[0].MEM> in unit <ram_1swar_gen.3>.
Entity <ram_1swar_gen.3> analyzed. Unit <ram_1swar_gen.3> generated.

Analyzing generic Entity <ram_1swar_gen.1> in library <work> (Architecture <syn>).
	AWIDTH = 5
	DWIDTH = 8
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[7].MEM> in unit <ram_1swar_gen.1>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[6].MEM> in unit <ram_1swar_gen.1>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[5].MEM> in unit <ram_1swar_gen.1>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[4].MEM> in unit <ram_1swar_gen.1>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[3].MEM> in unit <ram_1swar_gen.1>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[2].MEM> in unit <ram_1swar_gen.1>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[1].MEM> in unit <ram_1swar_gen.1>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[0].MEM> in unit <ram_1swar_gen.1>.
Entity <ram_1swar_gen.1> analyzed. Unit <ram_1swar_gen.1> generated.

Analyzing generic Entity <ram_1swar_gen.4> in library <work> (Architecture <syn>).
	AWIDTH = 5
	DWIDTH = 7
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[6].MEM> in unit <ram_1swar_gen.4>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[5].MEM> in unit <ram_1swar_gen.4>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[4].MEM> in unit <ram_1swar_gen.4>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[3].MEM> in unit <ram_1swar_gen.4>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[2].MEM> in unit <ram_1swar_gen.4>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[1].MEM> in unit <ram_1swar_gen.4>.
    Set user-defined property "INIT =  00000000" for instance <AW_5.GL[0].MEM> in unit <ram_1swar_gen.4>.
Entity <ram_1swar_gen.4> analyzed. Unit <ram_1swar_gen.4> generated.

Analyzing generic Entity <ib_sel.6> in library <work> (Architecture <syn>).
	IB_ADDR = "1111000010000000"
	SAWIDTH = 6
Entity <ib_sel.6> analyzed. Unit <ib_sel.6> generated.

Analyzing Entity <ib_sres_or_2> in library <work> (Architecture <syn>).
Entity <ib_sres_or_2> analyzed. Unit <ib_sres_or_2> generated.

Analyzing generic Entity <ib_sel.1> in library <work> (Architecture <syn>).
	IB_ADDR = "1111111111111100"
	SAWIDTH = 0
Entity <ib_sel.1> analyzed. Unit <ib_sel.1> generated.

Analyzing Entity <pdp11_dpath> in library <work> (Architecture <syn>).
Entity <pdp11_dpath> analyzed. Unit <pdp11_dpath> generated.

Analyzing Entity <pdp11_gpr> in library <work> (Architecture <syn>).
Entity <pdp11_gpr> analyzed. Unit <pdp11_gpr> generated.

Analyzing generic Entity <ram_1swar_1ar_gen.3> in library <work> (Architecture <syn>).
	AWIDTH = 4
	DWIDTH = 8
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[7].MEM> in unit <ram_1swar_1ar_gen.3>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[6].MEM> in unit <ram_1swar_1ar_gen.3>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[5].MEM> in unit <ram_1swar_1ar_gen.3>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[4].MEM> in unit <ram_1swar_1ar_gen.3>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[3].MEM> in unit <ram_1swar_1ar_gen.3>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[2].MEM> in unit <ram_1swar_1ar_gen.3>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[1].MEM> in unit <ram_1swar_1ar_gen.3>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[0].MEM> in unit <ram_1swar_1ar_gen.3>.
Entity <ram_1swar_1ar_gen.3> analyzed. Unit <ram_1swar_1ar_gen.3> generated.

Analyzing Entity <pdp11_psr> in library <work> (Architecture <syn>).
Entity <pdp11_psr> analyzed. Unit <pdp11_psr> generated.

Analyzing generic Entity <ib_sel.7> in library <work> (Architecture <syn>).
	IB_ADDR = "1111111111111110"
	SAWIDTH = 0
Entity <ib_sel.7> analyzed. Unit <ib_sel.7> generated.

Analyzing Entity <pdp11_ounit> in library <work> (Architecture <syn>).
Entity <pdp11_ounit> analyzed. Unit <pdp11_ounit> generated.

Analyzing Entity <pdp11_aunit> in library <work> (Architecture <syn>).
Entity <pdp11_aunit> analyzed. Unit <pdp11_aunit> generated.

Analyzing Entity <pdp11_lunit> in library <work> (Architecture <syn>).
Entity <pdp11_lunit> analyzed. Unit <pdp11_lunit> generated.

Analyzing Entity <pdp11_munit> in library <work> (Architecture <syn>).
Entity <pdp11_munit> analyzed. Unit <pdp11_munit> generated.

Analyzing Entity <pdp11_decode> in library <work> (Architecture <syn>).
Entity <pdp11_decode> analyzed. Unit <pdp11_decode> generated.

Analyzing Entity <pdp11_sequencer> in library <work> (Architecture <syn>).
INFO:Xst:1561 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_sequencer.vhd" line 929: Mux is complete : default of case is discarded
INFO:Xst:1561 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_sequencer.vhd" line 469: Mux is complete : default of case is discarded
INFO:Xst:1561 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_sequencer.vhd" line 939: Mux is complete : default of case is discarded
INFO:Xst:1561 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_sequencer.vhd" line 469: Mux is complete : default of case is discarded
INFO:Xst:1561 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_sequencer.vhd" line 469: Mux is complete : default of case is discarded
INFO:Xst:1561 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_sequencer.vhd" line 469: Mux is complete : default of case is discarded
INFO:Xst:1561 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_sequencer.vhd" line 1988: Mux is complete : default of case is discarded
Entity <pdp11_sequencer> analyzed. Unit <pdp11_sequencer> generated.

Analyzing generic Entity <ib_sel.2> in library <work> (Architecture <syn>).
	IB_ADDR = "1111111111110110"
	SAWIDTH = 0
Entity <ib_sel.2> analyzed. Unit <ib_sel.2> generated.

Analyzing Entity <pdp11_irq> in library <work> (Architecture <syn>).
Entity <pdp11_irq> analyzed. Unit <pdp11_irq> generated.

Analyzing generic Entity <ib_sel.3> in library <work> (Architecture <syn>).
	IB_ADDR = "1111111111111010"
	SAWIDTH = 0
Entity <ib_sel.3> analyzed. Unit <ib_sel.3> generated.

Analyzing Entity <pdp11_reg70> in library <work> (Architecture <syn>).
Entity <pdp11_reg70> analyzed. Unit <pdp11_reg70> generated.

Analyzing Entity <ib_sres_or_4> in library <work> (Architecture <syn>).
Entity <ib_sres_or_4> analyzed. Unit <ib_sres_or_4> generated.

Analyzing Entity <pdp11_cache> in library <work> (Architecture <syn>).
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_cache.vhd" line 115: Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen'.
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_cache.vhd" line 134: Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen'.
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_cache.vhd" line 153: Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen'.
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_cache.vhd" line 172: Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen'.
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_cache.vhd" line 191: Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen'.
Entity <pdp11_cache> analyzed. Unit <pdp11_cache> generated.

Analyzing generic Entity <ram_2swsr_rfirst_gen.1> in library <work> (Architecture <syn>).
	AWIDTH = 11
	DWIDTH = 9
Entity <ram_2swsr_rfirst_gen.1> analyzed. Unit <ram_2swsr_rfirst_gen.1> generated.

Analyzing generic Entity <ram_2swsr_xfirst_gen_unisim.1> in library <work> (Architecture <syn>).
	AWIDTH = 11
	DWIDTH = 9
	WRITE_MODE = "READ_FIRST"
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_A =  000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_B =  000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "SRVAL_A =  000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "SRVAL_B =  000000000" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "WRITE_MODE_A =  READ_FIRST" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
    Set user-defined property "WRITE_MODE_B =  READ_FIRST" for instance <AW_11_S9.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.1>.
Entity <ram_2swsr_xfirst_gen_unisim.1> analyzed. Unit <ram_2swsr_xfirst_gen_unisim.1> generated.

Analyzing Entity <pdp11_mem70> in library <work> (Architecture <syn>).
Entity <pdp11_mem70> analyzed. Unit <pdp11_mem70> generated.

Analyzing generic Entity <ibd_ibmon> in library <work> (Architecture <syn>).
	AWIDTH = 9
	IB_ADDR = "1110000000000000"
Entity <ibd_ibmon> analyzed. Unit <ibd_ibmon> generated.

Analyzing Entity <ib_sres_or_3> in library <work> (Architecture <syn>).
Entity <ib_sres_or_3> analyzed. Unit <ib_sres_or_3> generated.

Analyzing generic Entity <pdp11_dmscnt> in library <work> (Architecture <syn>).
	RB_ADDR = "0000000001000000"
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_dmscnt.vhd" line 133: Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen'.
Entity <pdp11_dmscnt> analyzed. Unit <pdp11_dmscnt> generated.

Analyzing generic Entity <ram_2swsr_rfirst_gen.2> in library <work> (Architecture <syn>).
	AWIDTH = 9
	DWIDTH = 36
Entity <ram_2swsr_rfirst_gen.2> analyzed. Unit <ram_2swsr_rfirst_gen.2> generated.

Analyzing generic Entity <ram_2swsr_xfirst_gen_unisim.2> in library <work> (Architecture <syn>).
	AWIDTH = 9
	DWIDTH = 36
	WRITE_MODE = "READ_FIRST"
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_A =  000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_B =  000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "SRVAL_A =  000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "SRVAL_B =  000000000" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "WRITE_MODE_A =  READ_FIRST" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
    Set user-defined property "WRITE_MODE_B =  READ_FIRST" for instance <AW_09_S36.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim.2>.
Entity <ram_2swsr_xfirst_gen_unisim.2> analyzed. Unit <ram_2swsr_xfirst_gen_unisim.2> generated.

Analyzing generic Entity <pdp11_dmcmon> in library <work> (Architecture <syn>).
	AWIDTH = 8
	RB_ADDR = "0000000001001000"
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_dmcmon.vhd" line 377: Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'.
Entity <pdp11_dmcmon> analyzed. Unit <pdp11_dmcmon> generated.

Analyzing generic Entity <ram_1swar_1ar_gen.1> in library <work> (Architecture <syn>).
	AWIDTH = 4
	DWIDTH = 16
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[15].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[14].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[13].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[12].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[11].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[10].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[9].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[8].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[7].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[6].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[5].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[4].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[3].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[2].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[1].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[0].MEM> in unit <ram_1swar_1ar_gen.1>.
Entity <ram_1swar_1ar_gen.1> analyzed. Unit <ram_1swar_1ar_gen.1> generated.

Analyzing generic Entity <pdp11_dmhbpt> in library <work> (Architecture <syn>).
	NUNIT = 2
	RB_ADDR = "0000000001010000"
Entity <pdp11_dmhbpt> analyzed. Unit <pdp11_dmhbpt> generated.

Analyzing generic Entity <pdp11_dmhbpt_unit.1> in library <work> (Architecture <syn>).
	INDEX = 1
	RB_ADDR = "0000000001010000"
Entity <pdp11_dmhbpt_unit.1> analyzed. Unit <pdp11_dmhbpt_unit.1> generated.

Analyzing generic Entity <pdp11_dmhbpt_unit.2> in library <work> (Architecture <syn>).
	INDEX = 0
	RB_ADDR = "0000000001010000"
Entity <pdp11_dmhbpt_unit.2> analyzed. Unit <pdp11_dmhbpt_unit.2> generated.

Analyzing Entity <rb_sres_or_4> in library <work> (Architecture <syn>).
Entity <rb_sres_or_4> analyzed. Unit <rb_sres_or_4> generated.

Analyzing Entity <ibdr_maxisys> in library <work> (Architecture <syn>).
    Set property "fsm_encoding = one-hot" for unit <ibdr_rhrp>.
Entity <ibdr_maxisys> analyzed. Unit <ibdr_maxisys> generated.

Analyzing generic Entity <ibd_iist> in library <work> (Architecture <syn>).
	SID = "00"
Entity <ibd_iist> analyzed. Unit <ibd_iist> generated.

Analyzing Entity <ibd_kw11l> in library <work> (Architecture <syn>).
Entity <ibd_kw11l> analyzed. Unit <ibd_kw11l> generated.

Analyzing Entity <ibdr_rhrp> in library <work> (Architecture <syn>).
Entity <ibdr_rhrp> analyzed. Unit <ibdr_rhrp> generated.

Analyzing Entity <ibdr_rl11> in library <work> (Architecture <syn>).
Entity <ibdr_rl11> analyzed. Unit <ibdr_rl11> generated.

Analyzing generic Entity <ram_1swar_gen.2> in library <work> (Architecture <syn>).
	AWIDTH = 4
	DWIDTH = 8
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[7].MEM> in unit <ram_1swar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[6].MEM> in unit <ram_1swar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[5].MEM> in unit <ram_1swar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[4].MEM> in unit <ram_1swar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[3].MEM> in unit <ram_1swar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[2].MEM> in unit <ram_1swar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[1].MEM> in unit <ram_1swar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[0].MEM> in unit <ram_1swar_gen.2>.
Entity <ram_1swar_gen.2> analyzed. Unit <ram_1swar_gen.2> generated.

Analyzing Entity <ibdr_rk11> in library <work> (Architecture <syn>).
Entity <ibdr_rk11> analyzed. Unit <ibdr_rk11> generated.

Analyzing Entity <ibdr_tm11> in library <work> (Architecture <syn>).
Entity <ibdr_tm11> analyzed. Unit <ibdr_tm11> generated.

Analyzing generic Entity <ibdr_dl11.1> in library <work> (Architecture <syn>).
	IB_ADDR = "1111111101110000"
Entity <ibdr_dl11.1> analyzed. Unit <ibdr_dl11.1> generated.

Analyzing generic Entity <ibdr_dl11.2> in library <work> (Architecture <syn>).
	IB_ADDR = "1111110101000000"
Entity <ibdr_dl11.2> analyzed. Unit <ibdr_dl11.2> generated.

Analyzing Entity <ibdr_pc11> in library <work> (Architecture <syn>).
Entity <ibdr_pc11> analyzed. Unit <ibdr_pc11> generated.

Analyzing Entity <ibdr_lp11> in library <work> (Architecture <syn>).
Entity <ibdr_lp11> analyzed. Unit <ibdr_lp11> generated.

Analyzing Entity <ibdr_sdreg> in library <work> (Architecture <syn>).
Entity <ibdr_sdreg> analyzed. Unit <ibdr_sdreg> generated.

Analyzing generic Entity <ib_intmap> in library <work> (Architecture <syn>).
	INTMAP = ((vec => 176
	           pri => 6),
	          (vec => 64
	           pri => 6),
	          (vec => 172
	           pri => 5),
	          (vec => 112
	           pri => 5),
	          (vec => 144
	           pri => 5),
	          (vec => 148
	           pri => 5),
	          (vec => 200
	           pri => 5),
	          (vec => 204
	           pri => 5),
	          (vec => 48
	           pri => 4),
	          (vec => 52
	           pri => 4),
	          (vec => 192
	           pri => 4),
	          (vec => 196
	           pri => 4),
	          (vec => 56
	           pri => 4),
	          (vec => 60
	           pri => 4),
	          (vec => 128
	           pri => 4),
	          (vec => 0
	           pri => 0))
Entity <ib_intmap> analyzed. Unit <ib_intmap> generated.

Analyzing Entity <s3_sram_memctl> in library <work> (Architecture <syn>).
Entity <s3_sram_memctl> analyzed. Unit <s3_sram_memctl> generated.

Analyzing generic Entity <iob_reg_o_gen.1> in library <work> (Architecture <syn>).
	DWIDTH = 2
	INIT = '1'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.1> analyzed. Unit <iob_reg_o_gen.1> generated.

Analyzing generic Entity <iob_reg_o_gen.2> in library <work> (Architecture <syn>).
	DWIDTH = 4
	INIT = '1'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.2> analyzed. Unit <iob_reg_o_gen.2> generated.

Analyzing generic Entity <iob_reg_o_gen.3> in library <work> (Architecture <syn>).
	DWIDTH = 18
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.3> analyzed. Unit <iob_reg_o_gen.3> generated.

Analyzing generic Entity <iob_reg_io_gen> in library <work> (Architecture <syn>).
	DWIDTH = 32
	INITE = '0'
	INITI = '0'
	INITO = '0'
	PULL = "KEEP"
    Set user-defined property "IOB =  true" for signal <R_TE>.
    Set user-defined property "IOB =  true" for signal <R_DI>.
    Set user-defined property "IOB =  true" for signal <R_DO>.
WARNING:Xst:795 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_io_gen.vhd" line 73: Size of operands are different : result is <false>.
Entity <iob_reg_io_gen> analyzed. Unit <iob_reg_io_gen> generated.

Analyzing Entity <ioleds_sp1c> in library <work> (Architecture <syn>).
Entity <ioleds_sp1c> analyzed. Unit <ioleds_sp1c> generated.

Analyzing generic Entity <pdp11_hio70> in library <work> (Architecture <syn>).
	DCWIDTH = 2
	LWIDTH = 8
Entity <pdp11_hio70> analyzed. Unit <pdp11_hio70> generated.

Analyzing Entity <pdp11_statleds> in library <work> (Architecture <syn>).
Entity <pdp11_statleds> analyzed. Unit <pdp11_statleds> generated.

Analyzing generic Entity <pdp11_ledmux> in library <work> (Architecture <syn>).
	LWIDTH = 8
Entity <pdp11_ledmux> analyzed. Unit <pdp11_ledmux> generated.

Analyzing generic Entity <pdp11_dspmux> in library <work> (Architecture <syn>).
	DCWIDTH = 2
Entity <pdp11_dspmux> analyzed. Unit <pdp11_dspmux> generated.

Analyzing generic Entity <sn_humanio_rbus> in library <work> (Architecture <syn>).
	BWIDTH = 4
	DCWIDTH = 2
	DEBOUNCE = true
	LWIDTH = 8
	RB_ADDR = "1111111011110000"
	SWIDTH = 8
Entity <sn_humanio_rbus> analyzed. Unit <sn_humanio_rbus> generated.

Analyzing generic Entity <sn_humanio> in library <work> (Architecture <syn>).
	BWIDTH = 4
	DCWIDTH = 2
	DEBOUNCE = true
	LWIDTH = 8
	SWIDTH = 8
Entity <sn_humanio> analyzed. Unit <sn_humanio> generated.

Analyzing generic Entity <iob_reg_o_gen.5> in library <work> (Architecture <syn>).
	DWIDTH = 4
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.5> analyzed. Unit <iob_reg_o_gen.5> generated.

Analyzing generic Entity <iob_reg_o_gen.6> in library <work> (Architecture <syn>).
	DWIDTH = 8
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.6> analyzed. Unit <iob_reg_o_gen.6> generated.

Analyzing generic Entity <bp_swibtnled> in library <work> (Architecture <syn>).
	BWIDTH = 4
	DEBOUNCE = true
	LWIDTH = 8
	SWIDTH = 8
Entity <bp_swibtnled> analyzed. Unit <bp_swibtnled> generated.

Analyzing generic Entity <iob_reg_i_gen.3> in library <work> (Architecture <syn>).
	DWIDTH = 8
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DI>.
Entity <iob_reg_i_gen.3> analyzed. Unit <iob_reg_i_gen.3> generated.

Analyzing generic Entity <iob_reg_i_gen.4> in library <work> (Architecture <syn>).
	DWIDTH = 4
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DI>.
Entity <iob_reg_i_gen.4> analyzed. Unit <iob_reg_i_gen.4> generated.

Analyzing generic Entity <debounce_gen.1> in library <work> (Architecture <syn>).
	CEDIV = 3
	CWIDTH = 2
	DWIDTH = 8
Entity <debounce_gen.1> analyzed. Unit <debounce_gen.1> generated.

Analyzing generic Entity <debounce_gen.2> in library <work> (Architecture <syn>).
	CEDIV = 3
	CWIDTH = 2
	DWIDTH = 4
Entity <debounce_gen.2> analyzed. Unit <debounce_gen.2> generated.

Analyzing generic Entity <sn_7segctl> in library <work> (Architecture <syn>).
	CDWIDTH = 7
	DCWIDTH = 2
Entity <sn_7segctl> analyzed. Unit <sn_7segctl> generated.

Analyzing Entity <rb_sres_or_2> in library <work> (Architecture <syn>).
Entity <rb_sres_or_2> analyzed. Unit <rb_sres_or_2> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <clkdivce>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/genlib/clkdivce.vhd".
    Found 6-bit subtractor for signal <N_REGS.ucnt$addsub0000> created at line 96.
    Found 10-bit down counter for signal <R_REGS.mcnt>.
    Found 1-bit register for signal <R_REGS.msec>.
    Found 6-bit register for signal <R_REGS.ucnt>.
    Found 1-bit register for signal <R_REGS.usec>.
    Summary:
	inferred   1 Counter(s).
	inferred   8 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <clkdivce> synthesized.


Synthesizing Unit <ioleds_sp1c>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rlink/ioleds_sp1c.vhd".
WARNING:Xst:647 - Input <SER_MONI.rxovr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SER_MONI.abact> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SER_MONI.rxerr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SER_MONI.abdone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SER_MONI.abclkdiv_f> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SER_MONI.abclkdiv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <ioleds_sp1c> synthesized.


Synthesizing Unit <rb_sres_or_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rbus/rb_sres_or_2.vhd".
Unit <rb_sres_or_2> synthesized.


Synthesizing Unit <iob_reg_i_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_i_gen.vhd".
    Found 1-bit register for signal <R_DI<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <iob_reg_i_gen_1> synthesized.


Synthesizing Unit <iob_reg_o_gen_4>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 1-bit register for signal <R_DO<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <iob_reg_o_gen_4> synthesized.


Synthesizing Unit <iob_reg_i_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_i_gen.vhd".
    Found 1-bit register for signal <R_DI<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <iob_reg_i_gen_2> synthesized.


Synthesizing Unit <iob_reg_o_gen_7>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 1-bit register for signal <R_DO<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <iob_reg_o_gen_7> synthesized.


Synthesizing Unit <byte2cdata>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/comlib/byte2cdata.vhd".
    Found 9-bit register for signal <R_REGS.data>.
    Found 3-bit comparator equal for signal <R_REGS.data$cmp_eq0001> created at line 103.
    Found 1-bit register for signal <R_REGS.dataval>.
    Found 1-bit register for signal <R_REGS.edpend>.
    Summary:
	inferred  11 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <byte2cdata> synthesized.


Synthesizing Unit <cdata2byte>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/comlib/cdata2byte.vhd".
    Found 8-bit register for signal <R_REGS.data>.
    Found 1-bit register for signal <R_REGS.dataval>.
    Found 3-bit register for signal <R_REGS.ecode>.
    Found 1-bit register for signal <R_REGS.ecodeval>.
    Summary:
	inferred  13 D-type flip-flop(s).
Unit <cdata2byte> synthesized.


Synthesizing Unit <crc16>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/comlib/crc16.vhd".
    Found 16-bit register for signal <R_CRC>.
    Found 1-bit xor3 for signal <R_CRC$xor0000> created at line 246.
    Found 1-bit xor3 for signal <R_CRC$xor0001> created at line 245.
    Found 1-bit xor3 for signal <R_CRC$xor0002> created at line 244.
    Found 1-bit xor3 for signal <R_CRC$xor0003> created at line 243.
    Found 1-bit xor2 for signal <R_CRC$xor0004> created at line 242.
    Found 1-bit xor2 for signal <R_CRC$xor0005> created at line 241.
    Found 1-bit xor2 for signal <R_CRC$xor0006> created at line 240.
    Found 1-bit xor3 for signal <R_CRC$xor0007> created at line 239.
    Found 1-bit xor3 for signal <R_CRC$xor0008> created at line 237.
    Found 1-bit xor3 for signal <R_CRC$xor0009> created at line 236.
    Found 1-bit xor2 for signal <R_CRC$xor0010> created at line 235.
    Found 1-bit xor2 for signal <R_CRC$xor0011> created at line 228.
    Found 1-bit xor2 for signal <R_CRC$xor0012> created at line 233.
    Found 1-bit xor2 for signal <R_CRC$xor0013> created at line 232.
    Found 1-bit xor2 for signal <R_CRC$xor0014> created at line 231.
    Found 1-bit xor3 for signal <R_CRC$xor0015> created at line 230.
    Found 1-bit xor2 for signal <R_CRC$xor0016> created at line 246.
    Found 1-bit xor2 for signal <R_CRC$xor0017> created at line 246.
    Found 1-bit xor2 for signal <R_CRC$xor0018> created at line 245.
    Found 1-bit xor2 for signal <R_CRC$xor0019> created at line 245.
    Found 1-bit xor2 for signal <R_CRC$xor0020> created at line 244.
    Found 1-bit xor2 for signal <R_CRC$xor0021> created at line 244.
    Summary:
	inferred  16 D-type flip-flop(s).
	inferred   8 Xor(s).
Unit <crc16> synthesized.


Synthesizing Unit <rb_sel>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rbus/rb_sel.vhd".
WARNING:Xst:647 - Input <RB_MREQ.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.addr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <rb_sel> synthesized.


Synthesizing Unit <serport_xonrx>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_xonrx.vhd".
    Found 1-bit register for signal <R_REGS.escseen>.
    Found 8-bit register for signal <R_REGS.rxdata>.
    Found 1-bit register for signal <R_REGS.rxovr>.
    Found 1-bit register for signal <R_REGS.rxval>.
    Found 1-bit register for signal <R_REGS.txok>.
    Summary:
	inferred  12 D-type flip-flop(s).
Unit <serport_xonrx> synthesized.


Synthesizing Unit <serport_xontx>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_xontx.vhd".
    Found 1-bit register for signal <R_REGS.enaxon_1>.
    Found 1-bit register for signal <R_REGS.escpend>.
    Found 8-bit register for signal <R_REGS.ibuf>.
    Found 1-bit register for signal <R_REGS.ival>.
    Found 8-bit register for signal <R_REGS.obuf>.
    Found 1-bit xor2 for signal <R_REGS.obuf$xor0000> created at line 111.
    Found 1-bit register for signal <R_REGS.oval>.
    Found 1-bit register for signal <R_REGS.rxok>.
    Summary:
	inferred  21 D-type flip-flop(s).
Unit <serport_xontx> synthesized.


Synthesizing Unit <serport_uart_autobaud>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_uart_autobaud.vhd".
    Found finite state machine <FSM_0> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 4                                              |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | RESET                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 00                                             |
    | Power Up State     | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 16-bit adder for signal <N_REGS.ccnt$addsub0000> created at line 165.
    Found 16-bit register for signal <R_REGS.ccnt>.
    Found 7-bit up counter for signal <R_REGS.mcnt>.
    Found 1-bit register for signal <R_REGS.seen1>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  17 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <serport_uart_autobaud> synthesized.


Synthesizing Unit <serport_uart_rx>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_uart_rx.vhd".
    Found finite state machine <FSM_1> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 23                                             |
    | Inputs             | 4                                              |
    | Outputs            | 8                                              |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | RESET                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Power Up State     | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 14-bit comparator greater for signal <dbit$cmp_gt0000> created at line 153.
    Found 14-bit adder for signal <n.dcnt$add0000> created at line 290.
    Found 13-bit subtractor for signal <N_REGS.ccnt$addsub0000> created at line 282.
    Found 4-bit up counter for signal <R_REGS.bcnt>.
    Found 13-bit register for signal <R_REGS.ccnt>.
    Found 14-bit register for signal <R_REGS.dcnt>.
    Found 8-bit register for signal <R_REGS.sreg>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  35 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <serport_uart_rx> synthesized.


Synthesizing Unit <serport_uart_tx>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_uart_tx.vhd".
    Found 13-bit subtractor for signal <N_REGS.ccnt$addsub0000> created at line 126.
    Found 4-bit up counter for signal <R_REGS.bcnt>.
    Found 1-bit register for signal <R_REGS.busy>.
    Found 13-bit register for signal <R_REGS.ccnt>.
    Found 9-bit register for signal <R_REGS.sreg>.
    Summary:
	inferred   1 Counter(s).
	inferred  23 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <serport_uart_tx> synthesized.


Synthesizing Unit <pdp11_core_rbus>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_core_rbus.vhd".
WARNING:Xst:647 - Input <CP_STAT.cpuwait> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CP_STAT.cmdbusy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found finite state machine <FSM_2> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 22                                             |
    | Inputs             | 8                                              |
    | Outputs            | 4                                              |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | RESET                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 00                                             |
    | Power Up State     | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 21-bit adder for signal <n.addr$addsub0000> created at line 369.
    Found 21-bit register for signal <R_REGS.addr>.
    Found 5-bit register for signal <R_REGS.cpfunc>.
    Found 1-bit register for signal <R_REGS.cpreq>.
    Found 1-bit register for signal <R_REGS.cpuact_1>.
    Found 1-bit register for signal <R_REGS.doinc>.
    Found 1-bit register for signal <R_REGS.ena_22bit>.
    Found 1-bit register for signal <R_REGS.ena_ubmap>.
    Found 2-bit register for signal <R_REGS.membe>.
    Found 1-bit register for signal <R_REGS.membestick>.
    Found 1-bit register for signal <R_REGS.rbinit>.
    Found 1-bit register for signal <R_REGS.rbselc>.
    Found 1-bit register for signal <R_REGS.rbseli>.
    Found 1-bit register for signal <R_REGS.waitstep>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  38 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <pdp11_core_rbus> synthesized.


Synthesizing Unit <pdp11_mem70>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_mem70.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din<15:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_REGS.cr_distrap>.
    Found 1-bit register for signal <R_REGS.cr_disutrap>.
    Found 2-bit register for signal <R_REGS.cr_fmiss>.
    Found 2-bit register for signal <R_REGS.cr_frep>.
    Found 6-bit register for signal <R_REGS.hm_data>.
    Found 1-bit register for signal <R_REGS.ibsel_cr>.
    Found 1-bit register for signal <R_REGS.ibsel_hm>.
    Found 1-bit register for signal <R_REGS.ibsel_ls>.
    Found 1-bit register for signal <R_REGS.ibsel_nn>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <pdp11_mem70> synthesized.


Synthesizing Unit <ib_sres_or_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_sres_or_3.vhd".
Unit <ib_sres_or_3> synthesized.


Synthesizing Unit <rb_sres_or_4>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rbus/rb_sres_or_4.vhd".
Unit <rb_sres_or_4> synthesized.


Synthesizing Unit <pdp11_decode>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_decode.vhd".
    Found 8x4-bit ROM for signal <IREG_8_6$rom0000>.
    Found 4x8-bit ROM for signal <IREG_5_4$rom0000>.
    Found 4x2-bit ROM for signal <STAT.fork_srcr>.
    Found 4x4-bit ROM for signal <STAT.fork_opg$mux0001>.
    Found 1-bit 4-to-1 multiplexer for signal <nstat.is_res$mux0028>.
    Summary:
	inferred   4 ROM(s).
	inferred   1 Multiplexer(s).
Unit <pdp11_decode> synthesized.


Synthesizing Unit <pdp11_reg70>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_reg70.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din<15:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_REGS.ibsel_mbrk>.
    Found 1-bit register for signal <R_REGS.ibsel_sysid>.
    Found 8-bit register for signal <R_REGS.mbrk>.
    Summary:
	inferred  10 D-type flip-flop(s).
Unit <pdp11_reg70> synthesized.


Synthesizing Unit <ib_sres_or_4>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_sres_or_4.vhd".
Unit <ib_sres_or_4> synthesized.


Synthesizing Unit <ib_sres_or_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_sres_or_2.vhd".
Unit <ib_sres_or_2> synthesized.


Synthesizing Unit <ib_sel_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_sel.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_1> synthesized.


Synthesizing Unit <ib_sel_4>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_sel.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_4> synthesized.


Synthesizing Unit <ib_sel_5>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_sel.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_5> synthesized.


Synthesizing Unit <ib_sel_8>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_sel.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_8> synthesized.


Synthesizing Unit <ib_sel_9>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_sel.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_9> synthesized.


Synthesizing Unit <ib_sel_6>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_sel.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.addr<6:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_6> synthesized.


Synthesizing Unit <pdp11_ounit>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_ounit.vhd".
    Found 16-bit 4-to-1 multiplexer for signal <mb$mux0000> created at line 85.
    Found 16-bit addsub for signal <sum$mux0000> created at line 95.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  16 Multiplexer(s).
Unit <pdp11_ounit> synthesized.


Synthesizing Unit <pdp11_aunit>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_aunit.vhd".
    Found 1-bit xor2 for signal <CCOUT_1$xor0000> created at line 195.
    Found 1-bit xor2 for signal <CCOUT_1$xor0001> created at line 195.
    Found 1-bit xor2 for signal <CCOUT_1$xor0002> created at line 200.
    Found 1-bit 4-to-1 multiplexer for signal <mci$mux0000> created at line 138.
    Found 16-bit 4-to-1 multiplexer for signal <mdst$mux0000> created at line 130.
    Found 16-bit 4-to-1 multiplexer for signal <msrc$mux0000> created at line 122.
    Found 8-bit adder carry in/out for signal <tmp$addsub0000> created at line 113.
    Found 8-bit adder carry in/out for signal <tmp0$addsub0000> created at line 113.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  33 Multiplexer(s).
Unit <pdp11_aunit> synthesized.


Synthesizing Unit <pdp11_lunit>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_lunit.vhd".
WARNING:Xst:647 - Input <CCIN<2:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit xor2 for signal <CCOUT_1$xor0000> created at line 100.
    Found 1-bit xor2 for signal <CCOUT_1$xor0001> created at line 105.
    Found 1-bit xor2 for signal <CCOUT_1$xor0002> created at line 110.
    Found 1-bit xor2 for signal <CCOUT_1$xor0003> created at line 141.
    Found 1-bit xor2 for signal <CCOUT_1$xor0004> created at line 146.
    Found 1-bit xor2 for signal <iout_0$xor0000> created at line 199.
    Found 1-bit xor2 for signal <iout_1$xor0000> created at line 199.
    Found 1-bit 8-to-1 multiplexer for signal <iout_10$mux0001> created at line 137.
    Found 1-bit xor2 for signal <iout_10$xor0000> created at line 199.
    Found 1-bit xor2 for signal <iout_11$xor0000> created at line 199.
    Found 1-bit xor2 for signal <iout_12$xor0000> created at line 199.
    Found 1-bit xor2 for signal <iout_13$xor0000> created at line 199.
    Found 1-bit xor2 for signal <iout_14$xor0000> created at line 199.
    Found 1-bit xor2 for signal <iout_15$xor0000> created at line 199.
    Found 1-bit xor2 for signal <iout_2$xor0000> created at line 199.
    Found 1-bit xor2 for signal <iout_3$xor0000> created at line 199.
    Found 1-bit xor2 for signal <iout_4$xor0000> created at line 199.
    Found 1-bit xor2 for signal <iout_5$xor0000> created at line 199.
    Found 1-bit xor2 for signal <iout_6$xor0000> created at line 199.
    Found 1-bit xor2 for signal <iout_7$xor0000> created at line 199.
    Found 1-bit xor2 for signal <iout_8$xor0000> created at line 199.
    Found 1-bit xor2 for signal <iout_9$xor0000> created at line 199.
    Summary:
	inferred   1 Multiplexer(s).
Unit <pdp11_lunit> synthesized.


Synthesizing Unit <pdp11_munit>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_munit.vhd".
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <omux_sel$mux0000> of Case statement line 415 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
   	- add an 'INIT' attribute on signal <omux_sel$mux0000> (optimization is then done without any risk)
   	- use the attribute 'signal_encoding user' to avoid onehot optimization
   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Using one-hot encoding for signal <omux_sel$mux0000>.
    Found 4-bit 4-to-1 multiplexer for signal <CCOUT>.
    Found 16-bit comparator greatequal for signal <dd_ge$cmp_ge0000> created at line 257.
    Found 16-bit addsub for signal <dd_h_new$mux0000> created at line 245.
    Found 16-bit comparator lessequal for signal <dd_le$cmp_le0000> created at line 252.
    Found 1-bit xor2 for signal <DIV_CQ$xor0000> created at line 341.
    Found 1-bit xor2 for signal <DIV_CR$xor0000> created at line 339.
    Found 1-bit xor2 for signal <div_ovfl$xor0000> created at line 293.
    Found 16-bit comparator greater for signal <DTMP_POS$cmp_gt0000> created at line 160.
    Found 4-bit 4-to-1 multiplexer for signal <omux_sel$mux0000> created at line 395.
    Found 16x16-bit multiplier for signal <prod$mult0000> created at line 393.
    Found 1-bit xor2 for signal <qbit$xor0000> created at line 270.
    Found 1-bit xor2 for signal <qbit$xor0001> created at line 273.
    Found 1-bit register for signal <R_ASH_C>.
    Found 1-bit register for signal <R_ASH_V>.
    Found 1-bit xor2 for signal <R_ASH_V$xor0000> created at line 365.
    Found 1-bit register for signal <R_C1>.
    Found 16-bit register for signal <R_DD_L>.
    Found 1-bit register for signal <R_DDO_LT>.
    Found 1-bit register for signal <R_DIV_V>.
    Found 1-bit register for signal <R_MAXFIX>.
    Found 1-bit register for signal <R_MSBO>.
    Found 1-bit register for signal <R_QO_LT>.
    Found 1-bit xor2 for signal <R_QO_LT$xor0000> created at line 286.
    Found 6-bit register for signal <R_SHC>.
    Found 6-bit addsub for signal <R_SHC$addsub0000>.
    Summary:
	inferred  30 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Multiplier(s).
	inferred   3 Comparator(s).
	inferred   8 Multiplexer(s).
Unit <pdp11_munit> synthesized.


Synthesizing Unit <ib_sel_7>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_sel.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_7> synthesized.


Synthesizing Unit <ib_sel_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_sel.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_2> synthesized.


Synthesizing Unit <ib_sel_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_sel.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_3> synthesized.


Synthesizing Unit <pdp11_dmhbpt_unit_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_dmhbpt_unit.vhd".
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.err_mmu> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.aval> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.cancel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmaddr<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.fail> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.cpustep> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.be> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.pc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmdin> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dsrc_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE.snum> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.pri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ireg_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibsres.busy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.cmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emsres.ack_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.req> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.tflag> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emsres.ack_w> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dres> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.pmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.err_nxm> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_mode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emsres.dout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.err> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.trap_ysv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ireg> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ddst_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.suspext> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.addr<15:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.cpugo> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.rset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.ack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.cpususp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dtmp_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE.idone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.cc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_adst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.err_iobto> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmcntl.bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dsrc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE.vfetch> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.suspint> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibsres.dout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dtmp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.trap_mmu> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmcntl.kstack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.err_rsv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.cpdout_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmdout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ddst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmcntl.macc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmcntl.intrsv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibsres.ack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmcntl.trap_done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.err_odd> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 2-bit comparator equal for signal <N_REGS.dwseen$cmp_eq0000> created at line 227.
    Found 15-bit comparator greatequal for signal <N_REGS.dwseen$cmp_ge0000> created at line 227.
    Found 15-bit comparator lessequal for signal <N_REGS.dwseen$cmp_le0000> created at line 227.
    Found 1-bit register for signal <R_REGS.drena>.
    Found 1-bit register for signal <R_REGS.drseen>.
    Found 1-bit register for signal <R_REGS.dwena>.
    Found 1-bit register for signal <R_REGS.dwseen>.
    Found 15-bit register for signal <R_REGS.hilim>.
    Found 1-bit register for signal <R_REGS.irena>.
    Found 1-bit register for signal <R_REGS.irseen>.
    Found 15-bit register for signal <R_REGS.lolim>.
    Found 2-bit register for signal <R_REGS.mode>.
    Found 1-bit register for signal <R_REGS.rbsel>.
    Summary:
	inferred  39 D-type flip-flop(s).
	inferred   3 Comparator(s).
Unit <pdp11_dmhbpt_unit_1> synthesized.


Synthesizing Unit <pdp11_dmhbpt_unit_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_dmhbpt_unit.vhd".
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.err_mmu> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.aval> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.cancel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmaddr<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.fail> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.cpustep> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.be> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.pc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmdin> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dsrc_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE.snum> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.pri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ireg_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibsres.busy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.cmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emsres.ack_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.req> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.tflag> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emsres.ack_w> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dres> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.pmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.err_nxm> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_mode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emsres.dout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.err> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.trap_ysv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ireg> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ddst_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.suspext> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.addr<15:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.cpugo> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.rset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.ack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.cpususp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dtmp_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE.idone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.cc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_adst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.err_iobto> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmcntl.bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dsrc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE.vfetch> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.suspint> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibsres.dout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dtmp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.trap_mmu> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmcntl.kstack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.err_rsv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.cpdout_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmdout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ddst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmcntl.macc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmcntl.intrsv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibsres.ack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmcntl.trap_done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.err_odd> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 2-bit comparator equal for signal <N_REGS.dwseen$cmp_eq0000> created at line 227.
    Found 15-bit comparator greatequal for signal <N_REGS.dwseen$cmp_ge0000> created at line 227.
    Found 15-bit comparator lessequal for signal <N_REGS.dwseen$cmp_le0000> created at line 227.
    Found 1-bit register for signal <R_REGS.drena>.
    Found 1-bit register for signal <R_REGS.drseen>.
    Found 1-bit register for signal <R_REGS.dwena>.
    Found 1-bit register for signal <R_REGS.dwseen>.
    Found 15-bit register for signal <R_REGS.hilim>.
    Found 1-bit register for signal <R_REGS.irena>.
    Found 1-bit register for signal <R_REGS.irseen>.
    Found 15-bit register for signal <R_REGS.lolim>.
    Found 2-bit register for signal <R_REGS.mode>.
    Found 1-bit register for signal <R_REGS.rbsel>.
    Summary:
	inferred  39 D-type flip-flop(s).
	inferred   3 Comparator(s).
Unit <pdp11_dmhbpt_unit_2> synthesized.


Synthesizing Unit <ibd_iist>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibd_iist.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EI_ACK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Using one-hot encoding for signal <R_REGS.state>.
    Found 1-bit 4-to-1 multiplexer for signal <eff_bus<0>.bmask$mux0001> created at line 603.
    Found 1-bit 4-to-1 multiplexer for signal <eff_bus<0>.imask$mux0001> created at line 602.
    Found 1-bit 4-to-1 multiplexer for signal <eff_bus<1>.bmask$mux0001> created at line 603.
    Found 1-bit 4-to-1 multiplexer for signal <eff_bus<1>.imask$mux0001> created at line 602.
    Found 1-bit 4-to-1 multiplexer for signal <eff_bus<2>.bmask$mux0001> created at line 603.
    Found 1-bit 4-to-1 multiplexer for signal <eff_bus<2>.imask$mux0001> created at line 602.
    Found 1-bit 4-to-1 multiplexer for signal <eff_bus<3>.bmask$mux0001> created at line 603.
    Found 1-bit 4-to-1 multiplexer for signal <eff_bus<3>.imask$mux0001> created at line 602.
    Found 1-bit xor10 for signal <n.exc_rte_3$xor0000> created at line 614.
    Found 1-bit xor10 for signal <n.exc_ui_1$xor0000> created at line 614.
    Found 1-bit xor10 for signal <n.exc_ui_2$xor0000> created at line 614.
    Found 1-bit xor10 for signal <n.pgf_pbf_0$xor0000> created at line 614.
    Found 8-bit adder for signal <N_REGS.tcnt256$add0000> created at line 284.
    Found 8-bit adder for signal <N_REGS.tcntsnd$addsub0000> created at line 291.
    Found 4-bit up counter for signal <R_REGS.acr_ac>.
    Found 4-bit comparator greater for signal <R_REGS.acr_ac$cmp_gt0000> created at line 561.
    Found 4-bit register for signal <R_REGS.dcf_brk>.
    Found 4-bit register for signal <R_REGS.dcf_dcf>.
    Found 4-bit register for signal <R_REGS.exc_rte>.
    Found 4-bit register for signal <R_REGS.exc_ui>.
    Found 1-bit register for signal <R_REGS.ibsel>.
    Found 4-bit register for signal <R_REGS.msk_bm>.
    Found 4-bit register for signal <R_REGS.msk_im>.
    Found 1-bit register for signal <R_REGS.mtc_dsbt>.
    Found 1-bit register for signal <R_REGS.mtc_dsdrv>.
    Found 1-bit register for signal <R_REGS.mtc_enmlp>.
    Found 1-bit register for signal <R_REGS.mtc_enmxd>.
    Found 1-bit register for signal <R_REGS.mtc_mfrm>.
    Found 2-bit register for signal <R_REGS.mtc_mid>.
    Found 1-bit register for signal <R_REGS.mtc_mttp>.
    Found 1-bit register for signal <R_REGS.pgc_grj>.
    Found 1-bit register for signal <R_REGS.pgc_ie>.
    Found 1-bit register for signal <R_REGS.pgc_pgrmr>.
    Found 1-bit register for signal <R_REGS.pgc_ptp>.
    Found 1-bit register for signal <R_REGS.pgc_strmr>.
    Found 4-bit register for signal <R_REGS.pge_pbe>.
    Found 4-bit register for signal <R_REGS.pge_pie>.
    Found 4-bit register for signal <R_REGS.pgf_pbf>.
    Found 4-bit register for signal <R_REGS.pgf_pif>.
    Found 1-bit register for signal <R_REGS.req_boot>.
    Found 1-bit register for signal <R_REGS.req_clear>.
    Found 1-bit register for signal <R_REGS.req_lock>.
    Found 1-bit register for signal <R_REGS.req_pgsnd>.
    Found 1-bit register for signal <R_REGS.req_stsnd>.
    Found 4-bit register for signal <R_REGS.state>.
    Found 8-bit down counter for signal <R_REGS.stc_count>.
    Found 1-bit register for signal <R_REGS.stc_enb>.
    Found 1-bit register for signal <R_REGS.stc_lke>.
    Found 1-bit register for signal <R_REGS.stc_stp>.
    Found 1-bit register for signal <R_REGS.stc_tmo>.
    Found 4-bit register for signal <R_REGS.ste_sbe>.
    Found 4-bit register for signal <R_REGS.ste_sie>.
    Found 4-bit register for signal <R_REGS.stf_sbf>.
    Found 4-bit register for signal <R_REGS.stf_sif>.
    Found 8-bit register for signal <R_REGS.tcnt256>.
    Found 8-bit register for signal <R_REGS.tcntsnd>.
    Summary:
	inferred   2 Counter(s).
	inferred  99 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Comparator(s).
	inferred   8 Multiplexer(s).
	inferred   4 Xor(s).
Unit <ibd_iist> synthesized.


Synthesizing Unit <ibd_kw11l>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibd_kw11l.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din<15:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din<5:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 5-bit adder for signal <N_REGS.tcnt$addsub0000> created at line 148.
    Found 1-bit register for signal <R_REGS.ibsel>.
    Found 1-bit register for signal <R_REGS.ie>.
    Found 1-bit register for signal <R_REGS.intreq>.
    Found 1-bit register for signal <R_REGS.moni>.
    Found 5-bit register for signal <R_REGS.tcnt>.
    Summary:
	inferred   9 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <ibd_kw11l> synthesized.


Synthesizing Unit <ibdr_tm11>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_tm11.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 3-bit comparator lessequal for signal <N_REGS.ibsel$cmp_le0000> created at line 217.
    Found 1-bit 4-to-1 multiplexer for signal <r.sreof$mux0000> created at line 238.
    Found 1-bit 4-to-1 multiplexer for signal <r.sreot$mux0000> created at line 239.
    Found 15-bit register for signal <R_REGS.ba>.
    Found 16-bit register for signal <R_REGS.bc>.
    Found 2-bit register for signal <R_REGS.crden>.
    Found 2-bit register for signal <R_REGS.crea>.
    Found 3-bit register for signal <R_REGS.crfunc>.
    Found 1-bit register for signal <R_REGS.crie>.
    Found 1-bit register for signal <R_REGS.crpevn>.
    Found 1-bit register for signal <R_REGS.crrdy>.
    Found 2-bit register for signal <R_REGS.crunit>.
    Found 1-bit register for signal <R_REGS.crunit2>.
    Found 1-bit register for signal <R_REGS.ibsel>.
    Found 1-bit register for signal <R_REGS.ireq>.
    Found 1-bit register for signal <R_REGS.resreq>.
    Found 2-bit register for signal <R_REGS.runit>.
    Found 4-bit register for signal <R_REGS.srbot>.
    Found 1-bit register for signal <R_REGS.srbte>.
    Found 4-bit register for signal <R_REGS.sreof>.
    Found 4-bit register for signal <R_REGS.sreot>.
    Found 1-bit register for signal <R_REGS.sricmd>.
    Found 1-bit register for signal <R_REGS.srnxm>.
    Found 4-bit register for signal <R_REGS.sronl>.
    Found 1-bit register for signal <R_REGS.srpae>.
    Found 4-bit register for signal <R_REGS.srrew>.
    Found 1-bit register for signal <R_REGS.srrle>.
    Found 4-bit register for signal <R_REGS.srwrl>.
    Summary:
	inferred  78 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   2 Multiplexer(s).
Unit <ibdr_tm11> synthesized.


Synthesizing Unit <ibdr_dl11_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_dl11.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din<15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din<11:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 10-bit subtractor for signal <N_REGS.rdlycnt$addsub0000> created at line 315.
    Found 1-bit register for signal <R_REGS.ibsel>.
    Found 8-bit register for signal <R_REGS.rbuf>.
    Found 1-bit register for signal <R_REGS.rdlybsy>.
    Found 10-bit register for signal <R_REGS.rdlycnt>.
    Found 1-bit register for signal <R_REGS.rdone>.
    Found 1-bit register for signal <R_REGS.rie>.
    Found 1-bit register for signal <R_REGS.rintreq>.
    Found 3-bit register for signal <R_REGS.rrlim>.
    Found 1-bit register for signal <R_REGS.rval>.
    Found 8-bit register for signal <R_REGS.xbuf>.
    Found 1-bit register for signal <R_REGS.xie>.
    Found 1-bit register for signal <R_REGS.xintreq>.
    Found 1-bit register for signal <R_REGS.xmaint>.
    Found 1-bit register for signal <R_REGS.xrdy>.
    Summary:
	inferred  39 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <ibdr_dl11_1> synthesized.


Synthesizing Unit <ibdr_dl11_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_dl11.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din<15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din<11:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 10-bit subtractor for signal <N_REGS.rdlycnt$addsub0000> created at line 315.
    Found 1-bit register for signal <R_REGS.ibsel>.
    Found 8-bit register for signal <R_REGS.rbuf>.
    Found 1-bit register for signal <R_REGS.rdlybsy>.
    Found 10-bit register for signal <R_REGS.rdlycnt>.
    Found 1-bit register for signal <R_REGS.rdone>.
    Found 1-bit register for signal <R_REGS.rie>.
    Found 1-bit register for signal <R_REGS.rintreq>.
    Found 3-bit register for signal <R_REGS.rrlim>.
    Found 1-bit register for signal <R_REGS.rval>.
    Found 8-bit register for signal <R_REGS.xbuf>.
    Found 1-bit register for signal <R_REGS.xie>.
    Found 1-bit register for signal <R_REGS.xintreq>.
    Found 1-bit register for signal <R_REGS.xmaint>.
    Found 1-bit register for signal <R_REGS.xrdy>.
    Summary:
	inferred  39 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <ibdr_dl11_2> synthesized.


Synthesizing Unit <ibdr_pc11>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_pc11.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din<14:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_REGS.ibsel>.
    Found 8-bit register for signal <R_REGS.pbuf>.
    Found 1-bit register for signal <R_REGS.perr>.
    Found 1-bit register for signal <R_REGS.pie>.
    Found 1-bit register for signal <R_REGS.pintreq>.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS.pintreq$mux0001> created at line 165.
    Found 1-bit register for signal <R_REGS.prdy>.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS.prdy$mux0001> created at line 165.
    Found 8-bit register for signal <R_REGS.rbuf>.
    Found 8-bit 4-to-1 multiplexer for signal <R_REGS.rbuf$mux0001> created at line 165.
    Found 1-bit register for signal <R_REGS.rbusy>.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS.rbusy$mux0001> created at line 165.
    Found 1-bit register for signal <R_REGS.rdone>.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS.rdone$mux0001> created at line 165.
    Found 1-bit register for signal <R_REGS.rerr>.
    Found 1-bit register for signal <R_REGS.rie>.
    Found 1-bit register for signal <R_REGS.rintreq>.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS.rintreq$mux0001> created at line 165.
    Summary:
	inferred  26 D-type flip-flop(s).
	inferred  13 Multiplexer(s).
Unit <ibdr_pc11> synthesized.


Synthesizing Unit <ibdr_lp11>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_lp11.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.din<14:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 7-bit register for signal <R_REGS.buf>.
    Found 1-bit register for signal <R_REGS.done>.
    Found 1-bit register for signal <R_REGS.err>.
    Found 1-bit register for signal <R_REGS.ibsel>.
    Found 1-bit register for signal <R_REGS.ie>.
    Found 1-bit register for signal <R_REGS.intreq>.
    Summary:
	inferred  12 D-type flip-flop(s).
Unit <ibdr_lp11> synthesized.


Synthesizing Unit <ibdr_sdreg>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_sdreg.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16-bit register for signal <R_REGS.dreg>.
    Found 1-bit register for signal <R_REGS.ibsel>.
    Found 16-bit register for signal <R_REGS.sreg>.
    Summary:
	inferred  33 D-type flip-flop(s).
Unit <ibdr_sdreg> synthesized.


Synthesizing Unit <ib_intmap>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ib_intmap.vhd".
    Found 16x3-bit ROM for signal <EI_PRI$rom0000> created at line 126.
    Found 16x9-bit ROM for signal <EI_VECT$rom0000> created at line 126.
    Summary:
	inferred   2 ROM(s).
Unit <ib_intmap> synthesized.


Synthesizing Unit <iob_reg_o_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 2-bit register for signal <R_DO>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <iob_reg_o_gen_1> synthesized.


Synthesizing Unit <iob_reg_o_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 4-bit register for signal <R_DO>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <iob_reg_o_gen_2> synthesized.


Synthesizing Unit <iob_reg_o_gen_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 18-bit register for signal <R_DO>.
    Summary:
	inferred  18 D-type flip-flop(s).
Unit <iob_reg_o_gen_3> synthesized.


Synthesizing Unit <iob_reg_io_gen>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_io_gen.vhd".
    Found 32-bit tristate buffer for signal <PAD>.
    Found 32-bit register for signal <R_DI>.
    Found 32-bit register for signal <R_DO>.
    Found 1-bit register for signal <R_TE>.
    Summary:
	inferred  65 D-type flip-flop(s).
	inferred  32 Tristate(s).
Unit <iob_reg_io_gen> synthesized.


Synthesizing Unit <pdp11_statleds>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_statleds.vhd".
WARNING:Xst:647 - Input <CP_STAT.cpustep> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CP_STAT.cmderr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.pc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CP_STAT.cmdack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dsrc_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ireg_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.tflag> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dres> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.pmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_mode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CP_STAT.suspext> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ireg> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ddst_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CP_STAT.cpususp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.rset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dtmp_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.cc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_adst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dsrc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CP_STAT.suspint> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dtmp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.cpdout_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ddst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CP_STAT.cmdmerr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <pdp11_statleds> synthesized.


Synthesizing Unit <pdp11_ledmux>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_ledmux.vhd".
WARNING:Xst:647 - Input <DM_STAT_DP.pc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dsrc_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.pri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ireg_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.cmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.tflag> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dres> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.pmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_mode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ireg> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ddst_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.rset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dtmp_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.cc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_adst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dsrc<15:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dsrc<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dtmp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.cpdout_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ddst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <pdp11_ledmux> synthesized.


Synthesizing Unit <pdp11_dspmux>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_dspmux.vhd".
WARNING:Xst:647 - Input <DM_STAT_DP.dsrc_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.pri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ireg_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.cmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.tflag> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dres> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.pmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_mode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ireg> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ddst_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.rset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dtmp_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.cc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_adst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dtmp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.cpdout_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ddst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16-bit 4-to-1 multiplexer for signal <DSP_DAT>.
    Summary:
	inferred  16 Multiplexer(s).
Unit <pdp11_dspmux> synthesized.


Synthesizing Unit <iob_reg_o_gen_5>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 4-bit register for signal <R_DO>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <iob_reg_o_gen_5> synthesized.


Synthesizing Unit <iob_reg_o_gen_6>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 8-bit register for signal <R_DO>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <iob_reg_o_gen_6> synthesized.


Synthesizing Unit <sn_7segctl>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/bpgen/sn_7segctl.vhd".
    Found 16x7-bit ROM for signal <SEG_N$rom0000> created at line 154.
    Found 1-bit 4-to-1 multiplexer for signal <CDP>.
    Found 4-bit 4-to-1 multiplexer for signal <CHEX>.
    Found 7-bit down counter for signal <R_REGS.cdiv>.
    Found 2-bit up counter for signal <R_REGS.dcnt>.
    Summary:
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred   5 Multiplexer(s).
Unit <sn_7segctl> synthesized.


Synthesizing Unit <iob_reg_i_gen_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_i_gen.vhd".
    Found 8-bit register for signal <R_DI>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <iob_reg_i_gen_3> synthesized.


Synthesizing Unit <iob_reg_i_gen_4>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_i_gen.vhd".
    Found 4-bit register for signal <R_DI>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <iob_reg_i_gen_4> synthesized.


Synthesizing Unit <debounce_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/genlib/debounce_gen.vhd".
    Found 1-bit xor2 for signal <n.dchange_0$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_1$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_2$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_3$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_4$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_5$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_6$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_7$xor0000> created at line 104.
    Found 2-bit down counter for signal <R_REGS.cecnt>.
    Found 8-bit register for signal <R_REGS.dchange>.
    Found 8-bit register for signal <R_REGS.dout>.
    Found 8-bit register for signal <R_REGS.dref>.
    Summary:
	inferred   1 Counter(s).
	inferred  24 D-type flip-flop(s).
Unit <debounce_gen_1> synthesized.


Synthesizing Unit <debounce_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/genlib/debounce_gen.vhd".
    Found 1-bit xor2 for signal <n.dchange_0$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_1$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_2$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_3$xor0000> created at line 104.
    Found 2-bit down counter for signal <R_REGS.cecnt>.
    Found 4-bit register for signal <R_REGS.dchange>.
    Found 4-bit register for signal <R_REGS.dout>.
    Found 4-bit register for signal <R_REGS.dref>.
    Summary:
	inferred   1 Counter(s).
	inferred  12 D-type flip-flop(s).
Unit <debounce_gen_2> synthesized.


Synthesizing Unit <pdp11_hio70>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_hio70.vhd".
Unit <pdp11_hio70> synthesized.


Synthesizing Unit <iob_reg_i_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_i.vhd".
Unit <iob_reg_i_1> synthesized.


Synthesizing Unit <iob_reg_o_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_o.vhd".
Unit <iob_reg_o_1> synthesized.


Synthesizing Unit <iob_reg_i_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_i.vhd".
Unit <iob_reg_i_2> synthesized.


Synthesizing Unit <iob_reg_o_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/xlib/iob_reg_o.vhd".
Unit <iob_reg_o_2> synthesized.


Synthesizing Unit <ram_2swsr_xfirst_gen_unisim_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd".
Unit <ram_2swsr_xfirst_gen_unisim_3> synthesized.


Synthesizing Unit <ram_1swar_1ar_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swar_1ar_gen_unisim.vhd".
Unit <ram_1swar_1ar_gen_2> synthesized.


Synthesizing Unit <serport_uart_rxtx>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_uart_rxtx.vhd".
Unit <serport_uart_rxtx> synthesized.


Synthesizing Unit <ram_1swsr_xfirst_gen_unisim>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd".
Unit <ram_1swsr_xfirst_gen_unisim> synthesized.


Synthesizing Unit <pdp11_dmhbpt>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_dmhbpt.vhd".
Unit <pdp11_dmhbpt> synthesized.


Synthesizing Unit <pdp11_sequencer>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_sequencer.vhd".
WARNING:Xst:647 - Input <IREG<14:11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <R_VMSTAT.trap_ysv> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <R_VMSTAT.trap_mmu> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <R_VMSTAT.ack> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <R_IDSTAT.is_res> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <R_IDSTAT.fork_srcr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <R_IDSTAT.fork_op> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <R_IDSTAT.force_srcsp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <R_IDSTAT.do_pref_dec> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <R_IDSTAT.do_fork_srcr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <R_IDSTAT.do_fork_opg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <R_IDSTAT.do_fork_op> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <R_IDSTAT.do_fork_dsta> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found finite state machine <FSM_3> for signal <R_STATE>.
    -----------------------------------------------------------------------
    | States             | 113                                            |
    | Transitions        | 611                                            |
    | Inputs             | 109                                            |
    | Outputs            | 130                                            |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | GRESET                    (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | s_idle                                         |
    | Power Up State     | s_idle                                         |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 16x226-bit ROM for signal <R_IDSTAT.fork_opg$rom0000>.
    Found 4x113-bit ROM for signal <nstate57$mux0000> created at line 510.
    Found 4x113-bit ROM for signal <nstate$mux0072>.
    Found 1-bit 8-to-1 multiplexer for signal <brcond$mux0000> created at line 1621.
    Found 1-bit xor2 for signal <brcond$xor0000> created at line 1627.
    Found 3-bit comparator equal for signal <DP_CNTL.ddst_we$cmp_eq0000> created at line 1061.
    Found 1-bit xor2 for signal <DP_CNTL.gpr_pcinc$xor0000> created at line 1643.
    Found 113-bit 4-to-1 multiplexer for signal <nstate$mux0022> created at line 1037.
    Found 1-bit register for signal <R_CPUERR.adderr>.
    Found 1-bit register for signal <R_CPUERR.illhlt>.
    Found 1-bit register for signal <R_CPUERR.iobto>.
    Found 1-bit register for signal <R_CPUERR.nxm>.
    Found 1-bit register for signal <R_CPUERR.rsv>.
    Found 1-bit register for signal <R_CPUERR.ysv>.
    Found 1-bit register for signal <R_IDSTAT.aunit_cc1op>.
    Found 3-bit register for signal <R_IDSTAT.aunit_ccmode>.
    Found 2-bit register for signal <R_IDSTAT.aunit_cimod>.
    Found 2-bit register for signal <R_IDSTAT.aunit_dstmod>.
    Found 2-bit register for signal <R_IDSTAT.aunit_srcmod>.
    Found 1-bit register for signal <R_IDSTAT.do_fork_dstr>.
    Found 2-bit register for signal <R_IDSTAT.fork_dsta>.
    Found 2-bit register for signal <R_IDSTAT.fork_dstr>.
    Found 3-bit register for signal <R_IDSTAT.fork_opa>.
    Found 4-bit register for signal <R_IDSTAT.fork_opg>.
    Found 1-bit register for signal <R_IDSTAT.is_bytop>.
    Found 1-bit register for signal <R_IDSTAT.is_dstmode0>.
    Found 1-bit register for signal <R_IDSTAT.is_dstpc>.
    Found 1-bit register for signal <R_IDSTAT.is_dstw_pc>.
    Found 1-bit register for signal <R_IDSTAT.is_dstw_reg>.
    Found 1-bit register for signal <R_IDSTAT.is_rmwop>.
    Found 1-bit register for signal <R_IDSTAT.is_srcpc>.
    Found 1-bit register for signal <R_IDSTAT.is_srcpcmode1>.
    Found 4-bit register for signal <R_IDSTAT.lunit_func>.
    Found 2-bit register for signal <R_IDSTAT.munit_func>.
    Found 1-bit register for signal <R_IDSTAT.op_mov>.
    Found 1-bit register for signal <R_IDSTAT.op_rtt>.
    Found 3-bit register for signal <R_IDSTAT.res_sel>.
    Found 3-bit register for signal <R_IDSTAT.trap_vec>.
    Found 1-bit register for signal <R_IDSTAT.updt_dstadsrc>.
    Found 3-bit comparator greater for signal <R_STATE$cmp_gt0000> created at line 509.
    Found 1-bit register for signal <R_STATUS.breset>.
    Found 1-bit register for signal <R_STATUS.cmdack>.
    Found 1-bit register for signal <R_STATUS.cmdbusy>.
    Found 1-bit register for signal <R_STATUS.cmderr>.
    Found 1-bit register for signal <R_STATUS.cmdmerr>.
    Found 5-bit register for signal <R_STATUS.cpfunc>.
    Found 3-bit register for signal <R_STATUS.cprnum>.
    Found 1-bit register for signal <R_STATUS.cpugo>.
    Found 4-bit register for signal <R_STATUS.cpurust>.
    Found 1-bit register for signal <R_STATUS.cpustep>.
    Found 1-bit register for signal <R_STATUS.cpususp>.
    Found 1-bit register for signal <R_STATUS.cpuwait>.
    Found 1-bit register for signal <R_STATUS.creset>.
    Found 1-bit register for signal <R_STATUS.do_gprwe>.
    Found 1-bit register for signal <R_STATUS.do_intrsv>.
    Found 1-bit register for signal <R_STATUS.intack>.
    Found 7-bit register for signal <R_STATUS.intvect>.
    Found 1-bit register for signal <R_STATUS.itimer>.
    Found 1-bit register for signal <R_STATUS.prefdone>.
    Found 1-bit register for signal <R_STATUS.suspext>.
    Found 1-bit register for signal <R_STATUS.suspint>.
    Found 1-bit register for signal <R_STATUS.trap_mmu>.
    Found 1-bit register for signal <R_STATUS.trap_ysv>.
    Found 1-bit register for signal <R_STATUS.waitsusp>.
    Found 1-bit register for signal <R_VMSTAT.err>.
    Found 1-bit register for signal <R_VMSTAT.err_iobto>.
    Found 1-bit register for signal <R_VMSTAT.err_mmu>.
    Found 1-bit register for signal <R_VMSTAT.err_nxm>.
    Found 1-bit register for signal <R_VMSTAT.err_odd>.
    Found 1-bit register for signal <R_VMSTAT.err_rsv>.
    Found 1-bit register for signal <R_VMSTAT.fail>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   3 ROM(s).
	inferred  97 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred 114 Multiplexer(s).
Unit <pdp11_sequencer> synthesized.


Synthesizing Unit <pdp11_irq>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_irq.vhd".
    Found 7-bit register for signal <R_PIRQ>.
    Found 3-bit comparator greater for signal <VECT$cmp_gt0000> created at line 129.
    Summary:
	inferred   7 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <pdp11_irq> synthesized.


Synthesizing Unit <pdp11_mmu_ssr12>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_mmu_ssr12.vhd".
WARNING:Xst:647 - Input <MONI.idone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MONI.trace_prev> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 5-bit register for signal <R_SSR1.ra_delta>.
    Found 5-bit addsub for signal <R_SSR1.ra_delta$addsub0000>.
    Found 3-bit register for signal <R_SSR1.ra_num>.
    Found 5-bit register for signal <R_SSR1.rb_delta>.
    Found 5-bit addsub for signal <R_SSR1.rb_delta$addsub0000>.
    Found 3-bit register for signal <R_SSR1.rb_num>.
    Found 16-bit register for signal <R_SSR2>.
    Found 3-bit comparator not equal for signal <use_rb$cmp_ne0000> created at line 142.
    Summary:
	inferred  32 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <pdp11_mmu_ssr12> synthesized.


Synthesizing Unit <ram_1swar_gen_5>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swar_gen_unisim.vhd".
Unit <ram_1swar_gen_5> synthesized.


Synthesizing Unit <ram_1swar_gen_6>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swar_gen_unisim.vhd".
Unit <ram_1swar_gen_6> synthesized.


Synthesizing Unit <ram_1swar_gen_7>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swar_gen_unisim.vhd".
Unit <ram_1swar_gen_7> synthesized.


Synthesizing Unit <ram_1swar_gen_8>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swar_gen_unisim.vhd".
Unit <ram_1swar_gen_8> synthesized.


Synthesizing Unit <ram_1swar_gen_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swar_gen_unisim.vhd".
Unit <ram_1swar_gen_3> synthesized.


Synthesizing Unit <ram_1swar_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swar_gen_unisim.vhd".
Unit <ram_1swar_gen_1> synthesized.


Synthesizing Unit <ram_1swar_gen_4>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swar_gen_unisim.vhd".
Unit <ram_1swar_gen_4> synthesized.


Synthesizing Unit <pdp11_psr>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_psr.vhd".
WARNING:Xst:647 - Input <DIN<10:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 4-bit register for signal <R_PSW.cc>.
    Found 2-bit register for signal <R_PSW.cmode>.
    Found 2-bit register for signal <R_PSW.pmode>.
    Found 3-bit register for signal <R_PSW.pri>.
    Found 1-bit register for signal <R_PSW.rset>.
    Found 1-bit register for signal <R_PSW.tflag>.
    Summary:
	inferred  13 D-type flip-flop(s).
Unit <pdp11_psr> synthesized.


Synthesizing Unit <ram_1swar_1ar_gen_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swar_1ar_gen_unisim.vhd".
Unit <ram_1swar_1ar_gen_3> synthesized.


Synthesizing Unit <ram_2swsr_xfirst_gen_unisim_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd".
Unit <ram_2swsr_xfirst_gen_unisim_1> synthesized.


Synthesizing Unit <ram_2swsr_xfirst_gen_unisim_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd".
Unit <ram_2swsr_xfirst_gen_unisim_2> synthesized.


Synthesizing Unit <ram_1swar_1ar_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swar_1ar_gen_unisim.vhd".
Unit <ram_1swar_1ar_gen_1> synthesized.


Synthesizing Unit <ram_1swar_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swar_gen_unisim.vhd".
Unit <ram_1swar_gen_2> synthesized.


Synthesizing Unit <bp_swibtnled>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/bpgen/bp_swibtnled.vhd".
Unit <bp_swibtnled> synthesized.


Synthesizing Unit <s3_sram_memctl>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/s3board/s3_sram_memctl.vhd".
    Found finite state machine <FSM_4> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 12                                             |
    | Inputs             | 2                                              |
    | Outputs            | 10                                             |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | RESET                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Power Up State     | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <R_REGS.ackr>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 D-type flip-flop(s).
Unit <s3_sram_memctl> synthesized.


Synthesizing Unit <bp_rs232_2line_iob>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/bpgen/bp_rs232_2line_iob.vhd".
Unit <bp_rs232_2line_iob> synthesized.


Synthesizing Unit <bp_rs232_4line_iob>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/bpgen/bp_rs232_4line_iob.vhd".
Unit <bp_rs232_4line_iob> synthesized.


Synthesizing Unit <ram_2swsr_rfirst_gen_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd".
Unit <ram_2swsr_rfirst_gen_3> synthesized.


Synthesizing Unit <fifo_1c_dram_raw>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/fifo_1c_dram_raw.vhd".
    Found 1-bit register for signal <R_REGS.empty>.
    Found 1-bit register for signal <R_REGS.full>.
    Found 5-bit up counter for signal <R_REGS.raddr>.
    Found 5-bit up counter for signal <R_REGS.waddr>.
    Found 5-bit subtractor for signal <SIZE$sub0000> created at line 120.
    Summary:
	inferred   2 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <fifo_1c_dram_raw> synthesized.


Synthesizing Unit <serport_uart_rxtx_ab>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_uart_rxtx_ab.vhd".
Unit <serport_uart_rxtx_ab> synthesized.


Synthesizing Unit <ram_1swsr_wfirst_gen>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd".
Unit <ram_1swsr_wfirst_gen> synthesized.


Synthesizing Unit <pdp11_ubmap>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_ubmap.vhd".
    Found 21-bit adder for signal <ADDR_PM>.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <pdp11_ubmap> synthesized.


Synthesizing Unit <pdp11_mmu_sadr>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_mmu_sadr.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_IBSEL_AR>.
    Found 1-bit register for signal <R_IBSEL_DR>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <pdp11_mmu_sadr> synthesized.


Synthesizing Unit <pdp11_gpr>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_gpr.vhd".
    Found 16-bit register for signal <R_PC>.
    Found 15-bit adder for signal <R_PC_15_1$add0000> created at line 151.
    Summary:
	inferred  16 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <pdp11_gpr> synthesized.


Synthesizing Unit <ram_2swsr_rfirst_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd".
Unit <ram_2swsr_rfirst_gen_1> synthesized.


Synthesizing Unit <ram_2swsr_rfirst_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd".
Unit <ram_2swsr_rfirst_gen_2> synthesized.


Synthesizing Unit <ibdr_rhrp>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_rhrp.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found finite state machine <FSM_5> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 22                                             |
    | Transitions        | 215                                            |
    | Inputs             | 56                                             |
    | Outputs            | 27                                             |
    | Clock              | CLK                       (rising_edge)        |
    | Power Up State     | 00000                                          |
    | Encoding           | one-hot                                        |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <R_REGS.clrmode>.
    Using one-hot encoding for signal <R_REGS.omux>.
    Found 32x1-bit ROM for signal <imbreg$mux0000> created at line 610.
    Found 2-bit comparator not equal for signal <idout_7$cmp_ne0000> created at line 1224.
    Found 10-bit comparator greater for signal <n.er1iae_2$cmp_gt0000> created at line 1136.
    Found 6-bit comparator greater for signal <n.er1iae_2$cmp_gt0001> created at line 1144.
    Found 5-bit comparator greater for signal <n.er1iae_2$cmp_gt0002> created at line 1144.
    Found 5-bit comparator lessequal for signal <N_REGS.ibsel$cmp_le0000> created at line 533.
    Found 1-bit 4-to-1 multiplexer for signal <r.dsdpr$mux0000> created at line 600.
    Found 1-bit 4-to-1 multiplexer for signal <r.dserp$mux0000> created at line 1029.
    Found 1-bit 4-to-1 multiplexer for signal <r.dsmol$mux0000> created at line 1068.
    Found 1-bit 4-to-1 multiplexer for signal <r.dsmol$mux0001> created at line 1216.
    Found 1-bit 4-to-1 multiplexer for signal <r.dspip$mux0000> created at line 770.
    Found 1-bit 4-to-1 multiplexer for signal <r.dspip$mux0001> created at line 1215.
    Found 1-bit 4-to-1 multiplexer for signal <r.dswrl$mux0000> created at line 1113.
    Found 1-bit 4-to-1 multiplexer for signal <r.dte0$mux0000> created at line 556.
    Found 1-bit 4-to-1 multiplexer for signal <r.dte1$mux0000> created at line 555.
    Found 1-bit 4-to-1 multiplexer for signal <r.dtrm$mux0000> created at line 554.
    Found 1-bit 4-to-1 multiplexer for signal <r.dtrm$mux0001> created at line 606.
    Found 1-bit 4-to-1 multiplexer for signal <r.er1iae$mux0000> created at line 1152.
    Found 1-bit 4-to-1 multiplexer for signal <r.er1wle$mux0000> created at line 1152.
    Found 5-bit register for signal <R_REGS.amap>.
    Found 6-bit register for signal <R_REGS.bae>.
    Found 10-bit register for signal <R_REGS.camax>.
    Found 1-bit register for signal <R_REGS.cerm>.
    Found 4-bit register for signal <R_REGS.clrmode>.
    Found 3-bit register for signal <R_REGS.clrreg>.
    Found 3-bit adder for signal <R_REGS.clrreg$addsub0000> created at line 1379.
    Found 1-bit register for signal <R_REGS.cs1ie>.
    Found 1-bit register for signal <R_REGS.cs1rdy>.
    Found 1-bit register for signal <R_REGS.cs1sc>.
    Found 1-bit register for signal <R_REGS.cs1tre>.
    Found 1-bit register for signal <R_REGS.cs2bai>.
    Found 1-bit register for signal <R_REGS.cs2mxf>.
    Found 1-bit register for signal <R_REGS.cs2ned>.
    Found 1-bit register for signal <R_REGS.cs2nem>.
    Found 1-bit register for signal <R_REGS.cs2pat>.
    Found 1-bit register for signal <R_REGS.cs2pge>.
    Found 2-bit register for signal <R_REGS.cs2unit>.
    Found 1-bit register for signal <R_REGS.cs2unit2>.
    Found 1-bit register for signal <R_REGS.cs2wce>.
    Found 1-bit register for signal <R_REGS.cs3wco>.
    Found 16-bit register for signal <R_REGS.dinmsk>.
    Found 4-bit register for signal <R_REGS.dsata>.
    Found 4-bit register for signal <R_REGS.dsdpr>.
    Found 4-bit register for signal <R_REGS.dserp>.
    Found 4-bit register for signal <R_REGS.dslbt>.
    Found 4-bit register for signal <R_REGS.dsmol>.
    Found 4-bit register for signal <R_REGS.dsom>.
    Found 4-bit register for signal <R_REGS.dspip>.
    Found 4-bit register for signal <R_REGS.dsvv>.
    Found 4-bit register for signal <R_REGS.dswrl>.
    Found 4-bit register for signal <R_REGS.dte0>.
    Found 4-bit register for signal <R_REGS.dte1>.
    Found 4-bit register for signal <R_REGS.dtrm>.
    Found 6-bit register for signal <R_REGS.dtyp>.
    Found 4-bit register for signal <R_REGS.er1aoe>.
    Found 4-bit register for signal <R_REGS.er1iae>.
    Found 4-bit register for signal <R_REGS.er1ilf>.
    Found 4-bit register for signal <R_REGS.er1rmr>.
    Found 4-bit register for signal <R_REGS.er1uns>.
    Found 4-bit register for signal <R_REGS.er1wle>.
    Found 2-bit register for signal <R_REGS.eunit>.
    Found 2-bit adder for signal <R_REGS.eunit$addsub0000> created at line 1387.
    Found 5-bit register for signal <R_REGS.ffunc>.
    Found 2-bit register for signal <R_REGS.funit>.
    Found 1-bit register for signal <R_REGS.fxfer>.
    Found 1-bit register for signal <R_REGS.ibsel>.
    Found 8-bit register for signal <R_REGS.idlycnt>.
    Found 8-bit subtractor for signal <R_REGS.idlycnt$addsub0000> created at line 805.
    Found 8-bit register for signal <R_REGS.idlyval>.
    Found 1-bit register for signal <R_REGS.ireq>.
    Found 1-bit register for signal <R_REGS.ned>.
    Found 12-bit register for signal <R_REGS.omux>.
    Found 1-bit register for signal <R_REGS.packdone>.
    Found 1-bit register for signal <R_REGS.poredone>.
    Found 2-bit register for signal <R_REGS.runit>.
    Found 6-bit register for signal <R_REGS.samax>.
    Found 6-bit up counter for signal <R_REGS.sc>.
    Found 6-bit comparator greatequal for signal <R_REGS.sc$cmp_ge0000> created at line 1425.
    Found 1-bit register for signal <R_REGS.seardone>.
    Found 1-bit register for signal <R_REGS.seekdone>.
    Found 2-bit comparator equal for signal <R_REGS.state$cmp_eq0022> created at line 770.
    Found 5-bit comparator greatequal for signal <R_REGS.state$cmp_ge0000> created at line 1023.
    Found 5-bit register for signal <R_REGS.tamax>.
    Found 7-bit up counter for signal <R_REGS.uscnt>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred 196 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   8 Comparator(s).
	inferred  13 Multiplexer(s).
Unit <ibdr_rhrp> synthesized.


Synthesizing Unit <ibdr_rl11>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_rl11.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CE_MSEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <R_REGS.crdone> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found finite state machine <FSM_6> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 25                                             |
    | Inputs             | 17                                             |
    | Outputs            | 10                                             |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | BRESET                    (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 1000                                           |
    | Power Up State     | 1000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <idout$mux0002> created at line 339.
    Found 2-bit register for signal <R_REGS.csbae>.
    Found 1-bit register for signal <R_REGS.cscrdy>.
    Found 1-bit register for signal <R_REGS.csde>.
    Found 1-bit register for signal <R_REGS.csdrdy>.
    Found 2-bit register for signal <R_REGS.csds>.
    Found 4-bit register for signal <R_REGS.cse>.
    Found 1-bit register for signal <R_REGS.cserr>.
    Found 3-bit register for signal <R_REGS.csfunc>.
    Found 1-bit register for signal <R_REGS.csie>.
    Found 16-bit register for signal <R_REGS.da>.
    Found 1-bit register for signal <R_REGS.gshs>.
    Found 4-bit up counter for signal <R_REGS.iaddr>.
    Found 1-bit register for signal <R_REGS.ibsel>.
    Found 1-bit register for signal <R_REGS.ireq>.
    Found 3-bit register for signal <R_REGS.mploc>.
    Found 5-bit register for signal <R_REGS.mprem>.
    Found 5-bit 4-to-1 multiplexer for signal <R_REGS.mprem$mux0001> created at line 339.
    Found 9-bit register for signal <R_REGS.seekcac>.
    Found 10-bit register for signal <R_REGS.seekcan>.
    Found 10-bit addsub for signal <R_REGS.seekcan$mux0001>.
    Found 1-bit register for signal <R_REGS.seekdt>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  63 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred  21 Multiplexer(s).
Unit <ibdr_rl11> synthesized.


Synthesizing Unit <ibdr_rk11>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_rk11.vhd".
WARNING:Xst:647 - Input <IB_MREQ.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Using one-hot encoding for signal <$n0001>.
    Found 3-bit 1-of-5 priority encoder for internal node.
    Found 4-bit comparator equal for signal <idout_4$cmp_eq0001> created at line 303.
    Found 1-bit 8-to-1 multiplexer for signal <r.sbusy$mux0000> created at line 311.
    Found 1-bit register for signal <R_REGS.crdone>.
    Found 1-bit register for signal <R_REGS.creset>.
    Found 1-bit register for signal <R_REGS.cse>.
    Found 3-bit register for signal <R_REGS.drsel>.
    Found 1-bit register for signal <R_REGS.fireq>.
    Found 1-bit register for signal <R_REGS.he>.
    Found 1-bit register for signal <R_REGS.ibsel>.
    Found 3-bit up counter for signal <R_REGS.icnt>.
    Found 3-bit register for signal <R_REGS.id>.
    Found 1-bit register for signal <R_REGS.ide>.
    Found 1-bit register for signal <R_REGS.maint>.
    Found 1-bit register for signal <R_REGS.rdy>.
    Found 3-bit register for signal <R_REGS.rid>.
    Found 8-bit register for signal <R_REGS.sbusy>.
    Found 4-bit up counter for signal <R_REGS.sc>.
    Found 1-bit register for signal <R_REGS.scp>.
    Found 8-bit register for signal <R_REGS.sireq>.
    Found 1-bit register for signal <R_REGS.state<0>>.
    Found 1-bit register for signal <R_REGS.wce>.
    Summary:
	inferred   2 Counter(s).
	inferred  37 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   1 Multiplexer(s).
	inferred   3 Priority encoder(s).
Unit <ibdr_rk11> synthesized.


Synthesizing Unit <sn_humanio>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/bpgen/sn_humanio.vhd".
Unit <sn_humanio> synthesized.


Synthesizing Unit <bp_rs232_2l4l_iob>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/bpgen/bp_rs232_2l4l_iob.vhd".
    Found 1-bit register for signal <R_CTS_N>.
    Found 1-bit register for signal <R_RTS1_N>.
    Found 1-bit register for signal <R_RXD>.
    Found 1-bit register for signal <R_TXD0>.
    Found 1-bit register for signal <R_TXD1>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <bp_rs232_2l4l_iob> synthesized.


Synthesizing Unit <ibdr_maxisys>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibdr_maxisys.vhd".
WARNING:Xst:653 - Signal <RB_LAM_DZ11> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <RB_LAM_DENUA> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <IIST_SRES.ack_lock> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <IIST_SRES.ack_boot> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <IIST_MREQ.lock> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <IIST_MREQ.boot> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <IB_SRES_KW11P.dout> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <IB_SRES_KW11P.busy> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <IB_SRES_KW11P.ack> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <IB_SRES_DZ11.dout> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <IB_SRES_DZ11.busy> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <IB_SRES_DZ11.ack> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <IB_SRES_DEUNA.dout> is used but never assigned. This sourceless signal will be automatically connected to value 0000000000000000.
WARNING:Xst:653 - Signal <IB_SRES_DEUNA.busy> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <IB_SRES_DEUNA.ack> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:1780 - Signal <EI_REQ_KW11P> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <EI_REQ_DZ11TX> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:653 - Signal <EI_REQ_DZ11RX> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:1780 - Signal <EI_REQ_DEUNA> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <EI_ACK_KW11P> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <EI_ACK_DZ11TX> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <EI_ACK_DZ11RX> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <EI_ACK_DEUNA> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <ibdr_maxisys> synthesized.


Synthesizing Unit <sn_humanio_rbus>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../bplib/bpgen/sn_humanio_rbus.vhd".
WARNING:Xst:647 - Input <RB_MREQ.init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 4-bit register for signal <R_REGS.btn>.
    Found 4-bit register for signal <R_REGS.btneff>.
    Found 16-bit register for signal <R_REGS.dateff>.
    Found 1-bit register for signal <R_REGS.dp_en>.
    Found 4-bit register for signal <R_REGS.dpeff>.
    Found 1-bit register for signal <R_REGS.dsp0_en>.
    Found 1-bit register for signal <R_REGS.dsp1_en>.
    Found 16-bit register for signal <R_REGS.dsp_dat>.
    Found 16-bit 8-to-1 multiplexer for signal <R_REGS.dsp_dat$mux0001> created at line 284.
    Found 4-bit register for signal <R_REGS.dsp_dp>.
    Found 8-bit register for signal <R_REGS.led>.
    Found 1-bit register for signal <R_REGS.led_en>.
    Found 8-bit register for signal <R_REGS.ledeff>.
    Found 8-bit register for signal <R_REGS.ledin>.
    Found 1-bit register for signal <R_REGS.rbsel>.
    Found 8-bit register for signal <R_REGS.swi>.
    Found 1-bit register for signal <R_REGS.swi_en>.
    Found 8-bit register for signal <R_REGS.swieff>.
    Summary:
	inferred  94 D-type flip-flop(s).
	inferred  16 Multiplexer(s).
Unit <sn_humanio_rbus> synthesized.


Synthesizing Unit <rbd_rbmon>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rbus/rbd_rbmon.vhd".
    Found 14-bit adder for signal <N_REGS.rbndly$addsub0000> created at line 409.
    Found 1-bit register for signal <R_REGS.go>.
    Found 16-bit register for signal <R_REGS.hilim>.
    Found 9-bit register for signal <R_REGS.laddr>.
    Found 9-bit adder for signal <R_REGS.laddr$addsub0000> created at line 419.
    Found 16-bit register for signal <R_REGS.lolim>.
    Found 1-bit register for signal <R_REGS.rback>.
    Found 16-bit register for signal <R_REGS.rbaddr>.
    Found 1-bit register for signal <R_REGS.rbburst>.
    Found 1-bit register for signal <R_REGS.rbbusy>.
    Found 16-bit register for signal <R_REGS.rbdata>.
    Found 1-bit register for signal <R_REGS.rberr>.
    Found 1-bit register for signal <R_REGS.rbinit>.
    Found 1-bit register for signal <R_REGS.rbnak>.
    Found 10-bit up counter for signal <R_REGS.rbnbusy>.
    Found 14-bit register for signal <R_REGS.rbndly>.
    Found 1-bit register for signal <R_REGS.rbsel>.
    Found 1-bit register for signal <R_REGS.rbtake_1>.
    Found 1-bit register for signal <R_REGS.rbtout>.
    Found 1-bit register for signal <R_REGS.rbwe>.
    Found 2-bit register for signal <R_REGS.waddr>.
    Found 2-bit adder for signal <R_REGS.waddr$addsub0000> created at line 316.
    Found 1-bit register for signal <R_REGS.wena>.
    Found 1-bit register for signal <R_REGS.wrap>.
    Found 16-bit comparator greatequal for signal <rbtake$cmp_ge0000> created at line 362.
    Found 16-bit comparator lessequal for signal <rbtake$cmp_le0000> created at line 362.
    Summary:
	inferred   1 Counter(s).
	inferred 102 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   2 Comparator(s).
Unit <rbd_rbmon> synthesized.


Synthesizing Unit <fifo_1c_dram>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/memlib/fifo_1c_dram.vhd".
Unit <fifo_1c_dram> synthesized.


Synthesizing Unit <pdp11_cache>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_cache.vhd".
    Found finite state machine <FSM_7> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 16                                             |
    | Inputs             | 8                                              |
    | Outputs            | 4                                              |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | GRESET                    (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 00                                             |
    | Power Up State     | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 16-bit 4-to-1 multiplexer for signal <EM_SRES.dout>.
    Found 9-bit comparator equal for signal <itagok$cmp_eq0000> created at line 292.
    Found 4-bit comparator equal for signal <ivalok$cmp_eq0000> created at line 296.
    Found 11-bit register for signal <R_REGS.addr_l>.
    Found 9-bit register for signal <R_REGS.addr_t>.
    Found 1-bit register for signal <R_REGS.addr_w>.
    Found 4-bit register for signal <R_REGS.be>.
    Found 16-bit register for signal <R_REGS.di>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  41 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred  16 Multiplexer(s).
Unit <pdp11_cache> synthesized.


Synthesizing Unit <ibd_ibmon>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../ibus/ibd_ibmon.vhd".
    Found 12-bit comparator greatequal for signal <ibtake$cmp_ge0000> created at line 384.
    Found 12-bit comparator lessequal for signal <ibtake$cmp_le0000> created at line 384.
    Found 14-bit adder for signal <N_REGS.ibndly$addsub0000> created at line 432.
    Found 1-bit register for signal <R_REGS.conena>.
    Found 1-bit register for signal <R_REGS.go>.
    Found 12-bit register for signal <R_REGS.hilim>.
    Found 1-bit register for signal <R_REGS.iback>.
    Found 12-bit register for signal <R_REGS.ibaddr>.
    Found 1-bit register for signal <R_REGS.ibbe0>.
    Found 1-bit register for signal <R_REGS.ibbe1>.
    Found 1-bit register for signal <R_REGS.ibburst>.
    Found 1-bit register for signal <R_REGS.ibbusy>.
    Found 1-bit register for signal <R_REGS.ibcacc>.
    Found 16-bit register for signal <R_REGS.ibdata>.
    Found 1-bit register for signal <R_REGS.ibnak>.
    Found 10-bit up counter for signal <R_REGS.ibnbusy>.
    Found 14-bit register for signal <R_REGS.ibndly>.
    Found 1-bit register for signal <R_REGS.ibracc>.
    Found 1-bit register for signal <R_REGS.ibrmw>.
    Found 1-bit register for signal <R_REGS.ibsel>.
    Found 1-bit register for signal <R_REGS.ibtake_1>.
    Found 1-bit register for signal <R_REGS.ibtout>.
    Found 1-bit register for signal <R_REGS.ibwe>.
    Found 9-bit register for signal <R_REGS.laddr>.
    Found 9-bit adder for signal <R_REGS.laddr$addsub0000> created at line 442.
    Found 1-bit register for signal <R_REGS.locena>.
    Found 12-bit register for signal <R_REGS.lolim>.
    Found 1-bit register for signal <R_REGS.remena>.
    Found 2-bit register for signal <R_REGS.waddr>.
    Found 2-bit adder for signal <R_REGS.waddr$addsub0000> created at line 333.
    Found 1-bit register for signal <R_REGS.wena>.
    Found 1-bit register for signal <R_REGS.wrap>.
    Summary:
	inferred   1 Counter(s).
	inferred  96 D-type flip-flop(s).
	inferred   3 Adder/Subtractor(s).
	inferred   2 Comparator(s).
Unit <ibd_ibmon> synthesized.


Synthesizing Unit <pdp11_dmscnt>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_dmscnt.vhd".
WARNING:Xst:647 - Input <DM_STAT_SE.istart> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.cpustep> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.pc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dsrc_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.pri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ireg_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.din<15:11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.tflag> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dres> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.pmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_mode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ireg> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ddst_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.suspext> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.cpugo> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.rset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.cpususp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dtmp_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE.idone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.psw.cc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_adst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dsrc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE.vfetch> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.suspint> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dtmp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.cpdout_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.ddst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found finite state machine <FSM_8> for signal <R_REGS.waddr>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 18                                             |
    | Inputs             | 6                                              |
    | Outputs            | 3                                              |
    | Clock              | CLK                       (rising_edge)        |
    | Clock enable       | R_REGS.waddr$and0000      (positive)           |
    | Reset              | RESET                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 00                                             |
    | Power Up State     | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 9-bit comparator equal for signal <CMEM_CEA$cmp_eq0000> created at line 308.
    Found 36-bit adder for signal <CMEM_DIB>.
    Found 1-bit register for signal <R_REGS.clr>.
    Found 1-bit register for signal <R_REGS.ena0>.
    Found 1-bit register for signal <R_REGS.ena1>.
    Found 9-bit register for signal <R_REGS.laddr>.
    Found 9-bit adder for signal <R_REGS.laddr$share0000>.
    Found 20-bit register for signal <R_REGS.mbuf>.
    Found 1-bit register for signal <R_REGS.rbsel>.
    Found 1-bit register for signal <R_REGS.same>.
    Found 36-bit register for signal <R_REGS.scnt>.
    Found 9-bit register for signal <R_REGS.snum0>.
    Found 9-bit register for signal <R_REGS.snum1>.
    Found 1-bit register for signal <R_REGS.state<0>>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  89 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <pdp11_dmscnt> synthesized.


Synthesizing Unit <pdp11_dmcmon>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_dmcmon.vhd".
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.aval> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.cancel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmstat.fail> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.be> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.pc<0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibsres.busy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emsres.ack_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.req> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.din<15:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emsres.ack_w> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_mode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emsres.dout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.suspext> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.addr<15:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.emmreq.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.gpr_adst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmcntl.mode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO.suspint> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibsres.dout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP.dtmp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibmreq.addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmcntl.kstack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmcntl.intrsv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.ibsres.ack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM.vmcntl.trap_done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_REGS.active>.
    Found 8-bit up counter for signal <R_REGS.cnum>.
    Found 1-bit register for signal <R_REGS.dp_ddst_we>.
    Found 16-bit register for signal <R_REGS.dp_dres>.
    Found 1-bit register for signal <R_REGS.dp_dres_val>.
    Found 1-bit register for signal <R_REGS.dp_dsrc_we>.
    Found 16-bit register for signal <R_REGS.dp_ireg>.
    Found 1-bit register for signal <R_REGS.dp_ireg_we>.
    Found 1-bit register for signal <R_REGS.dp_ireg_we_1>.
    Found 15-bit register for signal <R_REGS.dp_pc_dec>.
    Found 15-bit register for signal <R_REGS.dp_pc_fet>.
    Found 1-bit register for signal <R_REGS.go>.
    Found 1-bit register for signal <R_REGS.imode>.
    Found 8-bit register for signal <R_REGS.laddr>.
    Found 8-bit adder for signal <R_REGS.laddr$addsub0000> created at line 695.
    Found 4-bit up counter for signal <R_REGS.mal_raddr>.
    Found 4-bit up counter for signal <R_REGS.mal_waddr>.
    Found 1-bit register for signal <R_REGS.mwdrop>.
    Found 1-bit register for signal <R_REGS.mwsup>.
    Found 1-bit register for signal <R_REGS.rbsel>.
    Found 1-bit register for signal <R_REGS.se_idone>.
    Found 1-bit register for signal <R_REGS.se_istart>.
    Found 1-bit register for signal <R_REGS.se_istart_1>.
    Found 8-bit register for signal <R_REGS.se_snum>.
    Found 1-bit register for signal <R_REGS.se_vfetch>.
    Found 1-bit register for signal <R_REGS.vm_ack>.
    Found 16-bit register for signal <R_REGS.vm_addr>.
    Found 16-bit register for signal <R_REGS.vm_addr_1>.
    Found 1-bit register for signal <R_REGS.vm_bytop>.
    Found 1-bit register for signal <R_REGS.vm_bytop_1>.
    Found 1-bit register for signal <R_REGS.vm_cacc>.
    Found 1-bit register for signal <R_REGS.vm_cacc_1>.
    Found 16-bit register for signal <R_REGS.vm_din>.
    Found 16-bit register for signal <R_REGS.vm_dout>.
    Found 16-bit register for signal <R_REGS.vm_dout_1>.
    Found 1-bit register for signal <R_REGS.vm_dspace>.
    Found 1-bit register for signal <R_REGS.vm_dspace_1>.
    Found 1-bit register for signal <R_REGS.vm_err>.
    Found 1-bit register for signal <R_REGS.vm_err_iobto>.
    Found 1-bit register for signal <R_REGS.vm_err_mmu>.
    Found 1-bit register for signal <R_REGS.vm_err_nxm>.
    Found 1-bit register for signal <R_REGS.vm_err_odd>.
    Found 1-bit register for signal <R_REGS.vm_err_rsv>.
    Found 1-bit register for signal <R_REGS.vm_macc>.
    Found 1-bit register for signal <R_REGS.vm_macc_1>.
    Found 1-bit register for signal <R_REGS.vm_pend>.
    Found 1-bit register for signal <R_REGS.vm_req>.
    Found 1-bit register for signal <R_REGS.vm_trap_mmu>.
    Found 1-bit register for signal <R_REGS.vm_trap_ysv>.
    Found 1-bit register for signal <R_REGS.vm_wacc>.
    Found 1-bit register for signal <R_REGS.vm_wacc_1>.
    Found 4-bit register for signal <R_REGS.waddr>.
    Found 4-bit adder for signal <R_REGS.waddr$addsub0000> created at line 507.
    Found 4-bit 8-to-1 multiplexer for signal <R_REGS.waddr$mux0001> created at line 469.
    Found 1-bit register for signal <R_REGS.wena>.
    Found 1-bit register for signal <R_REGS.wrap>.
    Summary:
	inferred   3 Counter(s).
	inferred 200 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   4 Multiplexer(s).
Unit <pdp11_dmcmon> synthesized.


Synthesizing Unit <pdp11_dpath>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_dpath.vhd".
    Found 16-bit 4-to-1 multiplexer for signal <VM_ADDR>.
    Found 4-bit 8-to-1 multiplexer for signal <CCOUT>.
    Found 16-bit 8-to-1 multiplexer for signal <DRES>.
    Found 16-bit register for signal <R_CPDOUT>.
    Found 16-bit register for signal <R_DDST>.
    Found 16-bit register for signal <R_DSRC>.
    Found 16-bit register for signal <R_DTMP>.
    Found 1-bit 4-to-1 multiplexer for signal <R_DTMP_0$mux0001> created at line 269.
    Found 1-bit 4-to-1 multiplexer for signal <R_DTMP_1$mux0001> created at line 269.
    Found 1-bit 4-to-1 multiplexer for signal <R_DTMP_10$mux0001> created at line 269.
    Found 1-bit 4-to-1 multiplexer for signal <R_DTMP_11$mux0001> created at line 269.
    Found 1-bit 4-to-1 multiplexer for signal <R_DTMP_12$mux0001> created at line 269.
    Found 1-bit 4-to-1 multiplexer for signal <R_DTMP_13$mux0001> created at line 269.
    Found 1-bit 4-to-1 multiplexer for signal <R_DTMP_14$mux0001> created at line 269.
    Found 1-bit 4-to-1 multiplexer for signal <R_DTMP_15$mux0001> created at line 269.
    Found 1-bit 4-to-1 multiplexer for signal <R_DTMP_2$mux0001> created at line 269.
    Found 1-bit 4-to-1 multiplexer for signal <R_DTMP_3$mux0001> created at line 269.
    Found 1-bit 4-to-1 multiplexer for signal <R_DTMP_4$mux0001> created at line 269.
    Found 1-bit 4-to-1 multiplexer for signal <R_DTMP_5$mux0001> created at line 269.
    Found 1-bit 4-to-1 multiplexer for signal <R_DTMP_6$mux0001> created at line 269.
    Found 1-bit 4-to-1 multiplexer for signal <R_DTMP_7$mux0001> created at line 269.
    Found 1-bit 4-to-1 multiplexer for signal <R_DTMP_8$mux0001> created at line 269.
    Found 1-bit 4-to-1 multiplexer for signal <R_DTMP_9$mux0001> created at line 269.
    Found 16-bit register for signal <R_IREG>.
    Summary:
	inferred  80 D-type flip-flop(s).
	inferred  52 Multiplexer(s).
Unit <pdp11_dpath> synthesized.


Synthesizing Unit <pdp11_mmu>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_mmu.vhd".
WARNING:Xst:647 - Input <CNTL.trap_done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <VADDR<5:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16-bit adder for signal <PADDRH>.
    Found 7-bit comparator greater for signal <abo_length$cmp_gt0000> created at line 299.
    Found 7-bit comparator less for signal <abo_length$cmp_lt0000> created at line 303.
    Found 1-bit 4-to-1 multiplexer for signal <dspace_en$mux0000> created at line 245.
    Found 1-bit register for signal <R_SSR0.abo_length>.
    Found 1-bit register for signal <R_SSR0.abo_nonres>.
    Found 1-bit register for signal <R_SSR0.abo_rdonly>.
    Found 1-bit register for signal <R_SSR0.dspace>.
    Found 1-bit register for signal <R_SSR0.ena_mmu>.
    Found 1-bit register for signal <R_SSR0.ena_trap>.
    Found 1-bit register for signal <R_SSR0.inst_compl>.
    Found 2-bit register for signal <R_SSR0.seg_mode>.
    Found 3-bit register for signal <R_SSR0.seg_num>.
    Found 1-bit register for signal <R_SSR0.trace_prev>.
    Found 1-bit register for signal <R_SSR0.trap_mmu>.
    Found 1-bit register for signal <R_SSR3.dspace_km>.
    Found 1-bit register for signal <R_SSR3.dspace_sm>.
    Found 1-bit register for signal <R_SSR3.dspace_um>.
    Found 1-bit register for signal <R_SSR3.ena_22bit>.
    Found 1-bit register for signal <R_SSR3.ena_ubmap>.
    Summary:
	inferred  19 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   2 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <pdp11_mmu> synthesized.


Synthesizing Unit <serport_1clock>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/serport/serport_1clock.vhd".
WARNING:Xst:646 - Signal <RXFIFO_SIZE<2:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <R_RXOK>.
    Found 3-bit comparator greatequal for signal <R_RXOK$cmp_ge0000> created at line 217.
    Found 3-bit comparator lessequal for signal <R_RXOK$cmp_le0000> created at line 218.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <serport_1clock> synthesized.


Synthesizing Unit <rlink_core>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rlink/rlink_core.vhd".
    Found finite state machine <FSM_9> for signal <R_BREGS.state>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 30                                             |
    | Inputs             | 10                                             |
    | Outputs            | 13                                             |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | RESET                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Power Up State     | 0000                                           |
    | Encoding           | one-hot                                        |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_10> for signal <R_LREGS.state>.
    -----------------------------------------------------------------------
    | States             | 40                                             |
    | Transitions        | 134                                            |
    | Inputs             | 31                                             |
    | Outputs            | 41                                             |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | RESET                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 000000                                         |
    | Power Up State     | 000000                                         |
    | Encoding           | one-hot                                        |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <L2B_CMD>.
    Found 6-bit subtractor for signal <N_BREGS.btocnt$addsub0000> created at line 1539.
    Found 1-bit register for signal <R_BREGS.blkabo>.
    Found 6-bit register for signal <R_BREGS.btocnt>.
    Found 11-bit down counter for signal <R_BREGS.cnt>.
    Found 1-bit register for signal <R_BREGS.dathpend>.
    Found 11-bit up counter for signal <R_BREGS.dcnt>.
    Found 1-bit register for signal <R_BREGS.rbaval>.
    Found 16-bit register for signal <R_BREGS.rbdout>.
    Found 1-bit register for signal <R_BREGS.rberr>.
    Found 1-bit register for signal <R_BREGS.rbinit>.
    Found 1-bit register for signal <R_BREGS.rbnak>.
    Found 1-bit register for signal <R_BREGS.rbre>.
    Found 1-bit register for signal <R_BREGS.rbtout>.
    Found 1-bit register for signal <R_BREGS.rbwe>.
    Found 4-bit register for signal <R_BREGS.stat>.
    Found 1-bit register for signal <R_BREGS.wfifo>.
    Found 6-bit comparator greatequal for signal <R_BREGS.wfifo$cmp_ge0000> created at line 1356.
    Found 6-bit comparator lessequal for signal <R_BREGS.wfifo$cmp_le0000> created at line 1357.
    Found 1-bit register for signal <R_CREGS.anena>.
    Found 1-bit register for signal <R_CREGS.atoena>.
    Found 8-bit register for signal <R_CREGS.atoval>.
    Found 16-bit register for signal <R_LREGS.addr>.
    Found 1-bit register for signal <R_LREGS.anact>.
    Found 1-bit register for signal <R_LREGS.anreq>.
    Found 1-bit register for signal <R_LREGS.arpend>.
    Found 8-bit down counter for signal <R_LREGS.atocnt>.
    Found 16-bit register for signal <R_LREGS.attn>.
    Found 1-bit register for signal <R_LREGS.babo>.
    Found 12-bit down counter for signal <R_LREGS.bcnt>.
    Found 1-bit register for signal <R_LREGS.cmdseen>.
    Found 16-bit register for signal <R_LREGS.cnt>.
    Found 16-bit register for signal <R_LREGS.din>.
    Found 8-bit register for signal <R_LREGS.dinl>.
    Found 1-bit register for signal <R_LREGS.doretra>.
    Found 8-bit register for signal <R_LREGS.lcmd>.
    Found 1-bit register for signal <R_LREGS.monattn>.
    Found 1-bit register for signal <R_LREGS.moneop>.
    Found 3-bit register for signal <R_LREGS.nakcode>.
    Found 1-bit register for signal <R_LREGS.nakdone>.
    Found 8-bit register for signal <R_LREGS.rcmd>.
    Found 12-bit up counter for signal <R_LREGS.rtaddra>.
    Found 1-bit register for signal <R_LREGS.rtaddra_bad>.
    Found 1-bit register for signal <R_LREGS.rtaddra_red>.
    Found 12-bit up counter for signal <R_LREGS.rtaddrb>.
    Found 1-bit register for signal <R_LREGS.rtaddrb_bad>.
    Found 1-bit register for signal <R_LREGS.rtaddrb_red>.
    Found 8-bit comparator not equal for signal <R_LREGS.state$cmp_ne0000> created at line 901.
    Found 8-bit comparator not equal for signal <R_LREGS.state$cmp_ne0001> created at line 917.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred   6 Counter(s).
	inferred 150 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   4 Comparator(s).
Unit <rlink_core> synthesized.


Synthesizing Unit <pdp11_vmbox>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_vmbox.vhd".
INFO:Xst:2117 - HDL ADVISOR - Mux Selector <paddr_sel$mux0003> of Case statement line 639 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
   	- add an 'INIT' attribute on signal <paddr_sel$mux0003> (optimization is then done without any risk)
   	- use the attribute 'signal_encoding user' to avoid onehot optimization
   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
    Found finite state machine <FSM_11> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 11                                             |
    | Transitions        | 52                                             |
    | Inputs             | 18                                             |
    | Outputs            | 13                                             |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | GRESET                    (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 0000                                           |
    | Power Up State     | 0000                                           |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <paddr_sel$mux0003>.
    Found 8-bit comparator lessequal for signal <is_stackred$cmp_le0000> created at line 371.
    Found 6-bit subtractor for signal <N_REGS.atocnt$addsub0000> created at line 628.
    Found 6-bit register for signal <R_REGS.atocnt>.
    Found 1-bit register for signal <R_REGS.bytop>.
    Found 1-bit register for signal <R_REGS.cacc>.
    Found 2-bit register for signal <R_REGS.ibbe>.
    Found 1-bit register for signal <R_REGS.ibcacc>.
    Found 16-bit register for signal <R_REGS.ibdout>.
    Found 1-bit register for signal <R_REGS.ibracc>.
    Found 1-bit register for signal <R_REGS.ibre>.
    Found 1-bit register for signal <R_REGS.ibrmw>.
    Found 1-bit register for signal <R_REGS.ibwe>.
    Found 1-bit register for signal <R_REGS.kstack>.
    Found 1-bit register for signal <R_REGS.macc>.
    Found 16-bit register for signal <R_REGS.mdin>.
    Found 22-bit register for signal <R_REGS.paddr>.
    Found 9-bit register for signal <R_REGS.paddr_iopage>.
    Found 9-bit comparator equal for signal <R_REGS.state$cmp_eq0000> created at line 443.
    Found 16-bit comparator greater for signal <R_REGS.state$cmp_gt0000> created at line 467.
    Found 1-bit register for signal <R_REGS.trap_mmu>.
    Found 1-bit register for signal <R_REGS.vaok>.
    Found 1-bit register for signal <R_REGS.wacc>.
    Found 1-bit register for signal <R_REGS.ysv>.
    Found 8-bit register for signal <R_SLIM>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  92 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   3 Comparator(s).
Unit <pdp11_vmbox> synthesized.


Synthesizing Unit <rlink_core8>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rlink/rlink_core8.vhd".
Unit <rlink_core8> synthesized.


Synthesizing Unit <pdp11_core>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_core.vhd".
WARNING:Xst:1780 - Signal <SNUM> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
Unit <pdp11_core> synthesized.


Synthesizing Unit <rlink_sp1c>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../vlib/rlink/rlink_sp1c.vhd".
WARNING:Xst:647 - Input <CE_USEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <rlink_sp1c> synthesized.


Synthesizing Unit <pdp11_sys70>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../../../../w11a/pdp11_sys70.vhd".
WARNING:Xst:1780 - Signal <DM_STAT_SY.dummy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <DM_STAT_SY.chit> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <pdp11_sys70> synthesized.


Synthesizing Unit <sys_w11a_s3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/s3board/ise/../sys_w11a_s3.vhd".
WARNING:Xst:646 - Signal <SWI<7:6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SWI<2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <STATLEDS> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <RESET> is used but never assigned. This sourceless signal will be automatically connected to value 0.
WARNING:Xst:646 - Signal <MEM_ADDR<19:18>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <CRESET> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <BTN> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <sys_w11a_s3> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 9
 16x226-bit ROM                                        : 1
 16x3-bit ROM                                          : 1
 16x7-bit ROM                                          : 1
 16x9-bit ROM                                          : 1
 32x1-bit ROM                                          : 1
 4x113-bit ROM                                         : 1
 4x2-bit ROM                                           : 1
 4x8-bit ROM                                           : 1
 8x4-bit ROM                                           : 1
# Multipliers                                          : 1
 16x16-bit multiplier                                  : 1
# Adders/Subtractors                                   : 40
 10-bit addsub                                         : 1
 10-bit subtractor                                     : 2
 13-bit subtractor                                     : 2
 14-bit adder                                          : 3
 15-bit adder                                          : 1
 16-bit adder                                          : 2
 16-bit addsub                                         : 2
 2-bit adder                                           : 3
 21-bit adder                                          : 2
 3-bit adder                                           : 1
 36-bit adder                                          : 1
 4-bit adder                                           : 1
 5-bit adder                                           : 1
 5-bit addsub                                          : 2
 5-bit subtractor                                      : 3
 6-bit addsub                                          : 1
 6-bit subtractor                                      : 3
 8-bit adder                                           : 3
 8-bit adder carry in/out                              : 2
 8-bit subtractor                                      : 1
 9-bit adder                                           : 3
# Counters                                             : 32
 10-bit down counter                                   : 1
 10-bit up counter                                     : 2
 11-bit down counter                                   : 1
 11-bit up counter                                     : 1
 12-bit down counter                                   : 1
 12-bit up counter                                     : 2
 2-bit down counter                                    : 2
 2-bit up counter                                      : 1
 3-bit up counter                                      : 1
 4-bit up counter                                      : 7
 5-bit up counter                                      : 6
 6-bit up counter                                      : 1
 7-bit down counter                                    : 1
 7-bit up counter                                      : 2
 8-bit down counter                                    : 2
 8-bit up counter                                      : 1
# Registers                                            : 659
 1-bit register                                        : 422
 10-bit register                                       : 4
 11-bit register                                       : 1
 12-bit register                                       : 4
 13-bit register                                       : 2
 14-bit register                                       : 3
 15-bit register                                       : 7
 16-bit register                                       : 36
 18-bit register                                       : 1
 2-bit register                                        : 29
 20-bit register                                       : 1
 21-bit register                                       : 1
 22-bit register                                       : 1
 3-bit register                                        : 20
 32-bit register                                       : 2
 36-bit register                                       : 1
 4-bit register                                        : 58
 5-bit register                                        : 9
 6-bit register                                        : 8
 7-bit register                                        : 3
 8-bit register                                        : 36
 9-bit register                                        : 10
# Comparators                                          : 44
 10-bit comparator greater                             : 1
 12-bit comparator greatequal                          : 1
 12-bit comparator lessequal                           : 1
 14-bit comparator greater                             : 1
 15-bit comparator greatequal                          : 2
 15-bit comparator lessequal                           : 2
 16-bit comparator greatequal                          : 2
 16-bit comparator greater                             : 2
 16-bit comparator lessequal                           : 2
 2-bit comparator equal                                : 3
 2-bit comparator not equal                            : 1
 3-bit comparator equal                                : 2
 3-bit comparator greatequal                           : 1
 3-bit comparator greater                              : 2
 3-bit comparator lessequal                            : 2
 3-bit comparator not equal                            : 1
 4-bit comparator equal                                : 2
 4-bit comparator greater                              : 1
 5-bit comparator greatequal                           : 1
 5-bit comparator greater                              : 1
 5-bit comparator lessequal                            : 1
 6-bit comparator greatequal                           : 2
 6-bit comparator greater                              : 1
 6-bit comparator lessequal                            : 1
 7-bit comparator greater                              : 1
 7-bit comparator less                                 : 1
 8-bit comparator lessequal                            : 1
 8-bit comparator not equal                            : 2
 9-bit comparator equal                                : 3
# Multiplexers                                         : 72
 1-bit 4-to-1 multiplexer                              : 55
 1-bit 8-to-1 multiplexer                              : 3
 16-bit 4-to-1 multiplexer                             : 7
 16-bit 8-to-1 multiplexer                             : 2
 4-bit 4-to-1 multiplexer                              : 1
 4-bit 8-to-1 multiplexer                              : 2
 5-bit 4-to-1 multiplexer                              : 1
 8-bit 4-to-1 multiplexer                              : 1
# Priority Encoders                                    : 1
 3-bit 1-of-5 priority encoder                         : 1
# Tristates                                            : 1
 32-bit tristate buffer                                : 1
# Xors                                                 : 94
 1-bit xor10                                           : 4
 1-bit xor2                                            : 74
 1-bit xor3                                            : 16

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_11> for best encoding.
Optimizing FSM <SYS70/W11A/VMBOX/R_REGS.state/FSM> on signal <R_REGS.state[1:11]> with one-hot encoding.
----------------------
 State | Encoding
----------------------
 0000  | 00000000001
 0001  | 00000001000
 0010  | 00000010000
 0011  | 00001000000
 0100  | 00010000000
 0101  | 01000000000
 0110  | 00000100000
 0111  | 10000000000
 1000  | 00000000010
 1001  | 00000000100
 1010  | 00100000000
----------------------
Optimizing FSM <RLINK/CORE/RL/R_LREGS.state/FSM> on signal <R_LREGS.state[1:40]> with one-hot encoding.
----------------------------------------------------
 State  | Encoding
----------------------------------------------------
 000000 | 0000000000000000000000000000000000000001
 000001 | 0000000000000000000000000000000000000010
 000010 | 0000000000000000000000000000000000000100
 000011 | 0000000000000000000000000000000010000000
 000100 | 0000000000000000000000000000000001000000
 000101 | 0000000000000000000000000000000000010000
 000110 | 0000000000000000000000000000001000000000
 000111 | 0000000000000000000000000000000100000000
 001000 | 0000000000000000000000000000000000100000
 001001 | 0000000000000000000000000000010000000000
 001010 | 0000000000000000000000000001000000000000
 001011 | 0000000000000000000000000010000000000000
 001100 | 0000000000000000000000001000000000000000
 001101 | 0000000000000000000000000100000000000000
 001110 | 0000000000000000000000010000000000000000
 001111 | 0000000000000000000000000000100000000000
 010000 | 0000000000000000000000100000000000000000
 010001 | 0000000000000000000001000000000000000000
 010010 | 0000000000000000000000000000000000001000
 010011 | 0000000000000100000000000000000000000000
 010100 | 0000000000000000000010000000000000000000
 010101 | 0000000000100000000000000000000000000000
 010110 | 0000000000000000001000000000000000000000
 010111 | 0000000001000000000000000000000000000000
 011000 | 0000000000000000010000000000000000000000
 011001 | 0000000010000000000000000000000000000000
 011010 | 0000000100000000000000000000000000000000
 011011 | 0000001000000000000000000000000000000000
 011100 | 0000010000000000000000000000000000000000
 011101 | 0000100000000000000000000000000000000000
 011110 | 0001000000000000000000000000000000000000
 011111 | 0000000000000000000100000000000000000000
 100000 | 0010000000000000000000000000000000000000
 100001 | 0000000000010000000000000000000000000000
 100010 | 0100000000000000000000000000000000000000
 100011 | 0000000000000000100000000000000000000000
 100100 | 0000000000000001000000000000000000000000
 100101 | 0000000000000010000000000000000000000000
 100110 | 0000000000001000000000000000000000000000
 100111 | 1000000000000000000000000000000000000000
----------------------------------------------------
Optimizing FSM <RLINK/CORE/RL/R_BREGS.state/FSM> on signal <R_BREGS.state[1:13]> with one-hot encoding.
------------------------
 State | Encoding
------------------------
 0000  | 0000000000001
 0001  | 0000000000010
 0010  | 0000000001000
 0011  | 0000000010000
 0100  | 0000000100000
 0101  | 0000010000000
 0110  | 0000100000000
 0111  | 0000001000000
 1000  | 0000000000100
 1001  | 0001000000000
 1010  | 0010000000000
 1011  | 0100000000000
 1100  | 1000000000000
------------------------
Analyzing FSM <FSM_8> for best encoding.
Optimizing FSM <SYS70/DMSCNT.I0/R_REGS.waddr/FSM> on signal <R_REGS.waddr[1:2]> with user encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 10
-------------------
Analyzing FSM <FSM_7> for best encoding.
Optimizing FSM <SYS70/CACHE/R_REGS.state/FSM> on signal <R_REGS.state[1:2]> with user encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 10
 11    | 11
-------------------
Analyzing FSM <FSM_6> for best encoding.
Optimizing FSM <IBDR_SYS/RL11.I0/R_REGS.state/FSM> on signal <R_REGS.state[1:4]> with user encoding.
-------------------
 State | Encoding
-------------------
 0000  | 0000
 0001  | 0001
 0010  | 0010
 0011  | 0011
 0100  | 0100
 0101  | 0101
 0110  | 0110
 0111  | 0111
 1000  | 1000
-------------------
Optimizing FSM <IBDR_SYS/RHRP.I0/R_REGS.state/FSM> on signal <R_REGS.state[1:22]> with one-hot encoding.
---------------------------------
 State | Encoding
---------------------------------
 00000 | 0000000000000000000001
 00001 | 0000000000000000000010
 00010 | 0000000000000000010000
 00011 | 0000000000100000000000
 00100 | 0000000000000001000000
 00101 | 0000000000000010000000
 00110 | 0000000000001000000000
 00111 | 0000000000000000100000
 01000 | 0000000000010000000000
 01001 | 0000000000000000001000
 01010 | 0000000000000000000100
 01011 | 0000000000000100000000
 01100 | 0000001000000000000000
 01101 | 0000010000000000000000
 01110 | 0000100000000000000000
 01111 | 0001000000000000000000
 10000 | 0010000000000000000000
 10001 | 0000000010000000000000
 10010 | 0000000001000000000000
 10011 | 0000000100000000000000
 10100 | 0100000000000000000000
 10101 | 1000000000000000000000
---------------------------------
Analyzing FSM <FSM_4> for best encoding.
Optimizing FSM <SRAM_CTL/R_REGS.state/FSM> on signal <R_REGS.state[1:6]> with one-hot encoding.
-------------------
 State | Encoding
-------------------
 000   | 000001
 001   | 000010
 010   | 000100
 011   | 010000
 100   | 001000
 101   | 100000
-------------------
Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <SYS70/W11A/SEQ/R_STATE/FSM> on signal <R_STATE[1:113]> with one-hot encoding.
---------------------------------------------------------------------------------------------------------------------------------------
 State            | Encoding
---------------------------------------------------------------------------------------------------------------------------------------
 s_idle           | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001
 s_cp_regread     | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000
 s_cp_rps         | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000
 s_cp_memr_w      | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000
 s_cp_memw_w      | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000
 s_ifetch         | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100
 s_ifetch_w       | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000
 s_idecode        | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000
 s_srcr_def       | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000
 s_srcr_def_w     | 00000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000
 s_srcr_inc       | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000
 s_srcr_inc_w     | 00000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000
 s_srcr_dec       | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000
 s_srcr_dec1      | 00000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000
 s_srcr_ind       | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000
 s_srcr_ind1_w    | 00000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000
 s_srcr_ind2      | 00000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000
 s_srcr_ind2_w    | 00000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000
 s_dstr_def       | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000
 s_dstr_def_w     | 00000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000
 s_dstr_inc       | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000
 s_dstr_inc_w     | 00000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000
 s_dstr_dec       | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000
 s_dstr_dec1      | 00000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000
 s_dstr_ind       | 00000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000
 s_dstr_ind1_w    | 00000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000
 s_dstr_ind2      | 00000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000
 s_dstr_ind2_w    | 00000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000
 s_dstw_def       | 00000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000
 s_dstw_def_w     | 00000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000
 s_dstw_inc       | 00000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000
 s_dstw_inc_w     | 00000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000
 s_dstw_incdef_w  | 00000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000
 s_dstw_dec       | 00000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000
 s_dstw_dec1      | 00000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000
 s_dstw_ind       | 00000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000
 s_dstw_ind_w     | 00000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000
 s_dstw_def246    | 00000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000
 s_dsta_inc       | 00000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000
 s_dsta_incdef_w  | 00000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000
 s_dsta_dec       | 00000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000
 s_dsta_dec1      | 00000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000
 s_dsta_ind       | 00000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000
 s_dsta_ind_w     | 00000000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000
 s_op_halt        | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000
 s_op_wait        | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000
 s_op_trap        | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000
 s_op_reset       | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000
 s_op_rts         | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000
 s_op_rts_pop     | 00000000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000
 s_op_rts_pop_w   | 00000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000
 s_op_spl         | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000
 s_op_mcc         | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000
 s_op_br          | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000
 s_op_mark        | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000
 s_op_mark1       | 00000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000
 s_op_mark_pop    | 00000000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000
 s_op_mark_pop_w  | 00000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000
 s_op_sob         | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000
 s_op_sob1        | 00000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opg_gen        | 00000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000
 s_opg_gen_rmw_w  | 00000000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opg_mul        | 00000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000
 s_opg_mul1       | 00000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opg_div        | 00000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000
 s_opg_div_cn     | 00000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opg_div_cr     | 00000000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opg_div_sq     | 00000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opg_div_sr     | 00000000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opg_div_quit   | 00000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opg_ash        | 00000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000000000
 s_opg_ash_cn     | 00000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opg_ashc       | 00000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000
 s_opg_ashc_cn    | 00000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opg_ashc_wl    | 00000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opa_jsr        | 00000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000
 s_opa_jsr1       | 00000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opa_jsr_push   | 00000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opa_jsr_push_w | 00000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opa_jsr2       | 00000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opa_jmp        | 00000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000
 s_opa_mtp        | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000
 s_opa_mtp_pop_w  | 00000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opa_mtp_reg    | 00000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opa_mtp_mem    | 00000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000
 s_opa_mtp_mem_w  | 00000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opa_mfp_reg    | 00000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000000000000000
 s_opa_mfp_mem    | 00000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000
 s_opa_mfp_mem_w  | 00000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opa_mfp_dec    | 00000000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opa_mfp_push   | 00000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_opa_mfp_push_w | 00000000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_trap_4         | 00000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000
 s_trap_10        | 00000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000
 s_trap_disp      | 00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000
 s_int_ext        | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010
 s_int_getpc      | 00000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000000
 s_int_getpc_w    | 00000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_int_getps      | 00000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_int_getps_w    | 00000000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_int_getsp      | 00000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_int_decsp      | 00000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_int_pushps     | 00000001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_int_pushps_w   | 00000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_int_pushpc     | 00000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_int_pushpc_w   | 00001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_rti_getpc      | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000
 s_rti_getpc_w    | 00010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_rti_getps      | 00100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_rti_getps_w    | 01000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_rti_newpc      | 10000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000
 s_vmerr          | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000
 s_cpufail        | 00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010000000000000000000000
---------------------------------------------------------------------------------------------------------------------------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <SYS70/RB2CP/R_REGS.state/FSM> on signal <R_REGS.state[1:2]> with user encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 10
-------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <RLINK/SERPORT/UART/RXTX/RX/R_REGS.state/FSM> on signal <R_REGS.state[1:7]> with one-hot encoding.
-------------------
 State | Encoding
-------------------
 000   | 0000001
 001   | 0000100
 010   | 0000010
 011   | 0010000
 100   | 0001000
 101   | 1000000
 110   | 0100000
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <RLINK/SERPORT/UART/AB/R_REGS.state/FSM> on signal <R_REGS.state[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 11
 11    | 10
-------------------

Synthesizing (advanced) Unit <pdp11_mmu_ssr12>.
The following registers are absorbed into accumulator <R_SSR1.rb_delta>: 1 register on signal <R_SSR1.rb_delta>.
The following registers are absorbed into accumulator <R_SSR1.ra_delta>: 1 register on signal <R_SSR1.ra_delta>.
Unit <pdp11_mmu_ssr12> synthesized (advanced).
WARNING:Xst:2677 - Node <R_REGS.omux_11> of sequential type is unconnected in block <ibdr_rhrp>.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 12
# ROMs                                                 : 7
 16x3-bit ROM                                          : 1
 16x7-bit ROM                                          : 1
 16x9-bit ROM                                          : 1
 32x1-bit ROM                                          : 1
 4x2-bit ROM                                           : 1
 4x8-bit ROM                                           : 1
 8x4-bit ROM                                           : 1
# Multipliers                                          : 1
 16x16-bit multiplier                                  : 1
# Adders/Subtractors                                   : 38
 10-bit addsub                                         : 1
 10-bit subtractor                                     : 2
 13-bit subtractor                                     : 2
 14-bit adder                                          : 3
 15-bit adder                                          : 1
 16-bit adder                                          : 2
 16-bit addsub                                         : 2
 2-bit adder                                           : 3
 21-bit adder                                          : 2
 3-bit adder                                           : 1
 36-bit adder                                          : 1
 4-bit adder                                           : 1
 5-bit adder                                           : 1
 5-bit subtractor                                      : 3
 6-bit addsub                                          : 1
 6-bit subtractor                                      : 3
 8-bit adder                                           : 3
 8-bit adder carry in/out                              : 2
 8-bit subtractor                                      : 1
 9-bit adder                                           : 3
# Counters                                             : 32
 10-bit down counter                                   : 1
 10-bit up counter                                     : 2
 11-bit down counter                                   : 1
 11-bit up counter                                     : 1
 12-bit down counter                                   : 1
 12-bit up counter                                     : 2
 2-bit down counter                                    : 2
 2-bit up counter                                      : 1
 3-bit up counter                                      : 1
 4-bit up counter                                      : 7
 5-bit up counter                                      : 6
 6-bit up counter                                      : 1
 7-bit down counter                                    : 1
 7-bit up counter                                      : 2
 8-bit down counter                                    : 2
 8-bit up counter                                      : 1
# Accumulators                                         : 2
 5-bit updown loadable accumulator                     : 2
# Registers                                            : 2282
 Flip-Flops                                            : 2282
# Comparators                                          : 44
 10-bit comparator greater                             : 1
 12-bit comparator greatequal                          : 1
 12-bit comparator lessequal                           : 1
 14-bit comparator greater                             : 1
 15-bit comparator greatequal                          : 2
 15-bit comparator lessequal                           : 2
 16-bit comparator greatequal                          : 2
 16-bit comparator greater                             : 2
 16-bit comparator lessequal                           : 2
 2-bit comparator equal                                : 3
 2-bit comparator not equal                            : 1
 3-bit comparator equal                                : 2
 3-bit comparator greatequal                           : 1
 3-bit comparator greater                              : 2
 3-bit comparator lessequal                            : 2
 3-bit comparator not equal                            : 1
 4-bit comparator equal                                : 2
 4-bit comparator greater                              : 1
 5-bit comparator greatequal                           : 1
 5-bit comparator greater                              : 1
 5-bit comparator lessequal                            : 1
 6-bit comparator greatequal                           : 2
 6-bit comparator greater                              : 1
 6-bit comparator lessequal                            : 1
 7-bit comparator greater                              : 1
 7-bit comparator less                                 : 1
 8-bit comparator lessequal                            : 1
 8-bit comparator not equal                            : 2
 9-bit comparator equal                                : 3
# Multiplexers                                         : 72
 1-bit 4-to-1 multiplexer                              : 55
 1-bit 8-to-1 multiplexer                              : 3
 16-bit 4-to-1 multiplexer                             : 7
 16-bit 8-to-1 multiplexer                             : 2
 4-bit 4-to-1 multiplexer                              : 1
 4-bit 8-to-1 multiplexer                              : 2
 5-bit 4-to-1 multiplexer                              : 1
 8-bit 4-to-1 multiplexer                              : 1
# Priority Encoders                                    : 1
 3-bit 1-of-5 priority encoder                         : 1
# Xors                                                 : 94
 1-bit xor10                                           : 4
 1-bit xor2                                            : 74
 1-bit xor3                                            : 16

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch <R_REGS.escseen> has a constant value of 0 in block <serport_xonrx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <R_REGS.escpend> has a constant value of 0 in block <serport_xontx>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <R_STATUS.suspext> has a constant value of 0 in block <pdp11_sequencer>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <R_REGS.dtyp_3> has a constant value of 0 in block <ibdr_rhrp>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <R_SSR0.inst_compl> has a constant value of 0 in block <pdp11_mmu>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <R_REGS.dcf_brk_1> in Unit <ibd_iist> is equivalent to the following 2 FFs/Latches, which will be removed : <R_REGS.dcf_brk_2> <R_REGS.dcf_brk_3> 
INFO:Xst:2261 - The FF/Latch <R_REGS.dtyp_5> in Unit <ibdr_rhrp> is equivalent to the following 3 FFs/Latches, which will be removed : <R_REGS.samax_5> <R_REGS.camax_0> <R_REGS.camax_6> 
INFO:Xst:2261 - The FF/Latch <R_REGS.tamax_1> in Unit <ibdr_rhrp> is equivalent to the following FF/Latch, which will be removed : <R_REGS.tamax_4> 
INFO:Xst:2261 - The FF/Latch <R_REGS.tamax_0> in Unit <ibdr_rhrp> is equivalent to the following FF/Latch, which will be removed : <R_REGS.tamax_3> 
INFO:Xst:2261 - The FF/Latch <R_REGS.camax_2> in Unit <ibdr_rhrp> is equivalent to the following 2 FFs/Latches, which will be removed : <R_REGS.camax_5> <R_REGS.camax_9> 
INFO:Xst:2261 - The FF/Latch <R_REGS.samax_1> in Unit <ibdr_rhrp> is equivalent to the following FF/Latch, which will be removed : <R_REGS.samax_3> 
INFO:Xst:2261 - The FF/Latch <R_REGS.paddr_iopage_3> in Unit <pdp11_vmbox> is equivalent to the following FF/Latch, which will be removed : <R_REGS.paddr_iopage_4> 
INFO:Xst:2261 - The FF/Latch <R_REGS.paddr_iopage_0> in Unit <pdp11_vmbox> is equivalent to the following 2 FFs/Latches, which will be removed : <R_REGS.paddr_iopage_1> <R_REGS.paddr_iopage_2> 
INFO:Xst:2261 - The FF/Latch <R_REGS.paddr_iopage_5> in Unit <pdp11_vmbox> is equivalent to the following 3 FFs/Latches, which will be removed : <R_REGS.paddr_iopage_6> <R_REGS.paddr_iopage_7> <R_REGS.paddr_iopage_8> 
INFO:Xst:1901 - Instance BRAM0/UMEM/AW_09_S32.GL[0].MEM in unit BRAM0/UMEM/AW_09_S32.GL[0].MEM of type RAMB16_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance BRAM1/UMEM/AW_09_S32.GL[0].MEM in unit BRAM1/UMEM/AW_09_S32.GL[0].MEM of type RAMB16_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM in unit CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance CMEM_DAT2/UMEM/AW_11_S9.GL[0].MEM in unit CMEM_DAT2/UMEM/AW_11_S9.GL[0].MEM of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM in unit CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance CMEM_DAT0/UMEM/AW_11_S9.GL[0].MEM in unit CMEM_DAT0/UMEM/AW_11_S9.GL[0].MEM of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM in unit CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM of type RAMB16_S9_S9 has been replaced by RAMB16
INFO:Xst:1901 - Instance BRAM0/UMEM/AW_09_S32.GL[0].MEM in unit BRAM0/UMEM/AW_09_S32.GL[0].MEM of type RAMB16_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance BRAM1/UMEM/AW_09_S32.GL[0].MEM in unit BRAM1/UMEM/AW_09_S32.GL[0].MEM of type RAMB16_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance CMEM/UMEM/AW_09_S36.GL[0].MEM in unit CMEM/UMEM/AW_09_S36.GL[0].MEM of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance BRAM1/UMEM/AW_09_S36.GL[0].MEM in unit BRAM1/UMEM/AW_09_S36.GL[0].MEM of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance BRAM0/UMEM/AW_09_S36.GL[0].MEM in unit BRAM0/UMEM/AW_09_S36.GL[0].MEM of type RAMB16_S36_S36 has been replaced by RAMB16
INFO:Xst:1901 - Instance RTBUF/UMEM/AW_12_S4.GL[1].MEM in unit RTBUF/UMEM/AW_12_S4.GL[1].MEM of type RAMB16_S4_S4 has been replaced by RAMB16
INFO:Xst:1901 - Instance RTBUF/UMEM/AW_12_S4.GL[0].MEM in unit RTBUF/UMEM/AW_12_S4.GL[0].MEM of type RAMB16_S4_S4 has been replaced by RAMB16
INFO:Xst:2261 - The FF/Latch <R_BREGS.rbwe> in Unit <rlink_core> is equivalent to the following FF/Latch, which will be removed : <R_BREGS.state_FSM_FFd4> 

Optimizing unit <sys_w11a_s3> ...

Optimizing unit <clkdivce> ...

Optimizing unit <byte2cdata> ...

Optimizing unit <cdata2byte> ...

Optimizing unit <crc16> ...

Optimizing unit <serport_xonrx> ...

Optimizing unit <serport_xontx> ...

Optimizing unit <serport_uart_autobaud> ...

Optimizing unit <serport_uart_rx> ...

Optimizing unit <serport_uart_tx> ...

Optimizing unit <pdp11_core_rbus> ...

Optimizing unit <pdp11_mem70> ...

Optimizing unit <pdp11_decode> ...

Optimizing unit <pdp11_reg70> ...

Optimizing unit <pdp11_ounit> ...

Optimizing unit <pdp11_aunit> ...

Optimizing unit <pdp11_munit> ...

Optimizing unit <pdp11_dmhbpt_unit_1> ...

Optimizing unit <pdp11_dmhbpt_unit_2> ...

Optimizing unit <ibd_iist> ...

Optimizing unit <ibd_kw11l> ...

Optimizing unit <ibdr_tm11> ...

Optimizing unit <ibdr_dl11_1> ...

Optimizing unit <ibdr_dl11_2> ...

Optimizing unit <ibdr_pc11> ...

Optimizing unit <ibdr_lp11> ...

Optimizing unit <ibdr_sdreg> ...

Optimizing unit <iob_reg_o_gen_3> ...

Optimizing unit <iob_reg_o_gen_6> ...

Optimizing unit <sn_7segctl> ...

Optimizing unit <iob_reg_i_gen_3> ...

Optimizing unit <debounce_gen_1> ...

Optimizing unit <debounce_gen_2> ...

Optimizing unit <ram_1swar_1ar_gen_2> ...

Optimizing unit <ram_1swar_gen_5> ...

Optimizing unit <ram_1swar_gen_1> ...

Optimizing unit <ram_1swar_1ar_gen_3> ...

Optimizing unit <ram_1swar_1ar_gen_1> ...

Optimizing unit <ram_1swar_gen_2> ...

Optimizing unit <pdp11_sequencer> ...
INFO:Xst:2261 - The FF/Latch <R_STATUS.intack> in Unit <pdp11_sequencer> is equivalent to the following FF/Latch, which will be removed : <R_STATE_FSM_FFd112> 
INFO:Xst:2261 - The FF/Latch <R_STATUS.intack> in Unit <pdp11_sequencer> is equivalent to the following FF/Latch, which will be removed : <R_STATE_FSM_FFd112> 
INFO:Xst:2261 - The FF/Latch <R_STATUS.intack> in Unit <pdp11_sequencer> is equivalent to the following FF/Latch, which will be removed : <R_STATE_FSM_FFd112> 

Optimizing unit <pdp11_irq> ...

Optimizing unit <pdp11_mmu_ssr12> ...

Optimizing unit <pdp11_psr> ...

Optimizing unit <fifo_1c_dram_raw> ...

Optimizing unit <pdp11_ubmap> ...

Optimizing unit <pdp11_mmu_sadr> ...

Optimizing unit <pdp11_gpr> ...

Optimizing unit <ibdr_rhrp> ...
INFO:Xst:2261 - The FF/Latch <R_REGS.dtyp_4> in Unit <ibdr_rhrp> is equivalent to the following 2 FFs/Latches, which will be removed : <R_REGS.samax_2> <R_REGS.camax_1> 
INFO:Xst:2261 - The FF/Latch <R_REGS.dtyp_2> in Unit <ibdr_rhrp> is equivalent to the following FF/Latch, which will be removed : <R_REGS.samax_1> 
INFO:Xst:2261 - The FF/Latch <R_REGS.dtyp_2> in Unit <ibdr_rhrp> is equivalent to the following FF/Latch, which will be removed : <R_REGS.samax_1> 

Optimizing unit <ibdr_rl11> ...

Optimizing unit <ibdr_rk11> ...

Optimizing unit <ibdr_maxisys> ...

Optimizing unit <rbd_rbmon> ...

Optimizing unit <pdp11_cache> ...

Optimizing unit <ibd_ibmon> ...

Optimizing unit <pdp11_dmscnt> ...

Optimizing unit <pdp11_dmcmon> ...

Optimizing unit <pdp11_dpath> ...

Optimizing unit <pdp11_mmu> ...

Optimizing unit <bp_rs232_2l4l_iob> ...

Optimizing unit <sn_humanio_rbus> ...

Optimizing unit <serport_1clock> ...

Optimizing unit <rlink_core> ...
INFO:Xst:2261 - The FF/Latch <R_BREGS.rbre> in Unit <rlink_core> is equivalent to the following FF/Latch, which will be removed : <R_BREGS.state_FSM_FFd10> 
INFO:Xst:2261 - The FF/Latch <R_BREGS.rbre> in Unit <rlink_core> is equivalent to the following FF/Latch, which will be removed : <R_BREGS.state_FSM_FFd10> 
INFO:Xst:2261 - The FF/Latch <R_BREGS.rbre> in Unit <rlink_core> is equivalent to the following FF/Latch, which will be removed : <R_BREGS.state_FSM_FFd10> 
INFO:Xst:2261 - The FF/Latch <R_BREGS.rbre> in Unit <rlink_core> is equivalent to the following FF/Latch, which will be removed : <R_BREGS.state_FSM_FFd10> 

Optimizing unit <pdp11_vmbox> ...

Optimizing unit <pdp11_sys70> ...
WARNING:Xst:1293 - FF/Latch <RLINK/CORE/RL/R_LREGS.attn_15> has a constant value of 0 in block <sys_w11a_s3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/CORE/RL/R_LREGS.attn_14> has a constant value of 0 in block <sys_w11a_s3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/CORE/RL/R_LREGS.attn_13> has a constant value of 0 in block <sys_w11a_s3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/CORE/RL/R_LREGS.attn_12> has a constant value of 0 in block <sys_w11a_s3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/CORE/RL/R_LREGS.attn_11> has a constant value of 0 in block <sys_w11a_s3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/CORE/RL/R_LREGS.attn_9> has a constant value of 0 in block <sys_w11a_s3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/CORE/RL/R_LREGS.attn_3> has a constant value of 0 in block <sys_w11a_s3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <SYS70/W11A/SEQ/R_STATUS.intvect_8> has a constant value of 0 in block <sys_w11a_s3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <SYS70/W11A/SEQ/R_IDSTAT.res_sel_2> has a constant value of 0 in block <sys_w11a_s3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <IBDR_SYS/IIST.I0/R_REGS.req_boot> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <IBDR_SYS/IIST.I0/R_REGS.req_lock> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swieff_7> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swieff_6> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swieff_2> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swi_7> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swi_6> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swi_2> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <HIO/R_REGS.btn_3> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <HIO/R_REGS.btn_2> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <HIO/R_REGS.btn_1> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <HIO/R_REGS.btn_0> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <HIO/R_REGS.btneff_3> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <HIO/R_REGS.btneff_2> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <HIO/R_REGS.btneff_1> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <HIO/R_REGS.btneff_0> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <RLINK/SERPORT/XONRX/R_REGS.rxovr> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <RLINK/CORE/RL/R_LREGS.monattn> of sequential type is unconnected in block <sys_w11a_s3>.
WARNING:Xst:2677 - Node <RLINK/CORE/RL/R_LREGS.moneop> of sequential type is unconnected in block <sys_w11a_s3>.

Mapping all equations...
Annotating constraints using XCF file 'sys_w11a_s3.xcf'
XCF parsing done.
Building and optimizing final netlist ...
INFO:Xst:2261 - The FF/Latch <IBDR_SYS/IIST.I0/R_REGS.dcf_brk_0> in Unit <sys_w11a_s3> is equivalent to the following FF/Latch, which will be removed : <IBDR_SYS/IIST.I0/R_REGS.dcf_brk_1> 
INFO:Xst:2261 - The FF/Latch <SYS70/DMCMON.I0/R_REGS.se_snum_6> in Unit <sys_w11a_s3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMSCNT.I0/R_REGS.snum0_6> 
INFO:Xst:2261 - The FF/Latch <SYS70/DMCMON.I0/R_REGS.se_snum_4> in Unit <sys_w11a_s3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMSCNT.I0/R_REGS.snum0_4> 
INFO:Xst:2261 - The FF/Latch <SYS70/DMCMON.I0/R_REGS.se_snum_1> in Unit <sys_w11a_s3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMSCNT.I0/R_REGS.snum0_1> 
INFO:Xst:2261 - The FF/Latch <SYS70/DMCMON.I0/R_REGS.se_snum_0> in Unit <sys_w11a_s3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMSCNT.I0/R_REGS.snum0_0> 
INFO:Xst:2261 - The FF/Latch <SYS70/DMCMON.I0/R_REGS.se_snum_7> in Unit <sys_w11a_s3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMSCNT.I0/R_REGS.snum0_7> 
INFO:Xst:2261 - The FF/Latch <SYS70/DMCMON.I0/R_REGS.se_snum_2> in Unit <sys_w11a_s3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMSCNT.I0/R_REGS.snum0_2> 
INFO:Xst:2261 - The FF/Latch <SYS70/DMCMON.I0/R_REGS.se_snum_5> in Unit <sys_w11a_s3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMSCNT.I0/R_REGS.snum0_5> 
INFO:Xst:2261 - The FF/Latch <SYS70/W11A/SEQ/R_IDSTAT.aunit_srcmod_1> in Unit <sys_w11a_s3> is equivalent to the following FF/Latch, which will be removed : <SYS70/W11A/SEQ/R_IDSTAT.aunit_cc1op> 
INFO:Xst:2261 - The FF/Latch <SYS70/W11A/SEQ/R_IDSTAT.fork_dsta_1> in Unit <sys_w11a_s3> is equivalent to the following FF/Latch, which will be removed : <SYS70/W11A/SEQ/R_IDSTAT.fork_dstr_1> 
INFO:Xst:2261 - The FF/Latch <SYS70/W11A/SEQ/R_IDSTAT.fork_dsta_0> in Unit <sys_w11a_s3> is equivalent to the following FF/Latch, which will be removed : <SYS70/W11A/SEQ/R_IDSTAT.fork_dstr_0> 
INFO:Xst:2261 - The FF/Latch <SYS70/DMCMON.I0/R_REGS.se_snum_3> in Unit <sys_w11a_s3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMSCNT.I0/R_REGS.snum0_3> 
Replicating register SRAM_CTL/IOB_MEM_DATA/R_TE to handle IOB=TRUE attribute

FlipFlop IBDR_SYS/RL11.I0/R_REGS.ibsel has been replicated 1 time(s)
FlipFlop IBDR_SYS/RL11.I0/R_REGS.state_FSM_FFd1 has been replicated 1 time(s)
FlipFlop IBDR_SYS/RL11.I0/R_REGS.state_FSM_FFd2 has been replicated 2 time(s)
FlipFlop IBDR_SYS/RL11.I0/R_REGS.state_FSM_FFd3 has been replicated 2 time(s)
FlipFlop IBDR_SYS/RL11.I0/R_REGS.state_FSM_FFd4 has been replicated 1 time(s)
FlipFlop SYS70/CACHE/R_REGS.state_FSM_FFd1 has been replicated 2 time(s)
FlipFlop SYS70/CACHE/R_REGS.state_FSM_FFd2 has been replicated 2 time(s)
FlipFlop SYS70/W11A/DPATH/PSR/R_PSW.cmode_0 has been replicated 1 time(s)
FlipFlop SYS70/W11A/DPATH/PSR/R_PSW.cmode_1 has been replicated 1 time(s)
FlipFlop SYS70/W11A/DPATH/R_DDST_15 has been replicated 1 time(s)
FlipFlop SYS70/W11A/DPATH/R_DSRC_15 has been replicated 1 time(s)
FlipFlop SYS70/W11A/DPATH/R_IREG_3 has been replicated 1 time(s)
FlipFlop SYS70/W11A/SEQ/R_STATE_FSM_FFd104 has been replicated 2 time(s)
FlipFlop SYS70/W11A/SEQ/R_STATE_FSM_FFd31 has been replicated 1 time(s)
FlipFlop SYS70/W11A/SEQ/R_STATE_FSM_FFd74 has been replicated 1 time(s)
FlipFlop SYS70/W11A/VMBOX/R_REGS.bytop has been replicated 1 time(s)
FlipFlop SYS70/W11A/VMBOX/R_REGS.ibre has been replicated 1 time(s)
FlipFlop SYS70/W11A/VMBOX/R_REGS.paddr_0 has been replicated 1 time(s)
FlipFlop SYS70/W11A/VMBOX/R_REGS.paddr_1 has been replicated 1 time(s)
FlipFlop SYS70/W11A/VMBOX/R_REGS.paddr_2 has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 2711
 Flip-Flops                                            : 2711

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : sys_w11a_s3
Output Format                      : ngc
Optimization Goal                  : SPEED
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 97

Cell Usage :
# BELS                             : 9020
#      GND                         : 15
#      INV                         : 96
#      LUT1                        : 169
#      LUT2                        : 692
#      LUT2_D                      : 43
#      LUT2_L                      : 42
#      LUT3                        : 1714
#      LUT3_D                      : 85
#      LUT3_L                      : 78
#      LUT4                        : 4080
#      LUT4_D                      : 179
#      LUT4_L                      : 331
#      MUXCY                       : 587
#      MUXF5                       : 501
#      MUXF6                       : 19
#      VCC                         : 1
#      XORCY                       : 388
# FlipFlops/Latches                : 2711
#      FD                          : 231
#      FDE                         : 354
#      FDR                         : 516
#      FDRE                        : 1168
#      FDRS                        : 201
#      FDRSE                       : 51
#      FDS                         : 131
#      FDSE                        : 59
# RAMS                             : 192
#      RAM16X1D                    : 80
#      RAM16X1S                    : 32
#      RAM32X1S                    : 37
#      RAM64X1S                    : 29
#      RAMB16                      : 14
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 96
#      IBUF                        : 15
#      IOBUF                       : 32
#      OBUF                        : 49
# MULTs                            : 1
#      MULT18X18                   : 1
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1000ft256-4 

 Number of Slices:                     4200  out of   7680    54%  
 Number of Slice Flip Flops:           2551  out of  15360    16%  
 Number of 4 input LUTs:               7891  out of  15360    51%  
    Number used as logic:              7509
    Number used as RAMs:                382
 Number of IOs:                          97
 Number of bonded IOBs:                  97  out of    173    56%  
    IOB Flip Flops:                     160
 Number of BRAMs:                        14  out of     24    58%  
 Number of MULT18X18s:                    1  out of     24     4%  
 Number of GCLKs:                         1  out of      8    12%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
I_CLK50                            | BUFGP                  | 2903  |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 21.055ns (Maximum Frequency: 47.495MHz)
   Minimum input arrival time before clock: 1.825ns
   Maximum output required time after clock: 7.408ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'I_CLK50'
  Clock period: 21.055ns (frequency: 47.495MHz)
  Total number of paths / destination ports: 2391084 / 7775
-------------------------------------------------------------------------
Delay:               21.055ns (Levels of Logic = 15)
  Source:            SYS70/W11A/SEQ/R_STATE_FSM_FFd19 (FF)
  Destination:       SYS70/DMCMON.I0/R_REGS.se_idone (FF)
  Source Clock:      I_CLK50 rising
  Destination Clock: I_CLK50 rising

  Data Path: SYS70/W11A/SEQ/R_STATE_FSM_FFd19 to SYS70/DMCMON.I0/R_REGS.se_idone
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              8   0.720   1.422  SYS70/W11A/SEQ/R_STATE_FSM_FFd19 (SYS70/W11A/SEQ/R_STATE_FSM_FFd19)
     LUT4_D:I0->O         13   0.551   1.196  SYS70/W11A/SEQ/DP_CNTL_ounit_asel<1>14 (SYS70/W11A/SEQ/DP_CNTL_ounit_asel<1>14)
     LUT4:I3->O            1   0.551   0.827  SYS70/W11A/SEQ/DP_CNTL_ounit_asel<0>23_SW0 (N1632)
     LUT4:I3->O           16   0.551   1.263  SYS70/W11A/SEQ/DP_CNTL_ounit_asel<0>23 (SYS70/W11A/DP_CNTL_ounit_asel<0>)
     LUT4:I3->O            1   0.551   0.996  SYS70/W11A/DPATH/OUNIT/ma_mux0001<1> (SYS70/W11A/DPATH/OUNIT/ma_mux0001<1>)
     LUT2:I1->O            1   0.551   0.827  SYS70/W11A/DPATH/OUNIT/Maddsub_sum_mux0000_lut<1>_SW0 (N1509)
     LUT4:I3->O            1   0.551   0.000  SYS70/W11A/DPATH/OUNIT/Maddsub_sum_mux0000_lut<1> (SYS70/W11A/DPATH/OUNIT/Maddsub_sum_mux0000_lut<1>)
     MUXCY:S->O            1   0.500   0.000  SYS70/W11A/DPATH/OUNIT/Maddsub_sum_mux0000_cy<1> (SYS70/W11A/DPATH/OUNIT/Maddsub_sum_mux0000_cy<1>)
     MUXCY:CI->O           1   0.064   0.000  SYS70/W11A/DPATH/OUNIT/Maddsub_sum_mux0000_cy<2> (SYS70/W11A/DPATH/OUNIT/Maddsub_sum_mux0000_cy<2>)
     XORCY:CI->O           2   0.904   1.216  SYS70/W11A/DPATH/OUNIT/Maddsub_sum_mux0000_xor<3> (SYS70/W11A/DPATH/OUNIT_DOUT<3>)
     LUT2_L:I0->LO         1   0.551   0.126  SYS70/W11A/DPATH/OUNIT/NZOUT_0_cmp_eq000028 (SYS70/W11A/DPATH/OUNIT/NZOUT_0_cmp_eq000028)
     LUT4:I3->O            1   0.551   0.827  SYS70/W11A/DPATH/OUNIT/NZOUT_0_cmp_eq000042 (SYS70/W11A/DPATH/OUNIT/NZOUT_0_cmp_eq000042)
     LUT4:I3->O            1   0.551   0.827  SYS70/W11A/DPATH/OUNIT/NZOUT_0_cmp_eq000090_SW1 (N1450)
     LUT4:I3->O            1   0.551   0.000  SYS70/W11A/DPATH/CNTL_cres_sel<2>_71 (SYS70/W11A/DPATH/CNTL_cres_sel<2>_71)
     MUXF5:I0->O           7   0.360   1.092  SYS70/W11A/DPATH/CNTL_cres_sel<2>_5_f5_0 (SYS70/W11A/DPATH/CNTL_cres_sel<2>_5_f51)
     LUT4:I3->O            1   0.551   0.801  SYS70/W11A/SEQ/MMU_MONI_idone11 (SYS70/W11A/SEQ/N33)
     FDRS:S                    1.026          SYS70/DMCMON.I0/R_REGS.se_idone
    ----------------------------------------
    Total                     21.055ns (9.635ns logic, 11.420ns route)
                                       (45.8% logic, 54.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'I_CLK50'
  Total number of paths / destination ports: 47 / 47
-------------------------------------------------------------------------
Offset:              1.825ns (Levels of Logic = 1)
  Source:            IO_MEM_DATA<0> (PAD)
  Destination:       SRAM_CTL/IOB_MEM_DATA/R_DI_0 (FF)
  Destination Clock: I_CLK50 rising

  Data Path: IO_MEM_DATA<0> to SRAM_CTL/IOB_MEM_DATA/R_DI_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O           1   0.821   0.801  IO_MEM_DATA_0_IOBUF (N1316)
     FDE:D                     0.203          SRAM_CTL/IOB_MEM_DATA/R_DI_0
    ----------------------------------------
    Total                      1.825ns (1.024ns logic, 0.801ns route)
                                       (56.1% logic, 43.9% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'I_CLK50'
  Total number of paths / destination ports: 113 / 81
-------------------------------------------------------------------------
Offset:              7.408ns (Levels of Logic = 1)
  Source:            SRAM_CTL/IOB_MEM_DATA/R_TE_1 (FF)
  Destination:       IO_MEM_DATA<31> (PAD)
  Source Clock:      I_CLK50 rising

  Data Path: SRAM_CTL/IOB_MEM_DATA/R_TE_1 to IO_MEM_DATA<31>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.720   0.801  SRAM_CTL/IOB_MEM_DATA/R_TE_1 (SRAM_CTL/IOB_MEM_DATA/R_TE_1)
     IOBUF:T->IO               5.887          IO_MEM_DATA_31_IOBUF (IO_MEM_DATA<31>)
    ----------------------------------------
    Total                      7.408ns (6.607ns logic, 0.801ns route)
                                       (89.2% logic, 10.8% route)

=========================================================================


Total REAL time to Xst completion: 194.00 secs
Total CPU time to Xst completion: 183.05 secs
 
--> 


Total memory usage is 908184 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  521 (   0 filtered)
Number of infos    :   56 (   0 filtered)

