Release 14.7 par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

athome::  Sat Mar 19 14:34:10 2016

par -w -ol high -xe n -intstyle xflow sys_w11a_s3_map.ncd sys_w11a_s3.ncd
sys_w11a_s3.pcf 


Constraints file: sys_w11a_s3.pcf.
Loading device for application Rf_Device from file '3s1000.nph' in environment
/mnt/data/opt/Xilinx/ISE/14.7/ISE_DS/ISE/.
   "sys_w11a_s3" is an NCD, version 3.2, device xc3s1000, package ft256, speed -4
WARNING:ConstraintSystem - The Offset constraint <OFFSET = IN 10 ns BEFORE COMP "I_CLK50";> [sys_w11a_s3.pcf(2648)], is
   specified without a duration.  This will result in a lack of hold time checks in timing reports.  If hold time checks
   are desired a duration value should be specified following the 'VALID' keyword.


Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.39 2013-10-13".


Device Utilization Summary:

   Number of BUFGMUXs                        1 out of 8      12%
   Number of External IOBs                  97 out of 173    56%
      Number of LOCed IOBs                  97 out of 97    100%

   Number of MULT18X18s                      1 out of 24      4%
   Number of RAMB16s                        14 out of 24     58%
   Number of Slices                       4666 out of 7680   60%
      Number of SLICEMs                    192 out of 3840    5%



Overall effort level (-ol):   High 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    High 
Extra effort level (-xe):     Normal 

Starting initial Timing Analysis.  REAL time: 5 secs 
Finished initial Timing Analysis.  REAL time: 6 secs 


Starting Placer
Total REAL time at the beginning of Placer: 6 secs 
Total CPU  time at the beginning of Placer: 5 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:9868888c) REAL time: 7 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:9868888c) REAL time: 7 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:9868888c) REAL time: 7 secs 

Phase 4.2  Initial Clock and IO Placement

Phase 4.2  Initial Clock and IO Placement (Checksum:190c0c84) REAL time: 9 secs 

Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:190c0c84) REAL time: 9 secs 

Phase 6.8  Global Placement
..........................
.............................................
..........................
......................................................................
..........................
.........................
........
.........
Phase 6.8  Global Placement (Checksum:f66461b3) REAL time: 38 secs 

Phase 7.5  Local Placement Optimization
Phase 7.5  Local Placement Optimization (Checksum:f66461b3) REAL time: 38 secs 

Phase 8.18  Placement Optimization
Phase 8.18  Placement Optimization (Checksum:fd78feb5) REAL time: 48 secs 

Phase 9.5  Local Placement Optimization
Phase 9.5  Local Placement Optimization (Checksum:fd78feb5) REAL time: 48 secs 

Total REAL time to Placer completion: 49 secs 
Total CPU  time to Placer completion: 46 secs 
Writing design to file sys_w11a_s3.ncd



Starting Router


Phase  1  : 34856 unrouted;      REAL time: 52 secs 

Phase  2  : 32524 unrouted;      REAL time: 53 secs 

Phase  3  : 9750 unrouted;      REAL time: 58 secs 

Phase  4  : 9803 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 7 secs 

Updating file: sys_w11a_s3.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 13 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 14 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 1 mins 16 secs 

Total REAL time to Router completion: 1 mins 17 secs 
Total CPU time to Router completion: 1 mins 12 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|       I_CLK50_BUFGP |      BUFGMUX0| No   | 2191 |  0.502     |  1.204      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_I_CLK50 = PERIOD TIMEGRP "I_CLK50" 20  | SETUP       |     0.069ns|    19.931ns|       0|           0
  ns HIGH 50%                               | HOLD        |     0.794ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  OFFSET = OUT 20 ns AFTER COMP "I_CLK50"   | MAXDELAY    |     5.256ns|    14.744ns|       0|           0
----------------------------------------------------------------------------------------------------------
  OFFSET = IN 10 ns BEFORE COMP "I_CLK50"   | SETUP       |     5.981ns|     4.019ns|       0|           0
----------------------------------------------------------------------------------------------------------


All constraints were met.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 1 mins 20 secs 
Total CPU time to PAR completion: 1 mins 15 secs 

Peak Memory Usage:  696 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 1
Number of info messages: 0

Writing design to file sys_w11a_s3.ncd



PAR done!
