Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
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Reading constraint file sys_w11a_n3.xcf.
XCF parsing done.
Reading design: /home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/ise/sys_w11a_n3.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/ise/sys_w11a_n3.prj"
Input Format                       : mixed
Synthesis Constraint File          : sys_w11a_n3.xcf
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "sys_w11a_n3"
Output Format                      : ngc
Target Device                      : xc6slx16-csg324-2

---- Source Options
Top Module Name                    : sys_w11a_n3
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Shift Register Extraction          : YES
Shift Register Minimum Size        : 3
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : SPEED
Optimization Effort                : 2
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : No
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/slvtypes.vhd" into library work
Parsing package <slvtypes>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/iblib.vhd" into library work
Parsing package <iblib>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ib_sel.vhd" into library work
Parsing entity <ib_sel>.
Parsing architecture <syn> of entity <ib_sel>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/rbus/rblib.vhd" into library work
Parsing package <rblib>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd" into library work
Parsing entity <ram_1swar_gen>.
Parsing architecture <syn> of entity <ram_1swar_gen>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11.vhd" into library work
Parsing package <pdp11>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vhd" into library work
Parsing entity <ram_1swar_1ar_gen>.
Parsing architecture <syn> of entity <ram_1swar_1ar_gen>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/memlib.vhd" into library work
Parsing package <memlib>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd" into library work
Parsing entity <ram_2swsr_xfirst_gen_unisim>.
Parsing architecture <syn> of entity <ram_2swsr_xfirst_gen_unisim>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/fifo_1c_dram_raw.vhd" into library work
Parsing entity <fifo_1c_dram_raw>.
Parsing architecture <syn> of entity <fifo_1c_dram_raw>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ib_sres_or_3.vhd" into library work
Parsing entity <ib_sres_or_3>.
Parsing architecture <syn> of entity <ib_sres_or_3>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_uart_rx.vhd" into library work
Parsing entity <serport_uart_rx>.
Parsing architecture <syn> of entity <serport_uart_rx>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_uart_tx.vhd" into library work
Parsing entity <serport_uart_tx>.
Parsing architecture <syn> of entity <serport_uart_tx>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serportlib.vhd" into library work
Parsing package <serportlib>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_mmu_sadr.vhd" into library work
Parsing entity <pdp11_mmu_sadr>.
Parsing architecture <syn> of entity <pdp11_mmu_sadr>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_mmu_ssr12.vhd" into library work
Parsing entity <pdp11_mmu_ssr12>.
Parsing architecture <syn> of entity <pdp11_mmu_ssr12>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd" into library work
Parsing entity <ram_2swsr_rfirst_gen>.
Parsing architecture <syn> of entity <ram_2swsr_rfirst_gen>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/genlib.vhd" into library work
Parsing package <genlib>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/fifo_1c_dram.vhd" into library work
Parsing entity <fifo_1c_dram>.
Parsing architecture <syn> of entity <fifo_1c_dram>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/xlib.vhd" into library work
Parsing package <xlib>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_i_gen.vhd" into library work
Parsing entity <iob_reg_i_gen>.
Parsing architecture <syn> of entity <iob_reg_i_gen>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_o_gen.vhd" into library work
Parsing entity <iob_reg_o_gen>.
Parsing architecture <syn> of entity <iob_reg_o_gen>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ib_sres_or_4.vhd" into library work
Parsing entity <ib_sres_or_4>.
Parsing architecture <syn> of entity <ib_sres_or_4>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/gray_cnt_4.vhd" into library work
Parsing entity <gray_cnt_4>.
Parsing architecture <syn> of entity <gray_cnt_4>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/rbus/rb_sres_or_2.vhd" into library work
Parsing entity <rb_sres_or_2>.
Parsing architecture <syn> of entity <rb_sres_or_2>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/gray_cnt_5.vhd" into library work
Parsing entity <gray_cnt_5>.
Parsing architecture <syn> of entity <gray_cnt_5>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd" into library work
Parsing entity <ram_1swsr_xfirst_gen_unisim>.
Parsing architecture <syn> of entity <ram_1swsr_xfirst_gen_unisim>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/comlib/comlib.vhd" into library work
Parsing package <comlib>.
Parsing package body <comlib>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/gray_cnt_n.vhd" into library work
Parsing entity <gray_cnt_n>.
Parsing architecture <syn> of entity <gray_cnt_n>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/bpgenlib.vhd" into library work
Parsing package <bpgenlib>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ib_sres_or_2.vhd" into library work
Parsing entity <ib_sres_or_2>.
Parsing architecture <syn> of entity <ib_sres_or_2>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/comlib/crc16.vhd" into library work
Parsing entity <crc16>.
Parsing architecture <syn> of entity <crc16>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/debounce_gen.vhd" into library work
Parsing entity <debounce_gen>.
Parsing architecture <syn> of entity <debounce_gen>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/gray2bin_gen.vhd" into library work
Parsing entity <gray2bin_gen>.
Parsing architecture <syn> of entity <gray2bin_gen>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/gray_cnt_gen.vhd" into library work
Parsing entity <gray_cnt_gen>.
Parsing architecture <syn> of entity <gray_cnt_gen>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/rbus/rb_sel.vhd" into library work
Parsing entity <rb_sel>.
Parsing architecture <syn> of entity <rb_sel>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/rlink/rlinklib.vhd" into library work
Parsing package <rlinklib>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_uart_autobaud.vhd" into library work
Parsing entity <serport_uart_autobaud>.
Parsing architecture <syn> of entity <serport_uart_autobaud>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_uart_rxtx.vhd" into library work
Parsing entity <serport_uart_rxtx>.
Parsing architecture <syn> of entity <serport_uart_rxtx>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_aunit.vhd" into library work
Parsing entity <pdp11_aunit>.
Parsing architecture <syn> of entity <pdp11_aunit>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_gpr.vhd" into library work
Parsing entity <pdp11_gpr>.
Parsing architecture <syn> of entity <pdp11_gpr>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_lunit.vhd" into library work
Parsing entity <pdp11_lunit>.
Parsing architecture <syn> of entity <pdp11_lunit>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_mmu.vhd" into library work
Parsing entity <pdp11_mmu>.
Parsing architecture <syn> of entity <pdp11_mmu>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_munit.vhd" into library work
Parsing entity <pdp11_munit>.
Parsing architecture <syn> of entity <pdp11_munit>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_ounit.vhd" into library work
Parsing entity <pdp11_ounit>.
Parsing architecture <syn> of entity <pdp11_ounit>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_psr.vhd" into library work
Parsing entity <pdp11_psr>.
Parsing architecture <syn> of entity <pdp11_psr>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_ubmap.vhd" into library work
Parsing entity <pdp11_ubmap>.
Parsing architecture <syn> of entity <pdp11_ubmap>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_o.vhd" into library work
Parsing entity <iob_reg_o>.
Parsing architecture <syn> of entity <iob_reg_o>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_conf.vhd" into library work
Parsing package <sys_conf>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd" into library work
Parsing entity <ram_1swsr_wfirst_gen>.
Parsing architecture <syn> of entity <ram_1swsr_wfirst_gen>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_i.vhd" into library work
Parsing entity <iob_reg_i>.
Parsing architecture <syn> of entity <iob_reg_i>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/rbus/rb_sres_or_4.vhd" into library work
Parsing entity <rb_sres_or_4>.
Parsing architecture <syn> of entity <rb_sres_or_4>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_io_gen.vhd" into library work
Parsing entity <iob_reg_io_gen>.
Parsing architecture <syn> of entity <iob_reg_io_gen>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/bp_swibtnled.vhd" into library work
Parsing entity <bp_swibtnled>.
Parsing architecture <syn> of entity <bp_swibtnled>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/sn_7segctl.vhd" into library work
Parsing entity <sn_7segctl>.
Parsing architecture <syn> of entity <sn_7segctl>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/comlib/byte2cdata.vhd" into library work
Parsing entity <byte2cdata>.
Parsing architecture <syn> of entity <byte2cdata>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/comlib/cdata2byte.vhd" into library work
Parsing entity <cdata2byte>.
Parsing architecture <syn> of entity <cdata2byte>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/fifo_2c_dram.vhd" into library work
Parsing entity <fifo_2c_dram>.
Parsing architecture <syn> of entity <fifo_2c_dram>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/rlink/rlink_core.vhd" into library work
Parsing entity <rlink_core>.
Parsing architecture <syn> of entity <rlink_core>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_uart_rxtx_ab.vhd" into library work
Parsing entity <serport_uart_rxtx_ab>.
Parsing architecture <syn> of entity <serport_uart_rxtx_ab>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_xonrx.vhd" into library work
Parsing entity <serport_xonrx>.
Parsing architecture <syn> of entity <serport_xonrx>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_xontx.vhd" into library work
Parsing entity <serport_xontx>.
Parsing architecture <syn> of entity <serport_xontx>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_decode.vhd" into library work
Parsing entity <pdp11_decode>.
Parsing architecture <syn> of entity <pdp11_decode>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmhbpt_unit.vhd" into library work
Parsing entity <pdp11_dmhbpt_unit>.
Parsing architecture <syn> of entity <pdp11_dmhbpt_unit>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dpath.vhd" into library work
Parsing entity <pdp11_dpath>.
Parsing architecture <syn> of entity <pdp11_dpath>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_irq.vhd" into library work
Parsing entity <pdp11_irq>.
Parsing architecture <syn> of entity <pdp11_irq>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_reg70.vhd" into library work
Parsing entity <pdp11_reg70>.
Parsing architecture <syn> of entity <pdp11_reg70>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_sequencer.vhd" into library work
Parsing entity <pdp11_sequencer>.
Parsing architecture <syn> of entity <pdp11_sequencer>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_vmbox.vhd" into library work
Parsing entity <pdp11_vmbox>.
Parsing architecture <syn> of entity <pdp11_vmbox>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/bplib/fx2lib/fx2lib.vhd" into library work
Parsing package <fx2lib>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ibdlib.vhd" into library work
Parsing package <ibdlib>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd" into library work
Parsing entity <bp_rs232_2line_iob>.
Parsing architecture <syn> of entity <bp_rs232_2line_iob>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd" into library work
Parsing entity <bp_rs232_4line_iob>.
Parsing architecture <syn> of entity <bp_rs232_4line_iob>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/sn_humanio.vhd" into library work
Parsing entity <sn_humanio>.
Parsing architecture <syn> of entity <sn_humanio>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/bplib/fx2lib/fx2_2fifoctl_ic.vhd" into library work
Parsing entity <fx2_2fifoctl_ic>.
Parsing architecture <syn> of entity <fx2_2fifoctl_ic>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ib_intmap.vhd" into library work
Parsing entity <ib_intmap>.
Parsing architecture <syn> of entity <ib_intmap>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ibd_ibmon.vhd" into library work
Parsing entity <ibd_ibmon>.
Parsing architecture <syn> of entity <ibd_ibmon>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ibd_iist.vhd" into library work
Parsing entity <ibd_iist>.
Parsing architecture <syn> of entity <ibd_iist>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ibd_kw11l.vhd" into library work
Parsing entity <ibd_kw11l>.
Parsing architecture <syn> of entity <ibd_kw11l>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_dl11.vhd" into library work
Parsing entity <ibdr_dl11>.
Parsing architecture <syn> of entity <ibdr_dl11>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_lp11.vhd" into library work
Parsing entity <ibdr_lp11>.
Parsing architecture <syn> of entity <ibdr_lp11>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_pc11.vhd" into library work
Parsing entity <ibdr_pc11>.
Parsing architecture <syn> of entity <ibdr_pc11>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_rhrp.vhd" into library work
Parsing entity <ibdr_rhrp>.
Parsing architecture <syn> of entity <ibdr_rhrp>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_rk11.vhd" into library work
Parsing entity <ibdr_rk11>.
Parsing architecture <syn> of entity <ibdr_rk11>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_rl11.vhd" into library work
Parsing entity <ibdr_rl11>.
Parsing architecture <syn> of entity <ibdr_rl11>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_sdreg.vhd" into library work
Parsing entity <ibdr_sdreg>.
Parsing architecture <syn> of entity <ibdr_sdreg>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_tm11.vhd" into library work
Parsing entity <ibdr_tm11>.
Parsing architecture <syn> of entity <ibdr_tm11>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/led_pulse_stretch.vhd" into library work
Parsing entity <led_pulse_stretch>.
Parsing architecture <syn> of entity <led_pulse_stretch>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/rbus/rbd_rbmon.vhd" into library work
Parsing entity <rbd_rbmon>.
Parsing architecture <syn> of entity <rbd_rbmon>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/rlink/rlink_core8.vhd" into library work
Parsing entity <rlink_core8>.
Parsing architecture <syn> of entity <rlink_core8>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/rlink/rlink_rlbmux.vhd" into library work
Parsing entity <rlink_rlbmux>.
Parsing architecture <syn> of entity <rlink_rlbmux>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_1clock.vhd" into library work
Parsing entity <serport_1clock>.
Parsing architecture <syn> of entity <serport_1clock>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_cache.vhd" into library work
Parsing entity <pdp11_cache>.
Parsing architecture <syn> of entity <pdp11_cache>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_core.vhd" into library work
Parsing entity <pdp11_core>.
Parsing architecture <syn> of entity <pdp11_core>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_core_rbus.vhd" into library work
Parsing entity <pdp11_core_rbus>.
Parsing architecture <syn> of entity <pdp11_core_rbus>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmcmon.vhd" into library work
Parsing entity <pdp11_dmcmon>.
Parsing architecture <syn> of entity <pdp11_dmcmon>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmhbpt.vhd" into library work
Parsing entity <pdp11_dmhbpt>.
Parsing architecture <syn> of entity <pdp11_dmhbpt>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmscnt.vhd" into library work
Parsing entity <pdp11_dmscnt>.
Parsing architecture <syn> of entity <pdp11_dmscnt>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dspmux.vhd" into library work
Parsing entity <pdp11_dspmux>.
Parsing architecture <syn> of entity <pdp11_dspmux>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_ledmux.vhd" into library work
Parsing entity <pdp11_ledmux>.
Parsing architecture <syn> of entity <pdp11_ledmux>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_mem70.vhd" into library work
Parsing entity <pdp11_mem70>.
Parsing architecture <syn> of entity <pdp11_mem70>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_statleds.vhd" into library work
Parsing entity <pdp11_statleds>.
Parsing architecture <syn> of entity <pdp11_statleds>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/rbus/rbdlib.vhd" into library work
Parsing package <rbdlib>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd" into library work
Parsing entity <bp_rs232_2l4l_iob>.
Parsing architecture <syn> of entity <bp_rs232_2l4l_iob>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/bpgenrbuslib.vhd" into library work
Parsing package <bpgenrbuslib>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/sn_humanio_rbus.vhd" into library work
Parsing entity <sn_humanio_rbus>.
Parsing architecture <syn> of entity <sn_humanio_rbus>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/bplib/fx2rlink/fx2rlinklib.vhd" into library work
Parsing package <fx2rlinklib>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/bplib/fx2rlink/ioleds_sp1c_fx2.vhd" into library work
Parsing entity <ioleds_sp1c_fx2>.
Parsing architecture <syn> of entity <ioleds_sp1c_fx2>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd" into library work
Parsing entity <rlink_sp1c_fx2>.
Parsing architecture <syn> of entity <rlink_sp1c_fx2>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd" into library work
Parsing entity <nx_cram_memctl_as>.
Parsing architecture <syn> of entity <nx_cram_memctl_as>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_maxisys.vhd" into library work
Parsing entity <ibdr_maxisys>.
Parsing architecture <syn> of entity <ibdr_maxisys>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/clkdivce.vhd" into library work
Parsing entity <clkdivce>.
Parsing architecture <syn> of entity <clkdivce>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/s6_cmt_sfs_unisim.vhd" into library work
Parsing entity <s6_cmt_sfs>.
Parsing architecture <syn> of entity <s6_cmt_sfs>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_hio70.vhd" into library work
Parsing entity <pdp11_hio70>.
Parsing architecture <syn> of entity <pdp11_hio70>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_sys70.vhd" into library work
Parsing entity <pdp11_sys70>.
Parsing architecture <syn> of entity <pdp11_sys70>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/bplib/nxcramlib/nxcramlib.vhd" into library work
Parsing package <nxcramlib>.
Parsing VHDL file "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" into library work
Parsing entity <sys_w11a_n3>.
Parsing architecture <syn> of entity <sys_w11a_n3>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <sys_w11a_n3> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:871 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" Line 188: Using initial value '0' for reset since it is never assigned

Elaborating entity <s6_cmt_sfs> (architecture <syn>) with generics from library <work>.

Elaborating entity <clkdivce> (architecture <syn>) with generics from library <work>.

Elaborating entity <bp_rs232_2l4l_iob> (architecture <syn>) with generics from library <work>.

Elaborating entity <bp_rs232_2line_iob> (architecture <syn>) from library <work>.

Elaborating entity <iob_reg_i> (architecture <syn>) with generics from library <work>.

Elaborating entity <iob_reg_i_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <iob_reg_o> (architecture <syn>) with generics from library <work>.

Elaborating entity <iob_reg_o_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <bp_rs232_4line_iob> (architecture <syn>) from library <work>.

Elaborating entity <iob_reg_i> (architecture <syn>) with generics from library <work>.

Elaborating entity <iob_reg_i_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <iob_reg_o> (architecture <syn>) with generics from library <work>.

Elaborating entity <iob_reg_o_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <rlink_sp1c_fx2> (architecture <syn>) with generics from library <work>.

Elaborating entity <rlink_core8> (architecture <syn>) with generics from library <work>.

Elaborating entity <rlink_core> (architecture <syn>) with generics from library <work>.

Elaborating entity <ram_2swsr_rfirst_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <ram_2swsr_xfirst_gen_unisim> (architecture <syn>) with generics from library <work>.

Elaborating entity <fifo_1c_dram> (architecture <syn>) with generics from library <work>.

Elaborating entity <fifo_1c_dram_raw> (architecture <syn>) with generics from library <work>.

Elaborating entity <ram_1swar_1ar_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <crc16> (architecture <syn>) with generics from library <work>.

Elaborating entity <rb_sel> (architecture <syn>) with generics from library <work>.

Elaborating entity <rb_sres_or_2> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:314 - "/build/xfndry10/P.20131013/rtf/vhdl/xst/src/std_1164.vhd" Line 1037: Choice with meta-value 'U' is ignored for synthesis
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/vlib/rlink/rlink_core.vhd" Line 1225. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/vlib/rlink/rlink_core.vhd" Line 1390. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/vlib/rlink/rlink_core.vhd" Line 1532. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/vlib/rlink/rlink_core.vhd" Line 1614. Case statement is complete. others clause is never selected

Elaborating entity <byte2cdata> (architecture <syn>) from library <work>.

Elaborating entity <cdata2byte> (architecture <syn>) from library <work>.

Elaborating entity <serport_1clock> (architecture <syn>) with generics from library <work>.

Elaborating entity <serport_uart_rxtx_ab> (architecture <syn>) with generics from library <work>.

Elaborating entity <serport_uart_autobaud> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_uart_autobaud.vhd" Line 168. Case statement is complete. others clause is never selected

Elaborating entity <serport_uart_rxtx> (architecture <syn>) with generics from library <work>.

Elaborating entity <serport_uart_rx> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_uart_rx.vhd" Line 268. Case statement is complete. others clause is never selected

Elaborating entity <serport_uart_tx> (architecture <syn>) with generics from library <work>.

Elaborating entity <serport_xonrx> (architecture <syn>) from library <work>.

Elaborating entity <serport_xontx> (architecture <syn>) from library <work>.

Elaborating entity <rlink_rlbmux> (architecture <syn>) from library <work>.

Elaborating entity <fx2_2fifoctl_ic> (architecture <syn>) with generics from library <work>.

Elaborating entity <iob_reg_o_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <iob_reg_i_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <iob_reg_io_gen> (architecture <syn>) with generics from library <work>.
WARNING:HDLCompiler:321 - "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_io_gen.vhd" Line 73: Comparison between arrays of unequal length always returns FALSE.

Elaborating entity <fifo_2c_dram> (architecture <syn>) with generics from library <work>.

Elaborating entity <gray_cnt_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <gray_cnt_5> (architecture <syn>) from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/gray_cnt_5.vhd" Line 114. Case statement is complete. others clause is never selected

Elaborating entity <gray2bin_gen> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/bplib/fx2lib/fx2_2fifoctl_ic.vhd" Line 459. Case statement is complete. others clause is never selected

Elaborating entity <rbd_rbmon> (architecture <syn>) with generics from library <work>.

Elaborating entity <ram_1swsr_wfirst_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <ram_1swsr_xfirst_gen_unisim> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/vlib/rbus/rbd_rbmon.vhd" Line 350. Case statement is complete. others clause is never selected

Elaborating entity <pdp11_sys70> (architecture <syn>) from library <work>.

Elaborating entity <pdp11_core_rbus> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_core_rbus.vhd" Line 393. Case statement is complete. others clause is never selected

Elaborating entity <pdp11_core> (architecture <syn>) from library <work>.

Elaborating entity <pdp11_vmbox> (architecture <syn>) from library <work>.

Elaborating entity <pdp11_mmu> (architecture <syn>) from library <work>.

Elaborating entity <pdp11_mmu_sadr> (architecture <syn>) from library <work>.

Elaborating entity <ram_1swar_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <ram_1swar_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <ram_1swar_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <ram_1swar_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <pdp11_mmu_ssr12> (architecture <syn>) from library <work>.

Elaborating entity <ib_sel> (architecture <syn>) with generics from library <work>.

Elaborating entity <ib_sel> (architecture <syn>) with generics from library <work>.

Elaborating entity <ib_sres_or_3> (architecture <syn>) from library <work>.

Elaborating entity <ib_sel> (architecture <syn>) with generics from library <work>.

Elaborating entity <ib_sel> (architecture <syn>) with generics from library <work>.

Elaborating entity <pdp11_ubmap> (architecture <syn>) from library <work>.

Elaborating entity <ram_1swar_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <ram_1swar_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <ram_1swar_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <ib_sel> (architecture <syn>) with generics from library <work>.

Elaborating entity <ib_sres_or_4> (architecture <syn>) from library <work>.

Elaborating entity <ib_sres_or_2> (architecture <syn>) from library <work>.

Elaborating entity <ib_sel> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_vmbox.vhd" Line 618. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_vmbox.vhd" Line 651. Case statement is complete. others clause is never selected

Elaborating entity <pdp11_dpath> (architecture <syn>) from library <work>.

Elaborating entity <pdp11_gpr> (architecture <syn>) from library <work>.

Elaborating entity <ram_1swar_1ar_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <pdp11_psr> (architecture <syn>) from library <work>.

Elaborating entity <ib_sel> (architecture <syn>) with generics from library <work>.

Elaborating entity <pdp11_ounit> (architecture <syn>) from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_ounit.vhd" Line 79. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_ounit.vhd" Line 92. Case statement is complete. others clause is never selected

Elaborating entity <pdp11_aunit> (architecture <syn>) from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_aunit.vhd" Line 127. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_aunit.vhd" Line 135. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_aunit.vhd" Line 143. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_aunit.vhd" Line 234. Case statement is complete. others clause is never selected

Elaborating entity <pdp11_lunit> (architecture <syn>) from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_lunit.vhd" Line 132. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_lunit.vhd" Line 174. Case statement is complete. others clause is never selected

Elaborating entity <pdp11_munit> (architecture <syn>) from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_munit.vhd" Line 406. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_munit.vhd" Line 428. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_munit.vhd" Line 475. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dpath.vhd" Line 227. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dpath.vhd" Line 243. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dpath.vhd" Line 281. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dpath.vhd" Line 321. Case statement is complete. others clause is never selected

Elaborating entity <pdp11_decode> (architecture <syn>) from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_decode.vhd" Line 318. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_decode.vhd" Line 347. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_decode.vhd" Line 512. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_decode.vhd" Line 524. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_decode.vhd" Line 537. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_decode.vhd" Line 550. Case statement is complete. others clause is never selected

Elaborating entity <pdp11_sequencer> (architecture <syn>) from library <work>.

Elaborating entity <ib_sel> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_sequencer.vhd" Line 930. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_sequencer.vhd" Line 470. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_sequencer.vhd" Line 940. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_sequencer.vhd" Line 470. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_sequencer.vhd" Line 470. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_sequencer.vhd" Line 470. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_sequencer.vhd" Line 1638. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_sequencer.vhd" Line 1989. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_sequencer.vhd" Line 2334. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_sequencer.vhd" Line 2531. Case statement is complete. others clause is never selected

Elaborating entity <pdp11_irq> (architecture <syn>) from library <work>.

Elaborating entity <ib_sel> (architecture <syn>) with generics from library <work>.

Elaborating entity <pdp11_reg70> (architecture <syn>) from library <work>.

Elaborating entity <pdp11_cache> (architecture <syn>) from library <work>.

Elaborating entity <ram_2swsr_rfirst_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <ram_2swsr_xfirst_gen_unisim> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_cache.vhd" Line 393. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_cache.vhd" Line 434. Case statement is complete. others clause is never selected

Elaborating entity <pdp11_mem70> (architecture <syn>) from library <work>.

Elaborating entity <ibd_ibmon> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibd_ibmon.vhd" Line 372. Case statement is complete. others clause is never selected

Elaborating entity <pdp11_dmscnt> (architecture <syn>) with generics from library <work>.

Elaborating entity <ram_2swsr_rfirst_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <ram_2swsr_xfirst_gen_unisim> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmscnt.vhd" Line 272. Case statement is complete. others clause is never selected

Elaborating entity <pdp11_dmcmon> (architecture <syn>) with generics from library <work>.

Elaborating entity <ram_1swar_1ar_gen> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmcmon.vhd" Line 524. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmcmon.vhd" Line 574. Case statement is complete. others clause is never selected

Elaborating entity <pdp11_dmhbpt> (architecture <syn>) with generics from library <work>.

Elaborating entity <pdp11_dmhbpt_unit> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmhbpt_unit.vhd" Line 201. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmhbpt_unit.vhd" Line 221. Case statement is complete. others clause is never selected

Elaborating entity <pdp11_dmhbpt_unit> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmhbpt_unit.vhd" Line 201. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmhbpt_unit.vhd" Line 221. Case statement is complete. others clause is never selected

Elaborating entity <rb_sres_or_4> (architecture <syn>) from library <work>.

Elaborating entity <ibdr_maxisys> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:871 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_maxisys.vhd" Line 138: Using initial value '0' for rb_lam_denua since it is never assigned
WARNING:HDLCompiler:871 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_maxisys.vhd" Line 143: Using initial value '0' for rb_lam_dz11 since it is never assigned
WARNING:HDLCompiler:871 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_maxisys.vhd" Line 150: Using initial value ('0','0',"0000000000000000") for ib_sres_kw11p since it is never assigned
WARNING:HDLCompiler:871 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_maxisys.vhd" Line 152: Using initial value ('0','0',"0000000000000000") for ib_sres_deuna since it is never assigned
WARNING:HDLCompiler:871 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_maxisys.vhd" Line 157: Using initial value ('0','0',"0000000000000000") for ib_sres_dz11 since it is never assigned
WARNING:HDLCompiler:871 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_maxisys.vhd" Line 180: Using initial value '0' for ei_req_dz11rx since it is never assigned
WARNING:HDLCompiler:871 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_maxisys.vhd" Line 181: Using initial value '0' for ei_req_dz11tx since it is never assigned
WARNING:HDLCompiler:871 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_maxisys.vhd" Line 211: Using initial value "00" for iist_sres since it is never assigned

Elaborating entity <ibd_iist> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibd_iist.vhd" Line 355. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:1127 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibd_iist.vhd" Line 242: Assignment to ibrd ignored, since the identifier is never used

Elaborating entity <ibd_kw11l> (architecture <syn>) from library <work>.

Elaborating entity <ibdr_rhrp> (architecture <syn>) from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_rhrp.vhd" Line 1373. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_rhrp.vhd" Line 1398. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:1127 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_rhrp.vhd" Line 448: Assignment to ibrd ignored, since the identifier is never used

Elaborating entity <ibdr_rl11> (architecture <syn>) from library <work>.

Elaborating entity <ram_1swar_gen> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_rl11.vhd" Line 514. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_rl11.vhd" Line 634. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:1127 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_rl11.vhd" Line 284: Assignment to ibwrem ignored, since the identifier is never used

Elaborating entity <ibdr_rk11> (architecture <syn>) from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_rk11.vhd" Line 282. Case statement is complete. others clause is never selected
WARNING:HDLCompiler:1127 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_rk11.vhd" Line 217: Assignment to ibrd ignored, since the identifier is never used

Elaborating entity <ibdr_tm11> (architecture <syn>) from library <work>.
WARNING:HDLCompiler:1127 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_tm11.vhd" Line 187: Assignment to ibrd ignored, since the identifier is never used

Elaborating entity <ibdr_dl11> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_dl11.vhd" Line 273. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_dl11.vhd" Line 306. Case statement is complete. others clause is never selected

Elaborating entity <ibdr_dl11> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_dl11.vhd" Line 273. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_dl11.vhd" Line 306. Case statement is complete. others clause is never selected

Elaborating entity <ibdr_pc11> (architecture <syn>) from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_pc11.vhd" Line 297. Case statement is complete. others clause is never selected

Elaborating entity <ibdr_lp11> (architecture <syn>) from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_lp11.vhd" Line 195. Case statement is complete. others clause is never selected

Elaborating entity <ibdr_sdreg> (architecture <syn>) from library <work>.

Elaborating entity <ib_intmap> (architecture <syn>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_maxisys.vhd" Line 465: Assignment to ei_ack_dz11rx ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_maxisys.vhd" Line 466: Assignment to ei_ack_dz11tx ignored, since the identifier is never used

Elaborating entity <nx_cram_memctl_as> (architecture <syn>) with generics from library <work>.

Elaborating entity <iob_reg_o_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <iob_reg_o_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <iob_reg_io_gen> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd" Line 539. Case statement is complete. others clause is never selected

Elaborating entity <ioleds_sp1c_fx2> (architecture <syn>) from library <work>.

Elaborating entity <led_pulse_stretch> (architecture <syn>) from library <work>.

Elaborating entity <pdp11_hio70> (architecture <syn>) with generics from library <work>.

Elaborating entity <pdp11_statleds> (architecture <syn>) from library <work>.

Elaborating entity <pdp11_ledmux> (architecture <syn>) with generics from library <work>.

Elaborating entity <pdp11_dspmux> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dspmux.vhd" Line 92. Case statement is complete. others clause is never selected

Elaborating entity <sn_humanio_rbus> (architecture <syn>) with generics from library <work>.

Elaborating entity <sn_humanio> (architecture <syn>) with generics from library <work>.

Elaborating entity <iob_reg_o_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <iob_reg_o_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <bp_swibtnled> (architecture <syn>) with generics from library <work>.

Elaborating entity <iob_reg_i_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <iob_reg_i_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <debounce_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <debounce_gen> (architecture <syn>) with generics from library <work>.

Elaborating entity <sn_7segctl> (architecture <syn>) with generics from library <work>.
INFO:HDLCompiler:679 - "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/sn_humanio_rbus.vhd" Line 345. Case statement is complete. others clause is never selected

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <sys_w11a_n3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd".
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 256: Output port <LOCKED> of the instance <GEN_CLKSYS> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 299: Output port <RL_MONI_eop> of the instance <RLINK> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 299: Output port <RL_MONI_attn> of the instance <RLINK> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 299: Output port <RL_MONI_lamp> of the instance <RLINK> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 299: Output port <FX2_MONI_fifo_ep4> of the instance <RLINK> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 299: Output port <FX2_MONI_fifo_ep6> of the instance <RLINK> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 299: Output port <FX2_MONI_fifo_ep8> of the instance <RLINK> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 299: Output port <FX2_MONI_flag_ep4_empty> of the instance <RLINK> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 299: Output port <FX2_MONI_flag_ep4_almost> of the instance <RLINK> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 299: Output port <FX2_MONI_flag_ep6_full> of the instance <RLINK> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 299: Output port <FX2_MONI_flag_ep6_almost> of the instance <RLINK> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 299: Output port <FX2_MONI_flag_ep8_full> of the instance <RLINK> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 299: Output port <FX2_MONI_flag_ep8_almost> of the instance <RLINK> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 299: Output port <FX2_MONI_slrd> of the instance <RLINK> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 299: Output port <FX2_MONI_slwr> of the instance <RLINK> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 299: Output port <FX2_MONI_pktend> of the instance <RLINK> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 344: Output port <CRESET> of the instance <SYS70> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 393: Output port <ACK_W> of the instance <SRAM_CTL> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd" line 458: Output port <BTN> of the instance <HIO> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <sys_w11a_n3> synthesized.

Synthesizing Unit <s6_cmt_sfs>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/s6_cmt_sfs_unisim.vhd".
        VCO_DIVIDE = 25
        VCO_MULTIPLY = 16
        OUT_DIVIDE = 1
        CLKIN_PERIOD = 10.0
        CLKIN_JITTER = 0.01
        STARTUP_WAIT = false
        GEN_TYPE = "DCM"
    Summary:
	no macro.
Unit <s6_cmt_sfs> synthesized.

Synthesizing Unit <clkdivce>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/clkdivce.vhd".
        CDUWIDTH = 7
        USECDIV = 64
        MSECDIV = 1000
    Found 10-bit register for signal <R_REGS_mcnt>.
    Found 1-bit register for signal <R_REGS_usec>.
    Found 1-bit register for signal <R_REGS_msec>.
    Found 7-bit register for signal <R_REGS_ucnt>.
    Found 7-bit subtractor for signal <GND_28_o_GND_28_o_sub_3_OUT<6:0>> created at line 1308.
    Found 10-bit subtractor for signal <GND_28_o_GND_28_o_sub_5_OUT<9:0>> created at line 1308.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  19 D-type flip-flop(s).
Unit <clkdivce> synthesized.

Synthesizing Unit <bp_rs232_2l4l_iob>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd".
        RELAY = false
    Found 1-bit register for signal <R_CTS_N>.
    Found 1-bit register for signal <R_TXD0>.
    Found 1-bit register for signal <R_TXD1>.
    Found 1-bit register for signal <R_RTS1_N>.
    Found 1-bit register for signal <R_RXD>.
    Summary:
	inferred   5 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <bp_rs232_2l4l_iob> synthesized.

Synthesizing Unit <bp_rs232_2line_iob>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/bp_rs232_2line_iob.vhd".
    Summary:
	no macro.
Unit <bp_rs232_2line_iob> synthesized.

Synthesizing Unit <iob_reg_i_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_i.vhd".
        INIT = '1'
    Summary:
	no macro.
Unit <iob_reg_i_1> synthesized.

Synthesizing Unit <iob_reg_i_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_i_gen.vhd".
        DWIDTH = 1
        INIT = '1'
    Set property "IOB = TRUE" for signal <R_DI>.
    Found 1-bit register for signal <R_DI>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <iob_reg_i_gen_1> synthesized.

Synthesizing Unit <iob_reg_o_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_o.vhd".
        INIT = '1'
    Summary:
	no macro.
Unit <iob_reg_o_1> synthesized.

Synthesizing Unit <iob_reg_o_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_o_gen.vhd".
        DWIDTH = 1
        INIT = '1'
    Set property "IOB = TRUE" for signal <R_DO>.
    Found 1-bit register for signal <R_DO>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <iob_reg_o_gen_1> synthesized.

Synthesizing Unit <bp_rs232_4line_iob>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/bp_rs232_4line_iob.vhd".
    Summary:
	no macro.
Unit <bp_rs232_4line_iob> synthesized.

Synthesizing Unit <iob_reg_i_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_i.vhd".
        INIT = '0'
    Summary:
	no macro.
Unit <iob_reg_i_2> synthesized.

Synthesizing Unit <iob_reg_i_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_i_gen.vhd".
        DWIDTH = 1
        INIT = '0'
    Set property "IOB = TRUE" for signal <R_DI>.
    Found 1-bit register for signal <R_DI>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <iob_reg_i_gen_2> synthesized.

Synthesizing Unit <iob_reg_o_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_o.vhd".
        INIT = '0'
    Summary:
	no macro.
Unit <iob_reg_o_2> synthesized.

Synthesizing Unit <iob_reg_o_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_o_gen.vhd".
        DWIDTH = 1
        INIT = '0'
    Set property "IOB = TRUE" for signal <R_DO>.
    Found 1-bit register for signal <R_DO>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <iob_reg_o_gen_2> synthesized.

Synthesizing Unit <rlink_sp1c_fx2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd".
        BTOWIDTH = 7
        RTAWIDTH = 12
        SYSID = "00000000000000000000000000000000"
        IFAWIDTH = 5
        OFAWIDTH = 5
        PETOWIDTH = 10
        CCWIDTH = 5
        ENAPIN_RLMON = 15
        ENAPIN_RLBMON = -1
        ENAPIN_RBMON = 13
        CDWIDTH = 13
        CDINIT = 554
        RBMON_AWIDTH = 9
        RBMON_RBADDR = "1111111111101000"
WARNING:Xst:647 - Input <CE_USEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd" line 213: Output port <RXAEMPTY> of the instance <FX2CNTL> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd" line 213: Output port <TXAFULL> of the instance <FX2CNTL> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <rlink_sp1c_fx2> synthesized.

Synthesizing Unit <rlink_core8>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/rlink/rlink_core8.vhd".
        BTOWIDTH = 7
        RTAWIDTH = 12
        SYSID = "00000000000000000000000000000000"
        ENAPIN_RLMON = 15
        ENAPIN_RLBMON = -1
        ENAPIN_RBMON = 13
    Summary:
	no macro.
Unit <rlink_core8> synthesized.

Synthesizing Unit <rlink_core>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/rlink/rlink_core.vhd".
        BTOWIDTH = 7
        RTAWIDTH = 12
        SYSID = "00000000000000000000000000000000"
        ENAPIN_RLMON = 15
        ENAPIN_RBMON = 13
    Set property "fsm_encoding = one-hot".
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/vlib/rlink/rlink_core.vhd" line 441: Output port <DOA> of the instance <RTBUF> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/vlib/rlink/rlink_core.vhd" line 460: Output port <BUSY> of the instance <DOFIFO> is unconnected or connected to loadless signal.
    Found 8-bit register for signal <R_LREGS_rcmd>.
    Found 8-bit register for signal <R_LREGS_lcmd>.
    Found 16-bit register for signal <R_LREGS_addr>.
    Found 16-bit register for signal <R_LREGS_din>.
    Found 16-bit register for signal <R_LREGS_cnt>.
    Found 12-bit register for signal <R_LREGS_bcnt>.
    Found 16-bit register for signal <R_LREGS_attn>.
    Found 1-bit register for signal <R_LREGS_anreq>.
    Found 1-bit register for signal <R_LREGS_anact>.
    Found 1-bit register for signal <RL_MONI_lamp>.
    Found 8-bit register for signal <R_LREGS_atocnt>.
    Found 1-bit register for signal <R_LREGS_babo>.
    Found 1-bit register for signal <R_LREGS_nakdone>.
    Found 3-bit register for signal <R_LREGS_nakcode>.
    Found 1-bit register for signal <R_LREGS_cmdseen>.
    Found 1-bit register for signal <R_LREGS_doretra>.
    Found 8-bit register for signal <R_LREGS_dinl>.
    Found 12-bit register for signal <R_LREGS_rtaddra>.
    Found 1-bit register for signal <R_LREGS_rtaddra_red>.
    Found 1-bit register for signal <R_LREGS_rtaddra_bad>.
    Found 12-bit register for signal <R_LREGS_rtaddrb>.
    Found 1-bit register for signal <R_LREGS_rtaddrb_red>.
    Found 1-bit register for signal <R_LREGS_rtaddrb_bad>.
    Found 1-bit register for signal <RL_MONI_eop>.
    Found 1-bit register for signal <RL_MONI_attn>.
    Found 4-bit register for signal <R_BREGS_state>.
    Found 1-bit register for signal <R_BREGS_rbinit>.
    Found 1-bit register for signal <R_BREGS_rbaval>.
    Found 1-bit register for signal <R_BREGS_rbre>.
    Found 1-bit register for signal <R_BREGS_rbwe>.
    Found 16-bit register for signal <R_BREGS_rbdout>.
    Found 1-bit register for signal <R_BREGS_rbtout>.
    Found 1-bit register for signal <R_BREGS_rbnak>.
    Found 1-bit register for signal <R_BREGS_rberr>.
    Found 1-bit register for signal <R_BREGS_blkabo>.
    Found 11-bit register for signal <R_BREGS_cnt>.
    Found 11-bit register for signal <R_BREGS_dcnt>.
    Found 7-bit register for signal <R_BREGS_btocnt>.
    Found 1-bit register for signal <R_BREGS_dathpend>.
    Found 1-bit register for signal <R_BREGS_wfifo>.
    Found 4-bit register for signal <R_BREGS_stat>.
    Found 1-bit register for signal <R_CREGS_anena>.
    Found 1-bit register for signal <R_CREGS_atoena>.
    Found 8-bit register for signal <R_CREGS_atoval>.
    Found 6-bit register for signal <R_LREGS_state>.
    Found finite state machine <FSM_0> for signal <R_BREGS_state>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 27                                             |
    | Inputs             | 7                                              |
    | Outputs            | 13                                             |
    | Clock              | CLK (rising_edge)                              |
    | Power Up State     | sb_idle                                        |
    | Encoding           | one-hot                                        |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_1> for signal <R_LREGS_state>.
    -----------------------------------------------------------------------
    | States             | 40                                             |
    | Transitions        | 130                                            |
    | Inputs             | 27                                             |
    | Outputs            | 12                                             |
    | Clock              | CLK (rising_edge)                              |
    | Power Up State     | sl_idle                                        |
    | Encoding           | one-hot                                        |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 12-bit adder for signal <R_LREGS_rtaddra[11]_GND_46_o_add_222_OUT> created at line 1241.
    Found 12-bit adder for signal <R_LREGS_rtaddrb[11]_GND_46_o_add_228_OUT> created at line 1241.
    Found 11-bit adder for signal <R_BREGS_dcnt[10]_GND_46_o_add_314_OUT> created at line 1241.
    Found 8-bit subtractor for signal <GND_46_o_GND_46_o_sub_48_OUT<7:0>> created at line 1308.
    Found 12-bit subtractor for signal <GND_46_o_GND_46_o_sub_234_OUT<11:0>> created at line 1308.
    Found 7-bit subtractor for signal <GND_46_o_GND_46_o_sub_310_OUT<6:0>> created at line 1308.
    Found 11-bit subtractor for signal <GND_46_o_GND_46_o_sub_312_OUT<10:0>> created at line 1308.
    Found 8x2-bit Read Only RAM for signal <_n2064>
    Found 16-bit 3-to-1 multiplexer for signal <RB_MREQ_L_addr[1]_R_CREGS_anena_wide_mux_334_OUT> created at line 1600.
    Found 8-bit comparator equal for signal <n0223> created at line 1053
    Found 8-bit comparator equal for signal <ICRC_OUT[15]_INV_129_o> created at line 1071
    Found 6-bit comparator greater for signal <n0411> created at line 1356
    Found 6-bit comparator lessequal for signal <n0413> created at line 1358
    Summary:
	inferred   1 RAM(s).
	inferred   7 Adder/Subtractor(s).
	inferred 217 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred 148 Multiplexer(s).
	inferred   2 Finite State Machine(s).
Unit <rlink_core> synthesized.

Synthesizing Unit <ram_2swsr_rfirst_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd".
        AWIDTH = 12
        DWIDTH = 8
    Summary:
	no macro.
Unit <ram_2swsr_rfirst_gen_1> synthesized.

Synthesizing Unit <ram_2swsr_xfirst_gen_unisim_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd".
        AWIDTH = 12
        DWIDTH = 8
        WRITE_MODE = "READ_FIRST"
    Summary:
	no macro.
Unit <ram_2swsr_xfirst_gen_unisim_1> synthesized.

Synthesizing Unit <fifo_1c_dram>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/fifo_1c_dram.vhd".
        AWIDTH = 5
        DWIDTH = 8
    Summary:
	no macro.
Unit <fifo_1c_dram> synthesized.

Synthesizing Unit <fifo_1c_dram_raw>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/fifo_1c_dram_raw.vhd".
        AWIDTH = 5
        DWIDTH = 8
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/fifo_1c_dram_raw.vhd" line 79: Output port <DOA> of the instance <RAM> is unconnected or connected to loadless signal.
    Found 5-bit register for signal <R_REGS_raddr>.
    Found 1-bit register for signal <R_REGS_empty>.
    Found 1-bit register for signal <R_REGS_full>.
    Found 5-bit register for signal <R_REGS_waddr>.
    Found 5-bit adder for signal <R_REGS_waddr[4]_GND_54_o_add_3_OUT> created at line 1241.
    Found 5-bit adder for signal <R_REGS_raddr[4]_GND_54_o_add_6_OUT> created at line 1241.
    Found 5-bit subtractor for signal <proc_next.isize> created at line 107.
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred  12 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <fifo_1c_dram_raw> synthesized.

Synthesizing Unit <ram_1swar_1ar_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vhd".
        AWIDTH = 5
        DWIDTH = 8
    Summary:
	inferred   2 Multiplexer(s).
Unit <ram_1swar_1ar_gen_1> synthesized.

Synthesizing Unit <crc16>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/comlib/crc16.vhd".
        INIT = "0000000000000000"
    Found 16-bit register for signal <R_CRC>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <crc16> synthesized.

Synthesizing Unit <rb_sel>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/rbus/rb_sel.vhd".
        RB_ADDR = "1111111111111100"
        SAWIDTH = 2
WARNING:Xst:647 - Input <RB_MREQ_addr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ_din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ_re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ_init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <rb_sel> synthesized.

Synthesizing Unit <rb_sres_or_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/rbus/rb_sres_or_2.vhd".
    Summary:
	no macro.
Unit <rb_sres_or_2> synthesized.

Synthesizing Unit <byte2cdata>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/comlib/byte2cdata.vhd".
    Found 1-bit register for signal <R_REGS_dataval>.
    Found 1-bit register for signal <R_REGS_edpend>.
    Found 9-bit register for signal <R_REGS_data>.
    Found 3-bit comparator equal for signal <DI[2]_DI[5]_equal_5_o> created at line 104
    Summary:
	inferred  11 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   3 Multiplexer(s).
Unit <byte2cdata> synthesized.

Synthesizing Unit <cdata2byte>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/comlib/cdata2byte.vhd".
    Found 3-bit register for signal <R_REGS_ecode>.
    Found 1-bit register for signal <R_REGS_dataval>.
    Found 1-bit register for signal <R_REGS_ecodeval>.
    Found 8-bit register for signal <R_REGS_data>.
    Summary:
	inferred  13 D-type flip-flop(s).
	inferred   7 Multiplexer(s).
Unit <cdata2byte> synthesized.

Synthesizing Unit <serport_1clock>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_1clock.vhd".
        CDWIDTH = 13
        CDINIT = 554
        RXFAWIDTH = 5
        TXFAWIDTH = 5
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_1clock.vhd" line 188: Output port <SIZE> of the instance <TXFIFO> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <R_RXOK>.
    Found 3-bit comparator lessequal for signal <n0001> created at line 217
    Found 3-bit comparator greater for signal <n0003> created at line 219
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred   2 Multiplexer(s).
Unit <serport_1clock> synthesized.

Synthesizing Unit <serport_uart_rxtx_ab>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_uart_rxtx_ab.vhd".
        CDWIDTH = 13
        CDINIT = 554
    Summary:
	no macro.
Unit <serport_uart_rxtx_ab> synthesized.

Synthesizing Unit <serport_uart_autobaud>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_uart_autobaud.vhd".
        CDWIDTH = 13
        CDINIT = 554
    Found 7-bit register for signal <R_REGS_mcnt>.
    Found 1-bit register for signal <R_REGS_seen1>.
    Found 2-bit register for signal <R_REGS_state>.
    Found 16-bit register for signal <R_REGS_ccnt>.
    Found finite state machine <FSM_2> for signal <R_REGS_state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 3                                              |
    | Clock              | CLK (rising_edge)                              |
    | Power Up State     | s_idle                                         |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 7-bit adder for signal <R_REGS_mcnt[6]_GND_65_o_add_6_OUT> created at line 1241.
    Found 16-bit adder for signal <R_REGS_ccnt[15]_GND_65_o_add_16_OUT> created at line 1241.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  24 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <serport_uart_autobaud> synthesized.

Synthesizing Unit <serport_uart_rxtx>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_uart_rxtx.vhd".
        CDWIDTH = 13
    Summary:
	no macro.
Unit <serport_uart_rxtx> synthesized.

Synthesizing Unit <serport_uart_rx>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_uart_rx.vhd".
        CDWIDTH = 13
    Found 13-bit register for signal <R_REGS_ccnt>.
    Found 14-bit register for signal <R_REGS_dcnt>.
    Found 4-bit register for signal <R_REGS_bcnt>.
    Found 8-bit register for signal <R_REGS_sreg>.
    Found 3-bit register for signal <R_REGS_state>.
    Found finite state machine <FSM_3> for signal <R_REGS_state>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 23                                             |
    | Inputs             | 4                                              |
    | Outputs            | 5                                              |
    | Clock              | CLK (rising_edge)                              |
    | Reset              | RESET (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | s_idle                                         |
    | Power Up State     | s_idle                                         |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 14-bit adder for signal <R_REGS_dcnt[13]_GND_67_o_add_34_OUT> created at line 1241.
    Found 4-bit adder for signal <R_REGS_bcnt[3]_GND_67_o_add_37_OUT> created at line 1241.
    Found 13-bit subtractor for signal <GND_67_o_GND_67_o_sub_33_OUT<12:0>> created at line 1308.
    Found 1-bit 7-to-1 multiplexer for signal <R_REGS_state[2]_X_54_o_Mux_26_o> created at line 157.
    Found 1-bit 7-to-1 multiplexer for signal <proc_next.ce_bcnt> created at line 157.
    Found 1-bit 7-to-1 multiplexer for signal <R_REGS_state[2]_X_54_o_Mux_28_o> created at line 157.
    Found 14-bit comparator greater for signal <proc_next.dbit> created at line 153
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred  39 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  27 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <serport_uart_rx> synthesized.

Synthesizing Unit <serport_uart_tx>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_uart_tx.vhd".
        CDWIDTH = 13
    Found 4-bit register for signal <R_REGS_bcnt>.
    Found 9-bit register for signal <R_REGS_sreg>.
    Found 1-bit register for signal <R_REGS_busy>.
    Found 13-bit register for signal <R_REGS_ccnt>.
    Found 4-bit adder for signal <R_REGS_bcnt[3]_GND_68_o_add_5_OUT> created at line 1241.
    Found 13-bit subtractor for signal <GND_68_o_GND_68_o_sub_12_OUT<12:0>> created at line 1308.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  27 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <serport_uart_tx> synthesized.

Synthesizing Unit <serport_xonrx>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_xonrx.vhd".
    Found 8-bit register for signal <R_REGS_rxdata>.
    Found 1-bit register for signal <R_REGS_rxval>.
    Found 1-bit register for signal <R_REGS_rxovr>.
    Found 1-bit register for signal <R_REGS_txok>.
    WARNING:Xst:2404 -  FFs/Latches <R_REGS_escseen<0:0>> (without init value) have a constant value of 0 in block <serport_xonrx>.
    Summary:
	inferred  11 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <serport_xonrx> synthesized.

Synthesizing Unit <serport_xontx>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/serport/serport_xontx.vhd".
    Found 1-bit register for signal <R_REGS_ival>.
    Found 8-bit register for signal <R_REGS_obuf>.
    Found 1-bit register for signal <R_REGS_oval>.
    Found 1-bit register for signal <R_REGS_rxok>.
    Found 1-bit register for signal <R_REGS_enaxon_1>.
    Found 1-bit register for signal <R_REGS_escpend>.
    Found 8-bit register for signal <R_REGS_ibuf>.
    Summary:
	inferred  20 D-type flip-flop(s).
	inferred   5 Multiplexer(s).
Unit <serport_xontx> synthesized.

Synthesizing Unit <rlink_rlbmux>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/rlink/rlink_rlbmux.vhd".
    Summary:
	inferred   7 Multiplexer(s).
Unit <rlink_rlbmux> synthesized.

Synthesizing Unit <fx2_2fifoctl_ic>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/bplib/fx2lib/fx2_2fifoctl_ic.vhd".
        RXFAWIDTH = 5
        TXFAWIDTH = 5
        PETOWIDTH = 10
        CCWIDTH = 5
        RXAEMPTY_THRES = 1
        TXAFULL_THRES = 1
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/bplib/fx2lib/fx2_2fifoctl_ic.vhd" line 266: Output port <SIZER> of the instance <TXFIFO> is unconnected or connected to loadless signal.
    Found 10-bit register for signal <R_REGS_petocnt>.
    Found 1-bit register for signal <R_REGS_pepend>.
    Found 1-bit register for signal <R_REGS_rxpipe1>.
    Found 1-bit register for signal <R_REGS_rxpipe2>.
    Found 5-bit register for signal <R_REGS_ccnt>.
    Found 1-bit register for signal <R_REGS_moni_ep4_sel>.
    Found 1-bit register for signal <R_REGS_moni_ep6_sel>.
    Found 1-bit register for signal <R_REGS_moni_ep4_pf>.
    Found 1-bit register for signal <R_REGS_moni_ep6_pf>.
    Found 12-bit register for signal <R_MONI_C_fifo_ep4_GND_75_o_mux_55_OUT>.
    Found 12-bit register for signal <n0194[11:0]>.
    Found 4-bit register for signal <R_REGS_state>.
    Found finite state machine <FSM_4> for signal <R_REGS_state>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 46                                             |
    | Inputs             | 10                                             |
    | Outputs            | 10                                             |
    | Clock              | I_FX2_IFCLK (rising_edge)                      |
    | Power Up State     | s_idle                                         |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 5-bit subtractor for signal <GND_75_o_GND_75_o_sub_37_OUT<4:0>> created at line 1308.
    Found 10-bit subtractor for signal <GND_75_o_GND_75_o_sub_41_OUT<9:0>> created at line 1308.
    Found 5-bit comparator greater for signal <GND_75_o_RXSIZE_FX2[4]_LessThan_13_o> created at line 397
    Found 5-bit comparator greater for signal <GND_75_o_R_REGS_ccnt[4]_LessThan_36_o> created at line 470
    Found 5-bit comparator lessequal for signal <n0137> created at line 548
    Found 5-bit comparator lessequal for signal <n0139> created at line 554
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  46 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred  20 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <fx2_2fifoctl_ic> synthesized.

Synthesizing Unit <iob_reg_o_gen_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_o_gen.vhd".
        DWIDTH = 2
        INIT = '0'
    Set property "IOB = TRUE" for signal <R_DO>.
    Found 2-bit register for signal <R_DO>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <iob_reg_o_gen_3> synthesized.

Synthesizing Unit <iob_reg_i_gen_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_i_gen.vhd".
        DWIDTH = 4
        INIT = '0'
    Set property "IOB = TRUE" for signal <R_DI>.
    Found 4-bit register for signal <R_DI>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <iob_reg_i_gen_3> synthesized.

Synthesizing Unit <iob_reg_io_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_io_gen.vhd".
        DWIDTH = 8
        INITI = '0'
        INITO = '0'
        INITE = '0'
        PULL = "KEEP"
    Set property "IOB = TRUE" for signal <R_DI>.
    Set property "IOB = TRUE" for signal <R_DO>.
    Set property "IOB = TRUE" for signal <R_TE>.
    Found 8-bit register for signal <R_DI>.
    Found 8-bit register for signal <R_DO>.
    Found 1-bit register for signal <R_TE>.
    Found 1-bit tristate buffer for signal <PAD<7>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<6>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<5>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<4>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<3>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<2>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<1>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<0>> created at line 90
    Summary:
	inferred  17 D-type flip-flop(s).
	inferred   8 Tristate(s).
Unit <iob_reg_io_gen_1> synthesized.

Synthesizing Unit <fifo_2c_dram>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/fifo_2c_dram.vhd".
        AWIDTH = 5
        DWIDTH = 8
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/fifo_2c_dram.vhd" line 138: Output port <DOA> of the instance <RAM> is unconnected or connected to loadless signal.
    Found 5-bit register for signal <R_REGW_raddr_s>.
    Found 5-bit register for signal <R_REGW_sizew>.
    Found 1-bit register for signal <R_REGW_busy>.
    Found 1-bit register for signal <R_REGW_rstw>.
    Found 1-bit register for signal <R_REGW_rstw_sc>.
    Found 1-bit register for signal <R_REGW_rstw_ss>.
    Found 1-bit register for signal <R_REGW_rstr_c>.
    Found 1-bit register for signal <R_REGW_rstr_s>.
    Found 5-bit register for signal <R_REGR_waddr_c>.
    Found 5-bit register for signal <R_REGR_waddr_s>.
    Found 5-bit register for signal <R_REGR_sizer>.
    Found 1-bit register for signal <R_REGR_val>.
    Found 1-bit register for signal <R_REGR_rstr>.
    Found 1-bit register for signal <R_REGR_rstr_sc>.
    Found 1-bit register for signal <R_REGR_rstr_ss>.
    Found 1-bit register for signal <R_REGR_rstw_c>.
    Found 1-bit register for signal <R_REGR_rstw_s>.
    Found 5-bit register for signal <R_REGW_raddr_c>.
    Found 5-bit adder for signal <RADDR_S_BIN[4]_WADDR_BIN[4]_add_4_OUT> created at line 206.
    Found 5-bit subtractor for signal <GND_87_o_GND_87_o_sub_22_OUT<4:0>> created at line 282.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  42 D-type flip-flop(s).
	inferred   6 Multiplexer(s).
Unit <fifo_2c_dram> synthesized.

Synthesizing Unit <gray_cnt_gen>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/gray_cnt_gen.vhd".
        DWIDTH = 5
    Summary:
	no macro.
Unit <gray_cnt_gen> synthesized.

Synthesizing Unit <gray_cnt_5>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/gray_cnt_5.vhd".
    Set property "fsm_extract = no" for signal <R_DATA>.
    Set property "rom_style = distributed" for signal <N_DATA>.
    Found 5-bit register for signal <R_DATA>.
    Found 32x5-bit Read Only RAM for signal <N_DATA>
    Summary:
	inferred   1 RAM(s).
	inferred   5 D-type flip-flop(s).
Unit <gray_cnt_5> synthesized.

Synthesizing Unit <gray2bin_gen>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/gray2bin_gen.vhd".
        DWIDTH = 5
    Summary:
Unit <gray2bin_gen> synthesized.

Synthesizing Unit <rbd_rbmon>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/rbus/rbd_rbmon.vhd".
        RB_ADDR = "1111111111101000"
        AWIDTH = 9
    Found 1-bit register for signal <R_REGS_wena>.
    Found 1-bit register for signal <R_REGS_go>.
    Found 16-bit register for signal <R_REGS_hilim>.
    Found 16-bit register for signal <R_REGS_lolim>.
    Found 1-bit register for signal <R_REGS_wrap>.
    Found 9-bit register for signal <R_REGS_laddr>.
    Found 2-bit register for signal <R_REGS_waddr>.
    Found 1-bit register for signal <R_REGS_rbtake_1>.
    Found 16-bit register for signal <R_REGS_rbaddr>.
    Found 1-bit register for signal <R_REGS_rbinit>.
    Found 1-bit register for signal <R_REGS_rbwe>.
    Found 1-bit register for signal <R_REGS_rback>.
    Found 1-bit register for signal <R_REGS_rbbusy>.
    Found 1-bit register for signal <R_REGS_rberr>.
    Found 1-bit register for signal <R_REGS_rbnak>.
    Found 1-bit register for signal <R_REGS_rbtout>.
    Found 1-bit register for signal <R_REGS_rbburst>.
    Found 16-bit register for signal <R_REGS_rbdata>.
    Found 10-bit register for signal <R_REGS_rbnbusy>.
    Found 14-bit register for signal <R_REGS_rbndly>.
    Found 1-bit register for signal <R_REGS_rbsel>.
    Found 2-bit adder for signal <R_REGS_waddr[1]_GND_93_o_add_25_OUT> created at line 1241.
    Found 10-bit adder for signal <R_REGS_rbnbusy[9]_GND_93_o_add_48_OUT> created at line 1241.
    Found 14-bit adder for signal <R_REGS_rbndly[13]_GND_93_o_add_52_OUT> created at line 1241.
    Found 9-bit adder for signal <R_REGS_laddr[8]_GND_93_o_add_59_OUT> created at line 1241.
    Found 16-bit 4-to-1 multiplexer for signal <R_REGS_waddr[1]_BRAM1_DO[31]_wide_mux_41_OUT> created at line 345.
    Found 16-bit 7-to-1 multiplexer for signal <RB_MREQ_addr[2]_GND_93_o_wide_mux_42_OUT> created at line 330.
    Found 16-bit comparator lessequal for signal <n0088> created at line 362
    Found 16-bit comparator lessequal for signal <n0090> created at line 363
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred 112 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred  26 Multiplexer(s).
Unit <rbd_rbmon> synthesized.

Synthesizing Unit <ram_1swsr_wfirst_gen>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd".
        AWIDTH = 9
        DWIDTH = 32
    Summary:
	no macro.
Unit <ram_1swsr_wfirst_gen> synthesized.

Synthesizing Unit <ram_1swsr_xfirst_gen_unisim>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd".
        AWIDTH = 9
        DWIDTH = 32
        WRITE_MODE = "WRITE_FIRST"
    Summary:
	no macro.
Unit <ram_1swsr_xfirst_gen_unisim> synthesized.

Synthesizing Unit <pdp11_sys70>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_sys70.vhd".
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_sys70.vhd" line 146: Output port <ESUSP_O> of the instance <W11A> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <pdp11_sys70> synthesized.

Synthesizing Unit <pdp11_core_rbus>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_core_rbus.vhd".
        RB_ADDR_CORE = "0000000000000000"
        RB_ADDR_IBUS = "0100000000000000"
WARNING:Xst:647 - Input <CP_STAT_cmdbusy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CP_STAT_cpuwait> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_REGS_rbselc>.
    Found 1-bit register for signal <proc_next.icpaddr_racc>.
    Found 1-bit register for signal <R_REGS_rbinit>.
    Found 1-bit register for signal <R_REGS_cpreq>.
    Found 5-bit register for signal <R_REGS_cpfunc>.
    Found 1-bit register for signal <R_REGS_cpuact_1>.
    Found 21-bit register for signal <R_REGS_addr>.
    Found 1-bit register for signal <R_REGS_ena_22bit>.
    Found 1-bit register for signal <R_REGS_ena_ubmap>.
    Found 2-bit register for signal <R_REGS_membe>.
    Found 1-bit register for signal <R_REGS_membestick>.
    Found 1-bit register for signal <R_REGS_doinc>.
    Found 1-bit register for signal <R_REGS_waitstep>.
    Found 2-bit register for signal <R_REGS_state>.
    Found finite state machine <FSM_5> for signal <R_REGS_state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 9                                              |
    | Inputs             | 6                                              |
    | Outputs            | 3                                              |
    | Clock              | CLK (rising_edge)                              |
    | Power Up State     | s_idle                                         |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 21-bit adder for signal <R_REGS_addr[21]_GND_103_o_add_44_OUT> created at line 1241.
    Found 16-bit 3-to-1 multiplexer for signal <proc_next.irb_dout> created at line 238.
    Found 1-bit 3-to-1 multiplexer for signal <proc_next.irb_busy> created at line 238.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  38 D-type flip-flop(s).
	inferred  47 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <pdp11_core_rbus> synthesized.

Synthesizing Unit <pdp11_core>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_core.vhd".
    Summary:
	no macro.
Unit <pdp11_core> synthesized.

Synthesizing Unit <pdp11_vmbox>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_vmbox.vhd".
    Found 4-bit register for signal <R_REGS_state>.
    Found 1-bit register for signal <R_REGS_wacc>.
    Found 1-bit register for signal <R_REGS_macc>.
    Found 1-bit register for signal <R_REGS_cacc>.
    Found 1-bit register for signal <R_REGS_bytop>.
    Found 1-bit register for signal <R_REGS_kstack>.
    Found 1-bit register for signal <R_REGS_ysv>.
    Found 1-bit register for signal <R_REGS_vaok>.
    Found 1-bit register for signal <R_REGS_trap_mmu>.
    Found 16-bit register for signal <R_REGS_mdin>.
    Found 22-bit register for signal <R_REGS_paddr>.
    Found 9-bit register for signal <R_REGS_paddr_iopage>.
    Found 6-bit register for signal <R_REGS_atocnt>.
    Found 1-bit register for signal <R_REGS_ibre>.
    Found 1-bit register for signal <R_REGS_ibwe>.
    Found 2-bit register for signal <R_REGS_ibbe>.
    Found 1-bit register for signal <R_REGS_ibrmw>.
    Found 1-bit register for signal <R_REGS_ibcacc>.
    Found 1-bit register for signal <R_REGS_ibracc>.
    Found 16-bit register for signal <R_REGS_ibdout>.
    Found 8-bit register for signal <R_SLIM>.
    Found finite state machine <FSM_6> for signal <R_REGS_state>.
    -----------------------------------------------------------------------
    | States             | 11                                             |
    | Transitions        | 40                                             |
    | Inputs             | 19                                             |
    | Outputs            | 16                                             |
    | Clock              | CLK (rising_edge)                              |
    | Reset              | GRESET (positive)                              |
    | Reset type         | synchronous                                    |
    | Reset State        | s_idle                                         |
    | Power Up State     | s_idle                                         |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 6-bit subtractor for signal <GND_105_o_GND_105_o_sub_116_OUT<5:0>> created at line 1308.
    Found 22-bit 4-to-1 multiplexer for signal <R_REGS_state[3]_UBMAP_ADDR_PM[21]_wide_mux_117_OUT> created at line 639.
    Found 8-bit comparator lessequal for signal <n0081> created at line 371
    Found 9-bit comparator equal for signal <R_REGS_paddr_iopage[8]_R_REGS_paddr[21]_equal_38_o> created at line 443
    Found 16-bit comparator greater for signal <PWR_93_o_R_REGS_paddr[21]_LessThan_42_o> created at line 467
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  92 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred 161 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <pdp11_vmbox> synthesized.

Synthesizing Unit <pdp11_mmu>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_mmu.vhd".
WARNING:Xst:647 - Input <VADDR<5:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CNTL_trap_done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SSR0_abo_length>.
    Found 1-bit register for signal <R_SSR0_abo_rdonly>.
    Found 1-bit register for signal <R_SSR0_trap_mmu>.
    Found 1-bit register for signal <R_SSR0_ena_trap>.
    Found 1-bit register for signal <R_SSR0_inst_compl>.
    Found 2-bit register for signal <R_SSR0_seg_mode>.
    Found 1-bit register for signal <R_SSR0_dspace>.
    Found 3-bit register for signal <R_SSR0_seg_num>.
    Found 1-bit register for signal <R_SSR0_ena_mmu>.
    Found 1-bit register for signal <R_SSR0_trace_prev>.
    Found 5-bit register for signal <n0183[4:0]>.
    Found 1-bit register for signal <R_SSR0_abo_nonres>.
    Found 16-bit adder for signal <proc_paddr.ipaddrh> created at line 256.
    Found 8x1-bit Read Only RAM for signal <proc_nssr0.abo_nonres>
    Found 1-bit 4-to-1 multiplexer for signal <proc_paddr.dspace_en> created at line 245.
    Found 7-bit comparator greater for signal <SARSDR_slf[6]_VADDR[12]_LessThan_19_o> created at line 299
    Found 7-bit comparator greater for signal <VADDR[12]_SARSDR_slf[6]_LessThan_20_o> created at line 303
    Summary:
	inferred   1 RAM(s).
	inferred   1 Adder/Subtractor(s).
	inferred  18 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred  26 Multiplexer(s).
Unit <pdp11_mmu> synthesized.

Synthesizing Unit <pdp11_mmu_sadr>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_mmu_sadr.vhd".
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_IBSEL_AR>.
    Found 1-bit register for signal <R_IBSEL_DR>.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred  16 Multiplexer(s).
Unit <pdp11_mmu_sadr> synthesized.

Synthesizing Unit <ram_1swar_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd".
        AWIDTH = 6
        DWIDTH = 8
    Summary:
	no macro.
Unit <ram_1swar_gen_1> synthesized.

Synthesizing Unit <ram_1swar_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd".
        AWIDTH = 6
        DWIDTH = 7
    Summary:
	no macro.
Unit <ram_1swar_gen_2> synthesized.

Synthesizing Unit <ram_1swar_gen_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd".
        AWIDTH = 6
        DWIDTH = 2
    Summary:
	no macro.
Unit <ram_1swar_gen_3> synthesized.

Synthesizing Unit <ram_1swar_gen_4>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd".
        AWIDTH = 6
        DWIDTH = 4
    Summary:
	no macro.
Unit <ram_1swar_gen_4> synthesized.

Synthesizing Unit <pdp11_mmu_ssr12>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_mmu_ssr12.vhd".
WARNING:Xst:647 - Input <MONI_idone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <MONI_trace_prev> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 3-bit register for signal <R_SSR1_rb_num>.
    Found 5-bit register for signal <R_SSR1_ra_delta>.
    Found 3-bit register for signal <R_SSR1_ra_num>.
    Found 16-bit register for signal <R_SSR2>.
    Found 5-bit register for signal <R_SSR1_rb_delta>.
    Found 5-bit adder for signal <R_SSR1_ra_delta[4]_GND_112_o_add_14_OUT> created at line 171.
    Found 5-bit adder for signal <R_SSR1_rb_delta[4]_GND_112_o_add_17_OUT> created at line 178.
    Found 5-bit subtractor for signal <R_SSR1_ra_delta[4]_GND_112_o_sub_16_OUT<4:0>> created at line 173.
    Found 5-bit subtractor for signal <R_SSR1_rb_delta[4]_GND_112_o_sub_19_OUT<4:0>> created at line 180.
    Found 3-bit comparator not equal for signal <n0011> created at line 142
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  32 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  10 Multiplexer(s).
Unit <pdp11_mmu_ssr12> synthesized.

Synthesizing Unit <ib_sel_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ib_sel.vhd".
        IB_ADDR = "1111111101111100"
        SAWIDTH = 0
WARNING:Xst:647 - Input <IB_MREQ_din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_1> synthesized.

Synthesizing Unit <ib_sel_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ib_sel.vhd".
        IB_ADDR = "1111111101111110"
        SAWIDTH = 0
WARNING:Xst:647 - Input <IB_MREQ_din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_2> synthesized.

Synthesizing Unit <ib_sres_or_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ib_sres_or_3.vhd".
    Summary:
	no macro.
Unit <ib_sres_or_3> synthesized.

Synthesizing Unit <ib_sel_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ib_sel.vhd".
        IB_ADDR = "1111111101111010"
        SAWIDTH = 0
WARNING:Xst:647 - Input <IB_MREQ_din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_3> synthesized.

Synthesizing Unit <ib_sel_4>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ib_sel.vhd".
        IB_ADDR = "1111010101001110"
        SAWIDTH = 0
WARNING:Xst:647 - Input <IB_MREQ_din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_4> synthesized.

Synthesizing Unit <pdp11_ubmap>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_ubmap.vhd".
    Found 21-bit adder for signal <ADDR_PM> created at line 165.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  10 Multiplexer(s).
Unit <pdp11_ubmap> synthesized.

Synthesizing Unit <ram_1swar_gen_5>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd".
        AWIDTH = 5
        DWIDTH = 6
    Summary:
	no macro.
Unit <ram_1swar_gen_5> synthesized.

Synthesizing Unit <ram_1swar_gen_6>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd".
        AWIDTH = 5
        DWIDTH = 8
    Summary:
	no macro.
Unit <ram_1swar_gen_6> synthesized.

Synthesizing Unit <ram_1swar_gen_7>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd".
        AWIDTH = 5
        DWIDTH = 7
    Summary:
	no macro.
Unit <ram_1swar_gen_7> synthesized.

Synthesizing Unit <ib_sel_5>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ib_sel.vhd".
        IB_ADDR = "1111000010000000"
        SAWIDTH = 6
WARNING:Xst:647 - Input <IB_MREQ_addr<6:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_5> synthesized.

Synthesizing Unit <ib_sres_or_4>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ib_sres_or_4.vhd".
    Summary:
	no macro.
Unit <ib_sres_or_4> synthesized.

Synthesizing Unit <ib_sres_or_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ib_sres_or_2.vhd".
    Summary:
	no macro.
Unit <ib_sres_or_2> synthesized.

Synthesizing Unit <ib_sel_6>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ib_sel.vhd".
        IB_ADDR = "1111111111111100"
        SAWIDTH = 0
WARNING:Xst:647 - Input <IB_MREQ_din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_6> synthesized.

Synthesizing Unit <pdp11_dpath>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dpath.vhd".
    Found 16-bit register for signal <R_DDST>.
    Found 16-bit register for signal <R_DTMP>.
    Found 16-bit register for signal <R_IREG>.
    Found 16-bit register for signal <R_CPDOUT>.
    Found 16-bit register for signal <R_DSRC>.
    Found 16-bit 8-to-1 multiplexer for signal <DRES> created at line 218.
    Found 4-bit 7-to-1 multiplexer for signal <CCOUT> created at line 234.
    Found 16-bit 4-to-1 multiplexer for signal <CNTL_dtmp_sel[1]_DRESE[15]_wide_mux_8_OUT> created at line 269.
    Found 16-bit 4-to-1 multiplexer for signal <VM_ADDR> created at line 316.
    Summary:
	inferred  80 D-type flip-flop(s).
	inferred   6 Multiplexer(s).
Unit <pdp11_dpath> synthesized.

Synthesizing Unit <pdp11_gpr>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_gpr.vhd".
    Found 16-bit register for signal <R_PC>.
    Found 15-bit adder for signal <R_PC[15]_GND_127_o_add_9_OUT> created at line 1241.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  16 D-type flip-flop(s).
	inferred  30 Multiplexer(s).
Unit <pdp11_gpr> synthesized.

Synthesizing Unit <ram_1swar_1ar_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vhd".
        AWIDTH = 4
        DWIDTH = 8
    Summary:
	no macro.
Unit <ram_1swar_1ar_gen_2> synthesized.

Synthesizing Unit <pdp11_psr>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_psr.vhd".
WARNING:Xst:647 - Input <DIN<10:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 2-bit register for signal <R_PSW_pmode>.
    Found 1-bit register for signal <R_PSW_rset>.
    Found 3-bit register for signal <R_PSW_pri>.
    Found 1-bit register for signal <R_PSW_tflag>.
    Found 4-bit register for signal <R_PSW_cc>.
    Found 2-bit register for signal <R_PSW_cmode>.
    Summary:
	inferred  13 D-type flip-flop(s).
	inferred  51 Multiplexer(s).
Unit <pdp11_psr> synthesized.

Synthesizing Unit <ib_sel_7>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ib_sel.vhd".
        IB_ADDR = "1111111111111110"
        SAWIDTH = 0
WARNING:Xst:647 - Input <IB_MREQ_din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_7> synthesized.

Synthesizing Unit <pdp11_ounit>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_ounit.vhd".
    Found 16-bit adder for signal <GND_131_o_BSEL[1]_add_3_OUT> created at line 96.
    Found 16-bit subtractor for signal <GND_131_o_GND_131_o_sub_5_OUT<15:0>> created at line 98.
    Found 16-bit 4-to-1 multiplexer for signal <ASEL[1]_DTMP[15]_wide_mux_0_OUT> created at line 74.
    Found 16-bit 4-to-1 multiplexer for signal <mb> created at line 85.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   3 Multiplexer(s).
Unit <pdp11_ounit> synthesized.

Synthesizing Unit <pdp11_aunit>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_aunit.vhd".
    Found 9-bit adder for signal <n0075> created at line 113.
    Found 9-bit adder for signal <n0057> created at line 113.
    Found 9-bit adder for signal <n0081> created at line 113.
    Found 9-bit adder for signal <n0056> created at line 113.
    Found 16-bit 4-to-1 multiplexer for signal <msrc> created at line 122.
    Found 16-bit 4-to-1 multiplexer for signal <mdst> created at line 130.
    Found 1-bit 4-to-1 multiplexer for signal <mci> created at line 138.
    Found 1-bit 7-to-1 multiplexer for signal <CCMODE[2]_GND_134_o_Mux_14_o> created at line 206.
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred  20 Multiplexer(s).
Unit <pdp11_aunit> synthesized.

Synthesizing Unit <pdp11_lunit>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_lunit.vhd".
WARNING:Xst:647 - Input <CCIN<2:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16-bit 8-to-1 multiplexer for signal <FUNC[2]_DSRC[15]_wide_mux_4_OUT> created at line 96.
    Found 1-bit 3-to-1 multiplexer for signal <FUNC[2]_CCIN[0]_Mux_5_o> created at line 96.
    Found 16-bit 8-to-1 multiplexer for signal <FUNC[2]_DSRC[7]_wide_mux_11_OUT> created at line 137.
    Found 1-bit 3-to-1 multiplexer for signal <FUNC[2]_CCIN[0]_Mux_12_o> created at line 137.
    Summary:
	inferred  36 Multiplexer(s).
Unit <pdp11_lunit> synthesized.

Synthesizing Unit <pdp11_munit>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_munit.vhd".
    Found 1-bit register for signal <R_DDO_LT>.
    Found 1-bit register for signal <R_MAXFIX>.
    Found 1-bit register for signal <R_QO_LT>.
    Found 1-bit register for signal <R_DIV_V>.
    Found 6-bit register for signal <R_SHC>.
    Found 1-bit register for signal <R_C1>.
    Found 1-bit register for signal <R_MSBO>.
    Found 1-bit register for signal <R_ASH_V>.
    Found 1-bit register for signal <R_ASH_C>.
    Found 16-bit register for signal <R_DD_L>.
    Found 6-bit adder for signal <R_SHC[5]_GND_136_o_add_11_OUT> created at line 1241.
    Found 16-bit adder for signal <DSRC[15]_DDST[15]_add_16_OUT> created at line 246.
    Found 6-bit subtractor for signal <GND_136_o_GND_136_o_sub_11_OUT<5:0>> created at line 1308.
    Found 16-bit subtractor for signal <DSRC[15]_DDST[15]_sub_18_OUT<15:0>> created at line 248.
    Found 16x16-bit multiplier for signal <proc_omux.prod> created at line 393.
    Found 16-bit 4-to-1 multiplexer for signal <DOUT> created at line 415.
    Found 16-bit 4-to-1 multiplexer for signal <DOUTE> created at line 415.
    Found 4-bit 4-to-1 multiplexer for signal <CCOUT> created at line 442.
    Found 16-bit comparator greater for signal <DTMP_POS> created at line 160
    Found 16-bit comparator lessequal for signal <n0037> created at line 252
    Found 16-bit comparator lessequal for signal <n0039> created at line 257
    Summary:
	inferred   1 Multiplier(s).
	inferred   2 Adder/Subtractor(s).
	inferred  30 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred  30 Multiplexer(s).
Unit <pdp11_munit> synthesized.

Synthesizing Unit <pdp11_decode>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_decode.vhd".
    Found 4x2-bit Read Only RAM for signal <proc_idecode.nstat_fork_srcr>
    Found 4x6-bit Read Only RAM for signal <_n0593>
    Found 1-bit 3-to-1 multiplexer for signal <_n0551> created at line 230.
    Summary:
	inferred   2 RAM(s).
	inferred 198 Multiplexer(s).
Unit <pdp11_decode> synthesized.

Synthesizing Unit <pdp11_sequencer>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_sequencer.vhd".
WARNING:Xst:647 - Input <IREG<14:11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_STATUS_cmdack>.
    Found 1-bit register for signal <R_STATUS_cmderr>.
    Found 1-bit register for signal <R_STATUS_cmdmerr>.
    Found 1-bit register for signal <R_STATUS_cpugo>.
    Found 1-bit register for signal <R_STATUS_cpustep>.
    Found 1-bit register for signal <R_STATUS_cpususp>.
    Found 1-bit register for signal <R_STATUS_cpuwait>.
    Found 4-bit register for signal <R_STATUS_cpurust>.
    Found 1-bit register for signal <R_STATUS_suspint>.
    Found 1-bit register for signal <R_STATUS_suspext>.
    Found 5-bit register for signal <R_STATUS_cpfunc>.
    Found 3-bit register for signal <R_STATUS_cprnum>.
    Found 1-bit register for signal <R_STATUS_waitsusp>.
    Found 1-bit register for signal <R_STATUS_itimer>.
    Found 1-bit register for signal <R_STATUS_creset>.
    Found 1-bit register for signal <R_STATUS_breset>.
    Found 1-bit register for signal <R_STATUS_intack>.
    Found 7-bit register for signal <R_STATUS_intvect>.
    Found 1-bit register for signal <R_STATUS_trap_mmu>.
    Found 1-bit register for signal <R_STATUS_trap_ysv>.
    Found 1-bit register for signal <R_STATUS_prefdone>.
    Found 1-bit register for signal <R_STATUS_do_gprwe>.
    Found 1-bit register for signal <R_STATUS_do_intrsv>.
    Found 6-bit register for signal <n1187[5:0]>.
    Found 1-bit register for signal <R_IDSTAT_is_dstmode0>.
    Found 1-bit register for signal <R_IDSTAT_is_srcpc>.
    Found 1-bit register for signal <R_IDSTAT_is_srcpcmode1>.
    Found 1-bit register for signal <R_IDSTAT_is_dstpc>.
    Found 1-bit register for signal <R_IDSTAT_is_dstw_reg>.
    Found 1-bit register for signal <R_IDSTAT_is_dstw_pc>.
    Found 1-bit register for signal <R_IDSTAT_is_rmwop>.
    Found 1-bit register for signal <R_IDSTAT_is_bytop>.
    Found 1-bit register for signal <R_IDSTAT_op_rtt>.
    Found 1-bit register for signal <R_IDSTAT_op_mov>.
    Found 3-bit register for signal <R_IDSTAT_trap_vec>.
    Found 1-bit register for signal <R_IDSTAT_updt_dstadsrc>.
    Found 2-bit register for signal <R_IDSTAT_aunit_srcmod>.
    Found 2-bit register for signal <R_IDSTAT_aunit_dstmod>.
    Found 2-bit register for signal <R_IDSTAT_aunit_cimod>.
    Found 1-bit register for signal <R_IDSTAT_aunit_cc1op>.
    Found 3-bit register for signal <R_IDSTAT_aunit_ccmode>.
    Found 4-bit register for signal <R_IDSTAT_lunit_func>.
    Found 2-bit register for signal <R_IDSTAT_munit_func>.
    Found 3-bit register for signal <R_IDSTAT_res_sel>.
    Found 2-bit register for signal <R_IDSTAT_fork_dstr>.
    Found 2-bit register for signal <R_IDSTAT_fork_dsta>.
    Found 4-bit register for signal <R_IDSTAT_fork_opg>.
    Found 3-bit register for signal <R_IDSTAT_fork_opa>.
    Found 1-bit register for signal <R_IDSTAT_do_fork_dstr>.
    Found 7-bit register for signal <n1189>.
    Found 7-bit register for signal <R_STATE>.
    Found 1-bit register for signal <R_STATUS_cmdbusy>.
    Found 16x1-bit Read Only RAM for signal <R_STATUS_cpfunc[4]_GND_139_o_Mux_83_o>
    Found 4x5-bit Read Only RAM for signal <R_IDSTAT_fork_dstr[1]_PWR_129_o_wide_mux_148_OUT>
    Found 16x7-bit Read Only RAM for signal <R_IDSTAT_fork_opg[3]_PWR_129_o_wide_mux_174_OUT>
    Found 8x7-bit Read Only RAM for signal <R_IDSTAT_fork_opa[2]_PWR_129_o_wide_mux_216_OUT>
    Found 4x7-bit Read Only RAM for signal <R_IDSTAT_fork_dsta[1]_GND_139_o_wide_mux_328_OUT>
    Found 32x14-bit Read Only RAM for signal <_n3125>
    Found 128x25-bit Read Only RAM for signal <_n3279>
    Found 1-bit 8-to-1 multiplexer for signal <IREG[15]_PSW_cc[0]_Mux_243_o> created at line 1621.
    Found 3-bit comparator greater for signal <proc_next.int_pending> created at line 595
    Found 3-bit comparator equal for signal <IREG[8]_IREG[2]_equal_142_o> created at line 1061
    Summary:
	inferred   7 RAM(s).
	inferred 104 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred 423 Multiplexer(s).
Unit <pdp11_sequencer> synthesized.

Synthesizing Unit <ib_sel_8>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ib_sel.vhd".
        IB_ADDR = "1111111111110110"
        SAWIDTH = 0
WARNING:Xst:647 - Input <IB_MREQ_din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_8> synthesized.

Synthesizing Unit <pdp11_irq>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_irq.vhd".
    Found 7-bit register for signal <R_PIRQ>.
    Found 3-bit comparator greater for signal <PI_PRI[2]_EI_PRI[2]_LessThan_13_o> created at line 129
    Summary:
	inferred   7 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  10 Multiplexer(s).
Unit <pdp11_irq> synthesized.

Synthesizing Unit <ib_sel_9>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ib_sel.vhd".
        IB_ADDR = "1111111111111010"
        SAWIDTH = 0
WARNING:Xst:647 - Input <IB_MREQ_din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_SEL>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <ib_sel_9> synthesized.

Synthesizing Unit <pdp11_reg70>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_reg70.vhd".
WARNING:Xst:647 - Input <IB_MREQ_din<15:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_REGS_ibsel_sysid>.
    Found 8-bit register for signal <R_REGS_mbrk>.
    Found 1-bit register for signal <R_REGS_ibsel_mbrk>.
    Summary:
	inferred  10 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <pdp11_reg70> synthesized.

Synthesizing Unit <pdp11_cache>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_cache.vhd".
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_cache.vhd" line 115: Output port <DOB> of the instance <CMEM_TAG> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_cache.vhd" line 134: Output port <DOB> of the instance <CMEM_DAT0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_cache.vhd" line 153: Output port <DOB> of the instance <CMEM_DAT1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_cache.vhd" line 172: Output port <DOB> of the instance <CMEM_DAT2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_cache.vhd" line 191: Output port <DOB> of the instance <CMEM_DAT3> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <R_REGS_addr_w>.
    Found 11-bit register for signal <R_REGS_addr_l>.
    Found 9-bit register for signal <R_REGS_addr_t>.
    Found 4-bit register for signal <R_REGS_be>.
    Found 16-bit register for signal <R_REGS_di>.
    Found 2-bit register for signal <R_REGS_state>.
    Found finite state machine <FSM_7> for signal <R_REGS_state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 16                                             |
    | Inputs             | 8                                              |
    | Outputs            | 4                                              |
    | Clock              | CLK (rising_edge)                              |
    | Reset              | GRESET (positive)                              |
    | Reset type         | synchronous                                    |
    | Reset State        | s_idle                                         |
    | Power Up State     | s_idle                                         |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit 4-to-1 multiplexer for signal <proc_next.iackr> created at line 311.
    Found 1-bit 3-to-1 multiplexer for signal <proc_next.icmem_tag_ceb> created at line 311.
    Found 1-bit 3-to-1 multiplexer for signal <proc_next.icmem_dat_ceb> created at line 311.
    Found 16-bit 4-to-1 multiplexer for signal <EM_SRES_dout> created at line 429.
    Found 9-bit comparator equal for signal <proc_next.itagok> created at line 292
    Found 4-bit comparator equal for signal <proc_next.ivalok> created at line 296
    Summary:
	inferred  41 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred  29 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <pdp11_cache> synthesized.

Synthesizing Unit <ram_2swsr_rfirst_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd".
        AWIDTH = 11
        DWIDTH = 9
    Summary:
	no macro.
Unit <ram_2swsr_rfirst_gen_2> synthesized.

Synthesizing Unit <ram_2swsr_xfirst_gen_unisim_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd".
        AWIDTH = 11
        DWIDTH = 9
        WRITE_MODE = "READ_FIRST"
    Summary:
	no macro.
Unit <ram_2swsr_xfirst_gen_unisim_2> synthesized.

Synthesizing Unit <pdp11_mem70>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_mem70.vhd".
WARNING:Xst:647 - Input <IB_MREQ_din<15:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_REGS_ibsel_hm>.
    Found 1-bit register for signal <R_REGS_ibsel_ls>.
    Found 1-bit register for signal <R_REGS_ibsel_nn>.
    Found 6-bit register for signal <R_REGS_hm_data>.
    Found 2-bit register for signal <R_REGS_cr_frep>.
    Found 2-bit register for signal <R_REGS_cr_fmiss>.
    Found 1-bit register for signal <R_REGS_cr_disutrap>.
    Found 1-bit register for signal <R_REGS_cr_distrap>.
    Found 1-bit register for signal <R_REGS_ibsel_cr>.
    Summary:
	inferred  16 D-type flip-flop(s).
	inferred  12 Multiplexer(s).
Unit <pdp11_mem70> synthesized.

Synthesizing Unit <ibd_ibmon>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ibd_ibmon.vhd".
        IB_ADDR = "1110000000000000"
        AWIDTH = 9
    Found 1-bit register for signal <R_REGS_conena>.
    Found 1-bit register for signal <R_REGS_remena>.
    Found 1-bit register for signal <R_REGS_locena>.
    Found 1-bit register for signal <R_REGS_wena>.
    Found 1-bit register for signal <R_REGS_go>.
    Found 12-bit register for signal <R_REGS_hilim>.
    Found 12-bit register for signal <R_REGS_lolim>.
    Found 1-bit register for signal <R_REGS_wrap>.
    Found 9-bit register for signal <R_REGS_laddr>.
    Found 2-bit register for signal <R_REGS_waddr>.
    Found 1-bit register for signal <R_REGS_ibtake_1>.
    Found 12-bit register for signal <R_REGS_ibaddr>.
    Found 1-bit register for signal <R_REGS_ibwe>.
    Found 1-bit register for signal <R_REGS_ibrmw>.
    Found 1-bit register for signal <R_REGS_ibbe0>.
    Found 1-bit register for signal <R_REGS_ibbe1>.
    Found 1-bit register for signal <R_REGS_ibcacc>.
    Found 1-bit register for signal <R_REGS_ibracc>.
    Found 1-bit register for signal <R_REGS_iback>.
    Found 1-bit register for signal <R_REGS_ibbusy>.
    Found 1-bit register for signal <R_REGS_ibnak>.
    Found 1-bit register for signal <R_REGS_ibtout>.
    Found 1-bit register for signal <R_REGS_ibburst>.
    Found 16-bit register for signal <R_REGS_ibdata>.
    Found 10-bit register for signal <R_REGS_ibnbusy>.
    Found 14-bit register for signal <R_REGS_ibndly>.
    Found 1-bit register for signal <R_REGS_ibsel>.
    Found 2-bit adder for signal <R_REGS_waddr[1]_GND_151_o_add_25_OUT> created at line 1241.
    Found 10-bit adder for signal <R_REGS_ibnbusy[9]_GND_151_o_add_51_OUT> created at line 1241.
    Found 14-bit adder for signal <R_REGS_ibndly[13]_GND_151_o_add_55_OUT> created at line 1241.
    Found 9-bit adder for signal <R_REGS_laddr[8]_GND_151_o_add_62_OUT> created at line 1241.
    Found 16-bit 4-to-1 multiplexer for signal <R_REGS_waddr[1]_BRAM1_DO[31]_wide_mux_44_OUT> created at line 367.
    Found 16-bit 7-to-1 multiplexer for signal <IB_MREQ_addr[3]_GND_151_o_wide_mux_45_OUT> created at line 347.
    Found 12-bit comparator lessequal for signal <n0110> created at line 384
    Found 12-bit comparator lessequal for signal <n0112> created at line 385
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred 106 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred  26 Multiplexer(s).
Unit <ibd_ibmon> synthesized.

Synthesizing Unit <pdp11_dmscnt>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmscnt.vhd".
        RB_ADDR = "0000000001000000"
WARNING:Xst:647 - Input <RB_MREQ_din<15:11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_pc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_pmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_pri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_cc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ireg> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dsrc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ddst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dtmp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dres> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_adst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_mode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ_init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE_istart> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE_idone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE_vfetch> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_rset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_tflag> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ireg_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dsrc_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ddst_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dtmp_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_cpdout_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_cpugo> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_cpustep> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_cpususp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_suspint> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_suspext> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmscnt.vhd" line 133: Output port <DOB> of the instance <CMEM> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <R_REGS_rbsel>.
    Found 1-bit register for signal <R_REGS_clr>.
    Found 1-bit register for signal <R_REGS_ena0>.
    Found 1-bit register for signal <R_REGS_ena1>.
    Found 9-bit register for signal <R_REGS_snum0>.
    Found 9-bit register for signal <R_REGS_snum1>.
    Found 1-bit register for signal <R_REGS_same>.
    Found 9-bit register for signal <R_REGS_laddr>.
    Found 2-bit register for signal <R_REGS_waddr>.
    Found 36-bit register for signal <R_REGS_scnt>.
    Found 20-bit register for signal <R_REGS_mbuf>.
    Found 1-bit register for signal <R_REGS_state>.
    Found finite state machine <FSM_8> for signal <R_REGS_waddr>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 20                                             |
    | Inputs             | 7                                              |
    | Outputs            | 3                                              |
    | Clock              | CLK (rising_edge)                              |
    | Reset              | R_REGS_state (positive)                        |
    | Reset type         | synchronous                                    |
    | Reset State        | 01                                             |
    | Power Up State     | 00                                             |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 9-bit adder for signal <R_REGS_laddr[8]_GND_152_o_add_19_OUT> created at line 1241.
    Found 36-bit adder for signal <proc_next.n_scnt> created at line 1241.
    Found 1-bit 4-to-1 multiplexer for signal <RB_MREQ_addr[1]_PWR_139_o_Mux_37_o> created at line 216.
    Found 16-bit 4-to-1 multiplexer for signal <R_REGS_waddr[1]_GND_152_o_wide_mux_50_OUT> created at line 286.
    Found 16-bit 4-to-1 multiplexer for signal <RB_MREQ_addr[1]_GND_152_o_wide_mux_51_OUT> created at line 278.
    Found 9-bit comparator equal for signal <R_REGS_snum1[8]_R_REGS_snum0[8]_equal_55_o> created at line 308
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  89 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  30 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <pdp11_dmscnt> synthesized.

Synthesizing Unit <ram_2swsr_rfirst_gen_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_2swsr_rfirst_gen_unisim.vhd".
        AWIDTH = 9
        DWIDTH = 36
    Summary:
	no macro.
Unit <ram_2swsr_rfirst_gen_3> synthesized.

Synthesizing Unit <ram_2swsr_xfirst_gen_unisim_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd".
        AWIDTH = 9
        DWIDTH = 36
        WRITE_MODE = "READ_FIRST"
    Summary:
	no macro.
Unit <ram_2swsr_xfirst_gen_unisim_3> synthesized.

Synthesizing Unit <pdp11_dmcmon>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmcmon.vhd".
        RB_ADDR = "0000000001001000"
        AWIDTH = 8
WARNING:Xst:647 - Input <RB_MREQ_addr<15:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ_din<15:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_pc<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dtmp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_adst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_mode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmcntl_mode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibsres_dout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_be> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emsres_dout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ_init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmcntl_kstack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmcntl_intrsv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmcntl_trap_done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_fail> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_aval> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibsres_ack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibsres_busy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_req> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_cancel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emsres_ack_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emsres_ack_w> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_suspint> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_suspext> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmcmon.vhd" line 377: Output port <DOA> of the instance <MAL> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <R_REGS_mwsup>.
    Found 1-bit register for signal <R_REGS_imode>.
    Found 1-bit register for signal <R_REGS_wena>.
    Found 1-bit register for signal <R_REGS_go>.
    Found 1-bit register for signal <R_REGS_active>.
    Found 1-bit register for signal <R_REGS_wrap>.
    Found 8-bit register for signal <R_REGS_laddr>.
    Found 4-bit register for signal <R_REGS_waddr>.
    Found 8-bit register for signal <R_REGS_cnum>.
    Found 4-bit register for signal <R_REGS_mal_waddr>.
    Found 4-bit register for signal <R_REGS_mal_raddr>.
    Found 15-bit register for signal <R_REGS_dp_pc_fet>.
    Found 15-bit register for signal <R_REGS_dp_pc_dec>.
    Found 16-bit register for signal <R_REGS_dp_ireg>.
    Found 1-bit register for signal <R_REGS_dp_ireg_we>.
    Found 1-bit register for signal <R_REGS_dp_ireg_we_1>.
    Found 16-bit register for signal <R_REGS_dp_dres>.
    Found 1-bit register for signal <R_REGS_dp_dsrc_we>.
    Found 1-bit register for signal <R_REGS_dp_ddst_we>.
    Found 1-bit register for signal <R_REGS_dp_dres_val>.
    Found 16-bit register for signal <R_REGS_vm_addr>.
    Found 16-bit register for signal <R_REGS_vm_din>.
    Found 16-bit register for signal <R_REGS_vm_dout>.
    Found 1-bit register for signal <R_REGS_vm_req>.
    Found 1-bit register for signal <R_REGS_vm_wacc>.
    Found 1-bit register for signal <R_REGS_vm_macc>.
    Found 1-bit register for signal <R_REGS_vm_cacc>.
    Found 1-bit register for signal <R_REGS_vm_bytop>.
    Found 1-bit register for signal <R_REGS_vm_dspace>.
    Found 16-bit register for signal <R_REGS_vm_addr_1>.
    Found 16-bit register for signal <R_REGS_vm_dout_1>.
    Found 1-bit register for signal <R_REGS_vm_wacc_1>.
    Found 1-bit register for signal <R_REGS_vm_macc_1>.
    Found 1-bit register for signal <R_REGS_vm_cacc_1>.
    Found 1-bit register for signal <R_REGS_vm_bytop_1>.
    Found 1-bit register for signal <R_REGS_vm_dspace_1>.
    Found 1-bit register for signal <R_REGS_vm_ack>.
    Found 1-bit register for signal <R_REGS_vm_err>.
    Found 1-bit register for signal <R_REGS_vm_err_odd>.
    Found 1-bit register for signal <R_REGS_vm_err_mmu>.
    Found 1-bit register for signal <R_REGS_vm_err_nxm>.
    Found 1-bit register for signal <R_REGS_vm_err_iobto>.
    Found 1-bit register for signal <R_REGS_vm_err_rsv>.
    Found 1-bit register for signal <R_REGS_vm_trap_ysv>.
    Found 1-bit register for signal <R_REGS_vm_trap_mmu>.
    Found 1-bit register for signal <R_REGS_vm_pend>.
    Found 1-bit register for signal <R_REGS_se_istart>.
    Found 1-bit register for signal <R_REGS_se_istart_1>.
    Found 1-bit register for signal <R_REGS_se_idone>.
    Found 1-bit register for signal <R_REGS_se_vfetch>.
    Found 8-bit register for signal <R_REGS_se_snum>.
    Found 1-bit register for signal <R_REGS_mwdrop>.
    Found 1-bit register for signal <R_REGS_rbsel>.
    Found 4-bit adder for signal <R_REGS_waddr[3]_GND_193_o_add_39_OUT> created at line 1241.
    Found 8-bit adder for signal <R_REGS_laddr[7]_GND_193_o_add_71_OUT> created at line 1241.
    Found 8-bit adder for signal <proc_next.n_cnum> created at line 1241.
    Found 4-bit adder for signal <R_REGS_mal_waddr[3]_GND_193_o_add_86_OUT> created at line 1241.
    Found 4-bit adder for signal <R_REGS_mal_raddr[3]_GND_193_o_add_89_OUT> created at line 1241.
    Found 16-bit 12-to-1 multiplexer for signal <R_REGS_waddr[3]_GND_193_o_wide_mux_55_OUT> created at line 548.
    Found 16-bit 8-to-1 multiplexer for signal <RB_MREQ_addr[2]_MAL_DO[15]_wide_mux_56_OUT> created at line 530.
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred 216 D-type flip-flop(s).
	inferred 122 Multiplexer(s).
Unit <pdp11_dmcmon> synthesized.

Synthesizing Unit <ram_1swar_1ar_gen_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swar_1ar_gen_unisim.vhd".
        AWIDTH = 4
        DWIDTH = 16
    Summary:
	no macro.
Unit <ram_1swar_1ar_gen_3> synthesized.

Synthesizing Unit <pdp11_dmhbpt>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmhbpt.vhd".
        RB_ADDR = "0000000001010000"
        NUNIT = 2
    Summary:
	no macro.
Unit <pdp11_dmhbpt> synthesized.

Synthesizing Unit <pdp11_dmhbpt_unit_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmhbpt_unit.vhd".
        RB_ADDR = "0000000001010000"
        INDEX = 1
WARNING:Xst:647 - Input <RB_MREQ_addr<15:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE_snum> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_pc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_cmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_pmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_pri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_cc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ireg> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dsrc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ddst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dtmp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dres> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_adst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_mode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmaddr<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmdin> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmdout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibsres_dout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_be> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emsres_dout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ_init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE_idone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE_vfetch> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_rset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_tflag> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ireg_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dsrc_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ddst_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dtmp_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_cpdout_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmcntl_macc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmcntl_bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmcntl_kstack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmcntl_intrsv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmcntl_trap_done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_ack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_err> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_fail> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_err_odd> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_err_mmu> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_err_nxm> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_err_iobto> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_err_rsv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_trap_ysv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_trap_mmu> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_aval> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibsres_ack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibsres_busy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_req> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_cancel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emsres_ack_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emsres_ack_w> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_cpugo> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_cpustep> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_cpususp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_suspint> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_suspext> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 2-bit register for signal <R_REGS_mode>.
    Found 1-bit register for signal <R_REGS_irena>.
    Found 1-bit register for signal <R_REGS_dwena>.
    Found 1-bit register for signal <R_REGS_drena>.
    Found 1-bit register for signal <R_REGS_irseen>.
    Found 1-bit register for signal <R_REGS_dwseen>.
    Found 1-bit register for signal <R_REGS_drseen>.
    Found 15-bit register for signal <R_REGS_hilim>.
    Found 15-bit register for signal <R_REGS_lolim>.
    Found 1-bit register for signal <R_REGS_rbsel>.
    Found 16-bit 4-to-1 multiplexer for signal <RB_MREQ_addr[1]_R_REGS_lolim[15]_wide_mux_23_OUT> created at line 207.
    Found 2-bit comparator equal for signal <R_REGS_mode[1]_DM_STAT_VM_vmcntl_mode[1]_equal_26_o> created at line 229
    Found 15-bit comparator lessequal for signal <n0058> created at line 230
    Found 15-bit comparator lessequal for signal <n0060> created at line 231
    Summary:
	inferred  39 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   9 Multiplexer(s).
Unit <pdp11_dmhbpt_unit_1> synthesized.

Synthesizing Unit <pdp11_dmhbpt_unit_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dmhbpt_unit.vhd".
        RB_ADDR = "0000000001010000"
        INDEX = 0
WARNING:Xst:647 - Input <RB_MREQ_addr<15:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE_snum> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_pc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_cmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_pmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_pri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_cc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ireg> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dsrc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ddst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dtmp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dres> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_adst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_mode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmaddr<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmdin> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmdout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibsres_dout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_be> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_addr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_din> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emsres_dout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ_init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE_idone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_SE_vfetch> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_rset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_tflag> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ireg_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dsrc_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ddst_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dtmp_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_cpdout_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmcntl_macc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmcntl_bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmcntl_kstack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmcntl_intrsv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmcntl_trap_done> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_ack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_err> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_fail> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_err_odd> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_err_mmu> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_err_nxm> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_err_iobto> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_err_rsv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_trap_ysv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_vmstat_trap_mmu> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_aval> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_re> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_be0> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibmreq_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibsres_ack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_ibsres_busy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_req> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emmreq_cancel> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emsres_ack_r> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_VM_emsres_ack_w> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_cpugo> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_cpustep> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_cpususp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_suspint> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_CO_suspext> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 2-bit register for signal <R_REGS_mode>.
    Found 1-bit register for signal <R_REGS_irena>.
    Found 1-bit register for signal <R_REGS_dwena>.
    Found 1-bit register for signal <R_REGS_drena>.
    Found 1-bit register for signal <R_REGS_irseen>.
    Found 1-bit register for signal <R_REGS_dwseen>.
    Found 1-bit register for signal <R_REGS_drseen>.
    Found 15-bit register for signal <R_REGS_hilim>.
    Found 15-bit register for signal <R_REGS_lolim>.
    Found 1-bit register for signal <R_REGS_rbsel>.
    Found 16-bit 4-to-1 multiplexer for signal <RB_MREQ_addr[1]_R_REGS_lolim[15]_wide_mux_23_OUT> created at line 207.
    Found 2-bit comparator equal for signal <R_REGS_mode[1]_DM_STAT_VM_vmcntl_mode[1]_equal_26_o> created at line 229
    Found 15-bit comparator lessequal for signal <n0058> created at line 230
    Found 15-bit comparator lessequal for signal <n0060> created at line 231
    Summary:
	inferred  39 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   9 Multiplexer(s).
Unit <pdp11_dmhbpt_unit_2> synthesized.

Synthesizing Unit <rb_sres_or_4>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/rbus/rb_sres_or_4.vhd".
    Summary:
	no macro.
Unit <rb_sres_or_4> synthesized.

Synthesizing Unit <ibdr_maxisys>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_maxisys.vhd".
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_maxisys.vhd" line 217: Output port <IIST_MREQ_lock> of the instance <IIST.I0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_maxisys.vhd" line 217: Output port <IIST_MREQ_boot> of the instance <IIST.I0> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <ibdr_maxisys> synthesized.

Synthesizing Unit <ibd_iist>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ibd_iist.vhd".
        SID = "00"
WARNING:Xst:647 - Input <IB_MREQ_din<7:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <EI_ACK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 4-bit register for signal <R_REGS_acr_ac>.
    Found 4-bit register for signal <R_REGS_pge_pbe>.
    Found 4-bit register for signal <R_REGS_pge_pie>.
    Found 1-bit register for signal <R_REGS_pgc_grj>.
    Found 1-bit register for signal <R_REGS_pgc_pgrmr>.
    Found 1-bit register for signal <R_REGS_pgc_strmr>.
    Found 1-bit register for signal <R_REGS_pgc_ie>.
    Found 1-bit register for signal <R_REGS_pgc_ptp>.
    Found 4-bit register for signal <R_REGS_ste_sbe>.
    Found 4-bit register for signal <R_REGS_ste_sie>.
    Found 8-bit register for signal <R_REGS_stc_count>.
    Found 1-bit register for signal <R_REGS_stc_tmo>.
    Found 1-bit register for signal <R_REGS_stc_lke>.
    Found 1-bit register for signal <R_REGS_stc_stp>.
    Found 1-bit register for signal <R_REGS_stc_enb>.
    Found 4-bit register for signal <R_REGS_msk_bm>.
    Found 4-bit register for signal <R_REGS_msk_im>.
    Found 4-bit register for signal <R_REGS_pgf_pbf>.
    Found 4-bit register for signal <R_REGS_pgf_pif>.
    Found 4-bit register for signal <R_REGS_stf_sbf>.
    Found 4-bit register for signal <R_REGS_stf_sif>.
    Found 4-bit register for signal <R_REGS_dcf_brk>.
    Found 4-bit register for signal <R_REGS_dcf_dcf>.
    Found 4-bit register for signal <R_REGS_exc_ui>.
    Found 4-bit register for signal <R_REGS_exc_rte>.
    Found 1-bit register for signal <R_REGS_mtc_mttp>.
    Found 1-bit register for signal <R_REGS_mtc_mfrm>.
    Found 2-bit register for signal <R_REGS_mtc_mid>.
    Found 1-bit register for signal <R_REGS_mtc_dsbt>.
    Found 1-bit register for signal <R_REGS_mtc_enmxd>.
    Found 1-bit register for signal <R_REGS_mtc_enmlp>.
    Found 1-bit register for signal <R_REGS_mtc_dsdrv>.
    Found 2-bit register for signal <R_REGS_state>.
    Found 1-bit register for signal <R_REGS_req_clear>.
    Found 1-bit register for signal <R_REGS_req_stsnd>.
    Found 1-bit register for signal <R_REGS_req_pgsnd>.
    Found 8-bit register for signal <R_REGS_tcnt256>.
    Found 8-bit register for signal <R_REGS_tcntsnd>.
    Found 1-bit register for signal <IIST_MREQ_lock>.
    Found 1-bit register for signal <IIST_MREQ_boot>.
    Found 1-bit register for signal <R_REGS_ibsel>.
    Found finite state machine <FSM_9> for signal <R_REGS_state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 46                                             |
    | Inputs             | 9                                              |
    | Outputs            | 2                                              |
    | Clock              | CLK (rising_edge)                              |
    | Reset              | BRESET_R_REGS_req_clear_OR_533_o (positive)       |
    | Reset type         | synchronous                                    |
    | Reset State        | s_idle                                         |
    | Power Up State     | s_idle                                         |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit adder for signal <R_REGS_tcnt256[7]_GND_201_o_add_43_OUT> created at line 1241.
    Found 8-bit adder for signal <R_REGS_tcntsnd[7]_GND_201_o_add_46_OUT> created at line 1241.
    Found 4-bit adder for signal <R_REGS_acr_ac[3]_GND_201_o_add_143_OUT> created at line 1241.
    Found 8-bit subtractor for signal <GND_201_o_GND_201_o_sub_185_OUT<7:0>> created at line 1308.
    Found 4-bit 3-to-1 multiplexer for signal <proc_next.iout_imask> created at line 316.
    Found 4-bit 3-to-1 multiplexer for signal <proc_next.iout_bmask> created at line 316.
    Found 1-bit 3-to-1 multiplexer for signal <proc_next.iout_par> created at line 316.
    Found 16-bit 14-to-1 multiplexer for signal <R_REGS_acr_ac[3]_GND_201_o_wide_mux_109_OUT> created at line 382.
    Found 1-bit 4-to-1 multiplexer for signal <GND_201_o_IIST_BUS[3]_imask[3]_Mux_195_o> created at line 602.
    Found 1-bit 4-to-1 multiplexer for signal <GND_201_o_IIST_BUS[3]_bmask[3]_Mux_196_o> created at line 603.
    Found 1-bit 4-to-1 multiplexer for signal <GND_201_o_IIST_BUS[2]_imask[3]_Mux_197_o> created at line 602.
    Found 1-bit 4-to-1 multiplexer for signal <GND_201_o_IIST_BUS[2]_bmask[3]_Mux_198_o> created at line 603.
    Found 1-bit 4-to-1 multiplexer for signal <GND_201_o_IIST_BUS[1]_bmask[3]_Mux_200_o> created at line 603.
    Found 1-bit 4-to-1 multiplexer for signal <proc_next.act_ibit> created at line 602.
    Found 1-bit 4-to-1 multiplexer for signal <proc_next.act_bbit> created at line 603.
    Found 1-bit 4-to-1 multiplexer for signal <_n1258> created at line 602.
    Found 4-bit comparator greater for signal <n0246> created at line 561
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred 107 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred 408 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <ibd_iist> synthesized.

Synthesizing Unit <ibd_kw11l>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ibd_kw11l.vhd".
WARNING:Xst:647 - Input <IB_MREQ_din<5:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_din<15:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_be1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_racc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_REGS_ie>.
    Found 1-bit register for signal <R_REGS_moni>.
    Found 1-bit register for signal <R_REGS_intreq>.
    Found 5-bit register for signal <R_REGS_tcnt>.
    Found 1-bit register for signal <R_REGS_ibsel>.
    Found 5-bit adder for signal <R_REGS_tcnt[4]_GND_204_o_add_5_OUT> created at line 1241.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   9 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <ibd_kw11l> synthesized.

Synthesizing Unit <ibdr_rhrp>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_rhrp.vhd".
    Set property "fsm_encoding = one-hot".
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 5-bit register for signal <R_REGS_state>.
    Found 5-bit register for signal <R_REGS_amap>.
    Found 4-bit register for signal <R_REGS_omux>.
    Found 16-bit register for signal <R_REGS_dinmsk>.
    Found 4-bit register for signal <R_REGS_dtrm>.
    Found 4-bit register for signal <R_REGS_dte1>.
    Found 4-bit register for signal <R_REGS_dte0>.
    Found 6-bit register for signal <R_REGS_bae>.
    Found 1-bit register for signal <R_REGS_cs1sc>.
    Found 1-bit register for signal <R_REGS_cs1tre>.
    Found 1-bit register for signal <R_REGS_cs1rdy>.
    Found 1-bit register for signal <R_REGS_cs1ie>.
    Found 5-bit register for signal <R_REGS_ffunc>.
    Found 1-bit register for signal <R_REGS_fxfer>.
    Found 1-bit register for signal <R_REGS_cs2wce>.
    Found 1-bit register for signal <R_REGS_cs2ned>.
    Found 1-bit register for signal <R_REGS_cs2nem>.
    Found 1-bit register for signal <R_REGS_cs2pge>.
    Found 1-bit register for signal <R_REGS_cs2mxf>.
    Found 1-bit register for signal <R_REGS_cs2pat>.
    Found 1-bit register for signal <R_REGS_cs2bai>.
    Found 1-bit register for signal <R_REGS_cs2unit2>.
    Found 2-bit register for signal <R_REGS_cs2unit>.
    Found 2-bit register for signal <R_REGS_funit>.
    Found 2-bit register for signal <R_REGS_runit>.
    Found 2-bit register for signal <R_REGS_eunit>.
    Found 4-bit register for signal <R_REGS_dsata>.
    Found 4-bit register for signal <R_REGS_dserp>.
    Found 4-bit register for signal <R_REGS_dspip>.
    Found 4-bit register for signal <R_REGS_dsmol>.
    Found 4-bit register for signal <R_REGS_dswrl>.
    Found 4-bit register for signal <R_REGS_dslbt>.
    Found 4-bit register for signal <R_REGS_dsdpr>.
    Found 4-bit register for signal <R_REGS_dsvv>.
    Found 4-bit register for signal <R_REGS_dsom>.
    Found 4-bit register for signal <R_REGS_er1uns>.
    Found 4-bit register for signal <R_REGS_er1wle>.
    Found 4-bit register for signal <R_REGS_er1iae>.
    Found 4-bit register for signal <R_REGS_er1aoe>.
    Found 4-bit register for signal <R_REGS_er1rmr>.
    Found 4-bit register for signal <R_REGS_er1ilf>.
    Found 1-bit register for signal <R_REGS_cs3wco>.
    Found 8-bit register for signal <R_REGS_idlyval>.
    Found 8-bit register for signal <R_REGS_idlycnt>.
    Found 1-bit register for signal <R_REGS_seekdone>.
    Found 1-bit register for signal <R_REGS_poredone>.
    Found 1-bit register for signal <R_REGS_packdone>.
    Found 1-bit register for signal <R_REGS_seardone>.
    Found 1-bit register for signal <R_REGS_ned>.
    Found 1-bit register for signal <R_REGS_cerm>.
    Found 6-bit register for signal <R_REGS_dtyp>.
    Found 10-bit register for signal <R_REGS_camax>.
    Found 5-bit register for signal <R_REGS_tamax>.
    Found 6-bit register for signal <R_REGS_samax>.
    Found 7-bit register for signal <R_REGS_uscnt>.
    Found 6-bit register for signal <R_REGS_sc>.
    Found 2-bit register for signal <R_REGS_clrmode>.
    Found 3-bit register for signal <R_REGS_clrreg>.
    Found 1-bit register for signal <R_REGS_ireq>.
    Found 1-bit register for signal <R_REGS_ibsel>.
    Found finite state machine <FSM_10> for signal <R_REGS_state>.
    -----------------------------------------------------------------------
    | States             | 22                                             |
    | Transitions        | 167                                            |
    | Inputs             | 31                                             |
    | Outputs            | 14                                             |
    | Clock              | CLK (rising_edge)                              |
    | Power Up State     | s_idle                                         |
    | Encoding           | one-hot                                        |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit adder for signal <R_REGS_clrreg[2]_GND_205_o_add_333_OUT> created at line 1241.
    Found 2-bit adder for signal <R_REGS_eunit[1]_GND_205_o_add_336_OUT> created at line 1241.
    Found 7-bit adder for signal <R_REGS_uscnt[6]_GND_205_o_add_421_OUT> created at line 1241.
    Found 6-bit adder for signal <R_REGS_sc[5]_GND_205_o_add_425_OUT> created at line 1241.
    Found 8-bit subtractor for signal <GND_205_o_GND_205_o_sub_74_OUT<7:0>> created at line 1308.
    Found 8x1-bit Read Only RAM for signal <R_REGS_clrreg[2]_GND_205_o_Mux_331_o>
    Found 8x27-bit Read Only RAM for signal <_n3778>
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_cs2unit[1]_R_REGS_dte1[3]_Mux_42_o> created at line 555.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_cs2unit[1]_R_REGS_dte0[3]_Mux_43_o> created at line 556.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_cs2unit[1]_R_REGS_dsdpr[3]_Mux_48_o> created at line 600.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_cs2unit[1]_R_REGS_dtrm[3]_Mux_49_o> created at line 606.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_cs2unit[1]_R_REGS_dspip[3]_Mux_60_o> created at line 773.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_cs2unit[1]_R_REGS_dserp[3]_Mux_188_o> created at line 1030.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_cs2unit[1]_R_REGS_dtrm[3]_Mux_41_o> created at line 1050.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_cs2unit[1]_R_REGS_dswrl[3]_Mux_229_o> created at line 1113.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_cs2unit[1]_INV_829_o> created at line 1119.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_cs2unit[1]_R_REGS_er1iae[3]_Mux_266_o> created at line 1152.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_cs2unit[1]_R_REGS_er1wle[3]_Mux_267_o> created at line 1153.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_dsata[3]_Mux_279_o> created at line 1213.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_dserp[3]_Mux_280_o> created at line 1214.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_dspip[3]_Mux_281_o> created at line 1215.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_dsmol[3]_Mux_282_o> created at line 1216.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_dswrl[3]_Mux_283_o> created at line 1217.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_dslbt[3]_Mux_284_o> created at line 1218.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_dsdpr[3]_Mux_285_o> created at line 1219.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_dsvv[3]_Mux_289_o> created at line 1230.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_dsom[3]_Mux_290_o> created at line 1231.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_er1uns[3]_Mux_291_o> created at line 1234.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_er1wle[3]_Mux_292_o> created at line 1235.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_er1iae[3]_Mux_293_o> created at line 1236.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_er1aoe[3]_Mux_294_o> created at line 1237.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_er1rmr[3]_Mux_295_o> created at line 1238.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_er1ilf[3]_Mux_296_o> created at line 1239.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_runit[1]_R_REGS_dtrm[3]_Mux_297_o> created at line 1252.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_runit[1]_R_REGS_dte1[3]_Mux_298_o> created at line 1253.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_runit[1]_R_REGS_dte0[3]_Mux_299_o> created at line 1254.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_dtrm[3]_Mux_301_o> created at line 1270.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_dte1[3]_Mux_302_o> created at line 1271.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_eunit[1]_R_REGS_dte0[3]_Mux_303_o> created at line 1272.
    Found 16-bit 13-to-1 multiplexer for signal <R_REGS_omux[3]_GND_205_o_wide_mux_304_OUT> created at line 1177.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_clrmode[1]_R_REGS_clrreg[2]_Mux_332_o> created at line 1347.
    Found 5-bit comparator lessequal for signal <n0061> created at line 535
    Found 2-bit comparator equal for signal <R_REGS_cs2unit[1]_R_REGS_funit[1]_equal_62_o> created at line 774
    Found 5-bit comparator greater for signal <n0324> created at line 1024
    Found 10-bit comparator lessequal for signal <R_REGS_camax[9]_MEM_DOUT[9]_LessThan_260_o> created at line 1136
    Found 6-bit comparator greater for signal <R_REGS_samax[5]_MEM_DOUT[5]_LessThan_263_o> created at line 1144
    Found 5-bit comparator greater for signal <R_REGS_tamax[4]_MEM_DOUT[12]_LessThan_264_o> created at line 1145
    Found 2-bit comparator not equal for signal <n0491> created at line 1224
    Found 6-bit comparator lessequal for signal <n0694> created at line 1425
    Summary:
	inferred   2 RAM(s).
	inferred   5 Adder/Subtractor(s).
	inferred 199 D-type flip-flop(s).
	inferred   8 Comparator(s).
	inferred 339 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <ibdr_rhrp> synthesized.

Synthesizing Unit <ibdr_rl11>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_rl11.vhd".
WARNING:Xst:647 - Input <CE_MSEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 4-bit register for signal <R_REGS_state>.
    Found 4-bit register for signal <R_REGS_iaddr>.
    Found 1-bit register for signal <R_REGS_cserr>.
    Found 1-bit register for signal <R_REGS_csde>.
    Found 4-bit register for signal <R_REGS_cse>.
    Found 2-bit register for signal <R_REGS_csds>.
    Found 1-bit register for signal <R_REGS_cscrdy>.
    Found 1-bit register for signal <R_REGS_csie>.
    Found 2-bit register for signal <R_REGS_csbae>.
    Found 3-bit register for signal <R_REGS_csfunc>.
    Found 1-bit register for signal <R_REGS_csdrdy>.
    Found 16-bit register for signal <R_REGS_da>.
    Found 1-bit register for signal <R_REGS_gshs>.
    Found 1-bit register for signal <R_REGS_seekdt>.
    Found 10-bit register for signal <R_REGS_seekcan>.
    Found 9-bit register for signal <R_REGS_seekcac>.
    Found 1-bit register for signal <R_REGS_ireq>.
    Found 3-bit register for signal <R_REGS_mploc>.
    Found 5-bit register for signal <R_REGS_mprem>.
    Found 1-bit register for signal <R_REGS_ibsel>.
    Found finite state machine <FSM_11> for signal <R_REGS_state>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 34                                             |
    | Inputs             | 17                                             |
    | Outputs            | 8                                              |
    | Clock              | CLK (rising_edge)                              |
    | Reset              | BRESET (positive)                              |
    | Reset type         | synchronous                                    |
    | Reset State        | s_init                                         |
    | Power Up State     | s_init                                         |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 10-bit adder for signal <GND_206_o_GND_206_o_add_133_OUT> created at line 576.
    Found 4-bit adder for signal <R_REGS_iaddr[3]_GND_206_o_add_141_OUT> created at line 1241.
    Found 10-bit subtractor for signal <GND_206_o_GND_206_o_sub_135_OUT<9:0>> created at line 579.
    Found 4-bit 4-to-1 multiplexer for signal <IB_MREQ_addr[2]_R_REGS_mprem[2]_wide_mux_101_OUT> created at line 339.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  67 D-type flip-flop(s).
	inferred 146 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <ibdr_rl11> synthesized.

Synthesizing Unit <ram_1swar_gen_8>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/memlib/ram_1swar_gen_unisim.vhd".
        AWIDTH = 4
        DWIDTH = 8
    Summary:
	no macro.
Unit <ram_1swar_gen_8> synthesized.

Synthesizing Unit <ibdr_rk11>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_rk11.vhd".
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <proc_next.icrip>.
    Found 3-bit register for signal <R_REGS_id>.
    Found 4-bit register for signal <R_REGS_sc>.
    Found 1-bit register for signal <R_REGS_cse>.
    Found 1-bit register for signal <R_REGS_wce>.
    Found 1-bit register for signal <R_REGS_he>.
    Found 1-bit register for signal <R_REGS_scp>.
    Found 1-bit register for signal <R_REGS_maint>.
    Found 1-bit register for signal <R_REGS_rdy>.
    Found 1-bit register for signal <R_REGS_ide>.
    Found 3-bit register for signal <R_REGS_drsel>.
    Found 1-bit register for signal <R_REGS_fireq>.
    Found 8-bit register for signal <R_REGS_sireq>.
    Found 8-bit register for signal <R_REGS_sbusy>.
    Found 3-bit register for signal <R_REGS_rid>.
    Found 3-bit register for signal <R_REGS_icnt>.
    Found 1-bit register for signal <R_REGS_creset>.
    Found 1-bit register for signal <R_REGS_crdone>.
    Found 1-bit register for signal <R_REGS_ibsel>.
    Found 3-bit adder for signal <R_REGS_icnt[2]_GND_208_o_add_16_OUT> created at line 1241.
    Found 4-bit adder for signal <R_REGS_sc[3]_GND_208_o_add_87_OUT> created at line 1241.
    Found 1-bit 8-to-1 multiplexer for signal <PWR_155_o_R_REGS_sbusy[7]_Mux_23_o> created at line 311.
    Found 16-bit 7-to-1 multiplexer for signal <IB_MREQ_addr[3]_MEM_DOUT[15]_wide_mux_46_OUT> created at line 293.
    Found 4-bit comparator equal for signal <MEM_DOUT[3]_R_REGS_sc[3]_equal_23_o> created at line 303
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  44 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  95 Multiplexer(s).
Unit <ibdr_rk11> synthesized.

Synthesizing Unit <ibdr_tm11>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_tm11.vhd".
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_REGS_sricmd>.
    Found 1-bit register for signal <R_REGS_srpae>.
    Found 1-bit register for signal <R_REGS_srrle>.
    Found 1-bit register for signal <R_REGS_srbte>.
    Found 1-bit register for signal <R_REGS_srnxm>.
    Found 4-bit register for signal <R_REGS_sreof>.
    Found 4-bit register for signal <R_REGS_sreot>.
    Found 4-bit register for signal <R_REGS_sronl>.
    Found 4-bit register for signal <R_REGS_srbot>.
    Found 4-bit register for signal <R_REGS_srwrl>.
    Found 4-bit register for signal <R_REGS_srrew>.
    Found 2-bit register for signal <R_REGS_crden>.
    Found 1-bit register for signal <R_REGS_crpevn>.
    Found 1-bit register for signal <R_REGS_crunit2>.
    Found 2-bit register for signal <R_REGS_crunit>.
    Found 1-bit register for signal <R_REGS_crrdy>.
    Found 1-bit register for signal <R_REGS_crie>.
    Found 2-bit register for signal <R_REGS_crea>.
    Found 3-bit register for signal <R_REGS_crfunc>.
    Found 16-bit register for signal <R_REGS_bc>.
    Found 15-bit register for signal <R_REGS_ba>.
    Found 2-bit register for signal <R_REGS_runit>.
    Found 1-bit register for signal <R_REGS_resreq>.
    Found 1-bit register for signal <R_REGS_ireq>.
    Found 1-bit register for signal <R_REGS_ibsel>.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_crunit[1]_R_REGS_sronl[3]_Mux_17_o> created at line 240.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_crunit[1]_R_REGS_srbot[3]_Mux_18_o> created at line 241.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_crunit[1]_R_REGS_srwrl[3]_Mux_19_o> created at line 242.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_crunit[1]_R_REGS_srrew[3]_Mux_20_o> created at line 243.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_crunit[1]_R_REGS_sreof[3]_Mux_21_o> created at line 248.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_crunit[1]_R_REGS_sreot[3]_Mux_22_o> created at line 250.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_runit[1]_R_REGS_sreof[3]_Mux_71_o> created at line 357.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_runit[1]_R_REGS_sreot[3]_Mux_72_o> created at line 358.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_runit[1]_R_REGS_sronl[3]_Mux_73_o> created at line 359.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_runit[1]_R_REGS_srbot[3]_Mux_74_o> created at line 360.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_runit[1]_R_REGS_srwrl[3]_Mux_75_o> created at line 361.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS_runit[1]_R_REGS_srrew[3]_Mux_76_o> created at line 362.
    Found 16-bit 7-to-1 multiplexer for signal <IB_MREQ_addr[3]_GND_209_o_wide_mux_96_OUT> created at line 227.
    Found 3-bit comparator lessequal for signal <n0028> created at line 219
    Summary:
	inferred  78 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred 101 Multiplexer(s).
Unit <ibdr_tm11> synthesized.

Synthesizing Unit <ibdr_dl11_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_dl11.vhd".
        IB_ADDR = "1111111101110000"
WARNING:Xst:647 - Input <IB_MREQ_din<11:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_din<15:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 3-bit register for signal <R_REGS_rrlim>.
    Found 1-bit register for signal <R_REGS_rdone>.
    Found 1-bit register for signal <R_REGS_rie>.
    Found 8-bit register for signal <R_REGS_rbuf>.
    Found 1-bit register for signal <R_REGS_rval>.
    Found 1-bit register for signal <R_REGS_rintreq>.
    Found 1-bit register for signal <R_REGS_rdlybsy>.
    Found 10-bit register for signal <R_REGS_rdlycnt>.
    Found 1-bit register for signal <R_REGS_xrdy>.
    Found 1-bit register for signal <R_REGS_xie>.
    Found 1-bit register for signal <R_REGS_xmaint>.
    Found 8-bit register for signal <R_REGS_xbuf>.
    Found 1-bit register for signal <R_REGS_xintreq>.
    Found 1-bit register for signal <R_REGS_ibsel>.
    Found 10-bit subtractor for signal <GND_210_o_GND_210_o_sub_40_OUT<9:0>> created at line 1308.
    Found 8x10-bit Read Only RAM for signal <proc_next.rdlyinit>
    Found 16-bit 4-to-1 multiplexer for signal <IB_MREQ_addr[2]_GND_210_o_wide_mux_18_OUT> created at line 174.
    Found 1-bit 4-to-1 multiplexer for signal <IB_MREQ_addr[2]_GND_210_o_Mux_31_o> created at line 174.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Adder/Subtractor(s).
	inferred  39 D-type flip-flop(s).
	inferred  44 Multiplexer(s).
Unit <ibdr_dl11_1> synthesized.

Synthesizing Unit <ibdr_dl11_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_dl11.vhd".
        IB_ADDR = "1111110101000000"
WARNING:Xst:647 - Input <IB_MREQ_din<11:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_din<15:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 3-bit register for signal <R_REGS_rrlim>.
    Found 1-bit register for signal <R_REGS_rdone>.
    Found 1-bit register for signal <R_REGS_rie>.
    Found 8-bit register for signal <R_REGS_rbuf>.
    Found 1-bit register for signal <R_REGS_rval>.
    Found 1-bit register for signal <R_REGS_rintreq>.
    Found 1-bit register for signal <R_REGS_rdlybsy>.
    Found 10-bit register for signal <R_REGS_rdlycnt>.
    Found 1-bit register for signal <R_REGS_xrdy>.
    Found 1-bit register for signal <R_REGS_xie>.
    Found 1-bit register for signal <R_REGS_xmaint>.
    Found 8-bit register for signal <R_REGS_xbuf>.
    Found 1-bit register for signal <R_REGS_xintreq>.
    Found 1-bit register for signal <R_REGS_ibsel>.
    Found 10-bit subtractor for signal <GND_211_o_GND_211_o_sub_40_OUT<9:0>> created at line 1308.
    Found 8x10-bit Read Only RAM for signal <proc_next.rdlyinit>
    Found 16-bit 4-to-1 multiplexer for signal <IB_MREQ_addr[2]_GND_211_o_wide_mux_18_OUT> created at line 174.
    Found 1-bit 4-to-1 multiplexer for signal <IB_MREQ_addr[2]_GND_211_o_Mux_31_o> created at line 174.
    Summary:
	inferred   1 RAM(s).
	inferred   1 Adder/Subtractor(s).
	inferred  39 D-type flip-flop(s).
	inferred  44 Multiplexer(s).
Unit <ibdr_dl11_2> synthesized.

Synthesizing Unit <ibdr_pc11>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_pc11.vhd".
WARNING:Xst:647 - Input <IB_MREQ_din<14:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_REGS_rerr>.
    Found 1-bit register for signal <R_REGS_rbusy>.
    Found 1-bit register for signal <R_REGS_rdone>.
    Found 1-bit register for signal <R_REGS_rie>.
    Found 8-bit register for signal <R_REGS_rbuf>.
    Found 1-bit register for signal <R_REGS_rintreq>.
    Found 1-bit register for signal <R_REGS_perr>.
    Found 1-bit register for signal <R_REGS_prdy>.
    Found 1-bit register for signal <R_REGS_pie>.
    Found 8-bit register for signal <R_REGS_pbuf>.
    Found 1-bit register for signal <R_REGS_pintreq>.
    Found 1-bit register for signal <R_REGS_ibsel>.
    Found 16-bit 4-to-1 multiplexer for signal <IB_MREQ_addr[2]_GND_212_o_wide_mux_16_OUT> created at line 165.
    Found 1-bit 4-to-1 multiplexer for signal <IB_MREQ_addr[2]_GND_212_o_Mux_28_o> created at line 165.
    Summary:
	inferred  26 D-type flip-flop(s).
	inferred  25 Multiplexer(s).
Unit <ibdr_pc11> synthesized.

Synthesizing Unit <ibdr_lp11>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_lp11.vhd".
WARNING:Xst:647 - Input <IB_MREQ_din<14:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_REGS_err>.
    Found 1-bit register for signal <R_REGS_done>.
    Found 1-bit register for signal <R_REGS_ie>.
    Found 7-bit register for signal <R_REGS_buf>.
    Found 1-bit register for signal <R_REGS_intreq>.
    Found 1-bit register for signal <R_REGS_ibsel>.
    Summary:
	inferred  12 D-type flip-flop(s).
	inferred  11 Multiplexer(s).
Unit <ibdr_lp11> synthesized.

Synthesizing Unit <ibdr_sdreg>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ibdr_sdreg.vhd".
WARNING:Xst:647 - Input <IB_MREQ_rmw> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <IB_MREQ_cacc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16-bit register for signal <R_REGS_sreg>.
    Found 16-bit register for signal <R_REGS_dreg>.
    Found 1-bit register for signal <R_REGS_ibsel>.
    Summary:
	inferred  33 D-type flip-flop(s).
	inferred  18 Multiplexer(s).
Unit <ibdr_sdreg> synthesized.

Synthesizing Unit <ib_intmap>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/ibus/ib_intmap.vhd".
        INTMAP = ((176,6),(64,6),(172,5),(112,5),(144,5),(148,5),(200,5),(204,5),(48,4),(52,4),(192,4),(196,4),(56,4),(60,4),(128,4),(0,0))
    Found 16x12-bit Read Only RAM for signal <_n0060>
    Summary:
	inferred   1 RAM(s).
	inferred  15 Multiplexer(s).
Unit <ib_intmap> synthesized.

Synthesizing Unit <nx_cram_memctl_as>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/bplib/nxcramlib/nx_cram_memctl_as.vhd".
        READ0DELAY = 4
        READ1DELAY = 4
        WRITEDELAY = 5
WARNING:Xst:647 - Input <I_MEM_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_REGS_ackr>.
    Found 1-bit register for signal <R_REGS_addr0>.
    Found 2-bit register for signal <R_REGS_be2nd>.
    Found 3-bit register for signal <R_REGS_cntdly>.
    Found 7-bit register for signal <R_REGS_cntce>.
    Found 1-bit register for signal <R_REGS_fidle>.
    Found 16-bit register for signal <R_REGS_memdo0>.
    Found 32-bit register for signal <R_REGS_memdi>.
    Found 4-bit register for signal <R_REGS_state>.
    Found finite state machine <FSM_12> for signal <R_REGS_state>.
    -----------------------------------------------------------------------
    | States             | 12                                             |
    | Transitions        | 28                                             |
    | Inputs             | 5                                              |
    | Outputs            | 14                                             |
    | Clock              | CLK (rising_edge)                              |
    | Reset              | RESET (positive)                               |
    | Reset type         | synchronous                                    |
    | Reset State        | s_idle                                         |
    | Power Up State     | s_idle                                         |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 7-bit adder for signal <R_REGS_cntce[6]_GND_270_o_add_93_OUT> created at line 1241.
    Found 3-bit subtractor for signal <GND_270_o_GND_270_o_sub_14_OUT<2:0>> created at line 1308.
    Found 7-bit comparator lessequal for signal <n0080> created at line 546
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  63 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred 125 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <nx_cram_memctl_as> synthesized.

Synthesizing Unit <iob_reg_o_gen_4>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_o_gen.vhd".
        DWIDTH = 2
        INIT = '1'
    Set property "IOB = TRUE" for signal <R_DO>.
    Found 2-bit register for signal <R_DO>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <iob_reg_o_gen_4> synthesized.

Synthesizing Unit <iob_reg_o_gen_5>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_o_gen.vhd".
        DWIDTH = 22
        INIT = '0'
    Set property "IOB = TRUE" for signal <R_DO>.
    Found 22-bit register for signal <R_DO>.
    Summary:
	inferred  22 D-type flip-flop(s).
Unit <iob_reg_o_gen_5> synthesized.

Synthesizing Unit <iob_reg_io_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_io_gen.vhd".
        DWIDTH = 16
        INITI = '0'
        INITO = '0'
        INITE = '0'
        PULL = "KEEP"
    Set property "IOB = TRUE" for signal <R_DI>.
    Set property "IOB = TRUE" for signal <R_DO>.
    Set property "IOB = TRUE" for signal <R_TE>.
    Found 16-bit register for signal <R_DI>.
    Found 16-bit register for signal <R_DO>.
    Found 1-bit register for signal <R_TE>.
    Found 1-bit tristate buffer for signal <PAD<15>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<14>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<13>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<12>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<11>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<10>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<9>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<8>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<7>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<6>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<5>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<4>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<3>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<2>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<1>> created at line 90
    Found 1-bit tristate buffer for signal <PAD<0>> created at line 90
    Summary:
	inferred  33 D-type flip-flop(s).
	inferred  16 Tristate(s).
Unit <iob_reg_io_gen_2> synthesized.

Synthesizing Unit <ioleds_sp1c_fx2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/bplib/fx2rlink/ioleds_sp1c_fx2.vhd".
WARNING:Xst:647 - Input <RB_SRES_dout> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SER_MONI_abclkdiv> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SER_MONI_abclkdiv_f> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RESET> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_SRES_ack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_SRES_err> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RLB_MONI_rxhold> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SER_MONI_rxerr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SER_MONI_rxovr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SER_MONI_abact> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SER_MONI_abdone> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 6-bit register for signal <R_LEDDIV>.
    Found 1-bit register for signal <R_LEDCE>.
    Found 6-bit subtractor for signal <GND_290_o_GND_290_o_sub_1_OUT<5:0>> created at line 1308.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   7 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <ioleds_sp1c_fx2> synthesized.

Synthesizing Unit <led_pulse_stretch>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/led_pulse_stretch.vhd".
    Found 2-bit register for signal <n0008>.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <led_pulse_stretch> synthesized.

Synthesizing Unit <pdp11_hio70>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_hio70.vhd".
        LWIDTH = 8
        DCWIDTH = 2
    Summary:
	no macro.
Unit <pdp11_hio70> synthesized.

Synthesizing Unit <pdp11_statleds>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_statleds.vhd".
WARNING:Xst:647 - Input <DM_STAT_DP_pc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_pmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_cc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ireg> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dsrc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ddst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dtmp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dres> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_adst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_mode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CP_STAT_cmdack> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CP_STAT_cmderr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CP_STAT_cmdmerr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CP_STAT_cpustep> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CP_STAT_cpususp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CP_STAT_suspint> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <CP_STAT_suspext> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_rset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_tflag> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ireg_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dsrc_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ddst_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dtmp_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_cpdout_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	inferred  10 Multiplexer(s).
Unit <pdp11_statleds> synthesized.

Synthesizing Unit <pdp11_ledmux>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_ledmux.vhd".
        LWIDTH = 8
WARNING:Xst:647 - Input <DM_STAT_DP_pc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_cmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_pmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_pri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_cc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ireg> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dsrc<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dsrc<15:12>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ddst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dtmp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dres> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_adst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_mode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_rset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_tflag> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ireg_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dsrc_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ddst_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dtmp_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_cpdout_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	inferred   1 Multiplexer(s).
Unit <pdp11_ledmux> synthesized.

Synthesizing Unit <pdp11_dspmux>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/w11a/pdp11_dspmux.vhd".
        DCWIDTH = 2
WARNING:Xst:647 - Input <DM_STAT_DP_psw_cmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_pmode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_pri> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_cc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ireg> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ddst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dtmp> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dres> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_adst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_mode> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_rset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psw_tflag> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_psr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ireg_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dsrc_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_ddst_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_dtmp_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_cpdout_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_bytop> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DM_STAT_DP_gpr_we> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16-bit 4-to-1 multiplexer for signal <proc_mux.idat> created at line 83.
    Summary:
	inferred   1 Multiplexer(s).
Unit <pdp11_dspmux> synthesized.

Synthesizing Unit <sn_humanio_rbus>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/sn_humanio_rbus.vhd".
        SWIDTH = 8
        BWIDTH = 5
        LWIDTH = 8
        DCWIDTH = 2
        DEBOUNCE = true
        RB_ADDR = "1111111011110000"
WARNING:Xst:647 - Input <RB_MREQ_init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 8-bit register for signal <R_REGS_swi>.
    Found 5-bit register for signal <R_REGS_btn>.
    Found 8-bit register for signal <R_REGS_led>.
    Found 16-bit register for signal <R_REGS_dsp_dat>.
    Found 4-bit register for signal <R_REGS_dsp_dp>.
    Found 8-bit register for signal <R_REGS_ledin>.
    Found 8-bit register for signal <R_REGS_swieff>.
    Found 5-bit register for signal <R_REGS_btneff>.
    Found 8-bit register for signal <R_REGS_ledeff>.
    Found 16-bit register for signal <R_REGS_dateff>.
    Found 4-bit register for signal <R_REGS_dpeff>.
    Found 1-bit register for signal <R_REGS_swi_en>.
    Found 1-bit register for signal <R_REGS_led_en>.
    Found 1-bit register for signal <R_REGS_dsp0_en>.
    Found 1-bit register for signal <R_REGS_dsp1_en>.
    Found 1-bit register for signal <R_REGS_dp_en>.
    Found 1-bit register for signal <R_REGS_rbsel>.
    Found 16-bit 7-to-1 multiplexer for signal <RB_MREQ_addr[2]_HIO_DSP_DAT[15]_wide_mux_29_OUT> created at line 284.
    Summary:
	inferred  96 D-type flip-flop(s).
	inferred   9 Multiplexer(s).
Unit <sn_humanio_rbus> synthesized.

Synthesizing Unit <sn_humanio>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/sn_humanio.vhd".
        SWIDTH = 8
        BWIDTH = 5
        LWIDTH = 8
        DCWIDTH = 2
        DEBOUNCE = true
    Summary:
	no macro.
Unit <sn_humanio> synthesized.

Synthesizing Unit <iob_reg_o_gen_6>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_o_gen.vhd".
        DWIDTH = 4
        INIT = '0'
    Set property "IOB = TRUE" for signal <R_DO>.
    Found 4-bit register for signal <R_DO>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <iob_reg_o_gen_6> synthesized.

Synthesizing Unit <iob_reg_o_gen_7>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_o_gen.vhd".
        DWIDTH = 8
        INIT = '0'
    Set property "IOB = TRUE" for signal <R_DO>.
    Found 8-bit register for signal <R_DO>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <iob_reg_o_gen_7> synthesized.

Synthesizing Unit <bp_swibtnled>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/bp_swibtnled.vhd".
        SWIDTH = 8
        BWIDTH = 5
        LWIDTH = 8
        DEBOUNCE = true
    Summary:
	no macro.
Unit <bp_swibtnled> synthesized.

Synthesizing Unit <iob_reg_i_gen_4>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_i_gen.vhd".
        DWIDTH = 8
        INIT = '0'
    Set property "IOB = TRUE" for signal <R_DI>.
    Found 8-bit register for signal <R_DI>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <iob_reg_i_gen_4> synthesized.

Synthesizing Unit <iob_reg_i_gen_5>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/xlib/iob_reg_i_gen.vhd".
        DWIDTH = 5
        INIT = '0'
    Set property "IOB = TRUE" for signal <R_DI>.
    Found 5-bit register for signal <R_DI>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <iob_reg_i_gen_5> synthesized.

Synthesizing Unit <debounce_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/debounce_gen.vhd".
        CWIDTH = 2
        CEDIV = 3
        DWIDTH = 8
    Found 8-bit register for signal <R_REGS_dref>.
    Found 8-bit register for signal <R_REGS_dchange>.
    Found 8-bit register for signal <R_REGS_dout>.
    Found 2-bit register for signal <R_REGS_cecnt>.
    Found 2-bit subtractor for signal <GND_305_o_GND_305_o_sub_10_OUT<1:0>> created at line 1308.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  26 D-type flip-flop(s).
	inferred  17 Multiplexer(s).
Unit <debounce_gen_1> synthesized.

Synthesizing Unit <debounce_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/vlib/genlib/debounce_gen.vhd".
        CWIDTH = 2
        CEDIV = 3
        DWIDTH = 5
    Found 5-bit register for signal <R_REGS_dref>.
    Found 5-bit register for signal <R_REGS_dchange>.
    Found 5-bit register for signal <R_REGS_dout>.
    Found 2-bit register for signal <R_REGS_cecnt>.
    Found 2-bit subtractor for signal <GND_306_o_GND_306_o_sub_10_OUT<1:0>> created at line 1308.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  17 D-type flip-flop(s).
	inferred  11 Multiplexer(s).
Unit <debounce_gen_2> synthesized.

Synthesizing Unit <sn_7segctl>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/bplib/bpgen/sn_7segctl.vhd".
        DCWIDTH = 2
        CDWIDTH = 7
    Found 2-bit register for signal <R_REGS_dcnt>.
    Found 7-bit register for signal <R_REGS_cdiv>.
    Found 2-bit adder for signal <R_REGS_dcnt[1]_GND_307_o_add_4_OUT> created at line 1241.
    Found 4-bit adder for signal <GND_307_o_R_REGS_dcnt[1]_add_19_OUT> created at line 162.
    Found 4-bit adder for signal <GND_307_o_R_REGS_dcnt[1]_add_21_OUT> created at line 163.
    Found 4-bit adder for signal <GND_307_o_R_REGS_dcnt[1]_add_23_OUT> created at line 164.
    Found 7-bit subtractor for signal <proc_next.n_cdiv> created at line 122.
    Found 1-bit 4-to-1 multiplexer for signal <CDP> created at line 160.
    Found 1-bit 16-to-1 multiplexer for signal <CHEX<0>> created at line 161.
    Found 1-bit 16-to-1 multiplexer for signal <CHEX<1>> created at line 162.
    Found 1-bit 16-to-1 multiplexer for signal <CHEX<2>> created at line 163.
    Found 1-bit 16-to-1 multiplexer for signal <CHEX<3>> created at line 164.
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred   9 D-type flip-flop(s).
	inferred   6 Multiplexer(s).
Unit <sn_7segctl> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 20
 128x25-bit single-port Read Only RAM                  : 1
 16x1-bit single-port Read Only RAM                    : 1
 16x12-bit single-port Read Only RAM                   : 1
 16x7-bit single-port Read Only RAM                    : 1
 32x14-bit single-port Read Only RAM                   : 1
 32x5-bit single-port Read Only RAM                    : 4
 4x2-bit single-port Read Only RAM                     : 1
 4x5-bit single-port Read Only RAM                     : 1
 4x6-bit single-port Read Only RAM                     : 1
 4x7-bit single-port Read Only RAM                     : 1
 8x1-bit single-port Read Only RAM                     : 2
 8x10-bit single-port Read Only RAM                    : 2
 8x2-bit single-port Read Only RAM                     : 1
 8x27-bit single-port Read Only RAM                    : 1
 8x7-bit single-port Read Only RAM                     : 1
# Multipliers                                          : 1
 16x16-bit multiplier                                  : 1
# Adders/Subtractors                                   : 86
 10-bit adder                                          : 2
 10-bit addsub                                         : 1
 10-bit subtractor                                     : 4
 11-bit adder                                          : 1
 11-bit subtractor                                     : 1
 12-bit adder                                          : 2
 12-bit subtractor                                     : 1
 13-bit subtractor                                     : 2
 14-bit adder                                          : 3
 15-bit adder                                          : 1
 16-bit adder                                          : 2
 16-bit addsub                                         : 2
 2-bit adder                                           : 4
 2-bit subtractor                                      : 2
 21-bit adder                                          : 2
 3-bit adder                                           : 2
 3-bit subtractor                                      : 1
 36-bit adder                                          : 1
 4-bit adder                                           : 11
 5-bit adder                                           : 9
 5-bit addsub                                          : 2
 5-bit subtractor                                      : 6
 6-bit adder                                           : 1
 6-bit addsub                                          : 1
 6-bit subtractor                                      : 2
 7-bit adder                                           : 3
 7-bit subtractor                                      : 3
 8-bit adder                                           : 4
 8-bit subtractor                                      : 3
 9-bit adder                                           : 7
# Registers                                            : 705
 1-bit register                                        : 406
 10-bit register                                       : 7
 11-bit register                                       : 2
 12-bit register                                       : 7
 13-bit register                                       : 2
 14-bit register                                       : 3
 15-bit register                                       : 7
 16-bit register                                       : 38
 2-bit register                                        : 37
 20-bit register                                       : 2
 21-bit register                                       : 1
 22-bit register                                       : 2
 27-bit register                                       : 1
 3-bit register                                        : 22
 32-bit register                                       : 3
 36-bit register                                       : 1
 4-bit register                                        : 58
 5-bit register                                        : 38
 6-bit register                                        : 7
 7-bit register                                        : 11
 8-bit register                                        : 41
 9-bit register                                        : 9
# Comparators                                          : 49
 10-bit comparator lessequal                           : 1
 12-bit comparator lessequal                           : 2
 14-bit comparator greater                             : 1
 15-bit comparator lessequal                           : 4
 16-bit comparator greater                             : 2
 16-bit comparator lessequal                           : 4
 2-bit comparator equal                                : 3
 2-bit comparator not equal                            : 1
 3-bit comparator equal                                : 2
 3-bit comparator greater                              : 3
 3-bit comparator lessequal                            : 2
 3-bit comparator not equal                            : 1
 4-bit comparator equal                                : 2
 4-bit comparator greater                              : 1
 5-bit comparator greater                              : 4
 5-bit comparator lessequal                            : 3
 6-bit comparator greater                              : 2
 6-bit comparator lessequal                            : 2
 7-bit comparator greater                              : 2
 7-bit comparator lessequal                            : 1
 8-bit comparator equal                                : 2
 8-bit comparator lessequal                            : 1
 9-bit comparator equal                                : 3
# Multiplexers                                         : 3044
 1-bit 16-to-1 multiplexer                             : 4
 1-bit 2-to-1 multiplexer                              : 2148
 1-bit 3-to-1 multiplexer                              : 7
 1-bit 4-to-1 multiplexer                              : 61
 1-bit 7-to-1 multiplexer                              : 4
 1-bit 8-to-1 multiplexer                              : 2
 10-bit 2-to-1 multiplexer                             : 16
 11-bit 2-to-1 multiplexer                             : 1
 12-bit 2-to-1 multiplexer                             : 3
 13-bit 2-to-1 multiplexer                             : 2
 14-bit 2-to-1 multiplexer                             : 1
 16-bit 12-to-1 multiplexer                            : 1
 16-bit 13-to-1 multiplexer                            : 1
 16-bit 14-to-1 multiplexer                            : 1
 16-bit 2-to-1 multiplexer                             : 106
 16-bit 3-to-1 multiplexer                             : 2
 16-bit 4-to-1 multiplexer                             : 19
 16-bit 7-to-1 multiplexer                             : 5
 16-bit 8-to-1 multiplexer                             : 4
 2-bit 2-to-1 multiplexer                              : 118
 21-bit 2-to-1 multiplexer                             : 3
 22-bit 2-to-1 multiplexer                             : 1
 22-bit 4-to-1 multiplexer                             : 1
 3-bit 2-to-1 multiplexer                              : 103
 32-bit 2-to-1 multiplexer                             : 1
 36-bit 2-to-1 multiplexer                             : 1
 4-bit 2-to-1 multiplexer                              : 172
 4-bit 3-to-1 multiplexer                              : 2
 4-bit 4-to-1 multiplexer                              : 2
 4-bit 7-to-1 multiplexer                              : 1
 5-bit 2-to-1 multiplexer                              : 34
 6-bit 2-to-1 multiplexer                              : 10
 7-bit 2-to-1 multiplexer                              : 107
 8-bit 2-to-1 multiplexer                              : 47
 9-bit 2-to-1 multiplexer                              : 53
# Tristates                                            : 24
 1-bit tristate buffer                                 : 24
# FSMs                                                 : 13
# Xors                                                 : 101
 1-bit xor10                                           : 4
 1-bit xor2                                            : 86
 1-bit xor3                                            : 6
 1-bit xor4                                            : 2
 16-bit xor2                                           : 1
 8-bit xor2                                            : 2

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


Synthesizing (advanced) Unit <clkdivce>.
The following registers are absorbed into counter <R_REGS_ucnt>: 1 register on signal <R_REGS_ucnt>.
The following registers are absorbed into counter <R_REGS_mcnt>: 1 register on signal <R_REGS_mcnt>.
Unit <clkdivce> synthesized (advanced).

Synthesizing (advanced) Unit <debounce_gen_1>.
The following registers are absorbed into counter <R_REGS_cecnt>: 1 register on signal <R_REGS_cecnt>.
Unit <debounce_gen_1> synthesized (advanced).

Synthesizing (advanced) Unit <debounce_gen_2>.
The following registers are absorbed into counter <R_REGS_cecnt>: 1 register on signal <R_REGS_cecnt>.
Unit <debounce_gen_2> synthesized (advanced).

Synthesizing (advanced) Unit <fifo_1c_dram_raw>.
The following registers are absorbed into counter <R_REGS_raddr>: 1 register on signal <R_REGS_raddr>.
The following registers are absorbed into counter <R_REGS_waddr>: 1 register on signal <R_REGS_waddr>.
Unit <fifo_1c_dram_raw> synthesized (advanced).

Synthesizing (advanced) Unit <fx2_2fifoctl_ic>.
The following registers are absorbed into counter <R_REGS_ccnt>: 1 register on signal <R_REGS_ccnt>.
The following registers are absorbed into counter <R_REGS_petocnt>: 1 register on signal <R_REGS_petocnt>.
Unit <fx2_2fifoctl_ic> synthesized (advanced).

Synthesizing (advanced) Unit <gray_cnt_5>.
INFO:Xst:3216 - HDL ADVISOR - LUT implementation is currently selected for the RAM <Mram_N_DATA>. If you want the register to be removed and the RAM to be implemented as block RAM, please change the RAM implementation style accordingly.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 32-word x 5-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <R_DATA>        |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to signal <N_DATA>        |          |
    -----------------------------------------------------------------------
Unit <gray_cnt_5> synthesized (advanced).

Synthesizing (advanced) Unit <ib_intmap>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram__n0060> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16-word x 12-bit                    |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <EI_LINE>       |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <ib_intmap> synthesized (advanced).

Synthesizing (advanced) Unit <ibd_ibmon>.
The following registers are absorbed into counter <R_REGS_laddr>: 1 register on signal <R_REGS_laddr>.
The following registers are absorbed into counter <R_REGS_ibnbusy>: 1 register on signal <R_REGS_ibnbusy>.
The following registers are absorbed into counter <R_REGS_ibndly>: 1 register on signal <R_REGS_ibndly>.
Unit <ibd_ibmon> synthesized (advanced).

Synthesizing (advanced) Unit <ibd_iist>.
The following registers are absorbed into counter <R_REGS_tcntsnd>: 1 register on signal <R_REGS_tcntsnd>.
The following registers are absorbed into counter <R_REGS_acr_ac>: 1 register on signal <R_REGS_acr_ac>.
The following registers are absorbed into counter <R_REGS_stc_count>: 1 register on signal <R_REGS_stc_count>.
Unit <ibd_iist> synthesized (advanced).

Synthesizing (advanced) Unit <ibd_kw11l>.
The following registers are absorbed into counter <R_REGS_tcnt>: 1 register on signal <R_REGS_tcnt>.
Unit <ibd_kw11l> synthesized (advanced).

Synthesizing (advanced) Unit <ibdr_dl11_1>.
The following registers are absorbed into counter <R_REGS_rdlycnt>: 1 register on signal <R_REGS_rdlycnt>.
INFO:Xst:3212 - HDL ADVISOR - Asynchronous or synchronous initialization of the register <R_REGS_rrlim> prevents it from being combined with the RAM <Mram_proc_next.rdlyinit> for implementation as read-only block RAM.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 10-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <R_REGS_rrlim>  |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to signal <proc_next.rdlyinit> |          |
    -----------------------------------------------------------------------
Unit <ibdr_dl11_1> synthesized (advanced).

Synthesizing (advanced) Unit <ibdr_dl11_2>.
The following registers are absorbed into counter <R_REGS_rdlycnt>: 1 register on signal <R_REGS_rdlycnt>.
INFO:Xst:3212 - HDL ADVISOR - Asynchronous or synchronous initialization of the register <R_REGS_rrlim> prevents it from being combined with the RAM <Mram_proc_next.rdlyinit> for implementation as read-only block RAM.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 10-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <R_REGS_rrlim>  |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to signal <proc_next.rdlyinit> |          |
    -----------------------------------------------------------------------
Unit <ibdr_dl11_2> synthesized (advanced).

Synthesizing (advanced) Unit <ibdr_rhrp>.
The following registers are absorbed into counter <R_REGS_eunit>: 1 register on signal <R_REGS_eunit>.
The following registers are absorbed into counter <R_REGS_idlycnt>: 1 register on signal <R_REGS_idlycnt>.
The following registers are absorbed into counter <R_REGS_uscnt>: 1 register on signal <R_REGS_uscnt>.
The following registers are absorbed into counter <R_REGS_clrreg>: 1 register on signal <R_REGS_clrreg>.
The following registers are absorbed into counter <R_REGS_sc>: 1 register on signal <R_REGS_sc>.
INFO:Xst:3231 - The small RAM <Mram__n3778> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 27-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <(R_REGS_cs2unit[1]_R_REGS_dtrm[3]_Mux_41_o,R_REGS_cs2unit[1]_R_REGS_dte1[3]_Mux_42_o,R_REGS_cs2unit[1]_R_REGS_dte0[3]_Mux_43_o)> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_R_REGS_clrreg[2]_GND_205_o_Mux_331_o> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 1-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <R_REGS_clrreg> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <ibdr_rhrp> synthesized (advanced).

Synthesizing (advanced) Unit <ibdr_rk11>.
The following registers are absorbed into counter <R_REGS_sc>: 1 register on signal <R_REGS_sc>.
The following registers are absorbed into counter <R_REGS_icnt>: 1 register on signal <R_REGS_icnt>.
Unit <ibdr_rk11> synthesized (advanced).

Synthesizing (advanced) Unit <ibdr_rl11>.
The following registers are absorbed into counter <R_REGS_iaddr>: 1 register on signal <R_REGS_iaddr>.
Unit <ibdr_rl11> synthesized (advanced).

Synthesizing (advanced) Unit <ioleds_sp1c_fx2>.
The following registers are absorbed into counter <R_LEDDIV>: 1 register on signal <R_LEDDIV>.
Unit <ioleds_sp1c_fx2> synthesized (advanced).

Synthesizing (advanced) Unit <nx_cram_memctl_as>.
The following registers are absorbed into counter <R_REGS_cntce>: 1 register on signal <R_REGS_cntce>.
Unit <nx_cram_memctl_as> synthesized (advanced).

Synthesizing (advanced) Unit <pdp11_core_rbus>.
The following registers are absorbed into counter <R_REGS_addr>: 1 register on signal <R_REGS_addr>.
Unit <pdp11_core_rbus> synthesized (advanced).

Synthesizing (advanced) Unit <pdp11_decode>.
INFO:Xst:3231 - The small RAM <Mram__n0593> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 6-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <IREG<5:4>>     |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
INFO:Xst:3231 - The small RAM <Mram_proc_idecode.nstat_fork_srcr> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 2-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <IREG<11:10>>   |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to signal <proc_idecode.nstat_fork_srcr> |          |
    -----------------------------------------------------------------------
Unit <pdp11_decode> synthesized (advanced).

Synthesizing (advanced) Unit <pdp11_dmcmon>.
The following registers are absorbed into counter <R_REGS_cnum>: 1 register on signal <R_REGS_cnum>.
The following registers are absorbed into counter <R_REGS_mal_raddr>: 1 register on signal <R_REGS_mal_raddr>.
The following registers are absorbed into counter <R_REGS_laddr>: 1 register on signal <R_REGS_laddr>.
The following registers are absorbed into counter <R_REGS_mal_waddr>: 1 register on signal <R_REGS_mal_waddr>.
Unit <pdp11_dmcmon> synthesized (advanced).

Synthesizing (advanced) Unit <pdp11_mmu>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_proc_nssr0.abo_nonres> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 1-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <SARSDR_acf>    |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to signal <proc_nssr0.abo_nonres> |          |
    -----------------------------------------------------------------------
Unit <pdp11_mmu> synthesized (advanced).

Synthesizing (advanced) Unit <pdp11_munit>.
The following registers are absorbed into counter <R_SHC>: 1 register on signal <R_SHC>.
Unit <pdp11_munit> synthesized (advanced).

Synthesizing (advanced) Unit <pdp11_sequencer>.
INFO:Xst:3212 - HDL ADVISOR - Asynchronous or synchronous initialization of the register <R_IDSTAT_fork_dstr> prevents it from being combined with the RAM <Mram_R_IDSTAT_fork_dstr[1]_PWR_129_o_wide_mux_148_OUT> for implementation as read-only block RAM.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 5-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <R_IDSTAT_fork_dstr> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
INFO:Xst:3212 - HDL ADVISOR - Asynchronous or synchronous initialization of the register <R_IDSTAT_fork_dsta> prevents it from being combined with the RAM <Mram_R_IDSTAT_fork_dsta[1]_GND_139_o_wide_mux_328_OUT> for implementation as read-only block RAM.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 7-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <R_IDSTAT_fork_dsta> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
INFO:Xst:3212 - HDL ADVISOR - Asynchronous or synchronous initialization of the register <R_IDSTAT_fork_opg> prevents it from being combined with the RAM <Mram_R_IDSTAT_fork_opg[3]_PWR_129_o_wide_mux_174_OUT> for implementation as read-only block RAM.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16-word x 7-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <R_IDSTAT_fork_opg> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
INFO:Xst:3212 - HDL ADVISOR - Asynchronous or synchronous initialization of the register <R_IDSTAT_fork_opa> prevents it from being combined with the RAM <Mram_R_IDSTAT_fork_opa[2]_PWR_129_o_wide_mux_216_OUT> for implementation as read-only block RAM.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 7-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <R_IDSTAT_fork_opa> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
INFO:Xst:3212 - HDL ADVISOR - Asynchronous or synchronous initialization of the register <R_STATUS_cpfunc> prevents it from being combined with the RAM <Mram_R_STATUS_cpfunc[4]_GND_139_o_Mux_83_o> for implementation as read-only block RAM.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16-word x 1-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <R_STATUS_cpfunc<4:1>> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
INFO:Xst:3212 - HDL ADVISOR - Asynchronous or synchronous initialization of the register <R_STATUS_cpfunc> prevents it from being combined with the RAM <Mram__n3125> for implementation as read-only block RAM.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 32-word x 14-bit                    |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <R_STATUS_cpfunc> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
INFO:Xst:3226 - The RAM <Mram__n3279> will be implemented as a BLOCK RAM, absorbing the following register(s): <R_STATE>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 128-word x 25-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkA           | connected to signal <CLK>           | rise     |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <proc_next.nstate> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <pdp11_sequencer> synthesized (advanced).

Synthesizing (advanced) Unit <pdp11_vmbox>.
The following registers are absorbed into counter <R_REGS_atocnt>: 1 register on signal <R_REGS_atocnt>.
Unit <pdp11_vmbox> synthesized (advanced).

Synthesizing (advanced) Unit <rbd_rbmon>.
The following registers are absorbed into counter <R_REGS_laddr>: 1 register on signal <R_REGS_laddr>.
The following registers are absorbed into counter <R_REGS_rbnbusy>: 1 register on signal <R_REGS_rbnbusy>.
The following registers are absorbed into counter <R_REGS_rbndly>: 1 register on signal <R_REGS_rbndly>.
Unit <rbd_rbmon> synthesized (advanced).

Synthesizing (advanced) Unit <rlink_core>.
The following registers are absorbed into counter <R_BREGS_btocnt>: 1 register on signal <R_BREGS_btocnt>.
The following registers are absorbed into counter <R_LREGS_bcnt>: 1 register on signal <R_LREGS_bcnt>.
The following registers are absorbed into counter <R_LREGS_atocnt>: 1 register on signal <R_LREGS_atocnt>.
The following registers are absorbed into counter <R_BREGS_cnt>: 1 register on signal <R_BREGS_cnt>.
The following registers are absorbed into counter <R_LREGS_rtaddra>: 1 register on signal <R_LREGS_rtaddra>.
The following registers are absorbed into counter <R_LREGS_rtaddrb>: 1 register on signal <R_LREGS_rtaddrb>.
The following registers are absorbed into counter <R_BREGS_dcnt>: 1 register on signal <R_BREGS_dcnt>.
INFO:Xst:3231 - The small RAM <Mram__n2064> will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on block, use option/constraint ram_style.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 2-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <R_LREGS_rcmd<2:0>> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <rlink_core> synthesized (advanced).

Synthesizing (advanced) Unit <serport_uart_autobaud>.
The following registers are absorbed into counter <R_REGS_ccnt>: 1 register on signal <R_REGS_ccnt>.
The following registers are absorbed into counter <R_REGS_mcnt>: 1 register on signal <R_REGS_mcnt>.
Unit <serport_uart_autobaud> synthesized (advanced).

Synthesizing (advanced) Unit <serport_uart_rx>.
The following registers are absorbed into counter <R_REGS_ccnt>: 1 register on signal <R_REGS_ccnt>.
The following registers are absorbed into counter <R_REGS_dcnt>: 1 register on signal <R_REGS_dcnt>.
The following registers are absorbed into counter <R_REGS_bcnt>: 1 register on signal <R_REGS_bcnt>.
Unit <serport_uart_rx> synthesized (advanced).

Synthesizing (advanced) Unit <serport_uart_tx>.
The following registers are absorbed into counter <R_REGS_ccnt>: 1 register on signal <R_REGS_ccnt>.
The following registers are absorbed into counter <R_REGS_bcnt>: 1 register on signal <R_REGS_bcnt>.
Unit <serport_uart_tx> synthesized (advanced).

Synthesizing (advanced) Unit <sn_7segctl>.
The following registers are absorbed into counter <R_REGS_dcnt>: 1 register on signal <R_REGS_dcnt>.
The following registers are absorbed into counter <R_REGS_cdiv>: 1 register on signal <R_REGS_cdiv>.
Unit <sn_7segctl> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 20
 128x25-bit single-port block Read Only RAM            : 1
 16x1-bit single-port distributed Read Only RAM        : 1
 16x12-bit single-port distributed Read Only RAM       : 1
 16x7-bit single-port distributed Read Only RAM        : 1
 32x14-bit single-port distributed Read Only RAM       : 1
 32x5-bit single-port distributed Read Only RAM        : 4
 4x2-bit single-port distributed Read Only RAM         : 1
 4x5-bit single-port distributed Read Only RAM         : 1
 4x6-bit single-port distributed Read Only RAM         : 1
 4x7-bit single-port distributed Read Only RAM         : 1
 8x1-bit single-port distributed Read Only RAM         : 2
 8x10-bit single-port distributed Read Only RAM        : 2
 8x2-bit single-port distributed Read Only RAM         : 1
 8x27-bit single-port distributed Read Only RAM        : 1
 8x7-bit single-port distributed Read Only RAM         : 1
# Multipliers                                          : 1
 16x16-bit multiplier                                  : 1
# Adders/Subtractors                                   : 27
 10-bit addsub                                         : 1
 15-bit adder                                          : 1
 16-bit adder                                          : 1
 16-bit addsub                                         : 2
 2-bit adder                                           : 2
 21-bit adder                                          : 1
 3-bit subtractor                                      : 1
 36-bit adder                                          : 1
 4-bit adder                                           : 4
 5-bit adder                                           : 2
 5-bit addsub                                          : 2
 5-bit subtractor                                      : 5
 8-bit adder                                           : 1
 9-bit adder                                           : 1
 9-bit adder carry in                                  : 2
# Counters                                             : 57
 10-bit down counter                                   : 4
 10-bit up counter                                     : 2
 11-bit down counter                                   : 1
 11-bit up counter                                     : 1
 12-bit down counter                                   : 1
 12-bit up counter                                     : 2
 13-bit down counter                                   : 2
 14-bit up counter                                     : 3
 16-bit up counter                                     : 1
 2-bit down counter                                    : 2
 2-bit up counter                                      : 2
 21-bit up counter                                     : 1
 3-bit up counter                                      : 2
 4-bit up counter                                      : 7
 5-bit down counter                                    : 1
 5-bit up counter                                      : 7
 6-bit down counter                                    : 2
 6-bit up counter                                      : 1
 6-bit updown counter                                  : 1
 7-bit down counter                                    : 3
 7-bit up counter                                      : 3
 8-bit down counter                                    : 3
 8-bit up counter                                      : 3
 9-bit up counter                                      : 2
# Registers                                            : 2280
 Flip-Flops                                            : 2280
# Comparators                                          : 49
 10-bit comparator lessequal                           : 1
 12-bit comparator lessequal                           : 2
 14-bit comparator greater                             : 1
 15-bit comparator lessequal                           : 4
 16-bit comparator greater                             : 2
 16-bit comparator lessequal                           : 4
 2-bit comparator equal                                : 3
 2-bit comparator not equal                            : 1
 3-bit comparator equal                                : 2
 3-bit comparator greater                              : 3
 3-bit comparator lessequal                            : 2
 3-bit comparator not equal                            : 1
 4-bit comparator equal                                : 2
 4-bit comparator greater                              : 1
 5-bit comparator greater                              : 4
 5-bit comparator lessequal                            : 3
 6-bit comparator greater                              : 2
 6-bit comparator lessequal                            : 2
 7-bit comparator greater                              : 2
 7-bit comparator lessequal                            : 1
 8-bit comparator equal                                : 2
 8-bit comparator lessequal                            : 1
 9-bit comparator equal                                : 3
# Multiplexers                                         : 3127
 1-bit 16-to-1 multiplexer                             : 4
 1-bit 2-to-1 multiplexer                              : 2260
 1-bit 3-to-1 multiplexer                              : 7
 1-bit 4-to-1 multiplexer                              : 61
 1-bit 7-to-1 multiplexer                              : 4
 1-bit 8-to-1 multiplexer                              : 18
 10-bit 2-to-1 multiplexer                             : 14
 12-bit 2-to-1 multiplexer                             : 1
 16-bit 12-to-1 multiplexer                            : 1
 16-bit 13-to-1 multiplexer                            : 1
 16-bit 14-to-1 multiplexer                            : 1
 16-bit 2-to-1 multiplexer                             : 102
 16-bit 3-to-1 multiplexer                             : 2
 16-bit 4-to-1 multiplexer                             : 19
 16-bit 7-to-1 multiplexer                             : 5
 16-bit 8-to-1 multiplexer                             : 3
 2-bit 2-to-1 multiplexer                              : 111
 21-bit 2-to-1 multiplexer                             : 2
 22-bit 2-to-1 multiplexer                             : 1
 22-bit 4-to-1 multiplexer                             : 1
 3-bit 2-to-1 multiplexer                              : 102
 32-bit 2-to-1 multiplexer                             : 1
 36-bit 2-to-1 multiplexer                             : 1
 4-bit 2-to-1 multiplexer                              : 168
 4-bit 3-to-1 multiplexer                              : 2
 4-bit 4-to-1 multiplexer                              : 2
 4-bit 7-to-1 multiplexer                              : 1
 5-bit 2-to-1 multiplexer                              : 33
 6-bit 2-to-1 multiplexer                              : 7
 7-bit 2-to-1 multiplexer                              : 106
 8-bit 2-to-1 multiplexer                              : 38
 9-bit 2-to-1 multiplexer                              : 48
# FSMs                                                 : 13
# Xors                                                 : 101
 1-bit xor10                                           : 4
 1-bit xor2                                            : 86
 1-bit xor3                                            : 6
 1-bit xor4                                            : 2
 16-bit xor2                                           : 1
 8-bit xor2                                            : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch <R_MONI_C_pktend_3> has a constant value of 0 in block <fx2_2fifoctl_ic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_MONI_C_pktend_4> has a constant value of 0 in block <fx2_2fifoctl_ic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_MONI_C_pktend_9> has a constant value of 0 in block <fx2_2fifoctl_ic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_MONI_S_pktend_3> has a constant value of 0 in block <fx2_2fifoctl_ic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_MONI_S_pktend_4> has a constant value of 0 in block <fx2_2fifoctl_ic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <R_MONI_S_pktend_9> has a constant value of 0 in block <fx2_2fifoctl_ic>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <R_STATUS_suspext> has a constant value of 0 in block <pdp11_sequencer>. This FF/Latch will be trimmed during the optimization process.
Optimizing FSM <RLINK/CORE/RL/FSM_0> on signal <R_BREGS_state[1:13]> with one-hot encoding.
----------------------------
 State     | Encoding
----------------------------
 sb_idle   | 0000000000001
 sb_rstart | 0000000000010
 sb_rreg0  | 0000000001000
 sb_rreg1  | 0000000010000
 sb_rwait  | 0000010000000
 sb_rend   | 0000000100000
 sb_rabo0  | 0000100000000
 sb_rabo1  | 0000001000000
 sb_wstart | 0000000000100
 sb_wreg0  | 0001000000000
 sb_wreg1  | 0010000000000
 sb_wabo0  | 0100000000000
 sb_wabo1  | 1000000000000
----------------------------
Optimizing FSM <RLINK/CORE/RL/FSM_1> on signal <R_LREGS_state[1:40]> with one-hot encoding.
----------------------------------------------------------
 State        | Encoding
----------------------------------------------------------
 sl_idle      | 0000000000000000000000000000000000000001
 sl_txanot    | 0000000000000000000000000000000000000100
 sl_txsop     | 0000000000000000000000000000000000000010
 sl_txnak     | 0000000000000000000000000000000100000000
 sl_txnakcode | 0000000000000000000000000000000001000000
 sl_txrtbuf   | 0000000000000000000000000000000000100000
 sl_txeop     | 0000000000000000000000000000001000000000
 sl_rxeop     | 0000000000000000000000000000000010000000
 sl_rxcmd     | 0000000000000000000000000000000000010000
 sl_rxaddrl   | 0000000000000000000000000000010000000000
 sl_rxaddrh   | 0000000000000000000000000001000000000000
 sl_rxdatl    | 0000000000000000000000000100000000000000
 sl_rxdath    | 0000000000000000000000001000000000000000
 sl_rxcntl    | 0000000000000000000000000010000000000000
 sl_rxcnth    | 0000000000000000000000010000000000000000
 sl_rxccrcl   | 0000000000000000000000000000100000000000
 sl_rxccrch   | 0000000000000000000000100000000000000000
 sl_txcmd     | 0000000000000000000001000000000000000000
 sl_txcntl    | 0000000000000000000000000000000000001000
 sl_txcnth    | 0000000000000100000000000000000000000000
 sl_rstart    | 0000000000000000000010000000000000000000
 sl_txdat     | 0000000000100000000000000000000000000000
 sl_wblk      | 0000000000000000010000000000000000000000
 sl_rxwblk    | 0000000001000000000000000000000000000000
 sl_rxdcrcl   | 0000000000000000001000000000000000000000
 sl_rxdcrch   | 0000000010000000000000000000000000000000
 sl_wblk0     | 0000000100000000000000000000000000000000
 sl_wblk1     | 0000001000000000000000000000000000000000
 sl_wblk2     | 0000010000000000000000000000000000000000
 sl_wblkl     | 0000100000000000000000000000000000000000
 sl_wblkh     | 0001000000000000000000000000000000000000
 sl_wwait0    | 0000000000000000000100000000000000000000
 sl_wwait1    | 0010000000000000000000000000000000000000
 sl_txdcntl   | 0000000000001000000000000000000000000000
 sl_txdcnth   | 0100000000000000000000000000000000000000
 sl_txlabo    | 0000000000000000100000000000000000000000
 sl_attn      | 0000000000000001000000000000000000000000
 sl_txstat    | 0000000000000010000000000000000000000000
 sl_txcrcl    | 0000000000010000000000000000000000000000
 sl_txcrch    | 1000000000000000000000000000000000000000
----------------------------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <RLINK/FX2CNTL/FSM_4> on signal <R_REGS_state[1:4]> with user encoding.
-----------------------
 State     | Encoding
-----------------------
 s_idle    | 0000
 s_rxprep0 | 0001
 s_rxprep1 | 0010
 s_rxprep2 | 0011
 s_rxdisp  | 0100
 s_rxpipe  | 0101
 s_txprep0 | 0110
 s_txprep1 | 0111
 s_txprep2 | 1000
 s_txdisp  | 1001
-----------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <RLINK/SERPORT/UART/RXTX/RX/FSM_3> on signal <R_REGS_state[1:3]> with user encoding.
---------------------
 State   | Encoding
---------------------
 s_idle  | 000
 s_colb0 | 001
 s_endb0 | 010
 s_colbx | 011
 s_endbx | 100
 s_colb9 | 101
 s_endb9 | 110
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <RLINK/SERPORT/UART/AB/FSM_2> on signal <R_REGS_state[1:2]> with user encoding.
---------------------
 State   | Encoding
---------------------
 s_idle  | 00
 s_break | 01
 s_wait  | 10
 s_sync  | 11
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <SRAM_CTL/FSM_12> on signal <R_REGS_state[1:4]> with user encoding.
-----------------------
 State     | Encoding
-----------------------
 s_idle    | 0000
 s_rdinit  | 0001
 s_rdwait0 | 0010
 s_rdget0  | 0011
 s_rdwait1 | 0100
 s_rdget1  | 0101
 s_wrinit  | 0110
 s_wrwait0 | 0111
 s_wrput0  | 1000
 s_wrini1  | 1001
 s_wrwait1 | 1010
 s_wrput1  | 1011
-----------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <SYS70/RB2CP/FSM_5> on signal <R_REGS_state[1:2]> with user encoding.
----------------------
 State    | Encoding
----------------------
 s_idle   | 00
 s_cpwait | 01
 s_cpstep | 10
----------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <SYS70/DMSCNT.I0/FSM_8> on signal <R_REGS_waddr[1:2]> with user encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 10
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <SYS70/W11A/VMBOX/FSM_6> on signal <R_REGS_state[1:4]> with user encoding.
---------------------------
 State         | Encoding
---------------------------
 s_idle        | 0000
 s_mem_w       | 0001
 s_ib_w        | 0010
 s_ib_wend     | 0011
 s_ib_rend     | 0100
 s_idle_mw_ib  | 0101
 s_idle_mw_mem | 0110
 s_mem_mw_w    | 0111
 s_fail        | 1000
 s_errrsv      | 1001
 s_errib       | 1010
---------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <SYS70/CACHE/FSM_7> on signal <R_REGS_state[1:2]> with gray encoding.
---------------------
 State   | Encoding
---------------------
 s_idle  | 00
 s_read  | 11
 s_rmiss | 10
 s_write | 01
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <IBDR_SYS/IIST.I0/FSM_9> on signal <R_REGS_state[1:2]> with sequential encoding.
---------------------
 State   | Encoding
---------------------
 s_idle  | 00
 s_clear | 11
 s_stsnd | 10
 s_pgsnd | 01
---------------------
Optimizing FSM <IBDR_SYS/RHRP.I0/FSM_10> on signal <R_REGS_state[1:22]> with one-hot encoding.
--------------------------------------
 State      | Encoding
--------------------------------------
 s_idle     | 0000000000000000000001
 s_wcs1     | 0000000000000000001000
 s_wcs2     | 0000000000000001000000
 s_wcs3     | 0000000010000000000000
 s_wer1     | 0000000000000100000000
 s_was      | 0000000000001000000000
 s_wdt      | 0000000000100000000000
 s_wds      | 0000000000000010000000
 s_wbae     | 0000000001000000000000
 s_wmem     | 0000000000000000100000
 s_wmembe   | 0000000000000000010000
 s_whr      | 0000000000010000000000
 s_funcchk  | 0000001000000000000000
 s_funcgo   | 0000010000000000000000
 s_chkdc    | 0000100000000000000000
 s_chkda    | 0001000000000000000000
 s_chkdo    | 0010000000000000000000
 s_read     | 0000000000000000000100
 s_setrmr   | 0000000100000000000000
 s_oot_clr0 | 0000000000000000000010
 s_oot_clr1 | 0100000000000000000000
 s_oot_clr2 | 1000000000000000000000
--------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <IBDR_SYS/RL11.I0/FSM_11> on signal <R_REGS_state[1:4]> with user encoding.
-------------------------
 State       | Encoding
-------------------------
 s_idle      | 0000
 s_csread    | 0001
 s_gs_rpos   | 0010
 s_gs_sta    | 0011
 s_seek_rsta | 0100
 s_seek_rpos | 0101
 s_seek_clip | 0110
 s_seek_wpos | 0111
 s_init      | 1000
-------------------------
WARNING:Xst:1293 - FF/Latch <R_REGS_samax_3> has a constant value of 0 in block <ibdr_rhrp>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:1901 - Instance RTBUF/UMEM/AW_12_S4.GL[0].MEM in unit rlink_core of type RAMB16_S4_S4 has been replaced by RAMB16BWER
INFO:Xst:1901 - Instance RTBUF/UMEM/AW_12_S4.GL[1].MEM in unit rlink_core of type RAMB16_S4_S4 has been replaced by RAMB16BWER
INFO:Xst:1901 - Instance BRAM1/UMEM/AW_09_S32.GL[0].MEM in unit rbd_rbmon of type RAMB16_S36 has been replaced by RAMB16BWER
INFO:Xst:1901 - Instance BRAM0/UMEM/AW_09_S32.GL[0].MEM in unit rbd_rbmon of type RAMB16_S36 has been replaced by RAMB16BWER
INFO:Xst:1901 - Instance CMEM/UMEM/AW_09_S36.GL[0].MEM in unit pdp11_dmscnt of type RAMB16_S36_S36 has been replaced by RAMB16BWER
INFO:Xst:1901 - Instance BRAM0/UMEM/AW_09_S36.GL[0].MEM in unit pdp11_dmcmon of type RAMB16_S36_S36 has been replaced by RAMB16BWER
INFO:Xst:1901 - Instance BRAM1/UMEM/AW_09_S36.GL[0].MEM in unit pdp11_dmcmon of type RAMB16_S36_S36 has been replaced by RAMB16BWER
INFO:Xst:1901 - Instance CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM in unit pdp11_cache of type RAMB16_S9_S9 has been replaced by RAMB16BWER
INFO:Xst:1901 - Instance CMEM_DAT0/UMEM/AW_11_S9.GL[0].MEM in unit pdp11_cache of type RAMB16_S9_S9 has been replaced by RAMB16BWER
INFO:Xst:1901 - Instance CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM in unit pdp11_cache of type RAMB16_S9_S9 has been replaced by RAMB16BWER
INFO:Xst:1901 - Instance CMEM_DAT2/UMEM/AW_11_S9.GL[0].MEM in unit pdp11_cache of type RAMB16_S9_S9 has been replaced by RAMB16BWER
INFO:Xst:1901 - Instance CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM in unit pdp11_cache of type RAMB16_S9_S9 has been replaced by RAMB16BWER
INFO:Xst:1901 - Instance BRAM1/UMEM/AW_09_S32.GL[0].MEM in unit ibd_ibmon of type RAMB16_S36 has been replaced by RAMB16BWER
INFO:Xst:1901 - Instance BRAM0/UMEM/AW_09_S32.GL[0].MEM in unit ibd_ibmon of type RAMB16_S36 has been replaced by RAMB16BWER
INFO:Xst:2261 - The FF/Latch <R_REGS_paddr_iopage_0> in Unit <pdp11_vmbox> is equivalent to the following 2 FFs/Latches, which will be removed : <R_REGS_paddr_iopage_1> <R_REGS_paddr_iopage_2> 
INFO:Xst:2261 - The FF/Latch <R_REGS_paddr_iopage_5> in Unit <pdp11_vmbox> is equivalent to the following 3 FFs/Latches, which will be removed : <R_REGS_paddr_iopage_6> <R_REGS_paddr_iopage_7> <R_REGS_paddr_iopage_8> 
INFO:Xst:2261 - The FF/Latch <R_REGS_paddr_iopage_3> in Unit <pdp11_vmbox> is equivalent to the following FF/Latch, which will be removed : <R_REGS_paddr_iopage_4> 
INFO:Xst:2261 - The FF/Latch <R_REGS_dcf_brk_1> in Unit <ibd_iist> is equivalent to the following 2 FFs/Latches, which will be removed : <R_REGS_dcf_brk_2> <R_REGS_dcf_brk_3> 
INFO:Xst:2261 - The FF/Latch <R_REGS_samax_2> in Unit <ibdr_rhrp> is equivalent to the following 2 FFs/Latches, which will be removed : <R_REGS_dtyp_1> <R_REGS_dtyp_3> 
INFO:Xst:2261 - The FF/Latch <R_REGS_tamax_2> in Unit <ibdr_rhrp> is equivalent to the following 2 FFs/Latches, which will be removed : <R_REGS_camax_0> <R_REGS_camax_4> 
INFO:Xst:2261 - The FF/Latch <R_REGS_samax_5> in Unit <ibdr_rhrp> is equivalent to the following 3 FFs/Latches, which will be removed : <R_REGS_tamax_0> <R_REGS_camax_1> <R_REGS_dtyp_5> 
INFO:Xst:2261 - The FF/Latch <R_REGS_camax_5> in Unit <ibdr_rhrp> is equivalent to the following FF/Latch, which will be removed : <R_REGS_camax_8> 
INFO:Xst:2261 - The FF/Latch <R_REGS_camax_6> in Unit <ibdr_rhrp> is equivalent to the following FF/Latch, which will be removed : <R_REGS_camax_9> 
INFO:Xst:2261 - The FF/Latch <R_REGS_samax_4> in Unit <ibdr_rhrp> is equivalent to the following 2 FFs/Latches, which will be removed : <R_REGS_tamax_1> <R_REGS_dtyp_2> 
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_S_pktend_11> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_S_pktend_10> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_S_pktend_8> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_S_pktend_7> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_S_pktend_6> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_S_pktend_5> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_S_pktend_2> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_S_pktend_1> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_S_pktend_0> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_C_pktend_11> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_C_pktend_10> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_C_pktend_8> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_C_pktend_7> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_C_pktend_6> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_C_pktend_5> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_C_pktend_2> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_C_pktend_1> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_MONI_C_pktend_0> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_REGS_moni_ep6_sel> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_REGS_moni_ep6_pf> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_REGS_moni_ep4_pf> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/R_REGS_moni_ep4_sel> of sequential type is unconnected in block <sys_w11a_n3>.

Optimizing unit <iob_reg_o_gen_7> ...

Optimizing unit <iob_reg_i_gen_4> ...

Optimizing unit <iob_reg_o_gen_5> ...

Optimizing unit <ram_1swar_1ar_gen_3> ...

Optimizing unit <ram_1swar_gen_1> ...

Optimizing unit <ram_1swar_gen_6> ...

Optimizing unit <ram_1swar_1ar_gen_2> ...

Optimizing unit <ram_1swar_gen_8> ...

Optimizing unit <sys_w11a_n3> ...

Optimizing unit <sn_humanio_rbus> ...

Optimizing unit <debounce_gen_1> ...

Optimizing unit <debounce_gen_2> ...

Optimizing unit <sn_7segctl> ...

Optimizing unit <byte2cdata> ...

Optimizing unit <rlink_core> ...
INFO:Xst:2261 - The FF/Latch <R_BREGS_rbwe> in Unit <rlink_core> is equivalent to the following FF/Latch, which will be removed : <R_BREGS_state_FSM_FFd4> 
INFO:Xst:2261 - The FF/Latch <R_BREGS_rbre> in Unit <rlink_core> is equivalent to the following FF/Latch, which will be removed : <R_BREGS_state_FSM_FFd10> 
INFO:Xst:2261 - The FF/Latch <R_BREGS_rbre> in Unit <rlink_core> is equivalent to the following FF/Latch, which will be removed : <R_BREGS_state_FSM_FFd10> 
INFO:Xst:2261 - The FF/Latch <R_BREGS_rbwe> in Unit <rlink_core> is equivalent to the following FF/Latch, which will be removed : <R_BREGS_state_FSM_FFd4> 

Optimizing unit <fifo_1c_dram_raw> ...

Optimizing unit <ram_1swar_1ar_gen_1> ...

Optimizing unit <crc16> ...

Optimizing unit <cdata2byte> ...

Optimizing unit <fifo_2c_dram> ...

Optimizing unit <serport_1clock> ...

Optimizing unit <serport_uart_rx> ...

Optimizing unit <serport_uart_tx> ...

Optimizing unit <serport_uart_autobaud> ...

Optimizing unit <serport_xonrx> ...

Optimizing unit <serport_xontx> ...

Optimizing unit <rbd_rbmon> ...

Optimizing unit <bp_rs232_2l4l_iob> ...

Optimizing unit <pdp11_sys70> ...

Optimizing unit <pdp11_core_rbus> ...

Optimizing unit <pdp11_dmscnt> ...

Optimizing unit <pdp11_dmcmon> ...

Optimizing unit <pdp11_dmhbpt_unit_1> ...

Optimizing unit <pdp11_dmhbpt_unit_2> ...

Optimizing unit <pdp11_sequencer> ...

Optimizing unit <pdp11_vmbox> ...

Optimizing unit <pdp11_mmu> ...

Optimizing unit <pdp11_mmu_sadr> ...

Optimizing unit <pdp11_mmu_ssr12> ...

Optimizing unit <pdp11_ubmap> ...

Optimizing unit <pdp11_dpath> ...

Optimizing unit <pdp11_gpr> ...

Optimizing unit <pdp11_psr> ...

Optimizing unit <pdp11_aunit> ...

Optimizing unit <pdp11_lunit> ...

Optimizing unit <pdp11_munit> ...

Optimizing unit <pdp11_irq> ...

Optimizing unit <pdp11_reg70> ...

Optimizing unit <pdp11_decode> ...

Optimizing unit <pdp11_cache> ...

Optimizing unit <pdp11_mem70> ...

Optimizing unit <ibd_ibmon> ...

Optimizing unit <ioleds_sp1c_fx2> ...

Optimizing unit <clkdivce> ...

Optimizing unit <ibdr_maxisys> ...

Optimizing unit <ibd_iist> ...

Optimizing unit <ibd_kw11l> ...

Optimizing unit <ibdr_rhrp> ...

Optimizing unit <ibdr_rl11> ...

Optimizing unit <ibdr_rk11> ...

Optimizing unit <ibdr_tm11> ...

Optimizing unit <ibdr_dl11_1> ...

Optimizing unit <ibdr_dl11_2> ...

Optimizing unit <ibdr_pc11> ...

Optimizing unit <ibdr_lp11> ...

Optimizing unit <ibdr_sdreg> ...
WARNING:Xst:1293 - FF/Latch <SYS70/W11A/SEQ/R_IDSTAT_res_sel_2> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <SYS70/W11A/SEQ/R_STATUS_intvect_8> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <RLINK/FX2CNTL/RXFIFO/R_REGR_rstr> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGW_rstw> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <RLINK/CORE/RL/R_LREGS_attn_3> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <RLINK/CORE/RL/R_LREGS_attn_9> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <RLINK/CORE/RL/R_LREGS_attn_11> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <RLINK/CORE/RL/R_LREGS_attn_12> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <RLINK/CORE/RL/R_LREGS_attn_13> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <RLINK/CORE/RL/R_LREGS_attn_14> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <RLINK/CORE/RL/R_LREGS_attn_15> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGR_rstw_c> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGR_rstr> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/FX2CNTL/RXFIFO/R_REGW_rstw> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGR_rstw_s> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/FX2CNTL/RXFIFO/R_REGR_rstw_c> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/FX2CNTL/RXFIFO/R_REGR_rstw_s> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <HIO/R_REGS_swieff_7> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <HIO/R_REGS_swieff_6> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <HIO/R_REGS_btn_4> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <HIO/R_REGS_btn_3> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <HIO/R_REGS_btn_2> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <HIO/R_REGS_btn_1> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <HIO/R_REGS_btn_0> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <HIO/R_REGS_swi_7> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <HIO/R_REGS_swi_6> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <HIO/R_REGS_btneff_4> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <HIO/R_REGS_btneff_3> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <HIO/R_REGS_btneff_2> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <HIO/R_REGS_btneff_1> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <HIO/R_REGS_btneff_0> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/CORE/RL/R_LREGS_monattn> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/CORE/RL/R_LREGS_moneop> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/TXFIFO/R_REGR_sizer_4> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/TXFIFO/R_REGR_sizer_3> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/TXFIFO/R_REGR_sizer_2> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/TXFIFO/R_REGR_sizer_1> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/TXFIFO/R_REGR_sizer_0> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/TXFIFO/R_REGW_sizew_4> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/TXFIFO/R_REGW_sizew_3> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/TXFIFO/R_REGW_sizew_2> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/TXFIFO/R_REGW_sizew_1> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/TXFIFO/R_REGW_sizew_0> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/RXFIFO/R_REGR_sizer_4> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/RXFIFO/R_REGR_sizer_3> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/RXFIFO/R_REGR_sizer_2> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/RXFIFO/R_REGR_sizer_1> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/RXFIFO/R_REGR_sizer_0> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/RXFIFO/R_REGW_sizew_1> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/FX2CNTL/RXFIFO/R_REGW_sizew_0> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <RLINK/SERPORT/XONRX/R_REGS_rxovr> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <IBDR_SYS/IIST.I0/R_REGS_req_lock> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:2677 - Node <IBDR_SYS/IIST.I0/R_REGS_req_boot> of sequential type is unconnected in block <sys_w11a_n3>.
WARNING:Xst:1293 - FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGW_rstw_sc> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGW_rstr_c> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGW_rstw_ss> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGW_rstr_s> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/FX2CNTL/RXFIFO/R_REGW_rstw_sc> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/FX2CNTL/RXFIFO/R_REGW_rstr_c> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGR_rstr_sc> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/FX2CNTL/RXFIFO/R_REGW_rstw_ss> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/FX2CNTL/RXFIFO/R_REGW_rstr_s> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGR_rstr_ss> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/FX2CNTL/RXFIFO/R_REGR_rstr_sc> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch <RLINK/FX2CNTL/RXFIFO/R_REGR_rstr_ss> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <SRAM_CTL/IOB_MEM_ADDRH/R_DO_21> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <SRAM_CTL/IOB_MEM_ADDRH/R_DO_20> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <CLKDIV/R_REGS_ucnt_6> has a constant value of 0 in block <sys_w11a_n3>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:638 - in unit sys_w11a_n3 Conflict on KEEP property on signal SRAM_CTL/IOB_MEM_ADDRH/R_DO<21> and SRAM_CTL/IOB_MEM_ADDRH/R_DO<20> SRAM_CTL/IOB_MEM_ADDRH/R_DO<20> signal will be lost.
INFO:Xst:2261 - The FF/Latch <SYS70/W11A/SEQ/R_IDSTAT_aunit_cc1op> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SYS70/W11A/SEQ/R_IDSTAT_aunit_srcmod_1> 
INFO:Xst:2261 - The FF/Latch <IBDR_SYS/IIST.I0/R_REGS_dcf_brk_1> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <IBDR_SYS/IIST.I0/R_REGS_dcf_brk_0> 
INFO:Xst:2261 - The FF/Latch <LED_IO/R_LEDDIV_0> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <IBDR_SYS/RHRP.I0/R_REGS_uscnt_0> 
INFO:Xst:2261 - The FF/Latch <HIO/HIO/HIO/DEB.DEB_SWI/R_REGS_cecnt_0> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <HIO/HIO/HIO/DEB.DEB_BTN/R_REGS_cecnt_0> 
INFO:Xst:2261 - The FF/Latch <HIO/HIO/HIO/DEB.DEB_SWI/R_REGS_cecnt_1> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <HIO/HIO/HIO/DEB.DEB_BTN/R_REGS_cecnt_1> 
INFO:Xst:2261 - The FF/Latch <HIO/HIO/DRV/R_REGS_cdiv_0> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMCMON.I0/R_REGS_cnum_0> 
INFO:Xst:2261 - The FF/Latch <SYS70/DMSCNT.I0/R_REGS_snum0_0> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMCMON.I0/R_REGS_se_snum_0> 
INFO:Xst:2261 - The FF/Latch <SYS70/DMSCNT.I0/R_REGS_snum0_1> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMCMON.I0/R_REGS_se_snum_1> 
INFO:Xst:2261 - The FF/Latch <SYS70/DMSCNT.I0/R_REGS_snum0_2> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMCMON.I0/R_REGS_se_snum_2> 
INFO:Xst:2261 - The FF/Latch <SYS70/DMSCNT.I0/R_REGS_snum0_3> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMCMON.I0/R_REGS_se_snum_3> 
INFO:Xst:2261 - The FF/Latch <SYS70/DMSCNT.I0/R_REGS_snum0_4> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMCMON.I0/R_REGS_se_snum_4> 
INFO:Xst:2261 - The FF/Latch <SYS70/DMSCNT.I0/R_REGS_snum0_5> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMCMON.I0/R_REGS_se_snum_5> 
INFO:Xst:2261 - The FF/Latch <SYS70/DMSCNT.I0/R_REGS_snum0_6> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMCMON.I0/R_REGS_se_snum_6> 
INFO:Xst:2261 - The FF/Latch <SYS70/DMSCNT.I0/R_REGS_snum0_7> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SYS70/DMCMON.I0/R_REGS_se_snum_7> 
INFO:Xst:2261 - The FF/Latch <SYS70/W11A/SEQ/R_IDSTAT_fork_dsta_0> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SYS70/W11A/SEQ/R_IDSTAT_fork_dstr_0> 
INFO:Xst:2261 - The FF/Latch <SYS70/W11A/SEQ/R_IDSTAT_fork_dsta_1> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SYS70/W11A/SEQ/R_IDSTAT_fork_dstr_1> 
INFO:Xst:2261 - The FF/Latch <SRAM_CTL/R_REGS_memdi_20> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SRAM_CTL/R_REGS_memdi_4> 
INFO:Xst:2261 - The FF/Latch <SRAM_CTL/R_REGS_memdi_21> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SRAM_CTL/R_REGS_memdi_5> 
INFO:Xst:2261 - The FF/Latch <SRAM_CTL/R_REGS_memdi_16> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SRAM_CTL/R_REGS_memdi_0> 
INFO:Xst:2261 - The FF/Latch <SRAM_CTL/R_REGS_memdi_22> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SRAM_CTL/R_REGS_memdi_6> 
INFO:Xst:2261 - The FF/Latch <SRAM_CTL/R_REGS_memdi_17> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SRAM_CTL/R_REGS_memdi_1> 
INFO:Xst:2261 - The FF/Latch <SRAM_CTL/R_REGS_memdi_23> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SRAM_CTL/R_REGS_memdi_7> 
INFO:Xst:2261 - The FF/Latch <SRAM_CTL/R_REGS_memdi_18> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SRAM_CTL/R_REGS_memdi_2> 
INFO:Xst:2261 - The FF/Latch <SRAM_CTL/R_REGS_memdi_24> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SRAM_CTL/R_REGS_memdi_8> 
INFO:Xst:2261 - The FF/Latch <SRAM_CTL/R_REGS_memdi_19> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SRAM_CTL/R_REGS_memdi_3> 
INFO:Xst:2261 - The FF/Latch <SRAM_CTL/R_REGS_memdi_30> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SRAM_CTL/R_REGS_memdi_14> 
INFO:Xst:2261 - The FF/Latch <SRAM_CTL/R_REGS_memdi_25> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SRAM_CTL/R_REGS_memdi_9> 
INFO:Xst:2261 - The FF/Latch <SRAM_CTL/R_REGS_memdi_31> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SRAM_CTL/R_REGS_memdi_15> 
INFO:Xst:2261 - The FF/Latch <SRAM_CTL/R_REGS_memdi_26> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SRAM_CTL/R_REGS_memdi_10> 
INFO:Xst:2261 - The FF/Latch <SRAM_CTL/R_REGS_memdi_27> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SRAM_CTL/R_REGS_memdi_11> 
INFO:Xst:2261 - The FF/Latch <SRAM_CTL/R_REGS_memdi_28> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SRAM_CTL/R_REGS_memdi_12> 
INFO:Xst:2261 - The FF/Latch <SRAM_CTL/R_REGS_memdi_29> in Unit <sys_w11a_n3> is equivalent to the following FF/Latch, which will be removed : <SRAM_CTL/R_REGS_memdi_13> 
INFO:Xst:3203 - The FF/Latch <SYS70/DMCMON.I0/R_REGS_cnum_4> in Unit <sys_w11a_n3> is the opposite to the following FF/Latch, which will be removed : <CLKDIV/R_REGS_ucnt_4> 
INFO:Xst:3203 - The FF/Latch <SYS70/DMCMON.I0/R_REGS_cnum_5> in Unit <sys_w11a_n3> is the opposite to the following FF/Latch, which will be removed : <CLKDIV/R_REGS_ucnt_5> 
INFO:Xst:3203 - The FF/Latch <SYS70/DMCMON.I0/R_REGS_cnum_6> in Unit <sys_w11a_n3> is the opposite to the following FF/Latch, which will be removed : <CLKDIV/R_REGS_mcnt_0> 
INFO:Xst:3203 - The FF/Latch <SYS70/DMCMON.I0/R_REGS_cnum_7> in Unit <sys_w11a_n3> is the opposite to the following FF/Latch, which will be removed : <CLKDIV/R_REGS_mcnt_1> 
INFO:Xst:3203 - The FF/Latch <HIO/HIO/DRV/R_REGS_cdiv_0> in Unit <sys_w11a_n3> is the opposite to the following FF/Latch, which will be removed : <CLKDIV/R_REGS_ucnt_0> 
INFO:Xst:3203 - The FF/Latch <RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0> in Unit <sys_w11a_n3> is the opposite to the following FF/Latch, which will be removed : <RLINK/FX2CNTL/R_REGS_rxpipe1> 
INFO:Xst:3203 - The FF/Latch <SYS70/DMCMON.I0/R_REGS_cnum_1> in Unit <sys_w11a_n3> is the opposite to the following FF/Latch, which will be removed : <CLKDIV/R_REGS_ucnt_1> 
INFO:Xst:3203 - The FF/Latch <SYS70/DMCMON.I0/R_REGS_cnum_2> in Unit <sys_w11a_n3> is the opposite to the following FF/Latch, which will be removed : <CLKDIV/R_REGS_ucnt_2> 
INFO:Xst:3203 - The FF/Latch <SYS70/DMCMON.I0/R_REGS_cnum_3> in Unit <sys_w11a_n3> is the opposite to the following FF/Latch, which will be removed : <CLKDIV/R_REGS_ucnt_3> 

Mapping all equations...
WARNING:Xst:2677 - Node <SRAM_CTL/R_REGS_addr0> of sequential type is unconnected in block <sys_w11a_n3>.
Annotating constraints using XCF file 'sys_w11a_n3.xcf'
XCF parsing done.
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block sys_w11a_n3, actual ratio is 81.
Replicating register SRAM_CTL/IOB_MEM_DATA/R_TE to handle IOB=TRUE attribute
Replicating register RLINK/FX2CNTL/IOB_FX2_DATA/R_TE to handle IOB=TRUE attribute
Replicating register RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0 to handle IOB=TRUE attribute

FlipFlop SYS70/W11A/DPATH/R_IREG_11 has been replicated 1 time(s)
FlipFlop SYS70/W11A/DPATH/R_IREG_15 has been replicated 1 time(s)
FlipFlop SYS70/W11A/DPATH/R_IREG_6 has been replicated 1 time(s)
FlipFlop SYS70/W11A/DPATH/R_IREG_8 has been replicated 1 time(s)
FlipFlop SYS70/W11A/SEQ/R_STATE_0 has been replicated 3 time(s)
FlipFlop SYS70/W11A/SEQ/R_STATE_1 has been replicated 3 time(s)
FlipFlop SYS70/W11A/SEQ/R_STATE_2 has been replicated 4 time(s)
FlipFlop SYS70/W11A/SEQ/R_STATE_3 has been replicated 3 time(s)
FlipFlop SYS70/W11A/SEQ/R_STATE_4 has been replicated 3 time(s)
FlipFlop SYS70/W11A/SEQ/R_STATE_5 has been replicated 3 time(s)
FlipFlop SYS70/W11A/SEQ/R_STATE_6 has been replicated 3 time(s)
FlipFlop SYS70/W11A/VMBOX/R_REGS_state_FSM_FFd1 has been replicated 1 time(s)
FlipFlop SYS70/W11A/VMBOX/R_REGS_state_FSM_FFd2 has been replicated 1 time(s)
FlipFlop SYS70/W11A/VMBOX/R_REGS_state_FSM_FFd3 has been replicated 1 time(s)
FlipFlop SYS70/W11A/VMBOX/R_REGS_state_FSM_FFd4 has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 2713
 Flip-Flops                                            : 2713

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : sys_w11a_n3.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 6961
#      GND                         : 1
#      INV                         : 59
#      LUT1                        : 106
#      LUT2                        : 331
#      LUT3                        : 817
#      LUT4                        : 950
#      LUT5                        : 1201
#      LUT6                        : 2478
#      MUXCY                       : 473
#      MUXF7                       : 112
#      VCC                         : 1
#      XORCY                       : 432
# FlipFlops/Latches                : 2713
#      FD                          : 450
#      FDE                         : 1132
#      FDR                         : 214
#      FDRE                        : 878
#      FDS                         : 21
#      FDSE                        : 18
# RAMS                             : 225
#      RAM16X1D                    : 112
#      RAM16X1S                    : 32
#      RAM32X1S                    : 37
#      RAM64X1S                    : 29
#      RAMB16BWER                  : 15
# Clock Buffers                    : 2
#      BUFG                        : 1
#      BUFGP                       : 1
# IO Buffers                       : 107
#      IBUF                        : 20
#      IBUFG                       : 1
#      IOBUF                       : 24
#      OBUF                        : 62
# DCMs                             : 1
#      DCM_SP                      : 1
# DSPs                             : 1
#      DSP48A1                     : 1

Device utilization summary:
---------------------------

Selected Device : 6slx16csg324-2 


Slice Logic Utilization: 
 Number of Slice Registers:            2566  out of  18224    14%  
 Number of Slice LUTs:                 6264  out of   9112    68%  
    Number used as Logic:              5942  out of   9112    65%  
    Number used as Memory:              322  out of   2176    14%  
       Number used as RAM:              322

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:   6953
   Number with an unused Flip Flop:    4387  out of   6953    63%  
   Number with an unused LUT:           689  out of   6953     9%  
   Number of fully used LUT-FF pairs:  1877  out of   6953    26%  
   Number of unique control sets:       346

IO Utilization: 
 Number of IOs:                         109
 Number of bonded IOBs:                 108  out of    232    46%  
    IOB Flip Flops/Latches:             147

Specific Feature Utilization:
 Number of Block RAM/FIFO:               15  out of     32    46%  
    Number using Block RAM only:         15
 Number of BUFG/BUFGCTRLs:                2  out of     16    12%  
 Number of DSP48A1s:                      1  out of     32     3%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
I_FX2_IFCLK                        | BUFGP                  | 107   |
I_CLK100                           | DCM_SP:CLKFX           | 2832  |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -2

   Minimum period: 9.091ns (Maximum Frequency: 109.997MHz)
   Minimum input arrival time before clock: 2.083ns
   Maximum output required time after clock: 4.118ns
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'I_FX2_IFCLK'
  Clock period: 6.999ns (frequency: 142.882MHz)
  Total number of paths / destination ports: 1406 / 193
-------------------------------------------------------------------------
Delay:               6.999ns (Levels of Logic = 5)
  Source:            RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_2 (FF)
  Destination:       RLINK/FX2CNTL/RXFIFO/R_REGW_busy (FF)
  Source Clock:      I_FX2_IFCLK rising
  Destination Clock: I_FX2_IFCLK rising

  Data Path: RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_2 to RLINK/FX2CNTL/RXFIFO/R_REGW_busy
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            55   0.525   1.968  RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_2 (RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_2)
     LUT3:I1->O            4   0.250   0.804  RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/Mram_N_DATA131 (RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/Mram_N_DATA13)
     LUT5:I4->O            3   0.254   0.874  RLINK/FX2CNTL/RXFIFO/Madd_RADDR_S_BIN[4]_WADDR_BIN[4]_add_4_OUT_lut<0>1 (RLINK/FX2CNTL/RXFIFO/Madd_RADDR_S_BIN[4]_WADDR_BIN[4]_add_4_OUT_lut<0>)
     LUT6:I4->O            3   0.250   0.766  RLINK/FX2CNTL/RXFIFO/Madd_RADDR_S_BIN[4]_WADDR_BIN[4]_add_4_OUT_cy<2>11 (RLINK/FX2CNTL/RXFIFO/Madd_RADDR_S_BIN[4]_WADDR_BIN[4]_add_4_OUT_cy<2>)
     LUT5:I4->O            2   0.254   0.726  RLINK/FX2CNTL/RXFIFO/Madd_RADDR_S_BIN[4]_WADDR_BIN[4]_add_4_OUT_xor<4>11 (RLINK/FX2CNTL/RXFIFO/RADDR_S_BIN[4]_WADDR_BIN[4]_add_4_OUT<4>)
     LUT6:I5->O            1   0.254   0.000  RLINK/FX2CNTL/RXFIFO/Mmux_RADDR_S_BIN[4]_RADDR_S_BIN[4]_MUX_544_o1 (RLINK/FX2CNTL/RXFIFO/RADDR_S_BIN[4]_RADDR_S_BIN[4]_MUX_544_o)
     FD:D                      0.074          RLINK/FX2CNTL/RXFIFO/R_REGW_busy
    ----------------------------------------
    Total                      6.999ns (1.861ns logic, 5.138ns route)
                                       (26.6% logic, 73.4% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'I_CLK100'
  Clock period: 9.091ns (frequency: 109.997MHz)
  Total number of paths / destination ports: 7255428 / 8040
-------------------------------------------------------------------------
Delay:               14.205ns (Levels of Logic = 10)
  Source:            IBDR_SYS/IIST.I0/R_REGS_pgf_pif_0 (FF)
  Destination:       SYS70/W11A/SEQ_Mram__n3279 (RAM)
  Source Clock:      I_CLK100 rising 0.6X
  Destination Clock: I_CLK100 rising 0.6X

  Data Path: IBDR_SYS/IIST.I0/R_REGS_pgf_pif_0 to SYS70/W11A/SEQ_Mram__n3279
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              3   0.525   1.196  IBDR_SYS/IIST.I0/R_REGS_pgf_pif_0 (IBDR_SYS/IIST.I0/R_REGS_pgf_pif_0)
     LUT5:I0->O            3   0.254   0.994  IBDR_SYS/IIST.I0/proc_next.int_or<0>1 (IBDR_SYS/IIST.I0/proc_next.int_or<0>)
     LUT6:I3->O           19   0.235   1.261  IBDR_SYS/IIST.I0/EI_REQ1 (IBDR_SYS/EI_REQ_IIST)
     LUT6:I5->O            3   0.254   0.766  IBDR_SYS/EI_PRI<0>1 (EI_PRI<0>)
     LUT6:I5->O            4   0.254   0.912  SYS70/W11A/IRQ/PI_PRI[2]_EI_PRI[2]_LessThan_13_o5_SW0 (N714)
     LUT5:I3->O           19   0.250   1.261  SYS70/W11A/IRQ/PI_PRI[2]_EI_PRI[2]_LessThan_13_o5 (SYS70/W11A/IRQ/PI_PRI[2]_EI_PRI[2]_LessThan_13_o)
     LUT5:I4->O           15   0.254   1.155  SYS70/W11A/SEQ/proc_next.int_pending3 (SYS70/W11A/SEQ/proc_next.int_pending)
     LUT6:I5->O            5   0.254   0.841  SYS70/W11A/SEQ/GND_139_o_GND_139_o_mux_259_OUT<3>1 (SYS70/W11A/SEQ/GND_139_o_GND_139_o_mux_259_OUT<3>)
     LUT6:I5->O            7   0.254   0.910  SYS70/W11A/SEQ/proc_next.nstate<4>111_SW0 (N816)
     LUT6:I5->O            1   0.254   0.790  SYS70/W11A/SEQ/proc_next.nstate<1>63_SW0_SW1 (N972)
     LUT6:I4->O            1   0.250   0.681  SYS70/W11A/SEQ/proc_next.nstate<1>11 (SYS70/W11A/SEQ/proc_next.nstate<1>_0)
     RAMB16BWER:ADDRA6         0.400          SYS70/W11A/SEQ_Mram__n3279
    ----------------------------------------
    Total                     14.205ns (3.438ns logic, 10.767ns route)
                                       (24.2% logic, 75.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'I_FX2_IFCLK'
  Total number of paths / destination ports: 12 / 12
-------------------------------------------------------------------------
Offset:              2.083ns (Levels of Logic = 1)
  Source:            I_FX2_FLAG<0> (PAD)
  Destination:       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0 (FF)
  Destination Clock: I_FX2_IFCLK rising

  Data Path: I_FX2_FLAG<0> to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.328   0.681  I_FX2_FLAG_0_IBUF (I_FX2_FLAG_0_IBUF)
     FD:D                      0.074          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0
    ----------------------------------------
    Total                      2.083ns (1.402ns logic, 0.681ns route)
                                       (67.3% logic, 32.7% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'I_CLK100'
  Total number of paths / destination ports: 32 / 32
-------------------------------------------------------------------------
Offset:              2.083ns (Levels of Logic = 1)
  Source:            IO_MEM_DATA<15> (PAD)
  Destination:       SRAM_CTL/IOB_MEM_DATA/R_DI_15 (FF)
  Destination Clock: I_CLK100 rising 0.6X

  Data Path: IO_MEM_DATA<15> to SRAM_CTL/IOB_MEM_DATA/R_DI_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IOBUF:IO->O           1   1.328   0.681  IO_MEM_DATA_15_IOBUF (N666)
     FDE:D                     0.074          SRAM_CTL/IOB_MEM_DATA/R_DI_15
    ----------------------------------------
    Total                      2.083ns (1.402ns logic, 0.681ns route)
                                       (67.3% logic, 32.7% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'I_CLK100'
  Total number of paths / destination ports: 81 / 65
-------------------------------------------------------------------------
Offset:              4.118ns (Levels of Logic = 1)
  Source:            HIO/HIO/HIO/IOB_LED/R_DO_7 (FF)
  Destination:       O_LED<7> (PAD)
  Source Clock:      I_CLK100 rising 0.6X

  Data Path: HIO/HIO/HIO/IOB_LED/R_DO_7 to O_LED<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   0.525   0.681  HIO/HIO/HIO/IOB_LED/R_DO_7 (HIO/HIO/HIO/IOB_LED/R_DO<7>)
     OBUF:I->O                 2.912          O_LED_7_OBUF (O_LED<7>)
    ----------------------------------------
    Total                      4.118ns (3.437ns logic, 0.681ns route)
                                       (83.5% logic, 16.5% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'I_FX2_IFCLK'
  Total number of paths / destination ports: 22 / 14
-------------------------------------------------------------------------
Offset:              4.118ns (Levels of Logic = 1)
  Source:            RLINK/FX2CNTL/IOB_FX2_FIFO/R_DO_1 (FF)
  Destination:       O_FX2_FIFO<1> (PAD)
  Source Clock:      I_FX2_IFCLK rising

  Data Path: RLINK/FX2CNTL/IOB_FX2_FIFO/R_DO_1 to O_FX2_FIFO<1>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   0.525   0.681  RLINK/FX2CNTL/IOB_FX2_FIFO/R_DO_1 (RLINK/FX2CNTL/IOB_FX2_FIFO/R_DO<1>)
     OBUF:I->O                 2.912          O_FX2_FIFO_1_OBUF (O_FX2_FIFO<1>)
    ----------------------------------------
    Total                      4.118ns (3.437ns logic, 0.681ns route)
                                       (83.5% logic, 16.5% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock I_CLK100
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
I_CLK100       |   14.205|         |    2.487|         |
I_FX2_IFCLK    |    7.332|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock I_FX2_IFCLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
I_CLK100       |    2.481|         |         |         |
I_FX2_IFCLK    |    6.999|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 101.00 secs
Total CPU time to Xst completion: 99.15 secs
 
--> 


Total memory usage is 518232 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :  550 (   0 filtered)
Number of infos    :  123 (   0 filtered)

