--------------------------------------------------------------------------------
Release 14.7 Trace  (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

/mnt/data/opt/Xilinx/ISE/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 3
-fastpaths -u 100 -intstyle xflow -xml sys_w11a_n3.twx -tsi sys_w11a_n3.tsi
sys_w11a_n3.ncd sys_w11a_n3.pcf

Design file:              sys_w11a_n3.ncd
Physical constraint file: sys_w11a_n3.pcf
Device,package,speed:     xc6slx16,csg324,C,-2 (PRODUCTION 1.23 2013-10-13)
Report level:             verbose report
                          unconstrained path report, limited to 100 items

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

WARNING:Timing:3391 - Timing constraint OFFSET = IN 10 ns BEFORE COMP 
   "I_CLK100"; does not specify a data valid duration and will not be hold 
   checked. To enable hold checking on this offset constraint please specify a 
   data valid duration using the VALID <duration> option.
INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more 
   information, see the TSI report.  Please consult the Xilinx Command Line 
   Tools User Guide for information on generating a TSI report.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_I_CLK100 = PERIOD TIMEGRP "I_CLK100" 10 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   5.340ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_I_CLK100 = PERIOD TIMEGRP "I_CLK100" 10 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 4.660ns (period - (min low pulse limit / (low pulse / period)))
  Period: 10.000ns
  Low pulse: 5.000ns
  Low pulse limit: 2.670ns (Tdcmpw_CLKIN_100_150)
  Physical resource: GEN_CLKSYS/USEDCM.DCM/CLKIN
  Logical resource: GEN_CLKSYS/USEDCM.DCM/CLKIN
  Location pin: DCM_X0Y1.CLKIN
  Clock network: GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
--------------------------------------------------------------------------------
Slack: 4.660ns (period - (min high pulse limit / (high pulse / period)))
  Period: 10.000ns
  High pulse: 5.000ns
  High pulse limit: 2.670ns (Tdcmpw_CLKIN_100_150)
  Physical resource: GEN_CLKSYS/USEDCM.DCM/CLKIN
  Logical resource: GEN_CLKSYS/USEDCM.DCM/CLKIN
  Location pin: DCM_X0Y1.CLKIN
  Clock network: GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
--------------------------------------------------------------------------------
Slack: 7.000ns (period - min period limit)
  Period: 10.000ns
  Min period limit: 3.000ns (333.333MHz) (Tdcmper_CLKIN)
  Physical resource: GEN_CLKSYS/USEDCM.DCM/CLKIN
  Logical resource: GEN_CLKSYS/USEDCM.DCM/CLKIN
  Location pin: DCM_X0Y1.CLKIN
  Clock network: GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_PAD_CLK = MAXDELAY FROM TIMEGRP "PADS(I_CLK100)" TO 
TIMEGRP "TNM_CLK" 10         ns;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 2912 paths analyzed, 2912 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   6.912ns.
--------------------------------------------------------------------------------
Slack (slowest paths):  3.088ns (requirement - data path)
  Source:               I_CLK100 (PAD)
  Destination:          IOB_RS232/P0/IOB_RXD/IOB/R_DI_0 (FF)
  Requirement:          10.000ns
  Data Path Delay:      6.912ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to IOB_RS232/P0/IOB_RXD/IOB/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X18Y19.CLK0   net (fanout=1212)     1.778   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.912ns (2.356ns logic, 4.556ns route)
                                                       (34.1% logic, 65.9% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  3.090ns (requirement - data path)
  Source:               I_CLK100 (PAD)
  Destination:          SRAM_CTL/IOB_MEM_DATA/R_DI_0 (FF)
  Requirement:          10.000ns
  Data Path Delay:      6.910ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SRAM_CTL/IOB_MEM_DATA/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X16Y1.CLK0    net (fanout=1212)     1.776   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.910ns (2.356ns logic, 4.554ns route)
                                                       (34.1% logic, 65.9% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  3.092ns (requirement - data path)
  Source:               I_CLK100 (PAD)
  Destination:          HIO/HIO/HIO/IOB_BTN/R_DI_3 (FF)
  Requirement:          10.000ns
  Data Path Delay:      6.908ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to HIO/HIO/HIO/IOB_BTN/R_DI_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X1Y62.CLK0    net (fanout=1212)     1.774   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.908ns (2.356ns logic, 4.552ns route)
                                                       (34.1% logic, 65.9% route)

--------------------------------------------------------------------------------
Hold Paths: TS_PAD_CLK = MAXDELAY FROM TIMEGRP "PADS(I_CLK100)" TO TIMEGRP "TNM_CLK" 10         ns;
--------------------------------------------------------------------------------
Delay (fastest path):   2.528ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/DMCMON.I0/R_REGS_vm_err_rsv (FF)
  Data Path Delay:      2.528ns (Levels of Logic = 4)

  Minimum Data Path at Fast Process Corner: I_CLK100 to SYS70/DMCMON.I0/R_REGS_vm_err_rsv
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    SLICE_X18Y24.CLK     net (fanout=1212)     0.396   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.528ns (1.274ns logic, 1.254ns route)
                                                       (50.4% logic, 49.6% route)
--------------------------------------------------------------------------------
Delay (fastest path):   2.528ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/W11A/SEQ/R_IDSTAT_lunit_func_3 (FF)
  Data Path Delay:      2.528ns (Levels of Logic = 4)

  Minimum Data Path at Fast Process Corner: I_CLK100 to SYS70/W11A/SEQ/R_IDSTAT_lunit_func_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    SLICE_X18Y7.CLK      net (fanout=1212)     0.396   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.528ns (1.274ns logic, 1.254ns route)
                                                       (50.4% logic, 49.6% route)
--------------------------------------------------------------------------------
Delay (fastest path):   2.528ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/W11A/VMBOX/R_REGS_ibre (FF)
  Data Path Delay:      2.528ns (Levels of Logic = 4)

  Minimum Data Path at Fast Process Corner: I_CLK100 to SYS70/W11A/VMBOX/R_REGS_ibre
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    SLICE_X18Y39.CLK     net (fanout=1212)     0.396   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.528ns (1.274ns logic, 1.254ns route)
                                                       (50.4% logic, 49.6% route)
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_PAD_IFCLK = MAXDELAY FROM TIMEGRP "PADS(I_FX2_IFCLK)" TO 
TIMEGRP         "TNM_IFCLK" 10 ns;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 122 paths analyzed, 122 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   4.482ns.
--------------------------------------------------------------------------------
Slack (slowest paths):  5.518ns (requirement - data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.482ns (Levels of Logic = 2)

  Maximum Data Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y56.CLK0    net (fanout=51)       1.710   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.482ns (1.766ns logic, 2.716ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  5.518ns (requirement - data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.482ns (Levels of Logic = 2)

  Maximum Data Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y31.CLK0    net (fanout=51)       1.710   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.482ns (1.766ns logic, 2.716ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  5.519ns (requirement - data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.481ns (Levels of Logic = 2)

  Maximum Data Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y28.CLK0    net (fanout=51)       1.709   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.481ns (1.766ns logic, 2.715ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------
Hold Paths: TS_PAD_IFCLK = MAXDELAY FROM TIMEGRP "PADS(I_FX2_IFCLK)" TO TIMEGRP         "TNM_IFCLK" 10 ns;
--------------------------------------------------------------------------------
Delay (fastest path):   1.493ns (data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c_4 (FF)
  Data Path Delay:      1.493ns (Levels of Logic = 2)

  Minimum Data Path at Fast Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 0.763   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.272   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.059   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    SLICE_X16Y57.CLK     net (fanout=51)       0.399   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      1.493ns (0.822ns logic, 0.671ns route)
                                                       (55.1% logic, 44.9% route)
--------------------------------------------------------------------------------
Delay (fastest path):   1.498ns (data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_s_4 (FF)
  Data Path Delay:      1.498ns (Levels of Logic = 2)

  Minimum Data Path at Fast Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_s_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 0.763   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.272   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.059   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    SLICE_X15Y57.CLK     net (fanout=51)       0.404   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      1.498ns (0.822ns logic, 0.676ns route)
                                                       (54.9% logic, 45.1% route)
--------------------------------------------------------------------------------
Delay (fastest path):   1.501ns (data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c_0 (FF)
  Data Path Delay:      1.501ns (Levels of Logic = 2)

  Minimum Data Path at Fast Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 0.763   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.272   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.059   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    SLICE_X13Y55.CLK     net (fanout=51)       0.407   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      1.501ns (0.822ns logic, 0.679ns route)
                                                       (54.8% logic, 45.2% route)
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_CDC_FIFO = MAXDELAY FROM TIMEGRP 
"FFS(\"*FIFO/GC?/GRAY_*.CNT/R_DATA*\")" TO         TIMEGRP 
"FFS(\"*FIFO/R_REG?_?addr_c*\")" 5 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 20 paths analyzed, 20 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   2.613ns.
--------------------------------------------------------------------------------
Slack (setup paths):    2.387ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_2 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c_2 (FF)
  Requirement:          5.000ns
  Data Path Delay:      2.613ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_2 to RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X0Y57.AQ       Tcko                  0.476   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_2
    SLICE_X15Y61.CX      net (fanout=12)       2.023   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<2>
    SLICE_X15Y61.CLK     Tdick                 0.114   RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c<3>
                                                       RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c_2
    -------------------------------------------------  ---------------------------
    Total                                      2.613ns (0.590ns logic, 2.023ns route)
                                                       (22.6% logic, 77.4% route)

--------------------------------------------------------------------------------
Slack (setup paths):    2.467ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_1 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c_1 (FF)
  Requirement:          5.000ns
  Data Path Delay:      2.533ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_1 to RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X0Y57.AMUX     Tshcko                0.535   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_1
    SLICE_X15Y61.BX      net (fanout=14)       1.884   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<1>
    SLICE_X15Y61.CLK     Tdick                 0.114   RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c<3>
                                                       RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c_1
    -------------------------------------------------  ---------------------------
    Total                                      2.533ns (0.649ns logic, 1.884ns route)
                                                       (25.6% logic, 74.4% route)

--------------------------------------------------------------------------------
Slack (setup paths):    2.655ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_3 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c_3 (FF)
  Requirement:          5.000ns
  Data Path Delay:      2.345ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_3 to RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X0Y57.BMUX     Tshcko                0.535   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_3
    SLICE_X15Y61.DX      net (fanout=14)       1.696   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<3>
    SLICE_X15Y61.CLK     Tdick                 0.114   RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c<3>
                                                       RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c_3
    -------------------------------------------------  ---------------------------
    Total                                      2.345ns (0.649ns logic, 1.696ns route)
                                                       (27.7% logic, 72.3% route)

--------------------------------------------------------------------------------
Hold Paths: TS_CDC_FIFO = MAXDELAY FROM TIMEGRP "FFS(\"*FIFO/GC?/GRAY_*.CNT/R_DATA*\")" TO         TIMEGRP "FFS(\"*FIFO/R_REG?_?addr_c*\")" 5 ns DATAPATHONLY;
--------------------------------------------------------------------------------
Slack (hold path):      0.491ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_4 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.491ns (Levels of Logic = 0)
  Positive Clock Path Skew: 0.000ns
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_4 to RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X0Y57.BQ       Tcko                  0.200   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_4
    SLICE_X0Y59.AX       net (fanout=7)        0.243   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<4>
    SLICE_X0Y59.CLK      Tckdi       (-Th)    -0.048   RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c<4>
                                                       RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c_4
    -------------------------------------------------  ---------------------------
    Total                                      0.491ns (0.248ns logic, 0.243ns route)
                                                       (50.5% logic, 49.5% route)
--------------------------------------------------------------------------------
Slack (hold path):      0.618ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_2 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGW_raddr_c_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.618ns (Levels of Logic = 0)
  Positive Clock Path Skew: 0.000ns
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_2 to RLINK/FX2CNTL/RXFIFO/R_REGW_raddr_c_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X1Y61.AQ       Tcko                  0.198   RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_2
    SLICE_X1Y58.CX       net (fanout=14)       0.361   RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA<2>
    SLICE_X1Y58.CLK      Tckdi       (-Th)    -0.059   RLINK/FX2CNTL/RXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/RXFIFO/R_REGW_raddr_c_2
    -------------------------------------------------  ---------------------------
    Total                                      0.618ns (0.257ns logic, 0.361ns route)
                                                       (41.6% logic, 58.4% route)
--------------------------------------------------------------------------------
Slack (hold path):      0.658ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_4 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGW_raddr_c_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.658ns (Levels of Logic = 1)
  Positive Clock Path Skew: 0.000ns
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_4 to RLINK/FX2CNTL/RXFIFO/R_REGW_raddr_c_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X1Y61.BQ       Tcko                  0.198   RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_4
    SLICE_X1Y58.D5       net (fanout=11)       0.305   RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
    SLICE_X1Y58.CLK      Tah         (-Th)    -0.155   RLINK/FX2CNTL/RXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA<4>_rt
                                                       RLINK/FX2CNTL/RXFIFO/R_REGW_raddr_c_4
    -------------------------------------------------  ---------------------------
    Total                                      0.658ns (0.353ns logic, 0.305ns route)
                                                       (53.6% logic, 46.4% route)
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_I_FX2_IFCLK = PERIOD TIMEGRP "I_FX2_IFCLK" 33.34 ns HIGH 
50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 1534 paths analyzed, 433 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   9.034ns.
--------------------------------------------------------------------------------
Slack (setup path):     24.306ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1 (FF)
  Destination:          RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO_0 (FF)
  Requirement:          33.340ns
  Data Path Delay:      8.884ns (Levels of Logic = 2)
  Clock Path Skew:      -0.115ns (1.044 - 1.159)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1 to RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    ILOGIC_X0Y31.Q4      Tickq                 1.778   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<1>
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1
    SLICE_X0Y50.A2       net (fanout=7)        2.183   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<1>
    SLICE_X0Y50.A        Tilo                  0.235   RLINK/FX2CNTL/R_REGS_state_FSM_FFd4-In3
                                                       RLINK/FX2CNTL/R_REGS_state_FSM_FFd4-In31
    SLICE_X1Y54.A3       net (fanout=6)        1.298   RLINK/FX2CNTL/R_REGS_state_FSM_FFd4-In3
    SLICE_X1Y54.AMUX     Tilo                  0.337   RLINK/FX2CNTL/proc_next.idata_ceo
                                                       RLINK/FX2CNTL/FX2_SLWR_N1
    OLOGIC_X0Y60.D1      net (fanout=9)        1.875   RLINK/FX2CNTL/FX2_SLWR_N
    OLOGIC_X0Y60.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO
                                                       RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO_0
    -------------------------------------------------  ---------------------------
    Total                                      8.884ns (3.528ns logic, 5.356ns route)
                                                       (39.7% logic, 60.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     24.862ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGR_val (FF)
  Requirement:          33.340ns
  Data Path Delay:      7.804ns (Levels of Logic = 4)
  Clock Path Skew:      -0.639ns (0.301 - 0.940)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2 to RLINK/FX2CNTL/TXFIFO/R_REGR_val
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    ILOGIC_X0Y56.Q4      Tickq                 1.778   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<2>
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2
    SLICE_X0Y51.A2       net (fanout=11)       1.663   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<2>
    SLICE_X0Y51.A        Tilo                  0.235   RLINK/FX2CNTL/R_REGS_ccnt<4>
                                                       RLINK/FX2CNTL/R_REGS_state_FSM_FFd2-In11
    SLICE_X7Y52.B4       net (fanout=6)        1.471   RLINK/FX2CNTL/R_REGS_state_FSM_FFd2-In1
    SLICE_X7Y52.B        Tilo                  0.259   RLINK/SERPORT/XONTX/R_REGS_enaxon_1
                                                       RLINK/FX2CNTL/TXFIFO/proc_nextr.igcr_ce1
    SLICE_X11Y55.C3      net (fanout=3)        1.061   RLINK/FX2CNTL/TXFIFO/proc_nextr.igcr_ce
    SLICE_X11Y55.C       Tilo                  0.259   RLINK/FX2CNTL/TXFIFO/R_REGR_val
                                                       RLINK/FX2CNTL/TXFIFO/Mmux_GND_87_o_GND_87_o_MUX_550_o1_SW0
    SLICE_X11Y55.B1      net (fanout=1)        0.705   N114
    SLICE_X11Y55.CLK     Tas                   0.373   RLINK/FX2CNTL/TXFIFO/R_REGR_val
                                                       RLINK/FX2CNTL/TXFIFO/Mmux_GND_87_o_GND_87_o_MUX_550_o1
                                                       RLINK/FX2CNTL/TXFIFO/R_REGR_val
    -------------------------------------------------  ---------------------------
    Total                                      7.804ns (2.904ns logic, 4.900ns route)
                                                       (37.2% logic, 62.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     25.131ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1 (FF)
  Destination:          RLINK/FX2CNTL/R_REGS_ccnt_1 (FF)
  Requirement:          33.340ns
  Data Path Delay:      7.569ns (Levels of Logic = 3)
  Clock Path Skew:      -0.605ns (0.554 - 1.159)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1 to RLINK/FX2CNTL/R_REGS_ccnt_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    ILOGIC_X0Y31.Q4      Tickq                 1.778   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<1>
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1
    SLICE_X3Y55.A1       net (fanout=7)        2.629   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<1>
    SLICE_X3Y55.A        Tilo                  0.259   RLINK/FX2CNTL/RXFIFO/R_REGW_sizew<2>
                                                       RLINK/FX2CNTL/FX2_SLRD_N
    SLICE_X3Y55.B3       net (fanout=2)        1.038   RLINK/FX2CNTL/FX2_SLRD_N
    SLICE_X3Y55.B        Tilo                  0.259   RLINK/FX2CNTL/RXFIFO/R_REGW_sizew<2>
                                                       RLINK/FX2CNTL/R_REGS_state[3]_GND_75_o_AND_73_o1
    SLICE_X1Y49.A1       net (fanout=5)        1.233   RLINK/FX2CNTL/R_REGS_state[3]_GND_75_o_AND_73_o
    SLICE_X1Y49.CLK      Tas                   0.373   RLINK/FX2CNTL/R_REGS_ccnt<3>
                                                       RLINK/FX2CNTL/R_REGS_ccnt_1_glue_set
                                                       RLINK/FX2CNTL/R_REGS_ccnt_1
    -------------------------------------------------  ---------------------------
    Total                                      7.569ns (2.669ns logic, 4.900ns route)
                                                       (35.3% logic, 64.7% route)

--------------------------------------------------------------------------------

Hold Paths: TS_I_FX2_IFCLK = PERIOD TIMEGRP "I_FX2_IFCLK" 33.34 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.413ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/R_REGS_petocnt_4 (FF)
  Destination:          RLINK/FX2CNTL/R_REGS_petocnt_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.413ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 33.340ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/R_REGS_petocnt_4 to RLINK/FX2CNTL/R_REGS_petocnt_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X8Y50.AQ       Tcko                  0.200   RLINK/FX2CNTL/R_REGS_petocnt<7>
                                                       RLINK/FX2CNTL/R_REGS_petocnt_4
    SLICE_X8Y50.A6       net (fanout=4)        0.023   RLINK/FX2CNTL/R_REGS_petocnt<4>
    SLICE_X8Y50.CLK      Tah         (-Th)    -0.190   RLINK/FX2CNTL/R_REGS_petocnt<7>
                                                       RLINK/FX2CNTL/R_REGS_petocnt_4_glue_set
                                                       RLINK/FX2CNTL/R_REGS_petocnt_4
    -------------------------------------------------  ---------------------------
    Total                                      0.413ns (0.390ns logic, 0.023ns route)
                                                       (94.4% logic, 5.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.415ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/R_REGS_petocnt_7 (FF)
  Destination:          RLINK/FX2CNTL/R_REGS_petocnt_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.415ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 33.340ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/R_REGS_petocnt_7 to RLINK/FX2CNTL/R_REGS_petocnt_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X8Y50.DQ       Tcko                  0.200   RLINK/FX2CNTL/R_REGS_petocnt<7>
                                                       RLINK/FX2CNTL/R_REGS_petocnt_7
    SLICE_X8Y50.D6       net (fanout=4)        0.025   RLINK/FX2CNTL/R_REGS_petocnt<7>
    SLICE_X8Y50.CLK      Tah         (-Th)    -0.190   RLINK/FX2CNTL/R_REGS_petocnt<7>
                                                       RLINK/FX2CNTL/R_REGS_petocnt_7_glue_set
                                                       RLINK/FX2CNTL/R_REGS_petocnt_7
    -------------------------------------------------  ---------------------------
    Total                                      0.415ns (0.390ns logic, 0.025ns route)
                                                       (94.0% logic, 6.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.444ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/R_REGS_pepend (FF)
  Destination:          RLINK/FX2CNTL/R_REGS_pepend (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.444ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 33.340ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/R_REGS_pepend to RLINK/FX2CNTL/R_REGS_pepend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X3Y50.AQ       Tcko                  0.198   RLINK/FX2CNTL/R_REGS_pepend
                                                       RLINK/FX2CNTL/R_REGS_pepend
    SLICE_X3Y50.A6       net (fanout=7)        0.031   RLINK/FX2CNTL/R_REGS_pepend
    SLICE_X3Y50.CLK      Tah         (-Th)    -0.215   RLINK/FX2CNTL/R_REGS_pepend
                                                       RLINK/FX2CNTL/R_REGS_pepend_glue_set
                                                       RLINK/FX2CNTL/R_REGS_pepend
    -------------------------------------------------  ---------------------------
    Total                                      0.444ns (0.413ns logic, 0.031ns route)
                                                       (93.0% logic, 7.0% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_I_FX2_IFCLK = PERIOD TIMEGRP "I_FX2_IFCLK" 33.34 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 30.674ns (period - min period limit)
  Period: 33.340ns
  Min period limit: 2.666ns (375.094MHz) (Tbcper_I)
  Physical resource: I_FX2_IFCLK_BUFGP/BUFG/I0
  Logical resource: I_FX2_IFCLK_BUFGP/BUFG/I0
  Location pin: BUFGMUX_X2Y9.I0
  Clock network: I_FX2_IFCLK_BUFGP/IBUFG
--------------------------------------------------------------------------------
Slack: 31.091ns (period - min period limit)
  Period: 33.340ns
  Min period limit: 2.249ns (444.642MHz) (Tockper)
  Physical resource: RLINK/FX2CNTL/IOB_FX2_SLOE/IOB/R_DO/CLK0
  Logical resource: RLINK/FX2CNTL/IOB_FX2_SLOE/IOB/R_DO_0/CK0
  Location pin: OLOGIC_X0Y45.CLK0
  Clock network: I_FX2_IFCLK_BUFGP
--------------------------------------------------------------------------------
Slack: 31.091ns (period - min period limit)
  Period: 33.340ns
  Min period limit: 2.249ns (444.642MHz) (Tockper)
  Physical resource: RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO/CLK0
  Logical resource: RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0/CK0
  Location pin: OLOGIC_X0Y61.CLK0
  Clock network: I_FX2_IFCLK_BUFGP
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_GEN_CLKSYS_USEDCM_CLKOUT0 = PERIOD TIMEGRP 
"GEN_CLKSYS_USEDCM_CLKOUT0"         TS_I_CLK100 / 0.64 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 7370960 paths analyzed, 15464 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is  15.247ns.
--------------------------------------------------------------------------------
Slack (setup path):     0.378ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SYS70/W11A/SEQ/R_STATE_1_1 (FF)
  Destination:          SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Requirement:          15.625ns
  Data Path Delay:      14.977ns (Levels of Logic = 10)
  Clock Path Skew:      0.022ns (0.464 - 0.442)
  Source Clock:         CLK rising at 0.000ns
  Destination Clock:    CLK rising at 15.625ns
  Clock Uncertainty:    0.292ns

  Clock Uncertainty:          0.292ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: SYS70/W11A/SEQ/R_STATE_1_1 to SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X22Y22.AQ      Tcko                  0.525   SYS70/W11A/SEQ/R_STATE_1_3
                                                       SYS70/W11A/SEQ/R_STATE_1_1
    SLICE_X23Y20.B4      net (fanout=5)        0.835   SYS70/W11A/SEQ/R_STATE_1_1
    SLICE_X23Y20.B       Tilo                  0.259   SYS70/W11A/SEQ/Mmux_proc_next.ndpcntl_dsrc_we2121
                                                       SYS70/W11A/SEQ/Mmux_proc_next.nstatus_trap_mmu1111
    SLICE_X18Y22.A2      net (fanout=13)       1.198   SYS70/W11A/SEQ/Mmux_proc_next.nstatus_trap_mmu111
    SLICE_X18Y22.A       Tilo                  0.254   SYS70/W11A/SEQ/_n6371
                                                       SYS70/W11A/SEQ/_n6371<6>1
    SLICE_X24Y21.D3      net (fanout=2)        0.872   SYS70/W11A/SEQ/_n6371
    SLICE_X24Y21.D       Tilo                  0.235   SYS70/W11A/SEQ/R_STATE_6_3
                                                       SYS70/W11A/SEQ/Mmux_proc_next.nvmcntl_dspace38_SW0_SW0
    SLICE_X25Y23.A5      net (fanout=1)        0.650   N810
    SLICE_X25Y23.A       Tilo                  0.259   SYS70/DMCMON.I0/R_REGS_vm_dspace
                                                       SYS70/W11A/SEQ/Mmux_proc_next.nvmcntl_dspace38
    SLICE_X25Y24.A3      net (fanout=2)        0.583   SYS70/W11A/SEQ/Mmux_proc_next.nvmcntl_dspace37
    SLICE_X25Y24.A       Tilo                  0.259   SYS70/W11A/VMBOX/MMU/SADR/proc_eaddr.eaddr<3>11
                                                       SYS70/W11A/VMBOX/MMU/proc_paddr.dspace_ok11
    SLICE_X25Y24.D3      net (fanout=3)        0.406   SYS70/W11A/VMBOX/MMU/proc_paddr.dspace_ok
    SLICE_X25Y24.D       Tilo                  0.259   SYS70/W11A/VMBOX/MMU/SADR/proc_eaddr.eaddr<3>11
                                                       SYS70/W11A/VMBOX/MMU/SADR/proc_eaddr.eaddr<3>1_2
    SLICE_X30Y23.D4      net (fanout=7)        2.080   SYS70/W11A/VMBOX/MMU/SADR/proc_eaddr.eaddr<3>11
    SLICE_X30Y23.D       Tilo                  0.254   SYS70/W11A/VMBOX/MMU/SARSDR_saf<0>
                                                       SYS70/W11A/VMBOX/MMU/SADR/SAR_LOW/AW_6.GL[0].MEM
    SLICE_X30Y26.A1      net (fanout=2)        1.391   SYS70/W11A/VMBOX/MMU/SARSDR_saf<0>
    SLICE_X30Y26.COUT    Topcya                0.474   SYS70/W11A/VMBOX/MMU/Madd_proc_paddr.ipaddrh_cy<3>
                                                       SYS70/W11A/VMBOX/MMU/Madd_proc_paddr.ipaddrh_lut<0>
                                                       SYS70/W11A/VMBOX/MMU/Madd_proc_paddr.ipaddrh_cy<3>
    SLICE_X30Y27.CIN     net (fanout=1)        0.003   SYS70/W11A/VMBOX/MMU/Madd_proc_paddr.ipaddrh_cy<3>
    SLICE_X30Y27.BMUX    Tcinb                 0.310   SYS70/W11A/VMBOX/MMU/Madd_proc_paddr.ipaddrh_cy<7>
                                                       SYS70/W11A/VMBOX/MMU/Madd_proc_paddr.ipaddrh_cy<7>
    SLICE_X31Y30.B2      net (fanout=1)        0.965   SYS70/W11A/VMBOX/PADDRH<5>
    SLICE_X31Y30.B       Tilo                  0.259   SYS70/W11A/VMBOX/R_REGS_paddr<19>
                                                       SYS70/W11A/VMBOX/Mmux_proc_next.ipaddr53
    RAMB16_X1Y6.ADDRA12  net (fanout=7)        2.247   SYS70/DM_STAT_VM_emmreq_addr<11>
    RAMB16_X1Y6.CLKA     Trcck_ADDRA           0.400   SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM
                                                       SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM
    -------------------------------------------------  ---------------------------
    Total                                     14.977ns (3.747ns logic, 11.230ns route)
                                                       (25.0% logic, 75.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.390ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SRAM_CTL/IOB_MEM_DATA/R_DI_9 (FF)
  Destination:          SYS70/W11A/SEQ/R_STATE_2_4 (FF)
  Requirement:          15.625ns
  Data Path Delay:      14.234ns (Levels of Logic = 10)
  Clock Path Skew:      -0.709ns (0.421 - 1.130)
  Source Clock:         CLK rising at 0.000ns
  Destination Clock:    CLK rising at 15.625ns
  Clock Uncertainty:    0.292ns

  Clock Uncertainty:          0.292ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: SRAM_CTL/IOB_MEM_DATA/R_DI_9 to SYS70/W11A/SEQ/R_STATE_2_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    ILOGIC_X1Y0.Q4       Tickq                 1.778   SRAM_CTL/IOB_MEM_DATA/R_DI<9>
                                                       SRAM_CTL/IOB_MEM_DATA/R_DI_9
    SLICE_X17Y4.A1       net (fanout=6)        1.913   SRAM_CTL/IOB_MEM_DATA/R_DI<9>
    SLICE_X17Y4.A        Tilo                  0.259   N1495
                                                       SYS70/W11A/VMBOX/Mmux_proc_next.ivm_dout81_SW2_G
    SLICE_X18Y4.B2       net (fanout=1)        1.219   N1495
    SLICE_X18Y4.B        Tilo                  0.254   N1491
                                                       SYS70/W11A/VMBOX/Mmux_proc_next.ivm_dout83_G
    SLICE_X19Y10.C4      net (fanout=1)        0.769   N1871
    SLICE_X19Y10.C       Tilo                  0.259   SYS70/DM_STAT_VM_vmdout<1>
                                                       SYS70/W11A/VMBOX/Mmux_proc_next.ivm_dout831
    SLICE_X19Y10.D5      net (fanout=5)        0.248   SYS70/DM_STAT_VM_vmdout<9>
    SLICE_X19Y10.D       Tilo                  0.259   SYS70/DM_STAT_VM_vmdout<1>
                                                       SYS70/W11A/VMBOX/Mmux_proc_next.ivm_dout<0>113
    SLICE_X22Y14.B3      net (fanout=4)        1.128   SYS70/DM_STAT_VM_vmdout<1>
    SLICE_X22Y14.COUT    Topcyb                0.483   SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<3>
                                                       SYS70/W11A/DPATH/OUNIT/Maddsub_sum_lut<1>
                                                       SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<3>
    SLICE_X22Y15.CIN     net (fanout=1)        0.003   SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<3>
    SLICE_X22Y15.COUT    Tbyp                  0.093   SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<7>
                                                       SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<7>
    SLICE_X22Y16.CIN     net (fanout=1)        0.003   SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<7>
    SLICE_X22Y16.AMUX    Tcina                 0.220   SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<11>
                                                       SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<11>
    SLICE_X23Y15.A2      net (fanout=2)        0.758   SYS70/W11A/DPATH/OUNIT_DOUT<8>
    SLICE_X23Y15.A       Tilo                  0.259   SYS70/DM_STAT_VM_vmdout<4>
                                                       SYS70/W11A/DPATH/Mmux_CCOUT312
    SLICE_X26Y20.A3      net (fanout=1)        1.063   SYS70/W11A/DPATH/Mmux_CCOUT311
    SLICE_X26Y20.A       Tilo                  0.254   SYS70/W11A/SEQ/Mmux_proc_next.nmmumoni_idone313
                                                       SYS70/W11A/DPATH/Mmux_CCOUT316
    SLICE_X27Y28.D3      net (fanout=19)       1.121   SYS70/W11A/DP_STAT_ccout_z
    SLICE_X27Y28.D       Tilo                  0.259   SYS70/W11A/SEQ/proc_next.nstate<2>
                                                       SYS70/W11A/SEQ/proc_next.nstate<2>30
    SLICE_X23Y21.DX      net (fanout=5)        1.518   SYS70/W11A/SEQ/proc_next.nstate<2>
    SLICE_X23Y21.CLK     Tdick                 0.114   SYS70/W11A/SEQ/R_STATE_2_4
                                                       SYS70/W11A/SEQ/R_STATE_2_4
    -------------------------------------------------  ---------------------------
    Total                                     14.234ns (4.491ns logic, 9.743ns route)
                                                       (31.6% logic, 68.4% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.400ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SRAM_CTL/IOB_MEM_DATA/R_DI_9 (FF)
  Destination:          SYS70/W11A/SEQ/R_STATE_2_4 (FF)
  Requirement:          15.625ns
  Data Path Delay:      14.224ns (Levels of Logic = 8)
  Clock Path Skew:      -0.709ns (0.421 - 1.130)
  Source Clock:         CLK rising at 0.000ns
  Destination Clock:    CLK rising at 15.625ns
  Clock Uncertainty:    0.292ns

  Clock Uncertainty:          0.292ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: SRAM_CTL/IOB_MEM_DATA/R_DI_9 to SYS70/W11A/SEQ/R_STATE_2_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    ILOGIC_X1Y0.Q4       Tickq                 1.778   SRAM_CTL/IOB_MEM_DATA/R_DI<9>
                                                       SRAM_CTL/IOB_MEM_DATA/R_DI_9
    SLICE_X17Y4.A1       net (fanout=6)        1.913   SRAM_CTL/IOB_MEM_DATA/R_DI<9>
    SLICE_X17Y4.A        Tilo                  0.259   N1495
                                                       SYS70/W11A/VMBOX/Mmux_proc_next.ivm_dout81_SW2_G
    SLICE_X18Y4.B2       net (fanout=1)        1.219   N1495
    SLICE_X18Y4.B        Tilo                  0.254   N1491
                                                       SYS70/W11A/VMBOX/Mmux_proc_next.ivm_dout83_G
    SLICE_X19Y10.C4      net (fanout=1)        0.769   N1871
    SLICE_X19Y10.C       Tilo                  0.259   SYS70/DM_STAT_VM_vmdout<1>
                                                       SYS70/W11A/VMBOX/Mmux_proc_next.ivm_dout831
    SLICE_X19Y10.D5      net (fanout=5)        0.248   SYS70/DM_STAT_VM_vmdout<9>
    SLICE_X19Y10.D       Tilo                  0.259   SYS70/DM_STAT_VM_vmdout<1>
                                                       SYS70/W11A/VMBOX/Mmux_proc_next.ivm_dout<0>113
    SLICE_X22Y14.B3      net (fanout=4)        1.128   SYS70/DM_STAT_VM_vmdout<1>
    SLICE_X22Y14.DMUX    Topbd                 0.695   SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<3>
                                                       SYS70/W11A/DPATH/OUNIT/Maddsub_sum_lut<1>
                                                       SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<3>
    SLICE_X26Y15.C3      net (fanout=2)        0.848   SYS70/W11A/DPATH/OUNIT_DOUT<3>
    SLICE_X26Y15.C       Tilo                  0.255   SYS70/W11A/DPATH/Mmux_CCOUT310
                                                       SYS70/W11A/DPATH/Mmux_CCOUT314_SW1
    SLICE_X26Y20.A6      net (fanout=1)        1.074   N765
    SLICE_X26Y20.A       Tilo                  0.254   SYS70/W11A/SEQ/Mmux_proc_next.nmmumoni_idone313
                                                       SYS70/W11A/DPATH/Mmux_CCOUT316
    SLICE_X27Y28.D3      net (fanout=19)       1.121   SYS70/W11A/DP_STAT_ccout_z
    SLICE_X27Y28.D       Tilo                  0.259   SYS70/W11A/SEQ/proc_next.nstate<2>
                                                       SYS70/W11A/SEQ/proc_next.nstate<2>30
    SLICE_X23Y21.DX      net (fanout=5)        1.518   SYS70/W11A/SEQ/proc_next.nstate<2>
    SLICE_X23Y21.CLK     Tdick                 0.114   SYS70/W11A/SEQ/R_STATE_2_4
                                                       SYS70/W11A/SEQ/R_STATE_2_4
    -------------------------------------------------  ---------------------------
    Total                                     14.224ns (4.386ns logic, 9.838ns route)
                                                       (30.8% logic, 69.2% route)

--------------------------------------------------------------------------------

Hold Paths: TS_GEN_CLKSYS_USEDCM_CLKOUT0 = PERIOD TIMEGRP "GEN_CLKSYS_USEDCM_CLKOUT0"
        TS_I_CLK100 / 0.64 HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.219ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/SERPORT/XONRX/R_REGS_rxdata_3 (FF)
  Destination:          RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[3].MEM1/SP (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.221ns (Levels of Logic = 0)
  Clock Path Skew:      0.002ns (0.032 - 0.030)
  Source Clock:         CLK rising at 15.625ns
  Destination Clock:    CLK rising at 15.625ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: RLINK/SERPORT/XONRX/R_REGS_rxdata_3 to RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[3].MEM1/SP
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X7Y56.DQ       Tcko                  0.198   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/SERPORT/XONRX/R_REGS_rxdata_3
    SLICE_X6Y56.DI       net (fanout=4)        0.025   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
    SLICE_X6Y56.CLK      Tdh         (-Th)     0.002   RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[3].MEM1/SP
    -------------------------------------------------  ---------------------------
    Total                                      0.221ns (0.196ns logic, 0.025ns route)
                                                       (88.7% logic, 11.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.266ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/RBMON.I0/R_REGS_rbdata_2 (FF)
  Destination:          RLINK/RBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.270ns (Levels of Logic = 0)
  Clock Path Skew:      0.004ns (0.117 - 0.113)
  Source Clock:         CLK rising at 15.625ns
  Destination Clock:    CLK rising at 15.625ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: RLINK/RBMON.I0/R_REGS_rbdata_2 to RLINK/RBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X3Y38.BQ       Tcko                  0.198   RLINK/RBMON.I0/R_REGS_rbdata_4
                                                       RLINK/RBMON.I0/R_REGS_rbdata_2
    RAMB16_X0Y18.DIA18   net (fanout=1)        0.125   RLINK/RBMON.I0/R_REGS_rbdata_2
    RAMB16_X0Y18.CLKA    Trckd_DIA   (-Th)     0.053   RLINK/RBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
                                                       RLINK/RBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
    -------------------------------------------------  ---------------------------
    Total                                      0.270ns (0.145ns logic, 0.125ns route)
                                                       (53.7% logic, 46.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.267ns (requirement - (clock path skew + uncertainty - data path))
  Source:               SYS70/IBMON.I0/R_REGS_ibaddr_10 (FF)
  Destination:          SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.270ns (Levels of Logic = 0)
  Clock Path Skew:      0.003ns (0.119 - 0.116)
  Source Clock:         CLK rising at 15.625ns
  Destination Clock:    CLK rising at 15.625ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: SYS70/IBMON.I0/R_REGS_ibaddr_10 to SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X33Y36.BQ      Tcko                  0.198   SYS70/IBMON.I0/R_REGS_ibaddr_12
                                                       SYS70/IBMON.I0/R_REGS_ibaddr_10
    RAMB16_X1Y18.DIA10   net (fanout=1)        0.125   SYS70/IBMON.I0/R_REGS_ibaddr_10
    RAMB16_X1Y18.CLKA    Trckd_DIA   (-Th)     0.053   SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
                                                       SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
    -------------------------------------------------  ---------------------------
    Total                                      0.270ns (0.145ns logic, 0.125ns route)
                                                       (53.7% logic, 46.3% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_GEN_CLKSYS_USEDCM_CLKOUT0 = PERIOD TIMEGRP "GEN_CLKSYS_USEDCM_CLKOUT0"
        TS_I_CLK100 / 0.64 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 12.055ns (period - min period limit)
  Period: 15.625ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: SYS70/DMSCNT.I0/CMEM/UMEM/AW_09_S36.GL[0].MEM/CLKA
  Logical resource: SYS70/DMSCNT.I0/CMEM/UMEM/AW_09_S36.GL[0].MEM/CLKA
  Location pin: RAMB16_X0Y16.CLKA
  Clock network: CLK
--------------------------------------------------------------------------------
Slack: 12.055ns (period - min period limit)
  Period: 15.625ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax))
  Physical resource: SYS70/DMSCNT.I0/CMEM/UMEM/AW_09_S36.GL[0].MEM/CLKB
  Logical resource: SYS70/DMSCNT.I0/CMEM/UMEM/AW_09_S36.GL[0].MEM/CLKB
  Location pin: RAMB16_X0Y16.CLKB
  Clock network: CLK
--------------------------------------------------------------------------------
Slack: 12.055ns (period - min period limit)
  Period: 15.625ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: SYS70/DMCMON.I0/BRAM0/UMEM/AW_09_S36.GL[0].MEM/CLKA
  Logical resource: SYS70/DMCMON.I0/BRAM0/UMEM/AW_09_S36.GL[0].MEM/CLKA
  Location pin: RAMB16_X0Y12.CLKA
  Clock network: CLK
--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = IN 10 ns BEFORE COMP "I_CLK100";
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 32 paths analyzed, 32 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Offset is  -0.513ns.
--------------------------------------------------------------------------------
Slack (setup path):     10.513ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               IO_MEM_DATA<14> (PAD)
  Destination:          SRAM_CTL/IOB_MEM_DATA/R_DI_14 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      1.834ns (Levels of Logic = 2)
  Clock Path Delay:     2.778ns (Levels of Logic = 4)
  Clock Uncertainty:    0.431ns

  Clock Uncertainty:          0.431ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Fast Process Corner: IO_MEM_DATA<14> to SRAM_CTL/IOB_MEM_DATA/R_DI_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R8.I                 Tiopi                 0.887   IO_MEM_DATA<14>
                                                       IO_MEM_DATA<14>
                                                       IO_MEM_DATA_14_IOBUF/IBUF
                                                       ProtoComp1497.IMUX.14
    ILOGIC_X8Y1.D        net (fanout=1)        0.190   N667
    ILOGIC_X8Y1.CLK0     Tidock                0.757   SRAM_CTL/IOB_MEM_DATA/R_DI<14>
                                                       ProtoComp1567.D2OFFBYP_SRC.14
                                                       SRAM_CTL/IOB_MEM_DATA/R_DI_14
    -------------------------------------------------  ---------------------------
    Total                                      1.834ns (1.644ns logic, 0.190ns route)
                                                       (89.6% logic, 10.4% route)

  Minimum Clock Path at Fast Process Corner: I_CLK100 to SRAM_CTL/IOB_MEM_DATA/R_DI_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X8Y1.CLK0     net (fanout=1212)     0.646   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.778ns (1.274ns logic, 1.504ns route)
                                                       (45.9% logic, 54.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     10.518ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               I_SWI<3> (PAD)
  Destination:          HIO/HIO/HIO/IOB_SWI/R_DI_3 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      1.834ns (Levels of Logic = 2)
  Clock Path Delay:     2.783ns (Levels of Logic = 4)
  Clock Uncertainty:    0.431ns

  Clock Uncertainty:          0.431ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Fast Process Corner: I_SWI<3> to HIO/HIO/HIO/IOB_SWI/R_DI_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    M8.I                 Tiopi                 0.887   I_SWI<3>
                                                       I_SWI<3>
                                                       I_SWI_3_IBUF
                                                       ProtoComp1504.IMUX.3
    ILOGIC_X7Y1.D        net (fanout=1)        0.190   I_SWI_3_IBUF
    ILOGIC_X7Y1.CLK0     Tidock                0.757   HIO/HIO/HIO/IOB_SWI/R_DI<3>
                                                       ProtoComp1567.D2OFFBYP_SRC.19
                                                       HIO/HIO/HIO/IOB_SWI/R_DI_3
    -------------------------------------------------  ---------------------------
    Total                                      1.834ns (1.644ns logic, 0.190ns route)
                                                       (89.6% logic, 10.4% route)

  Minimum Clock Path at Fast Process Corner: I_CLK100 to HIO/HIO/HIO/IOB_SWI/R_DI_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X7Y1.CLK0     net (fanout=1212)     0.651   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.783ns (1.274ns logic, 1.509ns route)
                                                       (45.8% logic, 54.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     10.541ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               I_SWI<0> (PAD)
  Destination:          HIO/HIO/HIO/IOB_SWI/R_DI_0 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      1.803ns (Levels of Logic = 2)
  Clock Path Delay:     2.775ns (Levels of Logic = 4)
  Clock Uncertainty:    0.431ns

  Clock Uncertainty:          0.431ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Fast Process Corner: I_SWI<0> to HIO/HIO/HIO/IOB_SWI/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T10.I                Tiopi                 0.887   I_SWI<0>
                                                       I_SWI<0>
                                                       I_SWI_0_IBUF
                                                       ProtoComp1504.IMUX
    ILOGIC_X9Y0.D        net (fanout=1)        0.159   I_SWI_0_IBUF
    ILOGIC_X9Y0.CLK0     Tidock                0.757   HIO/HIO/HIO/IOB_SWI/R_DI<0>
                                                       ProtoComp1567.D2OFFBYP_SRC.16
                                                       HIO/HIO/HIO/IOB_SWI/R_DI_0
    -------------------------------------------------  ---------------------------
    Total                                      1.803ns (1.644ns logic, 0.159ns route)
                                                       (91.2% logic, 8.8% route)

  Minimum Clock Path at Fast Process Corner: I_CLK100 to HIO/HIO/HIO/IOB_SWI/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X9Y0.CLK0     net (fanout=1212)     0.643   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.775ns (1.274ns logic, 1.501ns route)
                                                       (45.9% logic, 54.1% route)

--------------------------------------------------------------------------------

Hold Paths: OFFSET = IN 10 ns BEFORE COMP "I_CLK100";
--------------------------------------------------------------------------------
Offset (hold paths):    -3.990ns (data path - clock path + uncertainty)
  Source:               I_BTN<0> (PAD)
  Destination:          HIO/HIO/HIO/IOB_BTN/R_DI_0 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Data Path Delay:      2.445ns (Levels of Logic = 2)
  Clock Path Delay:     6.866ns (Levels of Logic = 4)
  Clock Uncertainty:    0.431ns

  Clock Uncertainty:          0.431ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Slow Process Corner: I_BTN<0> to HIO/HIO/HIO/IOB_BTN/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A8.I                 Tiopi                 0.902   I_BTN<0>
                                                       I_BTN<0>
                                                       I_BTN_0_IBUF
                                                       ProtoComp1504.IMUX.14
    ILOGIC_X7Y60.D       net (fanout=1)        0.164   I_BTN_0_IBUF
    ILOGIC_X7Y60.CLK0    Tiockd      (-Th)    -1.379   HIO/HIO/HIO/IOB_BTN/R_DI<0>
                                                       ProtoComp1567.D2OFFBYP_SRC.25
                                                       HIO/HIO/HIO/IOB_BTN/R_DI_0
    -------------------------------------------------  ---------------------------
    Total                                      2.445ns (2.281ns logic, 0.164ns route)
                                                       (93.3% logic, 6.7% route)

  Maximum Clock Path at Slow Process Corner: I_CLK100 to HIO/HIO/HIO/IOB_BTN/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X7Y60.CLK0    net (fanout=1212)     1.732   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.866ns (2.356ns logic, 4.510ns route)
                                                       (34.3% logic, 65.7% route)

--------------------------------------------------------------------------------
Offset (hold paths):    -3.971ns (data path - clock path + uncertainty)
  Source:               I_BTN<3> (PAD)
  Destination:          HIO/HIO/HIO/IOB_BTN/R_DI_3 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Data Path Delay:      2.506ns (Levels of Logic = 2)
  Clock Path Delay:     6.908ns (Levels of Logic = 4)
  Clock Uncertainty:    0.431ns

  Clock Uncertainty:          0.431ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Slow Process Corner: I_BTN<3> to HIO/HIO/HIO/IOB_BTN/R_DI_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C4.I                 Tiopi                 0.902   I_BTN<3>
                                                       I_BTN<3>
                                                       I_BTN_3_IBUF
                                                       ProtoComp1504.IMUX.17
    ILOGIC_X1Y62.D       net (fanout=1)        0.225   I_BTN_3_IBUF
    ILOGIC_X1Y62.CLK0    Tiockd      (-Th)    -1.379   HIO/HIO/HIO/IOB_BTN/R_DI<3>
                                                       ProtoComp1567.D2OFFBYP_SRC.28
                                                       HIO/HIO/HIO/IOB_BTN/R_DI_3
    -------------------------------------------------  ---------------------------
    Total                                      2.506ns (2.281ns logic, 0.225ns route)
                                                       (91.0% logic, 9.0% route)

  Maximum Clock Path at Slow Process Corner: I_CLK100 to HIO/HIO/HIO/IOB_BTN/R_DI_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X1Y62.CLK0    net (fanout=1212)     1.774   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.908ns (2.356ns logic, 4.552ns route)
                                                       (34.1% logic, 65.9% route)

--------------------------------------------------------------------------------
Offset (hold paths):    -3.925ns (data path - clock path + uncertainty)
  Source:               I_BTN<2> (PAD)
  Destination:          HIO/HIO/HIO/IOB_BTN/R_DI_2 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Data Path Delay:      2.506ns (Levels of Logic = 2)
  Clock Path Delay:     6.862ns (Levels of Logic = 4)
  Clock Uncertainty:    0.431ns

  Clock Uncertainty:          0.431ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Slow Process Corner: I_BTN<2> to HIO/HIO/HIO/IOB_BTN/R_DI_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C9.I                 Tiopi                 0.902   I_BTN<2>
                                                       I_BTN<2>
                                                       I_BTN_2_IBUF
                                                       ProtoComp1504.IMUX.16
    ILOGIC_X8Y62.D       net (fanout=1)        0.225   I_BTN_2_IBUF
    ILOGIC_X8Y62.CLK0    Tiockd      (-Th)    -1.379   HIO/HIO/HIO/IOB_BTN/R_DI<2>
                                                       ProtoComp1567.D2OFFBYP_SRC.27
                                                       HIO/HIO/HIO/IOB_BTN/R_DI_2
    -------------------------------------------------  ---------------------------
    Total                                      2.506ns (2.281ns logic, 0.225ns route)
                                                       (91.0% logic, 9.0% route)

  Maximum Clock Path at Slow Process Corner: I_CLK100 to HIO/HIO/HIO/IOB_BTN/R_DI_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X8Y62.CLK0    net (fanout=1212)     1.728   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.862ns (2.356ns logic, 4.506ns route)
                                                       (34.3% logic, 65.7% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = OUT 20 ns AFTER COMP "I_CLK100";
For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612).

 81 paths analyzed, 65 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
 Minimum allowable offset is  18.512ns.
--------------------------------------------------------------------------------
Slack (slowest paths):  1.488ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               SRAM_CTL/IOB_MEM_WE/IOB/R_DO_0 (FF)
  Destination:          O_MEM_WE_N (PAD)
  Source Clock:         CLK falling at 7.812ns
  Requirement:          20.000ns
  Data Path Delay:      3.371ns (Levels of Logic = 1)
  Clock Path Delay:     6.898ns (Levels of Logic = 4)
  Clock Uncertainty:    0.431ns

  Clock Uncertainty:          0.431ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Clock Path at Slow Process Corner: I_CLK100 to SRAM_CTL/IOB_MEM_WE/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    OLOGIC_X18Y21.CLK0   net (fanout=1212)     1.764   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.898ns (2.356ns logic, 4.542ns route)
                                                       (34.2% logic, 65.8% route)

  Maximum Data Path at Slow Process Corner: SRAM_CTL/IOB_MEM_WE/IOB/R_DO_0 to O_MEM_WE_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X18Y21.OQ     Tockq                 1.080   SRAM_CTL/IOB_MEM_WE/IOB/R_DO
                                                       SRAM_CTL/IOB_MEM_WE/IOB/R_DO_0
    M16.O                net (fanout=1)        0.309   SRAM_CTL/IOB_MEM_WE/IOB/R_DO
    M16.PAD              Tioop                 1.982   O_MEM_WE_N
                                                       O_MEM_WE_N_OBUF
                                                       O_MEM_WE_N
    -------------------------------------------------  ---------------------------
    Total                                      3.371ns (3.062ns logic, 0.309ns route)
                                                       (90.8% logic, 9.2% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  7.976ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               IOB_RS232/P1/IOB_TXD/IOB/R_DO_0 (FF)
  Destination:          O_FUSP_TXD (PAD)
  Source Clock:         CLK rising at 0.000ns
  Requirement:          20.000ns
  Data Path Delay:      4.702ns (Levels of Logic = 1)
  Clock Path Delay:     6.891ns (Levels of Logic = 4)
  Clock Uncertainty:    0.431ns

  Clock Uncertainty:          0.431ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Clock Path at Slow Process Corner: I_CLK100 to IOB_RS232/P1/IOB_TXD/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    OLOGIC_X0Y24.CLK0    net (fanout=1212)     1.757   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.891ns (2.356ns logic, 4.535ns route)
                                                       (34.2% logic, 65.8% route)

  Maximum Data Path at Slow Process Corner: IOB_RS232/P1/IOB_TXD/IOB/R_DO_0 to O_FUSP_TXD
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X0Y24.OQ      Tockq                 1.080   IOB_RS232/P1/IOB_TXD/IOB/R_DO
                                                       IOB_RS232/P1/IOB_TXD/IOB/R_DO_0
    L3.O                 net (fanout=1)        0.310   IOB_RS232/P1/IOB_TXD/IOB/R_DO
    L3.PAD               Tioop                 3.312   O_FUSP_TXD
                                                       O_FUSP_TXD_OBUF
                                                       O_FUSP_TXD
    -------------------------------------------------  ---------------------------
    Total                                      4.702ns (4.392ns logic, 0.310ns route)
                                                       (93.4% logic, 6.6% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  7.981ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               IOB_RS232/P1/IOB_RTS/IOB/R_DO_0 (FF)
  Destination:          O_FUSP_RTS_N (PAD)
  Source Clock:         CLK rising at 0.000ns
  Requirement:          20.000ns
  Data Path Delay:      4.702ns (Levels of Logic = 1)
  Clock Path Delay:     6.886ns (Levels of Logic = 4)
  Clock Uncertainty:    0.431ns

  Clock Uncertainty:          0.431ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Clock Path at Slow Process Corner: I_CLK100 to IOB_RS232/P1/IOB_RTS/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    OLOGIC_X0Y23.CLK0    net (fanout=1212)     1.752   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.886ns (2.356ns logic, 4.530ns route)
                                                       (34.2% logic, 65.8% route)

  Maximum Data Path at Slow Process Corner: IOB_RS232/P1/IOB_RTS/IOB/R_DO_0 to O_FUSP_RTS_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X0Y23.OQ      Tockq                 1.080   IOB_RS232/P1/IOB_RTS/IOB/R_DO
                                                       IOB_RS232/P1/IOB_RTS/IOB/R_DO_0
    K2.O                 net (fanout=1)        0.310   IOB_RS232/P1/IOB_RTS/IOB/R_DO
    K2.PAD               Tioop                 3.312   O_FUSP_RTS_N
                                                       O_FUSP_RTS_N_OBUF
                                                       O_FUSP_RTS_N
    -------------------------------------------------  ---------------------------
    Total                                      4.702ns (4.392ns logic, 0.310ns route)
                                                       (93.4% logic, 6.6% route)

--------------------------------------------------------------------------------

Fastest Paths: OFFSET = OUT 20 ns AFTER COMP "I_CLK100";
--------------------------------------------------------------------------------
Delay (fastest paths):  3.613ns (clock arrival + clock path + data path - uncertainty)
  Source:               SRAM_CTL/IOB_MEM_BE/R_DO_1 (FF)
  Destination:          O_MEM_BE_N<1> (PAD)
  Source Clock:         CLK rising at 0.000ns
  Data Path Delay:      1.225ns (Levels of Logic = 1)
  Clock Path Delay:     2.819ns (Levels of Logic = 4)
  Clock Uncertainty:    0.431ns

  Clock Uncertainty:          0.431ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Clock Path at Fast Process Corner: I_CLK100 to SRAM_CTL/IOB_MEM_BE/R_DO_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    OLOGIC_X18Y33.CLK0   net (fanout=1212)     0.687   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.819ns (1.274ns logic, 1.545ns route)
                                                       (45.2% logic, 54.8% route)

  Minimum Data Path at Fast Process Corner: SRAM_CTL/IOB_MEM_BE/R_DO_1 to O_MEM_BE_N<1>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X18Y33.OQ     Tockq                 0.336   SRAM_CTL/IOB_MEM_BE/R_DO<1>
                                                       SRAM_CTL/IOB_MEM_BE/R_DO_1
    K15.O                net (fanout=1)        0.190   SRAM_CTL/IOB_MEM_BE/R_DO<1>
    K15.PAD              Tioop                 0.699   O_MEM_BE_N<1>
                                                       O_MEM_BE_N_1_OBUF
                                                       O_MEM_BE_N<1>
    -------------------------------------------------  ---------------------------
    Total                                      1.225ns (1.035ns logic, 0.190ns route)
                                                       (84.5% logic, 15.5% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  3.613ns (clock arrival + clock path + data path - uncertainty)
  Source:               SRAM_CTL/IOB_MEM_BE/R_DO_0 (FF)
  Destination:          O_MEM_BE_N<0> (PAD)
  Source Clock:         CLK rising at 0.000ns
  Data Path Delay:      1.225ns (Levels of Logic = 1)
  Clock Path Delay:     2.819ns (Levels of Logic = 4)
  Clock Uncertainty:    0.431ns

  Clock Uncertainty:          0.431ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Clock Path at Fast Process Corner: I_CLK100 to SRAM_CTL/IOB_MEM_BE/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    OLOGIC_X18Y32.CLK0   net (fanout=1212)     0.687   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.819ns (1.274ns logic, 1.545ns route)
                                                       (45.2% logic, 54.8% route)

  Minimum Data Path at Fast Process Corner: SRAM_CTL/IOB_MEM_BE/R_DO_0 to O_MEM_BE_N<0>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X18Y32.OQ     Tockq                 0.336   SRAM_CTL/IOB_MEM_BE/R_DO<0>
                                                       SRAM_CTL/IOB_MEM_BE/R_DO_0
    K16.O                net (fanout=1)        0.190   SRAM_CTL/IOB_MEM_BE/R_DO<0>
    K16.PAD              Tioop                 0.699   O_MEM_BE_N<0>
                                                       O_MEM_BE_N_0_OBUF
                                                       O_MEM_BE_N<0>
    -------------------------------------------------  ---------------------------
    Total                                      1.225ns (1.035ns logic, 0.190ns route)
                                                       (84.5% logic, 15.5% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  3.601ns (clock arrival + clock path + data path - uncertainty)
  Source:               SRAM_CTL/IOB_MEM_OE/IOB/R_DO_0 (FF)
  Destination:          O_MEM_OE_N (PAD)
  Source Clock:         CLK rising at 0.000ns
  Data Path Delay:      1.225ns (Levels of Logic = 1)
  Clock Path Delay:     2.807ns (Levels of Logic = 4)
  Clock Uncertainty:    0.431ns

  Clock Uncertainty:          0.431ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Clock Path at Fast Process Corner: I_CLK100 to SRAM_CTL/IOB_MEM_OE/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    OLOGIC_X18Y22.CLK0   net (fanout=1212)     0.675   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.807ns (1.274ns logic, 1.533ns route)
                                                       (45.4% logic, 54.6% route)

  Minimum Data Path at Fast Process Corner: SRAM_CTL/IOB_MEM_OE/IOB/R_DO_0 to O_MEM_OE_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X18Y22.OQ     Tockq                 0.336   SRAM_CTL/IOB_MEM_OE/IOB/R_DO
                                                       SRAM_CTL/IOB_MEM_OE/IOB/R_DO_0
    L18.O                net (fanout=1)        0.190   SRAM_CTL/IOB_MEM_OE/IOB/R_DO
    L18.PAD              Tioop                 0.699   O_MEM_OE_N
                                                       O_MEM_OE_N_OBUF
                                                       O_MEM_OE_N
    -------------------------------------------------  ---------------------------
    Total                                      1.225ns (1.035ns logic, 0.190ns route)
                                                       (84.5% logic, 15.5% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = IN 2 ns VALID 33 ns BEFORE COMP "I_FX2_IFCLK";
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 11 paths analyzed, 11 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   0.981ns.
--------------------------------------------------------------------------------
Slack (setup path):     1.019ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               IO_FX2_DATA<4> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          2.000ns
  Data Path Delay:      4.724ns (Levels of Logic = 3)
  Clock Path Delay:     3.768ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: IO_FX2_DATA<4> to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    D1.I                 Tiopi                 1.557   IO_FX2_DATA<4>
                                                       IO_FX2_DATA<4>
                                                       IO_FX2_DATA_4_IOBUF/IBUF
                                                       ProtoComp1497.IMUX.20
    IODELAY_X0Y50.IDATAINnet (fanout=1)        0.168   N685
    IODELAY_X0Y50.DATAOUTTioddo_IDATAIN        2.460   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4_ML_IODELAY2
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4_ML_IODELAY2
    ILOGIC_X0Y50.DDLY    net (fanout=1)        0.007   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4_ML_IODELAY2_SIG_ML
    ILOGIC_X0Y50.CLK0    Tidockd               0.532   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI<4>
                                                       ProtoComp1594.D2OFFBYP_SRC.7
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4
    -------------------------------------------------  ---------------------------
    Total                                      4.724ns (4.549ns logic, 0.175ns route)
                                                       (96.3% logic, 3.7% route)

  Minimum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.344   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.855   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.197   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y50.CLK0    net (fanout=51)       1.372   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.768ns (1.541ns logic, 2.227ns route)
                                                       (40.9% logic, 59.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.019ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               IO_FX2_DATA<3> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          2.000ns
  Data Path Delay:      4.724ns (Levels of Logic = 3)
  Clock Path Delay:     3.768ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: IO_FX2_DATA<3> to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    D2.I                 Tiopi                 1.557   IO_FX2_DATA<3>
                                                       IO_FX2_DATA<3>
                                                       IO_FX2_DATA_3_IOBUF/IBUF
                                                       ProtoComp1497.IMUX.19
    IODELAY_X0Y51.IDATAINnet (fanout=1)        0.168   N686
    IODELAY_X0Y51.DATAOUTTioddo_IDATAIN        2.460   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3_ML_IODELAY2
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3_ML_IODELAY2
    ILOGIC_X0Y51.DDLY    net (fanout=1)        0.007   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3_ML_IODELAY2_SIG_ML
    ILOGIC_X0Y51.CLK0    Tidockd               0.532   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI<3>
                                                       ProtoComp1594.D2OFFBYP_SRC.6
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3
    -------------------------------------------------  ---------------------------
    Total                                      4.724ns (4.549ns logic, 0.175ns route)
                                                       (96.3% logic, 3.7% route)

  Minimum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.344   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.855   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.197   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y51.CLK0    net (fanout=51)       1.372   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.768ns (1.541ns logic, 2.227ns route)
                                                       (40.9% logic, 59.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.019ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               IO_FX2_DATA<5> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          2.000ns
  Data Path Delay:      4.724ns (Levels of Logic = 3)
  Clock Path Delay:     3.768ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: IO_FX2_DATA<5> to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H7.I                 Tiopi                 1.557   IO_FX2_DATA<5>
                                                       IO_FX2_DATA<5>
                                                       IO_FX2_DATA_5_IOBUF/IBUF
                                                       ProtoComp1497.IMUX.21
    IODELAY_X0Y53.IDATAINnet (fanout=1)        0.168   N684
    IODELAY_X0Y53.DATAOUTTioddo_IDATAIN        2.460   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5_ML_IODELAY2
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5_ML_IODELAY2
    ILOGIC_X0Y53.DDLY    net (fanout=1)        0.007   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5_ML_IODELAY2_SIG_ML
    ILOGIC_X0Y53.CLK0    Tidockd               0.532   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI<5>
                                                       ProtoComp1594.D2OFFBYP_SRC.8
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5
    -------------------------------------------------  ---------------------------
    Total                                      4.724ns (4.549ns logic, 0.175ns route)
                                                       (96.3% logic, 3.7% route)

  Minimum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.344   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.855   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.197   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y53.CLK0    net (fanout=51)       1.372   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.768ns (1.541ns logic, 2.227ns route)
                                                       (40.9% logic, 59.1% route)

--------------------------------------------------------------------------------

Hold Paths: OFFSET = IN 2 ns VALID 33 ns BEFORE COMP "I_FX2_IFCLK";
--------------------------------------------------------------------------------
Slack (hold path):      30.419ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               I_FX2_FLAG<2> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          31.000ns
  Data Path Delay:      3.926ns (Levels of Logic = 3)
  Clock Path Delay:     4.482ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path at Slow Process Corner: I_FX2_FLAG<2> to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    F5.I                 Tiopi                 1.344   I_FX2_FLAG<2>
                                                       I_FX2_FLAG<2>
                                                       I_FX2_FLAG_2_IBUF
                                                       ProtoComp1504.IMUX.12
    IODELAY_X0Y56.IDATAINnet (fanout=1)        0.168   I_FX2_FLAG_2_IBUF
    IODELAY_X0Y56.DATAOUTTioddo_IDATAIN        2.150   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2_ML_IODELAY2
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2_ML_IODELAY2
    ILOGIC_X0Y56.DDLY    net (fanout=1)        0.007   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2_ML_IODELAY2_SIG_ML
    ILOGIC_X0Y56.CLK0    Tiockdd     (-Th)    -0.257   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<2>
                                                       ProtoComp1594.D2OFFBYP_SRC.2
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2
    -------------------------------------------------  ---------------------------
    Total                                      3.926ns (3.751ns logic, 0.175ns route)
                                                       (95.5% logic, 4.5% route)

  Maximum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y56.CLK0    net (fanout=51)       1.710   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.482ns (1.766ns logic, 2.716ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      30.419ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               I_FX2_FLAG<1> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          31.000ns
  Data Path Delay:      3.926ns (Levels of Logic = 3)
  Clock Path Delay:     4.482ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path at Slow Process Corner: I_FX2_FLAG<1> to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    K4.I                 Tiopi                 1.344   I_FX2_FLAG<1>
                                                       I_FX2_FLAG<1>
                                                       I_FX2_FLAG_1_IBUF
                                                       ProtoComp1504.IMUX.11
    IODELAY_X0Y31.IDATAINnet (fanout=1)        0.168   I_FX2_FLAG_1_IBUF
    IODELAY_X0Y31.DATAOUTTioddo_IDATAIN        2.150   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1_ML_IODELAY2
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1_ML_IODELAY2
    ILOGIC_X0Y31.DDLY    net (fanout=1)        0.007   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1_ML_IODELAY2_SIG_ML
    ILOGIC_X0Y31.CLK0    Tiockdd     (-Th)    -0.257   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<1>
                                                       ProtoComp1594.D2OFFBYP_SRC.1
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1
    -------------------------------------------------  ---------------------------
    Total                                      3.926ns (3.751ns logic, 0.175ns route)
                                                       (95.5% logic, 4.5% route)

  Maximum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y31.CLK0    net (fanout=51)       1.710   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.482ns (1.766ns logic, 2.716ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      30.420ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               I_FX2_FLAG<0> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          31.000ns
  Data Path Delay:      3.926ns (Levels of Logic = 3)
  Clock Path Delay:     4.481ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path at Slow Process Corner: I_FX2_FLAG<0> to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H1.I                 Tiopi                 1.344   I_FX2_FLAG<0>
                                                       I_FX2_FLAG<0>
                                                       I_FX2_FLAG_0_IBUF
                                                       ProtoComp1504.IMUX.10
    IODELAY_X0Y28.IDATAINnet (fanout=1)        0.168   I_FX2_FLAG_0_IBUF
    IODELAY_X0Y28.DATAOUTTioddo_IDATAIN        2.150   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0_ML_IODELAY2
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0_ML_IODELAY2
    ILOGIC_X0Y28.DDLY    net (fanout=1)        0.007   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0_ML_IODELAY2_SIG_ML
    ILOGIC_X0Y28.CLK0    Tiockdd     (-Th)    -0.257   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<0>
                                                       ProtoComp1594.D2OFFBYP_SRC
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0
    -------------------------------------------------  ---------------------------
    Total                                      3.926ns (3.751ns logic, 0.175ns route)
                                                       (95.5% logic, 4.5% route)

  Maximum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y28.CLK0    net (fanout=51)       1.709   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.481ns (1.766ns logic, 2.715ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = OUT 10 ns VALID 33 ns AFTER COMP "I_FX2_IFCLK";
For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612).

 22 paths analyzed, 14 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
 Minimum allowable offset is   7.872ns.
--------------------------------------------------------------------------------
Slack (slowest paths):  2.128ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO_0 (FF)
  Destination:          O_FX2_SLWR_N (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      3.372ns (Levels of Logic = 1)
  Clock Path Delay:     4.475ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    OLOGIC_X0Y60.CLK0    net (fanout=51)       1.703   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.475ns (1.766ns logic, 2.709ns route)
                                                       (39.5% logic, 60.5% route)

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO_0 to O_FX2_SLWR_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X0Y60.OQ      Tockq                 1.080   RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO
                                                       RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO_0
    C1.O                 net (fanout=1)        0.310   RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO
    C1.PAD               Tioop                 1.982   O_FX2_SLWR_N
                                                       O_FX2_SLWR_N_OBUF
                                                       O_FX2_SLWR_N
    -------------------------------------------------  ---------------------------
    Total                                      3.372ns (3.062ns logic, 0.310ns route)
                                                       (90.8% logic, 9.2% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  2.128ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0 (FF)
  Destination:          O_FX2_SLRD_N (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      3.372ns (Levels of Logic = 1)
  Clock Path Delay:     4.475ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    OLOGIC_X0Y61.CLK0    net (fanout=51)       1.703   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.475ns (1.766ns logic, 2.709ns route)
                                                       (39.5% logic, 60.5% route)

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0 to O_FX2_SLRD_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X0Y61.OQ      Tockq                 1.080   RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO
                                                       RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0
    C2.O                 net (fanout=1)        0.310   RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO
    C2.PAD               Tioop                 1.982   O_FX2_SLRD_N
                                                       O_FX2_SLRD_N_OBUF
                                                       O_FX2_SLRD_N
    -------------------------------------------------  ---------------------------
    Total                                      3.372ns (3.062ns logic, 0.310ns route)
                                                       (90.8% logic, 9.2% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  2.133ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               RLINK/FX2CNTL/IOB_FX2_SLOE/IOB/R_DO_0 (FF)
  Destination:          O_FX2_SLOE_N (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      3.372ns (Levels of Logic = 1)
  Clock Path Delay:     4.470ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_SLOE/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    OLOGIC_X0Y45.CLK0    net (fanout=51)       1.698   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.470ns (1.766ns logic, 2.704ns route)
                                                       (39.5% logic, 60.5% route)

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/IOB_FX2_SLOE/IOB/R_DO_0 to O_FX2_SLOE_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X0Y45.OQ      Tockq                 1.080   RLINK/FX2CNTL/IOB_FX2_SLOE/IOB/R_DO
                                                       RLINK/FX2CNTL/IOB_FX2_SLOE/IOB/R_DO_0
    H6.O                 net (fanout=1)        0.310   RLINK/FX2CNTL/IOB_FX2_SLOE/IOB/R_DO
    H6.PAD               Tioop                 1.982   O_FX2_SLOE_N
                                                       O_FX2_SLOE_N_OBUF
                                                       O_FX2_SLOE_N
    -------------------------------------------------  ---------------------------
    Total                                      3.372ns (3.062ns logic, 0.310ns route)
                                                       (90.8% logic, 9.2% route)

--------------------------------------------------------------------------------

Fastest Paths: OFFSET = OUT 10 ns VALID 33 ns AFTER COMP "I_FX2_IFCLK";
--------------------------------------------------------------------------------
Delay (fastest paths):  2.895ns (clock arrival + clock path + data path - uncertainty)
  Source:               RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3 (FF)
  Destination:          IO_FX2_DATA<3> (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Data Path Delay:      1.226ns (Levels of Logic = 1)
  Clock Path Delay:     1.694ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Clock Path at Fast Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 0.763   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.272   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.059   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    OLOGIC_X0Y51.CLK0    net (fanout=51)       0.600   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      1.694ns (0.822ns logic, 0.872ns route)
                                                       (48.5% logic, 51.5% route)

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3 to IO_FX2_DATA<3>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X0Y51.OQ      Tockq                 0.336   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<3>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    D2.O                 net (fanout=1)        0.191   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<3>
    D2.PAD               Tioop                 0.699   IO_FX2_DATA<3>
                                                       IO_FX2_DATA_3_IOBUF/OBUFT
                                                       IO_FX2_DATA<3>
    -------------------------------------------------  ---------------------------
    Total                                      1.226ns (1.035ns logic, 0.191ns route)
                                                       (84.4% logic, 15.6% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  2.894ns (clock arrival + clock path + data path - uncertainty)
  Source:               RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5 (FF)
  Destination:          IO_FX2_DATA<5> (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Data Path Delay:      1.226ns (Levels of Logic = 1)
  Clock Path Delay:     1.693ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Clock Path at Fast Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 0.763   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.272   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.059   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    OLOGIC_X0Y53.CLK0    net (fanout=51)       0.599   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      1.693ns (0.822ns logic, 0.871ns route)
                                                       (48.6% logic, 51.4% route)

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5 to IO_FX2_DATA<5>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X0Y53.OQ      Tockq                 0.336   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<5>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    H7.O                 net (fanout=1)        0.191   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<5>
    H7.PAD               Tioop                 0.699   IO_FX2_DATA<5>
                                                       IO_FX2_DATA_5_IOBUF/OBUFT
                                                       IO_FX2_DATA<5>
    -------------------------------------------------  ---------------------------
    Total                                      1.226ns (1.035ns logic, 0.191ns route)
                                                       (84.4% logic, 15.6% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  2.894ns (clock arrival + clock path + data path - uncertainty)
  Source:               RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6 (FF)
  Destination:          IO_FX2_DATA<6> (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Data Path Delay:      1.226ns (Levels of Logic = 1)
  Clock Path Delay:     1.693ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Clock Path at Fast Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 0.763   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1504.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.272   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.059   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    OLOGIC_X0Y52.CLK0    net (fanout=51)       0.599   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      1.693ns (0.822ns logic, 0.871ns route)
                                                       (48.6% logic, 51.4% route)

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6 to IO_FX2_DATA<6>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X0Y52.OQ      Tockq                 0.336   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<6>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    G6.O                 net (fanout=1)        0.191   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<6>
    G6.PAD               Tioop                 0.699   IO_FX2_DATA<6>
                                                       IO_FX2_DATA_6_IOBUF/OBUFT
                                                       IO_FX2_DATA<6>
    -------------------------------------------------  ---------------------------
    Total                                      1.226ns (1.035ns logic, 0.191ns route)
                                                       (84.4% logic, 15.6% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: Unconstrained path analysis 

 250 paths analyzed, 74 endpoints analyzed, 14 failing endpoints
 14 timing errors detected. (0 setup errors, 14 hold errors)
 Minimum period is   8.343ns.
--------------------------------------------------------------------------------
Delay (setup path):     8.343ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6 (FF)
  Data Path Delay:      5.444ns (Levels of Logic = 1)
  Clock Path Skew:      -2.457ns (3.758 - 6.215)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y59.BMUX    Tshcko                1.131   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM1/DP
    SLICE_X15Y58.A4      net (fanout=1)        1.005   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<6>
    SLICE_X15Y58.AMUX    Tilo                  0.337   RLINK/CORE/RL/R_LREGS_state_proc_lnext.n_nakcode<1>4
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB71
    OLOGIC_X0Y52.D1      net (fanout=1)        1.793   RLINK/FX2CNTL/TXFIFO_DO<6>
    OLOGIC_X0Y52.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<6>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    -------------------------------------------------  ---------------------------
    Total                                      5.444ns (2.646ns logic, 2.798ns route)
                                                       (48.6% logic, 51.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.098ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5 (FF)
  Data Path Delay:      5.199ns (Levels of Logic = 1)
  Clock Path Skew:      -2.457ns (3.758 - 6.215)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y59.A       Tshcko                1.012   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM1/DP
    SLICE_X15Y59.B2      net (fanout=1)        1.259   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<5>
    SLICE_X15Y59.B       Tilo                  0.259   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB61
    OLOGIC_X0Y53.D1      net (fanout=1)        1.491   RLINK/FX2CNTL/TXFIFO_DO<5>
    OLOGIC_X0Y53.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<5>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    -------------------------------------------------  ---------------------------
    Total                                      5.199ns (2.449ns logic, 2.750ns route)
                                                       (47.1% logic, 52.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.097ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7 (FF)
  Data Path Delay:      5.203ns (Levels of Logic = 1)
  Clock Path Skew:      -2.452ns (3.763 - 6.215)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y59.B       Tshcko                1.106   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM1/DP
    SLICE_X15Y58.A1      net (fanout=1)        1.194   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
    SLICE_X15Y58.A       Tilo                  0.259   RLINK/CORE/RL/R_LREGS_state_proc_lnext.n_nakcode<1>4
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB81
    OLOGIC_X0Y55.D1      net (fanout=1)        1.466   RLINK/FX2CNTL/TXFIFO_DO<7>
    OLOGIC_X0Y55.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<7>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    -------------------------------------------------  ---------------------------
    Total                                      5.203ns (2.543ns logic, 2.660ns route)
                                                       (48.9% logic, 51.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.991ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4 (FF)
  Data Path Delay:      5.086ns (Levels of Logic = 1)
  Clock Path Skew:      -2.463ns (3.759 - 6.222)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y59.AMUX    Tshcko                1.081   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X15Y59.B3      net (fanout=1)        0.986   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X15Y59.BMUX    Tilo                  0.337   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB51
    OLOGIC_X0Y50.D1      net (fanout=1)        1.504   RLINK/FX2CNTL/TXFIFO_DO<4>
    OLOGIC_X0Y50.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<4>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    -------------------------------------------------  ---------------------------
    Total                                      5.086ns (2.596ns logic, 2.490ns route)
                                                       (51.0% logic, 49.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.885ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4 (FF)
  Data Path Delay:      4.987ns (Levels of Logic = 1)
  Clock Path Skew:      -2.456ns (3.759 - 6.215)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y59.AMUX    Tshcko                1.081   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X15Y59.B4      net (fanout=1)        0.887   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X15Y59.BMUX    Tilo                  0.337   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB51
    OLOGIC_X0Y50.D1      net (fanout=1)        1.504   RLINK/FX2CNTL/TXFIFO_DO<4>
    OLOGIC_X0Y50.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<4>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    -------------------------------------------------  ---------------------------
    Total                                      4.987ns (2.596ns logic, 2.391ns route)
                                                       (52.1% logic, 47.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.862ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3 (FF)
  Data Path Delay:      4.951ns (Levels of Logic = 1)
  Clock Path Skew:      -2.469ns (3.759 - 6.228)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y58.B       Tshcko                1.106   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X10Y57.C1      net (fanout=1)        1.102   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X10Y57.C       Tilo                  0.255   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB41
    OLOGIC_X0Y51.D1      net (fanout=1)        1.310   RLINK/FX2CNTL/TXFIFO_DO<3>
    OLOGIC_X0Y51.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<3>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    -------------------------------------------------  ---------------------------
    Total                                      4.951ns (2.539ns logic, 2.412ns route)
                                                       (51.3% logic, 48.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.783ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6 (FF)
  Data Path Delay:      4.877ns (Levels of Logic = 1)
  Clock Path Skew:      -2.464ns (3.758 - 6.222)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y59.BMUX    Tshcko                1.131   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X15Y58.A5      net (fanout=1)        0.438   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X15Y58.AMUX    Tilo                  0.337   RLINK/CORE/RL/R_LREGS_state_proc_lnext.n_nakcode<1>4
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB71
    OLOGIC_X0Y52.D1      net (fanout=1)        1.793   RLINK/FX2CNTL/TXFIFO_DO<6>
    OLOGIC_X0Y52.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<6>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    -------------------------------------------------  ---------------------------
    Total                                      4.877ns (2.646ns logic, 2.231ns route)
                                                       (54.3% logic, 45.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.703ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1 (FF)
  Data Path Delay:      4.791ns (Levels of Logic = 1)
  Clock Path Skew:      -2.470ns (3.761 - 6.231)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y59.A       Tshcko                1.012   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X9Y57.D2       net (fanout=1)        1.079   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X9Y57.D        Tilo                  0.259   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB21
    OLOGIC_X0Y49.D1      net (fanout=1)        1.263   RLINK/FX2CNTL/TXFIFO_DO<1>
    OLOGIC_X0Y49.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<1>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    -------------------------------------------------  ---------------------------
    Total                                      4.791ns (2.449ns logic, 2.342ns route)
                                                       (51.1% logic, 48.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.636ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7 (FF)
  Data Path Delay:      4.735ns (Levels of Logic = 1)
  Clock Path Skew:      -2.459ns (3.763 - 6.222)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y59.B       Tshcko                1.106   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM0/DP
    SLICE_X15Y58.A2      net (fanout=1)        0.726   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
    SLICE_X15Y58.A       Tilo                  0.259   RLINK/CORE/RL/R_LREGS_state_proc_lnext.n_nakcode<1>4
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB81
    OLOGIC_X0Y55.D1      net (fanout=1)        1.466   RLINK/FX2CNTL/TXFIFO_DO<7>
    OLOGIC_X0Y55.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<7>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    -------------------------------------------------  ---------------------------
    Total                                      4.735ns (2.543ns logic, 2.192ns route)
                                                       (53.7% logic, 46.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.627ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2 (FF)
  Data Path Delay:      4.715ns (Levels of Logic = 1)
  Clock Path Skew:      -2.470ns (3.761 - 6.231)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y59.BMUX    Tshcko                1.131   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X10Y57.C2      net (fanout=1)        0.750   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X10Y57.CMUX    Tilo                  0.326   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB31
    OLOGIC_X0Y48.D1      net (fanout=1)        1.330   RLINK/FX2CNTL/TXFIFO_DO<2>
    OLOGIC_X0Y48.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<2>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2
    -------------------------------------------------  ---------------------------
    Total                                      4.715ns (2.635ns logic, 2.080ns route)
                                                       (55.9% logic, 44.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.536ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0 (FF)
  Data Path Delay:      4.630ns (Levels of Logic = 1)
  Clock Path Skew:      -2.464ns (3.764 - 6.228)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y58.AMUX    Tshcko                1.081   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X9Y57.D1       net (fanout=1)        0.791   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X9Y57.DMUX     Tilo                  0.337   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB11
    OLOGIC_X0Y46.D1      net (fanout=1)        1.243   RLINK/FX2CNTL/TXFIFO_DO<0>
    OLOGIC_X0Y46.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<0>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    -------------------------------------------------  ---------------------------
    Total                                      4.630ns (2.596ns logic, 2.034ns route)
                                                       (56.1% logic, 43.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.460ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2 (FF)
  Data Path Delay:      4.551ns (Levels of Logic = 1)
  Clock Path Skew:      -2.467ns (3.761 - 6.228)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y58.BMUX    Tshcko                1.131   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X10Y57.C3      net (fanout=1)        0.586   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X10Y57.CMUX    Tilo                  0.326   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB31
    OLOGIC_X0Y48.D1      net (fanout=1)        1.330   RLINK/FX2CNTL/TXFIFO_DO<2>
    OLOGIC_X0Y48.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<2>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2
    -------------------------------------------------  ---------------------------
    Total                                      4.551ns (2.635ns logic, 1.916ns route)
                                                       (57.9% logic, 42.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.425ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0 (FF)
  Data Path Delay:      4.516ns (Levels of Logic = 1)
  Clock Path Skew:      -2.467ns (3.764 - 6.231)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y59.AMUX    Tshcko                1.081   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X9Y57.D5       net (fanout=1)        0.677   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X9Y57.DMUX     Tilo                  0.337   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB11
    OLOGIC_X0Y46.D1      net (fanout=1)        1.243   RLINK/FX2CNTL/TXFIFO_DO<0>
    OLOGIC_X0Y46.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<0>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    -------------------------------------------------  ---------------------------
    Total                                      4.516ns (2.596ns logic, 1.920ns route)
                                                       (57.5% logic, 42.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.367ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5 (FF)
  Data Path Delay:      4.461ns (Levels of Logic = 1)
  Clock Path Skew:      -2.464ns (3.758 - 6.222)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y59.A       Tshcko                1.012   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X15Y59.B1      net (fanout=1)        0.521   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X15Y59.B       Tilo                  0.259   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB61
    OLOGIC_X0Y53.D1      net (fanout=1)        1.491   RLINK/FX2CNTL/TXFIFO_DO<5>
    OLOGIC_X0Y53.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<5>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    -------------------------------------------------  ---------------------------
    Total                                      4.461ns (2.449ns logic, 2.012ns route)
                                                       (54.9% logic, 45.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.308ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3 (FF)
  Data Path Delay:      4.394ns (Levels of Logic = 1)
  Clock Path Skew:      -2.472ns (3.759 - 6.231)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y59.B       Tshcko                1.106   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM1/DP
    SLICE_X10Y57.C4      net (fanout=1)        0.545   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
    SLICE_X10Y57.C       Tilo                  0.255   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB41
    OLOGIC_X0Y51.D1      net (fanout=1)        1.310   RLINK/FX2CNTL/TXFIFO_DO<3>
    OLOGIC_X0Y51.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<3>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    -------------------------------------------------  ---------------------------
    Total                                      4.394ns (2.539ns logic, 1.855ns route)
                                                       (57.8% logic, 42.2% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.247ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1 (FF)
  Data Path Delay:      4.338ns (Levels of Logic = 1)
  Clock Path Skew:      -2.467ns (3.761 - 6.228)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y58.A       Tshcko                1.012   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X9Y57.D3       net (fanout=1)        0.626   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X9Y57.D        Tilo                  0.259   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB21
    OLOGIC_X0Y49.D1      net (fanout=1)        1.263   RLINK/FX2CNTL/TXFIFO_DO<1>
    OLOGIC_X0Y49.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<1>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    -------------------------------------------------  ---------------------------
    Total                                      4.338ns (2.449ns logic, 1.889ns route)
                                                       (56.5% logic, 43.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.330ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      7.173ns (Levels of Logic = 5)
  Clock Path Skew:      1.285ns (5.177 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X7Y56.B1       net (fanout=1)        1.406   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X7Y56.B        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.520   N0
    SLICE_X8Y56.B        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X11Y59.C4      net (fanout=6)        0.802   RLINK/RLB_DI<0>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.A1      net (fanout=6)        1.168   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      7.173ns (2.442ns logic, 4.731ns route)
                                                       (34.0% logic, 66.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.266ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.266ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y8.CLKB     net (fanout=1212)     1.132   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.266ns (2.356ns logic, 3.910ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.266ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.266ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y16.CLKB    net (fanout=1212)     1.132   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.266ns (2.356ns logic, 3.910ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.266ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.266ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y8.CLKA     net (fanout=1212)     1.132   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.266ns (2.356ns logic, 3.910ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.266ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.266ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y16.CLKA    net (fanout=1212)     1.132   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.266ns (2.356ns logic, 3.910ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.265ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.265ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y6.CLKA     net (fanout=1212)     1.131   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.265ns (2.356ns logic, 3.909ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.265ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/W11A/SEQ_Mram__n3279 (RAM)
  Data Path Delay:      6.265ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/W11A/SEQ_Mram__n3279
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y14.CLKA    net (fanout=1212)     1.131   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.265ns (2.356ns logic, 3.909ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.265ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.265ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y6.CLKB     net (fanout=1212)     1.131   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.265ns (2.356ns logic, 3.909ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.264ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/DMSCNT.I0/CMEM/UMEM/AW_09_S36.GL[0].MEM (RAM)
  Data Path Delay:      6.264ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/DMSCNT.I0/CMEM/UMEM/AW_09_S36.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y16.CLKA    net (fanout=1212)     1.130   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.264ns (2.356ns logic, 3.908ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.264ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/DMSCNT.I0/CMEM/UMEM/AW_09_S36.GL[0].MEM (RAM)
  Data Path Delay:      6.264ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/DMSCNT.I0/CMEM/UMEM/AW_09_S36.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y16.CLKB    net (fanout=1212)     1.130   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.264ns (2.356ns logic, 3.908ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.263ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/DMCMON.I0/BRAM1/UMEM/AW_09_S36.GL[0].MEM (RAM)
  Data Path Delay:      6.263ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/DMCMON.I0/BRAM1/UMEM/AW_09_S36.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y14.CLKA    net (fanout=1212)     1.129   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.263ns (2.356ns logic, 3.907ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.263ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/DMCMON.I0/BRAM1/UMEM/AW_09_S36.GL[0].MEM (RAM)
  Data Path Delay:      6.263ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/DMCMON.I0/BRAM1/UMEM/AW_09_S36.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y14.CLKB    net (fanout=1212)     1.129   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.263ns (2.356ns logic, 3.907ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.259ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[0].MEM (RAM)
  Data Path Delay:      6.259ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y26.CLKB    net (fanout=1212)     1.125   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.259ns (2.356ns logic, 3.903ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.259ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM (RAM)
  Data Path Delay:      6.259ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y18.CLKA    net (fanout=1212)     1.125   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.259ns (2.356ns logic, 3.903ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.259ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_DAT2/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.259ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_DAT2/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y10.CLKA    net (fanout=1212)     1.125   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.259ns (2.356ns logic, 3.903ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.259ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_DAT2/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.259ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_DAT2/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y10.CLKB    net (fanout=1212)     1.125   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.259ns (2.356ns logic, 3.903ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.259ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[0].MEM (RAM)
  Data Path Delay:      6.259ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y26.CLKA    net (fanout=1212)     1.125   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.259ns (2.356ns logic, 3.903ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.257ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[1].MEM (RAM)
  Data Path Delay:      6.257ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[1].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y28.CLKB    net (fanout=1212)     1.123   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.257ns (2.356ns logic, 3.901ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.257ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[1].MEM (RAM)
  Data Path Delay:      6.257ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[1].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y28.CLKA    net (fanout=1212)     1.123   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.257ns (2.356ns logic, 3.901ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.257ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          RLINK/RBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM (RAM)
  Data Path Delay:      6.257ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to RLINK/RBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y18.CLKA    net (fanout=1212)     1.123   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.257ns (2.356ns logic, 3.901ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.256ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/IBMON.I0/BRAM1/UMEM/AW_09_S32.GL[0].MEM (RAM)
  Data Path Delay:      6.256ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/IBMON.I0/BRAM1/UMEM/AW_09_S32.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y20.CLKA    net (fanout=1212)     1.122   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.256ns (2.356ns logic, 3.900ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.256ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_DAT0/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.256ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_DAT0/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y12.CLKB    net (fanout=1212)     1.122   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.256ns (2.356ns logic, 3.900ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.256ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_DAT0/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.256ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_DAT0/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y12.CLKA    net (fanout=1212)     1.122   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.256ns (2.356ns logic, 3.900ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.254ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/DMCMON.I0/BRAM0/UMEM/AW_09_S36.GL[0].MEM (RAM)
  Data Path Delay:      6.254ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/DMCMON.I0/BRAM0/UMEM/AW_09_S36.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y12.CLKA    net (fanout=1212)     1.120   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.254ns (2.356ns logic, 3.898ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.254ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          RLINK/RBMON.I0/BRAM1/UMEM/AW_09_S32.GL[0].MEM (RAM)
  Data Path Delay:      6.254ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to RLINK/RBMON.I0/BRAM1/UMEM/AW_09_S32.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y20.CLKA    net (fanout=1212)     1.120   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.254ns (2.356ns logic, 3.898ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.254ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/DMCMON.I0/BRAM0/UMEM/AW_09_S36.GL[0].MEM (RAM)
  Data Path Delay:      6.254ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/DMCMON.I0/BRAM0/UMEM/AW_09_S36.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y12.CLKB    net (fanout=1212)     1.120   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.254ns (2.356ns logic, 3.898ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.252ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/W11A/DPATH/MUNIT/Mmult_proc_omux.prod (DSP)
  Data Path Delay:      6.252ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/W11A/DPATH/MUNIT/Mmult_proc_omux.prod
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1504.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    DSP48_X1Y3.CLK       net (fanout=1212)     1.118   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.252ns (2.356ns logic, 3.896ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.159ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Data Path Delay:      7.008ns (Levels of Logic = 5)
  Clock Path Skew:      1.291ns (5.183 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.BMUX     Tshcko                1.131   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X5Y56.B1       net (fanout=1)        1.146   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X5Y56.BMUX     Tilo                  0.337   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.684   N4
    SLICE_X9Y56.A        Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X11Y59.C2      net (fanout=10)       1.161   RLINK/RLB_DI<2>
    SLICE_X11Y59.CMUX    Tilo                  0.337   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o_SW0
    SLICE_X8Y59.D1       net (fanout=1)        0.938   N40
    SLICE_X8Y59.D        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.C5       net (fanout=1)        0.431   RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      7.008ns (2.648ns logic, 4.360ns route)
                                                       (37.8% logic, 62.2% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.140ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      6.983ns (Levels of Logic = 5)
  Clock Path Skew:      1.285ns (5.177 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP
    SLICE_X7Y56.B3       net (fanout=1)        0.934   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
    SLICE_X7Y56.BMUX     Tilo                  0.337   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.358   N6
    SLICE_X7Y56.A        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X11Y59.C3      net (fanout=3)        1.119   RLINK/RLB_DI<3>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.A1      net (fanout=6)        1.168   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      6.983ns (2.569ns logic, 4.414ns route)
                                                       (36.8% logic, 63.2% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.111ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      6.954ns (Levels of Logic = 5)
  Clock Path Skew:      1.285ns (5.177 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X5Y56.B2       net (fanout=1)        1.192   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X5Y56.B        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.230   N2
    SLICE_X5Y56.A        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        1.132   RLINK/RLB_DI<1>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.A1      net (fanout=6)        1.168   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      6.954ns (2.397ns logic, 4.557ns route)
                                                       (34.5% logic, 65.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.101ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      6.950ns (Levels of Logic = 5)
  Clock Path Skew:      1.291ns (5.183 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X7Y56.B1       net (fanout=1)        1.406   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X7Y56.B        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.520   N0
    SLICE_X8Y56.B        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X11Y59.C4      net (fanout=6)        0.802   RLINK/RLB_DI<0>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.B1       net (fanout=6)        0.945   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      6.950ns (2.442ns logic, 4.508ns route)
                                                       (35.1% logic, 64.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.971ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      6.820ns (Levels of Logic = 5)
  Clock Path Skew:      1.291ns (5.183 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X7Y56.B1       net (fanout=1)        1.406   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X7Y56.B        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.520   N0
    SLICE_X8Y56.B        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X11Y59.C4      net (fanout=6)        0.802   RLINK/RLB_DI<0>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.D3       net (fanout=6)        0.815   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      6.820ns (2.442ns logic, 4.378ns route)
                                                       (35.8% logic, 64.2% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.911ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      6.760ns (Levels of Logic = 5)
  Clock Path Skew:      1.291ns (5.183 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP
    SLICE_X7Y56.B3       net (fanout=1)        0.934   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
    SLICE_X7Y56.BMUX     Tilo                  0.337   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.358   N6
    SLICE_X7Y56.A        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X11Y59.C3      net (fanout=3)        1.119   RLINK/RLB_DI<3>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.B1       net (fanout=6)        0.945   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      6.760ns (2.569ns logic, 4.191ns route)
                                                       (38.0% logic, 62.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.904ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      6.759ns (Levels of Logic = 5)
  Clock Path Skew:      1.297ns (5.177 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.997   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.230   N2
    SLICE_X5Y56.A        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        1.132   RLINK/RLB_DI<1>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.A1      net (fanout=6)        1.168   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      6.759ns (2.397ns logic, 4.362ns route)
                                                       (35.5% logic, 64.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.882ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      6.731ns (Levels of Logic = 5)
  Clock Path Skew:      1.291ns (5.183 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X5Y56.B2       net (fanout=1)        1.192   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X5Y56.B        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.230   N2
    SLICE_X5Y56.A        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        1.132   RLINK/RLB_DI<1>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.B1       net (fanout=6)        0.945   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      6.731ns (2.397ns logic, 4.334ns route)
                                                       (35.6% logic, 64.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.781ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      6.630ns (Levels of Logic = 5)
  Clock Path Skew:      1.291ns (5.183 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP
    SLICE_X7Y56.B3       net (fanout=1)        0.934   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
    SLICE_X7Y56.BMUX     Tilo                  0.337   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.358   N6
    SLICE_X7Y56.A        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X11Y59.C3      net (fanout=3)        1.119   RLINK/RLB_DI<3>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.D3       net (fanout=6)        0.815   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      6.630ns (2.569ns logic, 4.061ns route)
                                                       (38.7% logic, 61.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.752ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      6.601ns (Levels of Logic = 5)
  Clock Path Skew:      1.291ns (5.183 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X5Y56.B2       net (fanout=1)        1.192   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X5Y56.B        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.230   N2
    SLICE_X5Y56.A        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        1.132   RLINK/RLB_DI<1>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.D3       net (fanout=6)        0.815   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      6.601ns (2.397ns logic, 4.204ns route)
                                                       (36.3% logic, 63.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.749ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      6.582ns (Levels of Logic = 5)
  Clock Path Skew:      1.275ns (5.177 - 3.902)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X8Y60.B4       net (fanout=1)        0.949   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X8Y60.B        Tilo                  0.235   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.414   N8
    SLICE_X9Y59.A        Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X11Y59.C1      net (fanout=4)        0.774   RLINK/RLB_DI<4>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.A1      net (fanout=6)        1.168   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      6.582ns (2.442ns logic, 4.140ns route)
                                                       (37.1% logic, 62.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.744ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Data Path Delay:      6.593ns (Levels of Logic = 5)
  Clock Path Skew:      1.291ns (5.183 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X7Y56.B1       net (fanout=1)        1.406   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X7Y56.B        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.520   N0
    SLICE_X8Y56.B        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X11Y59.C4      net (fanout=6)        0.802   RLINK/RLB_DI<0>
    SLICE_X11Y59.CMUX    Tilo                  0.337   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o_SW0
    SLICE_X8Y59.D1       net (fanout=1)        0.938   N40
    SLICE_X8Y59.D        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.C5       net (fanout=1)        0.431   RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      6.593ns (2.496ns logic, 4.097ns route)
                                                       (37.9% logic, 62.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.705ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Data Path Delay:      6.547ns (Levels of Logic = 5)
  Clock Path Skew:      1.284ns (5.176 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X7Y56.B1       net (fanout=1)        1.406   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X7Y56.B        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.520   N0
    SLICE_X8Y56.B        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X11Y59.C4      net (fanout=6)        0.802   RLINK/RLB_DI<0>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y56.B1       net (fanout=6)        0.542   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y56.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      6.547ns (2.442ns logic, 4.105ns route)
                                                       (37.3% logic, 62.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.698ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Data Path Delay:      6.540ns (Levels of Logic = 5)
  Clock Path Skew:      1.284ns (5.176 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X7Y56.B1       net (fanout=1)        1.406   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X7Y56.B        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.520   N0
    SLICE_X8Y56.B        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X11Y59.C4      net (fanout=6)        0.802   RLINK/RLB_DI<0>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.C1       net (fanout=6)        0.559   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      6.540ns (2.418ns logic, 4.122ns route)
                                                       (37.0% logic, 63.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.675ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      6.536ns (Levels of Logic = 5)
  Clock Path Skew:      1.303ns (5.183 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.997   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.230   N2
    SLICE_X5Y56.A        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        1.132   RLINK/RLB_DI<1>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.B1       net (fanout=6)        0.945   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      6.536ns (2.397ns logic, 4.139ns route)
                                                       (36.7% logic, 63.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.646ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      6.501ns (Levels of Logic = 5)
  Clock Path Skew:      1.297ns (5.177 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X7Y56.B5       net (fanout=1)        0.452   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X7Y56.BMUX     Tilo                  0.337   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.358   N6
    SLICE_X7Y56.A        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X11Y59.C3      net (fanout=3)        1.119   RLINK/RLB_DI<3>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.A1      net (fanout=6)        1.168   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      6.501ns (2.569ns logic, 3.932ns route)
                                                       (39.5% logic, 60.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.638ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Data Path Delay:      6.499ns (Levels of Logic = 5)
  Clock Path Skew:      1.303ns (5.183 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.BMUX     Tshcko                1.131   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X5Y56.B4       net (fanout=1)        0.637   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X5Y56.BMUX     Tilo                  0.337   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.684   N4
    SLICE_X9Y56.A        Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X11Y59.C2      net (fanout=10)       1.161   RLINK/RLB_DI<2>
    SLICE_X11Y59.CMUX    Tilo                  0.337   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o_SW0
    SLICE_X8Y59.D1       net (fanout=1)        0.938   N40
    SLICE_X8Y59.D        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.C5       net (fanout=1)        0.431   RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      6.499ns (2.648ns logic, 3.851ns route)
                                                       (40.7% logic, 59.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.570ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Data Path Delay:      6.412ns (Levels of Logic = 5)
  Clock Path Skew:      1.284ns (5.176 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X7Y56.B1       net (fanout=1)        1.406   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X7Y56.B        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.520   N0
    SLICE_X8Y56.B        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X11Y59.C4      net (fanout=6)        0.802   RLINK/RLB_DI<0>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.C1       net (fanout=6)        0.559   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tas                   0.221   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      6.412ns (2.290ns logic, 4.122ns route)
                                                       (35.7% logic, 64.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.554ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Data Path Delay:      6.403ns (Levels of Logic = 5)
  Clock Path Skew:      1.291ns (5.183 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP
    SLICE_X7Y56.B3       net (fanout=1)        0.934   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
    SLICE_X7Y56.BMUX     Tilo                  0.337   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.358   N6
    SLICE_X7Y56.A        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X11Y59.C3      net (fanout=3)        1.119   RLINK/RLB_DI<3>
    SLICE_X11Y59.CMUX    Tilo                  0.337   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o_SW0
    SLICE_X8Y59.D1       net (fanout=1)        0.938   N40
    SLICE_X8Y59.D        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.C5       net (fanout=1)        0.431   RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      6.403ns (2.623ns logic, 3.780ns route)
                                                       (41.0% logic, 59.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.545ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      6.406ns (Levels of Logic = 5)
  Clock Path Skew:      1.303ns (5.183 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.997   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.230   N2
    SLICE_X5Y56.A        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        1.132   RLINK/RLB_DI<1>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.D3       net (fanout=6)        0.815   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      6.406ns (2.397ns logic, 4.009ns route)
                                                       (37.4% logic, 62.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.525ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Data Path Delay:      6.374ns (Levels of Logic = 5)
  Clock Path Skew:      1.291ns (5.183 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X5Y56.B2       net (fanout=1)        1.192   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X5Y56.B        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.230   N2
    SLICE_X5Y56.A        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        1.132   RLINK/RLB_DI<1>
    SLICE_X11Y59.CMUX    Tilo                  0.337   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o_SW0
    SLICE_X8Y59.D1       net (fanout=1)        0.938   N40
    SLICE_X8Y59.D        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.C5       net (fanout=1)        0.431   RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      6.374ns (2.451ns logic, 3.923ns route)
                                                       (38.5% logic, 61.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.520ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      6.359ns (Levels of Logic = 5)
  Clock Path Skew:      1.281ns (5.183 - 3.902)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X8Y60.B4       net (fanout=1)        0.949   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X8Y60.B        Tilo                  0.235   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.414   N8
    SLICE_X9Y59.A        Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X11Y59.C1      net (fanout=4)        0.774   RLINK/RLB_DI<4>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.B1       net (fanout=6)        0.945   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      6.359ns (2.442ns logic, 3.917ns route)
                                                       (38.4% logic, 61.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.515ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Data Path Delay:      6.357ns (Levels of Logic = 5)
  Clock Path Skew:      1.284ns (5.176 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP
    SLICE_X7Y56.B3       net (fanout=1)        0.934   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
    SLICE_X7Y56.BMUX     Tilo                  0.337   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.358   N6
    SLICE_X7Y56.A        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X11Y59.C3      net (fanout=3)        1.119   RLINK/RLB_DI<3>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y56.B1       net (fanout=6)        0.542   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y56.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      6.357ns (2.569ns logic, 3.788ns route)
                                                       (40.4% logic, 59.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.508ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Data Path Delay:      6.350ns (Levels of Logic = 5)
  Clock Path Skew:      1.284ns (5.176 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP
    SLICE_X7Y56.B3       net (fanout=1)        0.934   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
    SLICE_X7Y56.BMUX     Tilo                  0.337   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.358   N6
    SLICE_X7Y56.A        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X11Y59.C3      net (fanout=3)        1.119   RLINK/RLB_DI<3>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.C1       net (fanout=6)        0.559   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      6.350ns (2.545ns logic, 3.805ns route)
                                                       (40.1% logic, 59.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.506ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      6.361ns (Levels of Logic = 5)
  Clock Path Skew:      1.297ns (5.177 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X7Y56.B4       net (fanout=1)        0.594   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X7Y56.B        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.520   N0
    SLICE_X8Y56.B        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X11Y59.C4      net (fanout=6)        0.802   RLINK/RLB_DI<0>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.A1      net (fanout=6)        1.168   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      6.361ns (2.442ns logic, 3.919ns route)
                                                       (38.4% logic, 61.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.502ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Data Path Delay:      6.344ns (Levels of Logic = 5)
  Clock Path Skew:      1.284ns (5.176 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X7Y56.B1       net (fanout=1)        1.406   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X7Y56.B        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.520   N0
    SLICE_X8Y56.B        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X11Y59.C4      net (fanout=6)        0.802   RLINK/RLB_DI<0>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.D3       net (fanout=6)        0.363   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      6.344ns (2.418ns logic, 3.926ns route)
                                                       (38.1% logic, 61.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.486ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Data Path Delay:      6.328ns (Levels of Logic = 5)
  Clock Path Skew:      1.284ns (5.176 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X5Y56.B2       net (fanout=1)        1.192   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X5Y56.B        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.230   N2
    SLICE_X5Y56.A        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        1.132   RLINK/RLB_DI<1>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y56.B1       net (fanout=6)        0.542   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y56.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      6.328ns (2.397ns logic, 3.931ns route)
                                                       (37.9% logic, 62.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.479ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Data Path Delay:      6.321ns (Levels of Logic = 5)
  Clock Path Skew:      1.284ns (5.176 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X5Y56.B2       net (fanout=1)        1.192   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X5Y56.B        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.230   N2
    SLICE_X5Y56.A        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        1.132   RLINK/RLB_DI<1>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.C1       net (fanout=6)        0.559   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      6.321ns (2.373ns logic, 3.948ns route)
                                                       (37.5% logic, 62.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.417ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      6.278ns (Levels of Logic = 5)
  Clock Path Skew:      1.303ns (5.183 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X7Y56.B5       net (fanout=1)        0.452   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X7Y56.BMUX     Tilo                  0.337   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.358   N6
    SLICE_X7Y56.A        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X11Y59.C3      net (fanout=3)        1.119   RLINK/RLB_DI<3>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.B1       net (fanout=6)        0.945   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      6.278ns (2.569ns logic, 3.709ns route)
                                                       (40.9% logic, 59.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.397ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      6.263ns (Levels of Logic = 5)
  Clock Path Skew:      1.308ns (5.177 - 3.869)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X8Y60.B3       net (fanout=1)        0.630   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X8Y60.B        Tilo                  0.235   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.414   N8
    SLICE_X9Y59.A        Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X11Y59.C1      net (fanout=4)        0.774   RLINK/RLB_DI<4>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.A1      net (fanout=6)        1.168   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      6.263ns (2.442ns logic, 3.821ns route)
                                                       (39.0% logic, 61.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.390ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      6.229ns (Levels of Logic = 5)
  Clock Path Skew:      1.281ns (5.183 - 3.902)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X8Y60.B4       net (fanout=1)        0.949   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X8Y60.B        Tilo                  0.235   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.414   N8
    SLICE_X9Y59.A        Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X11Y59.C1      net (fanout=4)        0.774   RLINK/RLB_DI<4>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.D3       net (fanout=6)        0.815   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      6.229ns (2.442ns logic, 3.787ns route)
                                                       (39.2% logic, 60.8% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.383ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      6.216ns (Levels of Logic = 4)
  Clock Path Skew:      1.275ns (5.177 - 3.902)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP
    SLICE_X11Y60.C5      net (fanout=1)        1.067   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
    SLICE_X11Y60.CMUX    Tilo                  0.337   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X11Y60.A5      net (fanout=1)        0.852   N14
    SLICE_X11Y60.A       Tilo                  0.259   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X8Y56.A3       net (fanout=5)        0.819   RLINK/RLB_DI<7>
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.A1      net (fanout=6)        1.168   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      6.216ns (2.310ns logic, 3.906ns route)
                                                       (37.2% logic, 62.8% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.380ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Data Path Delay:      6.222ns (Levels of Logic = 5)
  Clock Path Skew:      1.284ns (5.176 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP
    SLICE_X7Y56.B3       net (fanout=1)        0.934   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
    SLICE_X7Y56.BMUX     Tilo                  0.337   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.358   N6
    SLICE_X7Y56.A        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X11Y59.C3      net (fanout=3)        1.119   RLINK/RLB_DI<3>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.C1       net (fanout=6)        0.559   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tas                   0.221   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      6.222ns (2.417ns logic, 3.805ns route)
                                                       (38.8% logic, 61.2% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.351ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Data Path Delay:      6.193ns (Levels of Logic = 5)
  Clock Path Skew:      1.284ns (5.176 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X5Y56.B2       net (fanout=1)        1.192   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X5Y56.B        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.230   N2
    SLICE_X5Y56.A        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        1.132   RLINK/RLB_DI<1>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.C1       net (fanout=6)        0.559   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tas                   0.221   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      6.193ns (2.245ns logic, 3.948ns route)
                                                       (36.3% logic, 63.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.318ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Data Path Delay:      6.179ns (Levels of Logic = 5)
  Clock Path Skew:      1.303ns (5.183 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.997   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.230   N2
    SLICE_X5Y56.A        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        1.132   RLINK/RLB_DI<1>
    SLICE_X11Y59.CMUX    Tilo                  0.337   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o_SW0
    SLICE_X8Y59.D1       net (fanout=1)        0.938   N40
    SLICE_X8Y59.D        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.C5       net (fanout=1)        0.431   RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      6.179ns (2.451ns logic, 3.728ns route)
                                                       (39.7% logic, 60.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.312ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Data Path Delay:      6.154ns (Levels of Logic = 5)
  Clock Path Skew:      1.284ns (5.176 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP
    SLICE_X7Y56.B3       net (fanout=1)        0.934   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
    SLICE_X7Y56.BMUX     Tilo                  0.337   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.358   N6
    SLICE_X7Y56.A        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X11Y59.C3      net (fanout=3)        1.119   RLINK/RLB_DI<3>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.D3       net (fanout=6)        0.363   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      6.154ns (2.545ns logic, 3.609ns route)
                                                       (41.4% logic, 58.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.287ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      6.148ns (Levels of Logic = 5)
  Clock Path Skew:      1.303ns (5.183 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X7Y56.B5       net (fanout=1)        0.452   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X7Y56.BMUX     Tilo                  0.337   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.358   N6
    SLICE_X7Y56.A        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X11Y59.C3      net (fanout=3)        1.119   RLINK/RLB_DI<3>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.D3       net (fanout=6)        0.815   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      6.148ns (2.569ns logic, 3.579ns route)
                                                       (41.8% logic, 58.2% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.283ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Data Path Delay:      6.125ns (Levels of Logic = 5)
  Clock Path Skew:      1.284ns (5.176 - 3.892)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X5Y56.B2       net (fanout=1)        1.192   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X5Y56.B        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.230   N2
    SLICE_X5Y56.A        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        1.132   RLINK/RLB_DI<1>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.D3       net (fanout=6)        0.363   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      6.125ns (2.373ns logic, 3.752ns route)
                                                       (38.7% logic, 61.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.279ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Data Path Delay:      6.133ns (Levels of Logic = 5)
  Clock Path Skew:      1.296ns (5.176 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.997   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.230   N2
    SLICE_X5Y56.A        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        1.132   RLINK/RLB_DI<1>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y56.B1       net (fanout=6)        0.542   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y56.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      6.133ns (2.397ns logic, 3.736ns route)
                                                       (39.1% logic, 60.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.277ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      6.138ns (Levels of Logic = 5)
  Clock Path Skew:      1.303ns (5.183 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X7Y56.B4       net (fanout=1)        0.594   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X7Y56.B        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.520   N0
    SLICE_X8Y56.B        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X11Y59.C4      net (fanout=6)        0.802   RLINK/RLB_DI<0>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.B1       net (fanout=6)        0.945   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      6.138ns (2.442ns logic, 3.696ns route)
                                                       (39.8% logic, 60.2% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.272ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Data Path Delay:      6.126ns (Levels of Logic = 5)
  Clock Path Skew:      1.296ns (5.176 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.997   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.230   N2
    SLICE_X5Y56.A        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        1.132   RLINK/RLB_DI<1>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.C1       net (fanout=6)        0.559   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      6.126ns (2.373ns logic, 3.753ns route)
                                                       (38.7% logic, 61.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.174ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      6.007ns (Levels of Logic = 4)
  Clock Path Skew:      1.275ns (5.177 - 3.902)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP
    SLICE_X8Y60.B5       net (fanout=1)        1.047   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<5>
    SLICE_X8Y60.BMUX     Tilo                  0.298   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X8Y60.A5       net (fanout=2)        0.433   N10
    SLICE_X8Y60.A        Tilo                  0.235   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X8Y56.A2       net (fanout=4)        1.206   RLINK/RLB_DI<5>
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.A1      net (fanout=6)        1.168   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      6.007ns (2.153ns logic, 3.854ns route)
                                                       (35.8% logic, 64.2% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.168ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      6.040ns (Levels of Logic = 5)
  Clock Path Skew:      1.314ns (5.183 - 3.869)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X8Y60.B3       net (fanout=1)        0.630   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X8Y60.B        Tilo                  0.235   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.414   N8
    SLICE_X9Y59.A        Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X11Y59.C1      net (fanout=4)        0.774   RLINK/RLB_DI<4>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.B1       net (fanout=6)        0.945   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      6.040ns (2.442ns logic, 3.598ns route)
                                                       (40.4% logic, 59.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.154ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      5.993ns (Levels of Logic = 4)
  Clock Path Skew:      1.281ns (5.183 - 3.902)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP
    SLICE_X11Y60.C5      net (fanout=1)        1.067   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
    SLICE_X11Y60.CMUX    Tilo                  0.337   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X11Y60.A5      net (fanout=1)        0.852   N14
    SLICE_X11Y60.A       Tilo                  0.259   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X8Y56.A3       net (fanout=5)        0.819   RLINK/RLB_DI<7>
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.B1       net (fanout=6)        0.945   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      5.993ns (2.310ns logic, 3.683ns route)
                                                       (38.5% logic, 61.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.147ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      6.008ns (Levels of Logic = 5)
  Clock Path Skew:      1.303ns (5.183 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X7Y56.B4       net (fanout=1)        0.594   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X7Y56.B        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.520   N0
    SLICE_X8Y56.B        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X11Y59.C4      net (fanout=6)        0.802   RLINK/RLB_DI<0>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.D3       net (fanout=6)        0.815   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      6.008ns (2.442ns logic, 3.566ns route)
                                                       (40.6% logic, 59.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.144ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Data Path Delay:      5.998ns (Levels of Logic = 5)
  Clock Path Skew:      1.296ns (5.176 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.997   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.230   N2
    SLICE_X5Y56.A        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        1.132   RLINK/RLB_DI<1>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.C1       net (fanout=6)        0.559   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tas                   0.221   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      5.998ns (2.245ns logic, 3.753ns route)
                                                       (37.4% logic, 62.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.124ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Data Path Delay:      5.956ns (Levels of Logic = 5)
  Clock Path Skew:      1.274ns (5.176 - 3.902)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X8Y60.B4       net (fanout=1)        0.949   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X8Y60.B        Tilo                  0.235   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.414   N8
    SLICE_X9Y59.A        Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X11Y59.C1      net (fanout=4)        0.774   RLINK/RLB_DI<4>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y56.B1       net (fanout=6)        0.542   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y56.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      5.956ns (2.442ns logic, 3.514ns route)
                                                       (41.0% logic, 59.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.117ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Data Path Delay:      5.949ns (Levels of Logic = 5)
  Clock Path Skew:      1.274ns (5.176 - 3.902)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X8Y60.B4       net (fanout=1)        0.949   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X8Y60.B        Tilo                  0.235   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.414   N8
    SLICE_X9Y59.A        Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X11Y59.C1      net (fanout=4)        0.774   RLINK/RLB_DI<4>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.C1       net (fanout=6)        0.559   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      5.949ns (2.418ns logic, 3.531ns route)
                                                       (40.6% logic, 59.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.076ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Data Path Delay:      5.930ns (Levels of Logic = 5)
  Clock Path Skew:      1.296ns (5.176 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.997   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.230   N2
    SLICE_X5Y56.A        Tilo                  0.259   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        1.132   RLINK/RLB_DI<1>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.D3       net (fanout=6)        0.363   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      5.930ns (2.373ns logic, 3.557ns route)
                                                       (40.0% logic, 60.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.060ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Data Path Delay:      5.921ns (Levels of Logic = 5)
  Clock Path Skew:      1.303ns (5.183 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X7Y56.B5       net (fanout=1)        0.452   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X7Y56.BMUX     Tilo                  0.337   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.358   N6
    SLICE_X7Y56.A        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X11Y59.C3      net (fanout=3)        1.119   RLINK/RLB_DI<3>
    SLICE_X11Y59.CMUX    Tilo                  0.337   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o_SW0
    SLICE_X8Y59.D1       net (fanout=1)        0.938   N40
    SLICE_X8Y59.D        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.C5       net (fanout=1)        0.431   RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      5.921ns (2.623ns logic, 3.298ns route)
                                                       (44.3% logic, 55.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.038ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      5.910ns (Levels of Logic = 5)
  Clock Path Skew:      1.314ns (5.183 - 3.869)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X8Y60.B3       net (fanout=1)        0.630   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X8Y60.B        Tilo                  0.235   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.414   N8
    SLICE_X9Y59.A        Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X11Y59.C1      net (fanout=4)        0.774   RLINK/RLB_DI<4>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.D3       net (fanout=6)        0.815   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      5.910ns (2.442ns logic, 3.468ns route)
                                                       (41.3% logic, 58.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.024ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      5.863ns (Levels of Logic = 4)
  Clock Path Skew:      1.281ns (5.183 - 3.902)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP
    SLICE_X11Y60.C5      net (fanout=1)        1.067   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
    SLICE_X11Y60.CMUX    Tilo                  0.337   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X11Y60.A5      net (fanout=1)        0.852   N14
    SLICE_X11Y60.A       Tilo                  0.259   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X8Y56.A3       net (fanout=5)        0.819   RLINK/RLB_DI<7>
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.D3       net (fanout=6)        0.815   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      5.863ns (2.310ns logic, 3.553ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.021ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Data Path Delay:      5.875ns (Levels of Logic = 5)
  Clock Path Skew:      1.296ns (5.176 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X7Y56.B5       net (fanout=1)        0.452   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X7Y56.BMUX     Tilo                  0.337   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.358   N6
    SLICE_X7Y56.A        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X11Y59.C3      net (fanout=3)        1.119   RLINK/RLB_DI<3>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y56.B1       net (fanout=6)        0.542   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y56.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      5.875ns (2.569ns logic, 3.306ns route)
                                                       (43.7% logic, 56.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.014ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Data Path Delay:      5.868ns (Levels of Logic = 5)
  Clock Path Skew:      1.296ns (5.176 - 3.880)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X7Y56.B5       net (fanout=1)        0.452   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X7Y56.BMUX     Tilo                  0.337   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.358   N6
    SLICE_X7Y56.A        Tilo                  0.259   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X11Y59.C3      net (fanout=3)        1.119   RLINK/RLB_DI<3>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.C1       net (fanout=6)        0.559   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tas                   0.349   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      5.868ns (2.545ns logic, 3.323ns route)
                                                       (43.4% logic, 56.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.989ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Data Path Delay:      5.821ns (Levels of Logic = 5)
  Clock Path Skew:      1.274ns (5.176 - 3.902)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X8Y60.B4       net (fanout=1)        0.949   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X8Y60.B        Tilo                  0.235   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.414   N8
    SLICE_X9Y59.A        Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X11Y59.C1      net (fanout=4)        0.774   RLINK/RLB_DI<4>
    SLICE_X11Y59.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X8Y56.A4       net (fanout=2)        0.835   N38
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.C1       net (fanout=6)        0.559   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tas                   0.221   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      5.821ns (2.290ns logic, 3.531ns route)
                                                       (39.3% logic, 60.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.987ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      5.853ns (Levels of Logic = 4)
  Clock Path Skew:      1.308ns (5.177 - 3.869)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.B       Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP
    SLICE_X11Y60.C1      net (fanout=1)        0.704   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
    SLICE_X11Y60.CMUX    Tilo                  0.337   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X11Y60.A5      net (fanout=1)        0.852   N14
    SLICE_X11Y60.A       Tilo                  0.259   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X8Y56.A3       net (fanout=5)        0.819   RLINK/RLB_DI<7>
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.A1      net (fanout=6)        1.168   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X11Y59.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      5.853ns (2.310ns logic, 3.543ns route)
                                                       (39.5% logic, 60.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.945ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      5.784ns (Levels of Logic = 4)
  Clock Path Skew:      1.281ns (5.183 - 3.902)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.A        Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP
    SLICE_X8Y60.B5       net (fanout=1)        1.047   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<5>
    SLICE_X8Y60.BMUX     Tilo                  0.298   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X8Y60.A5       net (fanout=2)        0.433   N10
    SLICE_X8Y60.A        Tilo                  0.235   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X8Y56.A2       net (fanout=4)        1.206   RLINK/RLB_DI<5>
    SLICE_X8Y56.A        Tilo                  0.235   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.B1       net (fanout=6)        0.945   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      5.784ns (2.153ns logic, 3.631ns route)
                                                       (37.2% logic, 62.8% route)

--------------------------------------------------------------------------------

Hold Paths: Unconstrained path analysis

--------------------------------------------------------------------------------
Slack (hold path):      -0.637ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.798ns (Levels of Logic = 2)
  Clock Path Skew:      2.993ns (6.237 - 3.244)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.A       Tshcko                0.953   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X8Y60.B1       net (fanout=1)        0.705   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X8Y60.BMUX     Tilo                  0.281   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X9Y59.C3       net (fanout=2)        0.569   N10
    SLICE_X9Y59.CLK      Tah         (-Th)    -0.290   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata61
                                                       RLINK/CORE/B2CD/R_REGS_data_5
    -------------------------------------------------  ---------------------------
    Total                                      2.798ns (1.524ns logic, 1.274ns route)
                                                       (54.5% logic, 45.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.519ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.916ns (Levels of Logic = 3)
  Clock Path Skew:      2.993ns (6.237 - 3.244)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.AMUX    Tshcko                1.018   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X8Y60.B3       net (fanout=1)        0.595   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X8Y60.B        Tilo                  0.222   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.391   N8
    SLICE_X9Y59.A        Tilo                  0.244   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X9Y59.B6       net (fanout=4)        0.156   RLINK/RLB_DI<4>
    SLICE_X9Y59.CLK      Tah         (-Th)    -0.290   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      2.916ns (1.774ns logic, 1.142ns route)
                                                       (60.8% logic, 39.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.352ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.552ns (Levels of Logic = 3)
  Clock Path Skew:      1.462ns (2.987 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.AMUX     Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X7Y56.B4       net (fanout=1)        0.241   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X7Y56.B        Tilo                  0.156   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.226   N0
    SLICE_X8Y56.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X9Y56.B5       net (fanout=6)        0.082   RLINK/RLB_DI<0>
    SLICE_X9Y56.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      1.552ns (1.003ns logic, 0.549ns route)
                                                       (64.6% logic, 35.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.313ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.089ns (Levels of Logic = 2)
  Clock Path Skew:      2.960ns (6.237 - 3.277)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.A        Tshcko                0.953   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP
    SLICE_X8Y60.B5       net (fanout=1)        0.996   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<5>
    SLICE_X8Y60.BMUX     Tilo                  0.281   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X9Y59.C3       net (fanout=2)        0.569   N10
    SLICE_X9Y59.CLK      Tah         (-Th)    -0.290   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata61
                                                       RLINK/CORE/B2CD/R_REGS_data_5
    -------------------------------------------------  ---------------------------
    Total                                      3.089ns (1.524ns logic, 1.565ns route)
                                                       (49.3% logic, 50.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.378ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.039ns (Levels of Logic = 3)
  Clock Path Skew:      2.975ns (6.230 - 3.255)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.AMUX     Tshcko                1.018   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X7Y56.B4       net (fanout=1)        0.563   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X7Y56.B        Tilo                  0.244   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.492   N0
    SLICE_X8Y56.B        Tilo                  0.222   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X8Y56.C4       net (fanout=6)        0.371   RLINK/RLB_DI<0>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.129   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      3.039ns (1.613ns logic, 1.426ns route)
                                                       (53.1% logic, 46.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.499ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.918ns (Levels of Logic = 3)
  Clock Path Skew:      2.975ns (6.230 - 3.255)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.AMUX     Tshcko                1.018   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X7Y56.B4       net (fanout=1)        0.563   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X7Y56.B        Tilo                  0.244   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.492   N0
    SLICE_X8Y56.B        Tilo                  0.222   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X8Y56.C4       net (fanout=6)        0.371   RLINK/RLB_DI<0>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.008   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      2.918ns (1.492ns logic, 1.426ns route)
                                                       (51.1% logic, 48.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.232ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.684ns (Levels of Logic = 3)
  Clock Path Skew:      1.474ns (2.988 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X8Y60.B1       net (fanout=1)        0.355   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X8Y60.BMUX     Tilo                  0.183   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X8Y60.A5       net (fanout=2)        0.188   N10
    SLICE_X8Y60.A        Tilo                  0.142   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X11Y59.B6      net (fanout=4)        0.160   RLINK/RLB_DI<5>
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      1.684ns (0.981ns logic, 0.703ns route)
                                                       (58.3% logic, 41.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.057ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.997ns (Levels of Logic = 1)
  Clock Path Skew:      -0.502ns (2.047 - 2.549)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y58.A       Tshcko                0.441   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X9Y57.D3       net (fanout=1)        0.300   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X9Y57.D        Tilo                  0.156   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB21
    OLOGIC_X0Y49.D1      net (fanout=1)        0.690   RLINK/FX2CNTL/TXFIFO_DO<1>
    OLOGIC_X0Y49.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<1>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    -------------------------------------------------  ---------------------------
    Total                                      1.997ns (1.007ns logic, 0.990ns route)
                                                       (50.4% logic, 49.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.178ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.224ns (Levels of Logic = 3)
  Clock Path Skew:      2.960ns (6.237 - 3.277)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.AMUX     Tshcko                1.018   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X8Y60.B4       net (fanout=1)        0.903   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X8Y60.B        Tilo                  0.222   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.391   N8
    SLICE_X9Y59.A        Tilo                  0.244   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X9Y59.B6       net (fanout=4)        0.156   RLINK/RLB_DI<4>
    SLICE_X9Y59.CLK      Tah         (-Th)    -0.290   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      3.224ns (1.774ns logic, 1.450ns route)
                                                       (55.0% logic, 45.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.212ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.205ns (Levels of Logic = 3)
  Clock Path Skew:      2.975ns (6.230 - 3.255)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.AMUX     Tshcko                1.018   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X7Y56.B4       net (fanout=1)        0.563   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X7Y56.B        Tilo                  0.244   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.492   N0
    SLICE_X8Y56.B        Tilo                  0.222   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X8Y56.D1       net (fanout=6)        0.537   RLINK/RLB_DI<0>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.129   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      3.205ns (1.613ns logic, 1.592ns route)
                                                       (50.3% logic, 49.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.210ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.694ns (Levels of Logic = 3)
  Clock Path Skew:      1.462ns (2.987 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X5Y56.B4       net (fanout=1)        0.269   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X9Y56.B6       net (fanout=10)       0.032   RLINK/RLB_DI<2>
    SLICE_X9Y56.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      1.694ns (1.069ns logic, 0.625ns route)
                                                       (63.1% logic, 36.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.067ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.002ns (Levels of Logic = 1)
  Clock Path Skew:      -0.507ns (2.045 - 2.552)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y59.B       Tshcko                0.449   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM1/DP
    SLICE_X10Y57.C4      net (fanout=1)        0.246   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
    SLICE_X10Y57.C       Tilo                  0.156   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB41
    OLOGIC_X0Y51.D1      net (fanout=1)        0.741   RLINK/FX2CNTL/TXFIFO_DO<3>
    OLOGIC_X0Y51.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<3>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    -------------------------------------------------  ---------------------------
    Total                                      2.002ns (1.015ns logic, 0.987ns route)
                                                       (50.7% logic, 49.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.136ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.079ns (Levels of Logic = 1)
  Clock Path Skew:      -0.499ns (2.044 - 2.543)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y59.A       Tshcko                0.441   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X15Y59.B1      net (fanout=1)        0.251   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X15Y59.B       Tilo                  0.156   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB61
    OLOGIC_X0Y53.D1      net (fanout=1)        0.821   RLINK/FX2CNTL/TXFIFO_DO<5>
    OLOGIC_X0Y53.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<5>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    -------------------------------------------------  ---------------------------
    Total                                      2.079ns (1.007ns logic, 1.072ns route)
                                                       (48.4% logic, 51.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.207ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.210ns (Levels of Logic = 3)
  Clock Path Skew:      2.975ns (6.230 - 3.255)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.B        Tshcko                1.042   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X7Y56.B5       net (fanout=1)        0.429   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X7Y56.BMUX     Tilo                  0.317   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.338   N6
    SLICE_X7Y56.A        Tilo                  0.244   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X8Y56.D5       net (fanout=3)        0.711   RLINK/RLB_DI<3>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.129   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      3.210ns (1.732ns logic, 1.478ns route)
                                                       (54.0% logic, 46.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.135ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.075ns (Levels of Logic = 1)
  Clock Path Skew:      -0.502ns (2.050 - 2.552)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y59.AMUX    Tshcko                0.490   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X9Y57.D5       net (fanout=1)        0.292   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X9Y57.DMUX     Tilo                  0.203   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB11
    OLOGIC_X0Y46.D1      net (fanout=1)        0.680   RLINK/FX2CNTL/TXFIFO_DO<0>
    OLOGIC_X0Y46.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<0>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    -------------------------------------------------  ---------------------------
    Total                                      2.075ns (1.103ns logic, 0.972ns route)
                                                       (53.2% logic, 46.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.057ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.847ns (Levels of Logic = 3)
  Clock Path Skew:      1.462ns (2.987 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.493   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X8Y56.D6       net (fanout=8)        0.345   RLINK/RLB_DI<1>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      1.847ns (0.943ns logic, 0.904ns route)
                                                       (51.1% logic, 48.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.148ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.088ns (Levels of Logic = 1)
  Clock Path Skew:      -0.502ns (2.047 - 2.549)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y58.BMUX    Tshcko                0.495   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X10Y57.C3      net (fanout=1)        0.270   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X10Y57.CMUX    Tilo                  0.191   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB31
    OLOGIC_X0Y48.D1      net (fanout=1)        0.722   RLINK/FX2CNTL/TXFIFO_DO<2>
    OLOGIC_X0Y48.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<2>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2
    -------------------------------------------------  ---------------------------
    Total                                      2.088ns (1.096ns logic, 0.992ns route)
                                                       (52.5% logic, 47.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.013ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.896ns (Levels of Logic = 3)
  Clock Path Skew:      1.441ns (2.988 - 1.547)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP
    SLICE_X8Y60.B5       net (fanout=1)        0.567   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<5>
    SLICE_X8Y60.BMUX     Tilo                  0.183   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X8Y60.A5       net (fanout=2)        0.188   N10
    SLICE_X8Y60.A        Tilo                  0.142   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X11Y59.B6      net (fanout=4)        0.160   RLINK/RLB_DI<5>
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      1.896ns (0.981ns logic, 0.915ns route)
                                                       (51.7% logic, 48.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.008ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.919ns (Levels of Logic = 3)
  Clock Path Skew:      1.469ns (2.994 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.AMUX     Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X7Y56.B4       net (fanout=1)        0.241   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X7Y56.B        Tilo                  0.156   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.226   N0
    SLICE_X8Y56.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X9Y59.B5       net (fanout=6)        0.449   RLINK/RLB_DI<0>
    SLICE_X9Y59.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      1.919ns (1.003ns logic, 0.916ns route)
                                                       (52.3% logic, 47.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.235ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.178ns (Levels of Logic = 1)
  Clock Path Skew:      -0.499ns (2.050 - 2.549)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y58.AMUX    Tshcko                0.490   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X9Y57.D1       net (fanout=1)        0.395   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X9Y57.DMUX     Tilo                  0.203   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB11
    OLOGIC_X0Y46.D1      net (fanout=1)        0.680   RLINK/FX2CNTL/TXFIFO_DO<0>
    OLOGIC_X0Y46.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<0>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    -------------------------------------------------  ---------------------------
    Total                                      2.178ns (1.103ns logic, 1.075ns route)
                                                       (50.6% logic, 49.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.091ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.829ns (Levels of Logic = 4)
  Clock Path Skew:      1.478ns (2.992 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.AMUX    Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X8Y60.B3       net (fanout=1)        0.272   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X8Y60.B        Tilo                  0.142   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.164   N8
    SLICE_X9Y59.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X8Y58.B4       net (fanout=4)        0.232   RLINK/RLB_DI<4>
    SLICE_X8Y58.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/_n0059_SW0
    SLICE_X8Y58.A5       net (fanout=1)        0.041   N42
    SLICE_X8Y58.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      1.829ns (1.120ns logic, 0.709ns route)
                                                       (61.2% logic, 38.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.063ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.841ns (Levels of Logic = 3)
  Clock Path Skew:      1.462ns (2.987 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X5Y56.B4       net (fanout=1)        0.269   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X8Y56.C5       net (fanout=10)       0.204   RLINK/RLB_DI<2>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      1.841ns (1.044ns logic, 0.797ns route)
                                                       (56.7% logic, 43.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.132ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.772ns (Levels of Logic = 3)
  Clock Path Skew:      1.462ns (2.987 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X5Y56.B4       net (fanout=1)        0.269   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X8Y56.C5       net (fanout=10)       0.204   RLINK/RLB_DI<2>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.121   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      1.772ns (0.975ns logic, 0.797ns route)
                                                       (55.0% logic, 45.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.205ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.153ns (Levels of Logic = 1)
  Clock Path Skew:      -0.494ns (2.049 - 2.543)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y59.B       Tshcko                0.449   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM0/DP
    SLICE_X15Y58.A2      net (fanout=1)        0.354   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
    SLICE_X15Y58.A       Tilo                  0.156   RLINK/CORE/RL/R_LREGS_state_proc_lnext.n_nakcode<1>4
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB81
    OLOGIC_X0Y55.D1      net (fanout=1)        0.784   RLINK/FX2CNTL/TXFIFO_DO<7>
    OLOGIC_X0Y55.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<7>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    -------------------------------------------------  ---------------------------
    Total                                      2.153ns (1.015ns logic, 1.138ns route)
                                                       (47.1% logic, 52.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.056ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.960ns (Levels of Logic = 3)
  Clock Path Skew:      1.462ns (2.987 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.493   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X9Y56.B4       net (fanout=8)        0.433   RLINK/RLB_DI<1>
    SLICE_X9Y56.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      1.960ns (0.968ns logic, 0.992ns route)
                                                       (49.4% logic, 50.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.018ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.904ns (Levels of Logic = 3)
  Clock Path Skew:      1.480ns (2.994 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X11Y60.C2      net (fanout=1)        0.450   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X11Y60.C       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X11Y60.B4      net (fanout=1)        0.099   N12
    SLICE_X11Y60.B       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X9Y59.D4       net (fanout=5)        0.333   RLINK/RLB_DI<6>
    SLICE_X9Y59.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      1.904ns (1.022ns logic, 0.882ns route)
                                                       (53.7% logic, 46.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.240ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.177ns (Levels of Logic = 1)
  Clock Path Skew:      -0.505ns (2.047 - 2.552)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y59.BMUX    Tshcko                0.495   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X10Y57.C2      net (fanout=1)        0.359   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X10Y57.CMUX    Tilo                  0.191   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB31
    OLOGIC_X0Y48.D1      net (fanout=1)        0.722   RLINK/FX2CNTL/TXFIFO_DO<2>
    OLOGIC_X0Y48.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<2>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2
    -------------------------------------------------  ---------------------------
    Total                                      2.177ns (1.096ns logic, 1.081ns route)
                                                       (50.3% logic, 49.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.022ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.938ns (Levels of Logic = 3)
  Clock Path Skew:      1.474ns (2.988 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X11Y60.C2      net (fanout=1)        0.450   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X11Y60.C       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X11Y60.B4      net (fanout=1)        0.099   N12
    SLICE_X11Y60.B       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X11Y59.B2      net (fanout=5)        0.367   RLINK/RLB_DI<6>
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      1.938ns (1.022ns logic, 0.916ns route)
                                                       (52.7% logic, 47.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.349ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.286ns (Levels of Logic = 1)
  Clock Path Skew:      -0.505ns (2.047 - 2.552)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y59.A       Tshcko                0.441   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X9Y57.D2       net (fanout=1)        0.589   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X9Y57.D        Tilo                  0.156   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB21
    OLOGIC_X0Y49.D1      net (fanout=1)        0.690   RLINK/FX2CNTL/TXFIFO_DO<1>
    OLOGIC_X0Y49.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<1>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    -------------------------------------------------  ---------------------------
    Total                                      2.286ns (1.007ns logic, 1.279ns route)
                                                       (44.1% logic, 55.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.017ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.903ns (Levels of Logic = 4)
  Clock Path Skew:      1.478ns (2.992 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X8Y60.B1       net (fanout=1)        0.355   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X8Y60.BMUX     Tilo                  0.183   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X8Y60.A5       net (fanout=2)        0.188   N10
    SLICE_X8Y60.A        Tilo                  0.142   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X8Y58.B6       net (fanout=4)        0.221   RLINK/RLB_DI<5>
    SLICE_X8Y58.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/_n0059_SW0
    SLICE_X8Y58.A5       net (fanout=1)        0.041   N42
    SLICE_X8Y58.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      1.903ns (1.098ns logic, 0.805ns route)
                                                       (57.7% logic, 42.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.050ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.955ns (Levels of Logic = 3)
  Clock Path Skew:      1.463ns (2.988 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X5Y56.B4       net (fanout=1)        0.269   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X11Y59.A6      net (fanout=10)       0.293   RLINK/RLB_DI<2>
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      1.955ns (1.069ns logic, 0.886ns route)
                                                       (54.7% logic, 45.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.050ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.970ns (Levels of Logic = 3)
  Clock Path Skew:      1.478ns (2.992 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X11Y60.C2      net (fanout=1)        0.450   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X11Y60.C       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X11Y60.B4      net (fanout=1)        0.099   N12
    SLICE_X11Y60.B       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X8Y58.A4       net (fanout=5)        0.424   RLINK/RLB_DI<6>
    SLICE_X8Y58.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      1.970ns (0.997ns logic, 0.973ns route)
                                                       (50.6% logic, 49.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.328ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.266ns (Levels of Logic = 1)
  Clock Path Skew:      -0.504ns (2.045 - 2.549)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y58.B       Tshcko                0.449   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X10Y57.C1      net (fanout=1)        0.510   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X10Y57.C       Tilo                  0.156   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB41
    OLOGIC_X0Y51.D1      net (fanout=1)        0.741   RLINK/FX2CNTL/TXFIFO_DO<3>
    OLOGIC_X0Y51.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<3>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    -------------------------------------------------  ---------------------------
    Total                                      2.266ns (1.015ns logic, 1.251ns route)
                                                       (44.8% logic, 55.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.156ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.060ns (Levels of Logic = 3)
  Clock Path Skew:      1.462ns (2.987 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.493   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X8Y56.C2       net (fanout=8)        0.558   RLINK/RLB_DI<1>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      2.060ns (0.943ns logic, 1.117ns route)
                                                       (45.8% logic, 54.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.087ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.991ns (Levels of Logic = 3)
  Clock Path Skew:      1.462ns (2.987 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.493   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X8Y56.C2       net (fanout=8)        0.558   RLINK/RLB_DI<1>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.121   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      1.991ns (0.874ns logic, 1.117ns route)
                                                       (43.9% logic, 56.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.168ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.060ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.987 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X5Y56.B2       net (fanout=1)        0.706   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X8Y56.D6       net (fanout=8)        0.345   RLINK/RLB_DI<1>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      2.060ns (0.943ns logic, 1.117ns route)
                                                       (45.8% logic, 54.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.079ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.995ns (Levels of Logic = 3)
  Clock Path Skew:      1.474ns (2.988 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.B       Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP
    SLICE_X11Y60.C1      net (fanout=1)        0.335   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
    SLICE_X11Y60.CMUX    Tilo                  0.203   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X11Y60.A5      net (fanout=1)        0.409   N14
    SLICE_X11Y60.A       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X11Y59.A4      net (fanout=5)        0.228   RLINK/RLB_DI<7>
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      1.995ns (1.023ns logic, 0.972ns route)
                                                       (51.3% logic, 48.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.363ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.306ns (Levels of Logic = 1)
  Clock Path Skew:      -0.499ns (2.044 - 2.543)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y59.BMUX    Tshcko                0.495   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X15Y58.A5      net (fanout=1)        0.174   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X15Y58.AMUX    Tilo                  0.203   RLINK/CORE/RL/R_LREGS_state_proc_lnext.n_nakcode<1>4
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB71
    OLOGIC_X0Y52.D1      net (fanout=1)        1.024   RLINK/FX2CNTL/TXFIFO_DO<6>
    OLOGIC_X0Y52.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<6>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    -------------------------------------------------  ---------------------------
    Total                                      2.306ns (1.108ns logic, 1.198ns route)
                                                       (48.0% logic, 52.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.128ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.032ns (Levels of Logic = 3)
  Clock Path Skew:      1.462ns (2.987 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X5Y56.B4       net (fanout=1)        0.269   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X8Y56.D2       net (fanout=10)       0.395   RLINK/RLB_DI<2>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      2.032ns (1.044ns logic, 0.988ns route)
                                                       (51.4% logic, 48.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.119ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.011ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.987 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.B        Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP
    SLICE_X7Y56.B3       net (fanout=1)        0.505   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
    SLICE_X7Y56.BMUX     Tilo                  0.203   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.152   N6
    SLICE_X7Y56.A        Tilo                  0.156   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X8Y56.D5       net (fanout=3)        0.356   RLINK/RLB_DI<3>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      2.011ns (0.998ns logic, 1.013ns route)
                                                       (49.6% logic, 50.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.238ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.143ns (Levels of Logic = 3)
  Clock Path Skew:      1.463ns (2.988 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.493   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.A5      net (fanout=8)        0.616   RLINK/RLB_DI<1>
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      2.143ns (0.968ns logic, 1.175ns route)
                                                       (45.2% logic, 54.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.248ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.140ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.987 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.AMUX     Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X7Y56.B1       net (fanout=1)        0.829   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X7Y56.B        Tilo                  0.156   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.226   N0
    SLICE_X8Y56.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X9Y56.B5       net (fanout=6)        0.082   RLINK/RLB_DI<0>
    SLICE_X9Y56.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      2.140ns (1.003ns logic, 1.137ns route)
                                                       (46.9% logic, 53.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.460ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.404ns (Levels of Logic = 1)
  Clock Path Skew:      -0.498ns (2.045 - 2.543)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y59.AMUX    Tshcko                0.490   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X15Y59.B3      net (fanout=1)        0.473   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X15Y59.BMUX    Tilo                  0.203   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB51
    OLOGIC_X0Y50.D1      net (fanout=1)        0.828   RLINK/FX2CNTL/TXFIFO_DO<4>
    OLOGIC_X0Y50.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<4>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    -------------------------------------------------  ---------------------------
    Total                                      2.404ns (1.103ns logic, 1.301ns route)
                                                       (45.9% logic, 54.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.281ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.173ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.987 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X5Y56.B2       net (fanout=1)        0.706   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X9Y56.B4       net (fanout=8)        0.433   RLINK/RLB_DI<1>
    SLICE_X9Y56.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      2.173ns (0.968ns logic, 1.205ns route)
                                                       (44.5% logic, 55.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.146ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.068ns (Levels of Logic = 4)
  Clock Path Skew:      1.480ns (2.994 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X8Y60.B1       net (fanout=1)        0.355   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X8Y60.BMUX     Tilo                  0.183   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X8Y60.A5       net (fanout=2)        0.188   N10
    SLICE_X8Y60.A        Tilo                  0.142   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X8Y59.D3       net (fanout=4)        0.244   RLINK/RLB_DI<5>
    SLICE_X8Y59.D        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.C5       net (fanout=1)        0.183   RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      2.068ns (1.098ns logic, 0.970ns route)
                                                       (53.1% logic, 46.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.183ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.094ns (Levels of Logic = 3)
  Clock Path Skew:      1.469ns (2.994 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X5Y56.B4       net (fanout=1)        0.269   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X9Y59.D6       net (fanout=10)       0.432   RLINK/RLB_DI<2>
    SLICE_X9Y59.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      2.094ns (1.069ns logic, 1.025ns route)
                                                       (51.1% logic, 48.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.203ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.095ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.987 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X5Y56.B1       net (fanout=1)        0.670   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X9Y56.B6       net (fanout=10)       0.032   RLINK/RLB_DI<2>
    SLICE_X9Y56.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      2.095ns (1.069ns logic, 1.026ns route)
                                                       (51.0% logic, 49.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.475ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.426ns (Levels of Logic = 1)
  Clock Path Skew:      -0.491ns (2.045 - 2.536)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y59.AMUX    Tshcko                0.490   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X15Y59.B4      net (fanout=1)        0.495   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X15Y59.BMUX    Tilo                  0.203   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB51
    OLOGIC_X0Y50.D1      net (fanout=1)        0.828   RLINK/FX2CNTL/TXFIFO_DO<4>
    OLOGIC_X0Y50.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<4>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    -------------------------------------------------  ---------------------------
    Total                                      2.426ns (1.103ns logic, 1.323ns route)
                                                       (45.5% logic, 54.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.177ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.093ns (Levels of Logic = 4)
  Clock Path Skew:      1.474ns (2.988 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.AMUX    Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X8Y60.B3       net (fanout=1)        0.272   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X8Y60.B        Tilo                  0.142   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.164   N8
    SLICE_X9Y59.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X11Y59.C1      net (fanout=4)        0.390   RLINK/RLB_DI<4>
    SLICE_X11Y59.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X11Y59.B4      net (fanout=2)        0.108   N38
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.093ns (1.159ns logic, 0.934ns route)
                                                       (55.4% logic, 44.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.190ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.077ns (Levels of Logic = 4)
  Clock Path Skew:      1.445ns (2.992 - 1.547)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.AMUX     Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X8Y60.B4       net (fanout=1)        0.520   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X8Y60.B        Tilo                  0.142   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.164   N8
    SLICE_X9Y59.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X8Y58.B4       net (fanout=4)        0.232   RLINK/RLB_DI<4>
    SLICE_X8Y58.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/_n0059_SW0
    SLICE_X8Y58.A5       net (fanout=1)        0.041   N42
    SLICE_X8Y58.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.077ns (1.120ns logic, 0.957ns route)
                                                       (53.9% logic, 46.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.199ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.091ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.987 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.AMUX     Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X7Y56.B1       net (fanout=1)        0.829   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X7Y56.B        Tilo                  0.156   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.226   N0
    SLICE_X8Y56.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X8Y56.C4       net (fanout=6)        0.127   RLINK/RLB_DI<0>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.121   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      2.091ns (0.909ns logic, 1.182ns route)
                                                       (43.5% logic, 56.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.268ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.160ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.987 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.AMUX     Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X7Y56.B1       net (fanout=1)        0.829   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X7Y56.B        Tilo                  0.156   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.226   N0
    SLICE_X8Y56.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X8Y56.C4       net (fanout=6)        0.127   RLINK/RLB_DI<0>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      2.160ns (0.978ns logic, 1.182ns route)
                                                       (45.3% logic, 54.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.194ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.099ns (Levels of Logic = 4)
  Clock Path Skew:      1.463ns (2.988 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.AMUX     Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X7Y56.B4       net (fanout=1)        0.241   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X7Y56.B        Tilo                  0.156   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.226   N0
    SLICE_X8Y56.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X11Y59.C4      net (fanout=6)        0.365   RLINK/RLB_DI<0>
    SLICE_X11Y59.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X11Y59.B4      net (fanout=2)        0.108   N38
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.099ns (1.159ns logic, 0.940ns route)
                                                       (55.2% logic, 44.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.253ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.142ns (Levels of Logic = 3)
  Clock Path Skew:      1.447ns (2.994 - 1.547)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP
    SLICE_X11Y60.C3      net (fanout=1)        0.688   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<6>
    SLICE_X11Y60.C       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X11Y60.B4      net (fanout=1)        0.099   N12
    SLICE_X11Y60.B       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X9Y59.D4       net (fanout=5)        0.333   RLINK/RLB_DI<6>
    SLICE_X9Y59.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      2.142ns (1.022ns logic, 1.120ns route)
                                                       (47.7% logic, 52.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.292ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.203ns (Levels of Logic = 3)
  Clock Path Skew:      1.469ns (2.994 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.493   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X9Y59.B2       net (fanout=8)        0.676   RLINK/RLB_DI<1>
    SLICE_X9Y59.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      2.203ns (0.968ns logic, 1.235ns route)
                                                       (43.9% logic, 56.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.305ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.216ns (Levels of Logic = 3)
  Clock Path Skew:      1.469ns (2.994 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.493   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X9Y59.D2       net (fanout=8)        0.689   RLINK/RLB_DI<1>
    SLICE_X9Y59.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      2.216ns (0.968ns logic, 1.248ns route)
                                                       (43.7% logic, 56.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.228ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.115ns (Levels of Logic = 4)
  Clock Path Skew:      1.445ns (2.992 - 1.547)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP
    SLICE_X8Y60.B5       net (fanout=1)        0.567   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<5>
    SLICE_X8Y60.BMUX     Tilo                  0.183   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X8Y60.A5       net (fanout=2)        0.188   N10
    SLICE_X8Y60.A        Tilo                  0.142   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X8Y58.B6       net (fanout=4)        0.221   RLINK/RLB_DI<5>
    SLICE_X8Y58.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/_n0059_SW0
    SLICE_X8Y58.A5       net (fanout=1)        0.041   N42
    SLICE_X8Y58.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.115ns (1.098ns logic, 1.017ns route)
                                                       (51.9% logic, 48.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.204ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.113ns (Levels of Logic = 4)
  Clock Path Skew:      1.467ns (2.992 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.AMUX     Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X7Y56.B4       net (fanout=1)        0.241   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X7Y56.B        Tilo                  0.156   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.226   N0
    SLICE_X8Y56.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X8Y58.B1       net (fanout=6)        0.485   RLINK/RLB_DI<0>
    SLICE_X8Y58.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/_n0059_SW0
    SLICE_X8Y58.A5       net (fanout=1)        0.041   N42
    SLICE_X8Y58.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.113ns (1.120ns logic, 0.993ns route)
                                                       (53.0% logic, 47.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.293ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.176ns (Levels of Logic = 3)
  Clock Path Skew:      1.441ns (2.988 - 1.547)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP
    SLICE_X11Y60.C3      net (fanout=1)        0.688   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<6>
    SLICE_X11Y60.C       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X11Y60.B4      net (fanout=1)        0.099   N12
    SLICE_X11Y60.B       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X11Y59.B2      net (fanout=5)        0.367   RLINK/RLB_DI<6>
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.176ns (1.022ns logic, 1.154ns route)
                                                       (47.0% logic, 53.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.212ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.134ns (Levels of Logic = 4)
  Clock Path Skew:      1.480ns (2.994 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.AMUX    Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X8Y60.B3       net (fanout=1)        0.272   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X8Y60.B        Tilo                  0.142   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.164   N8
    SLICE_X9Y59.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X8Y59.D2       net (fanout=4)        0.395   RLINK/RLB_DI<4>
    SLICE_X8Y59.D        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.C5       net (fanout=1)        0.183   RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      2.134ns (1.120ns logic, 1.014ns route)
                                                       (52.5% logic, 47.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.198ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.118ns (Levels of Logic = 3)
  Clock Path Skew:      1.478ns (2.992 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.B       Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP
    SLICE_X11Y60.C1      net (fanout=1)        0.335   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
    SLICE_X11Y60.CMUX    Tilo                  0.203   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X11Y60.A5      net (fanout=1)        0.409   N14
    SLICE_X11Y60.A       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X8Y58.A3       net (fanout=5)        0.376   RLINK/RLB_DI<7>
    SLICE_X8Y58.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.118ns (0.998ns logic, 1.120ns route)
                                                       (47.1% logic, 52.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.135ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.044ns (Levels of Logic = 4)
  Clock Path Skew:      1.467ns (2.992 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.B        Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X7Y56.B5       net (fanout=1)        0.192   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X7Y56.BMUX     Tilo                  0.203   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.152   N6
    SLICE_X7Y56.A        Tilo                  0.156   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X8Y58.B2       net (fanout=3)        0.519   RLINK/RLB_DI<3>
    SLICE_X8Y58.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/_n0059_SW0
    SLICE_X8Y58.A5       net (fanout=1)        0.041   N42
    SLICE_X8Y58.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.044ns (1.140ns logic, 0.904ns route)
                                                       (55.8% logic, 44.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.190ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.105ns (Levels of Logic = 4)
  Clock Path Skew:      1.473ns (2.987 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X11Y60.C2      net (fanout=1)        0.450   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X11Y60.C       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X11Y60.B4      net (fanout=1)        0.099   N12
    SLICE_X11Y60.B       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X8Y56.A6       net (fanout=5)        0.264   RLINK/RLB_DI<6>
    SLICE_X8Y56.A        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.D3       net (fanout=6)        0.153   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      2.105ns (1.139ns logic, 0.966ns route)
                                                       (54.1% logic, 45.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.255ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.164ns (Levels of Logic = 4)
  Clock Path Skew:      1.467ns (2.992 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.493   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X8Y58.B3       net (fanout=8)        0.479   RLINK/RLB_DI<1>
    SLICE_X8Y58.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/_n0059_SW0
    SLICE_X8Y58.A5       net (fanout=1)        0.041   N42
    SLICE_X8Y58.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.164ns (1.085ns logic, 1.079ns route)
                                                       (50.1% logic, 49.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.290ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.195ns (Levels of Logic = 3)
  Clock Path Skew:      1.463ns (2.988 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X5Y56.B4       net (fanout=1)        0.269   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X11Y59.B1      net (fanout=10)       0.533   RLINK/RLB_DI<2>
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.195ns (1.069ns logic, 1.126ns route)
                                                       (48.7% logic, 51.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.257ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.173ns (Levels of Logic = 3)
  Clock Path Skew:      1.474ns (2.988 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.B       Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP
    SLICE_X11Y60.C1      net (fanout=1)        0.335   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
    SLICE_X11Y60.CMUX    Tilo                  0.203   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X11Y60.A5      net (fanout=1)        0.409   N14
    SLICE_X11Y60.A       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X11Y59.B3      net (fanout=5)        0.406   RLINK/RLB_DI<7>
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.173ns (1.023ns logic, 1.150ns route)
                                                       (47.1% logic, 52.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.321ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.208ns (Levels of Logic = 3)
  Clock Path Skew:      1.445ns (2.992 - 1.547)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP
    SLICE_X11Y60.C3      net (fanout=1)        0.688   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<6>
    SLICE_X11Y60.C       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X11Y60.B4      net (fanout=1)        0.099   N12
    SLICE_X11Y60.B       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X8Y58.A4       net (fanout=5)        0.424   RLINK/RLB_DI<6>
    SLICE_X8Y58.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.208ns (0.997ns logic, 1.211ns route)
                                                       (45.2% logic, 54.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.381ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.273ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.987 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X5Y56.B2       net (fanout=1)        0.706   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X8Y56.C2       net (fanout=8)        0.558   RLINK/RLB_DI<1>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      2.273ns (0.943ns logic, 1.330ns route)
                                                       (41.5% logic, 58.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.312ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.204ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.987 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X5Y56.B2       net (fanout=1)        0.706   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X8Y56.C2       net (fanout=8)        0.558   RLINK/RLB_DI<1>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.121   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      2.204ns (0.874ns logic, 1.330ns route)
                                                       (39.7% logic, 60.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.547ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.502ns (Levels of Logic = 1)
  Clock Path Skew:      -0.487ns (2.049 - 2.536)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y59.B       Tshcko                0.449   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM1/DP
    SLICE_X15Y58.A1      net (fanout=1)        0.703   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
    SLICE_X15Y58.A       Tilo                  0.156   RLINK/CORE/RL/R_LREGS_state_proc_lnext.n_nakcode<1>4
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB81
    OLOGIC_X0Y55.D1      net (fanout=1)        0.784   RLINK/FX2CNTL/TXFIFO_DO<7>
    OLOGIC_X0Y55.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<7>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    -------------------------------------------------  ---------------------------
    Total                                      2.502ns (1.015ns logic, 1.487ns route)
                                                       (40.6% logic, 59.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.219ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.123ns (Levels of Logic = 4)
  Clock Path Skew:      1.462ns (2.987 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X5Y56.B4       net (fanout=1)        0.269   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X8Y56.A5       net (fanout=10)       0.191   RLINK/RLB_DI<2>
    SLICE_X8Y56.A        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.D3       net (fanout=6)        0.153   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      2.123ns (1.186ns logic, 0.937ns route)
                                                       (55.9% logic, 44.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.647ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.597ns (Levels of Logic = 1)
  Clock Path Skew:      -0.492ns (2.044 - 2.536)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y59.A       Tshcko                0.441   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM1/DP
    SLICE_X15Y59.B2      net (fanout=1)        0.769   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<5>
    SLICE_X15Y59.B       Tilo                  0.156   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB61
    OLOGIC_X0Y53.D1      net (fanout=1)        0.821   RLINK/FX2CNTL/TXFIFO_DO<5>
    OLOGIC_X0Y53.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<5>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    -------------------------------------------------  ---------------------------
    Total                                      2.597ns (1.007ns logic, 1.590ns route)
                                                       (38.8% logic, 61.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.321ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.232ns (Levels of Logic = 3)
  Clock Path Skew:      1.469ns (2.994 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X5Y56.B4       net (fanout=1)        0.269   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X9Y59.B3       net (fanout=10)       0.570   RLINK/RLB_DI<2>
    SLICE_X9Y59.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      2.232ns (1.069ns logic, 1.163ns route)
                                                       (47.9% logic, 52.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.239ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.161ns (Levels of Logic = 4)
  Clock Path Skew:      1.480ns (2.994 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X11Y60.C2      net (fanout=1)        0.450   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X11Y60.C       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X11Y60.B4      net (fanout=1)        0.099   N12
    SLICE_X11Y60.B       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X8Y59.D5       net (fanout=5)        0.290   RLINK/RLB_DI<6>
    SLICE_X8Y59.D        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.C5       net (fanout=1)        0.183   RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      2.161ns (1.139ns logic, 1.022ns route)
                                                       (52.7% logic, 47.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.407ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.299ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.987 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.AMUX     Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X7Y56.B1       net (fanout=1)        0.829   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X7Y56.B        Tilo                  0.156   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.226   N0
    SLICE_X8Y56.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X8Y56.D1       net (fanout=6)        0.266   RLINK/RLB_DI<0>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      2.299ns (0.978ns logic, 1.321ns route)
                                                       (42.5% logic, 57.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.350ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.242ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.987 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X5Y56.B1       net (fanout=1)        0.670   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X8Y56.C5       net (fanout=10)       0.204   RLINK/RLB_DI<2>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      2.242ns (1.044ns logic, 1.198ns route)
                                                       (46.6% logic, 53.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.281ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.173ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.987 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X5Y56.B1       net (fanout=1)        0.670   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X8Y56.C5       net (fanout=10)       0.204   RLINK/RLB_DI<2>
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.121   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      2.173ns (0.975ns logic, 1.198ns route)
                                                       (44.9% logic, 55.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.362ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.245ns (Levels of Logic = 3)
  Clock Path Skew:      1.441ns (2.988 - 1.547)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.B        Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP
    SLICE_X11Y60.C5      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
    SLICE_X11Y60.CMUX    Tilo                  0.203   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X11Y60.A5      net (fanout=1)        0.409   N14
    SLICE_X11Y60.A       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X11Y59.A4      net (fanout=5)        0.228   RLINK/RLB_DI<7>
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      2.245ns (1.023ns logic, 1.222ns route)
                                                       (45.6% logic, 54.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.463ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.356ns (Levels of Logic = 3)
  Clock Path Skew:      1.451ns (2.988 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X5Y56.B2       net (fanout=1)        0.706   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.A5      net (fanout=8)        0.616   RLINK/RLB_DI<1>
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      2.356ns (0.968ns logic, 1.388ns route)
                                                       (41.1% logic, 58.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.291ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.206ns (Levels of Logic = 4)
  Clock Path Skew:      1.473ns (2.987 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X11Y60.C2      net (fanout=1)        0.450   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X11Y60.C       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X11Y60.B4      net (fanout=1)        0.099   N12
    SLICE_X11Y60.B       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X8Y56.A6       net (fanout=5)        0.264   RLINK/RLB_DI<6>
    SLICE_X8Y56.A        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.C1       net (fanout=6)        0.254   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      2.206ns (1.139ns logic, 1.067ns route)
                                                       (51.6% logic, 48.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.222ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.137ns (Levels of Logic = 4)
  Clock Path Skew:      1.473ns (2.987 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X11Y60.C2      net (fanout=1)        0.450   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X11Y60.C       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X11Y60.B4      net (fanout=1)        0.099   N12
    SLICE_X11Y60.B       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X8Y56.A6       net (fanout=5)        0.264   RLINK/RLB_DI<6>
    SLICE_X8Y56.A        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.C1       net (fanout=6)        0.254   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.121   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      2.137ns (1.070ns logic, 1.067ns route)
                                                       (50.1% logic, 49.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.391ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.280ns (Levels of Logic = 4)
  Clock Path Skew:      1.447ns (2.994 - 1.547)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP
    SLICE_X8Y60.B5       net (fanout=1)        0.567   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<5>
    SLICE_X8Y60.BMUX     Tilo                  0.183   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X8Y60.A5       net (fanout=2)        0.188   N10
    SLICE_X8Y60.A        Tilo                  0.142   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X8Y59.D3       net (fanout=4)        0.244   RLINK/RLB_DI<5>
    SLICE_X8Y59.D        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.C5       net (fanout=1)        0.183   RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      2.280ns (1.098ns logic, 1.182ns route)
                                                       (48.2% logic, 51.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.334ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.249ns (Levels of Logic = 4)
  Clock Path Skew:      1.473ns (2.987 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X11Y60.C2      net (fanout=1)        0.450   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X11Y60.C       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X11Y60.B4      net (fanout=1)        0.099   N12
    SLICE_X11Y60.B       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X8Y56.A6       net (fanout=5)        0.264   RLINK/RLB_DI<6>
    SLICE_X8Y56.A        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y56.B1       net (fanout=6)        0.272   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y56.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      2.249ns (1.164ns logic, 1.085ns route)
                                                       (51.8% logic, 48.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.291ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.196ns (Levels of Logic = 4)
  Clock Path Skew:      1.463ns (2.988 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.B        Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X7Y56.B5       net (fanout=1)        0.192   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X7Y56.BMUX     Tilo                  0.203   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X7Y56.A3       net (fanout=1)        0.152   N6
    SLICE_X7Y56.A        Tilo                  0.156   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X11Y59.C3      net (fanout=3)        0.565   RLINK/RLB_DI<3>
    SLICE_X11Y59.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X11Y59.B4      net (fanout=2)        0.108   N38
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.196ns (1.179ns logic, 1.017ns route)
                                                       (53.7% logic, 46.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.320ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.224ns (Levels of Logic = 4)
  Clock Path Skew:      1.462ns (2.987 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X5Y56.B4       net (fanout=1)        0.269   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X8Y56.A5       net (fanout=10)       0.191   RLINK/RLB_DI<2>
    SLICE_X8Y56.A        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.C1       net (fanout=6)        0.254   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      2.224ns (1.186ns logic, 1.038ns route)
                                                       (53.3% logic, 46.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.251ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.155ns (Levels of Logic = 4)
  Clock Path Skew:      1.462ns (2.987 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X5Y56.B4       net (fanout=1)        0.269   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X8Y56.A5       net (fanout=10)       0.191   RLINK/RLB_DI<2>
    SLICE_X8Y56.A        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.C1       net (fanout=6)        0.254   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.121   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      2.155ns (1.117ns logic, 1.038ns route)
                                                       (51.8% logic, 48.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.517ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.416ns (Levels of Logic = 3)
  Clock Path Skew:      1.457ns (2.994 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X5Y56.B2       net (fanout=1)        0.706   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X9Y59.B2       net (fanout=8)        0.676   RLINK/RLB_DI<1>
    SLICE_X9Y59.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      2.416ns (0.968ns logic, 1.448ns route)
                                                       (40.1% logic, 59.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.530ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.429ns (Levels of Logic = 3)
  Clock Path Skew:      1.457ns (2.994 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X5Y56.B2       net (fanout=1)        0.706   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X9Y59.D2       net (fanout=8)        0.689   RLINK/RLB_DI<1>
    SLICE_X9Y59.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      2.429ns (0.968ns logic, 1.461ns route)
                                                       (39.9% logic, 60.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.363ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.267ns (Levels of Logic = 4)
  Clock Path Skew:      1.462ns (2.987 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X5Y56.B4       net (fanout=1)        0.269   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X8Y56.A5       net (fanout=10)       0.191   RLINK/RLB_DI<2>
    SLICE_X8Y56.A        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y56.B1       net (fanout=6)        0.272   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y56.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      2.267ns (1.211ns logic, 1.056ns route)
                                                       (53.4% logic, 46.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.458ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.341ns (Levels of Logic = 4)
  Clock Path Skew:      1.441ns (2.988 - 1.547)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.AMUX     Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X8Y60.B4       net (fanout=1)        0.520   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X8Y60.B        Tilo                  0.142   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.164   N8
    SLICE_X9Y59.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X11Y59.C1      net (fanout=4)        0.390   RLINK/RLB_DI<4>
    SLICE_X11Y59.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X11Y59.B4      net (fanout=2)        0.108   N38
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.341ns (1.159ns logic, 1.182ns route)
                                                       (49.5% logic, 50.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.463ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.356ns (Levels of Logic = 3)
  Clock Path Skew:      1.451ns (2.988 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X5Y56.B1       net (fanout=1)        0.670   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X11Y59.A6      net (fanout=10)       0.293   RLINK/RLB_DI<2>
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      2.356ns (1.069ns logic, 1.287ns route)
                                                       (45.4% logic, 54.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.344ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.253ns (Levels of Logic = 4)
  Clock Path Skew:      1.467ns (2.992 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X5Y56.B4       net (fanout=1)        0.269   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X5Y56.BMUX     Tilo                  0.203   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X9Y56.A6       net (fanout=1)        0.324   N4
    SLICE_X9Y56.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X8Y58.B5       net (fanout=10)       0.433   RLINK/RLB_DI<2>
    SLICE_X8Y58.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/_n0059_SW0
    SLICE_X8Y58.A5       net (fanout=1)        0.041   N42
    SLICE_X8Y58.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.253ns (1.186ns logic, 1.067ns route)
                                                       (52.6% logic, 47.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.481ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.386ns (Levels of Logic = 4)
  Clock Path Skew:      1.463ns (2.988 - 1.525)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X5Y56.B3       net (fanout=1)        0.493   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X11Y59.C5      net (fanout=8)        0.595   RLINK/RLB_DI<1>
    SLICE_X11Y59.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o_SW0
    SLICE_X11Y59.B4      net (fanout=2)        0.108   N38
    SLICE_X11Y59.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.386ns (1.124ns logic, 1.262ns route)
                                                       (47.1% logic, 52.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.480ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.377ns (Levels of Logic = 4)
  Clock Path Skew:      1.455ns (2.992 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X5Y56.B2       net (fanout=1)        0.706   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X5Y56.B        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X5Y56.A5       net (fanout=1)        0.066   N2
    SLICE_X5Y56.A        Tilo                  0.156   N2
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X8Y58.B3       net (fanout=8)        0.479   RLINK/RLB_DI<1>
    SLICE_X8Y58.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/_n0059_SW0
    SLICE_X8Y58.A5       net (fanout=1)        0.041   N42
    SLICE_X8Y58.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.377ns (1.085ns logic, 1.292ns route)
                                                       (45.6% logic, 54.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.493ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.382ns (Levels of Logic = 4)
  Clock Path Skew:      1.447ns (2.994 - 1.547)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.AMUX     Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X8Y60.B4       net (fanout=1)        0.520   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X8Y60.B        Tilo                  0.142   N8
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X9Y59.A5       net (fanout=1)        0.164   N8
    SLICE_X9Y59.A        Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X8Y59.D2       net (fanout=4)        0.395   RLINK/RLB_DI<4>
    SLICE_X8Y59.D        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.C5       net (fanout=1)        0.183   RLINK/CORE/B2CD/PWR_60_o_INV_190_o
    SLICE_X8Y59.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      2.382ns (1.120ns logic, 1.262ns route)
                                                       (47.0% logic, 53.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.481ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.368ns (Levels of Logic = 3)
  Clock Path Skew:      1.445ns (2.992 - 1.547)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.B        Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP
    SLICE_X11Y60.C5      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
    SLICE_X11Y60.CMUX    Tilo                  0.203   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X11Y60.A5      net (fanout=1)        0.409   N14
    SLICE_X11Y60.A       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X8Y58.A3       net (fanout=5)        0.376   RLINK/RLB_DI<7>
    SLICE_X8Y58.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.368ns (0.998ns logic, 1.370ns route)
                                                       (42.1% logic, 57.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.461ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.343ns (Levels of Logic = 4)
  Clock Path Skew:      1.440ns (2.987 - 1.547)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y61.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP
    SLICE_X11Y60.C3      net (fanout=1)        0.688   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<6>
    SLICE_X11Y60.C       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X11Y60.B4      net (fanout=1)        0.099   N12
    SLICE_X11Y60.B       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X8Y56.A6       net (fanout=5)        0.264   RLINK/RLB_DI<6>
    SLICE_X8Y56.A        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.D3       net (fanout=6)        0.153   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X8Y56.CLK      Tah         (-Th)    -0.190   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      2.343ns (1.139ns logic, 1.204ns route)
                                                       (48.6% logic, 51.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.608ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.507ns (Levels of Logic = 3)
  Clock Path Skew:      1.457ns (2.994 - 1.537)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X2Y55.AMUX     Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X7Y56.B1       net (fanout=1)        0.829   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X7Y56.B        Tilo                  0.156   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X8Y56.B5       net (fanout=1)        0.226   N0
    SLICE_X8Y56.B        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X9Y59.B5       net (fanout=6)        0.449   RLINK/RLB_DI<0>
    SLICE_X9Y59.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      2.507ns (1.003ns logic, 1.504ns route)
                                                       (40.0% logic, 60.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.458ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.380ns (Levels of Logic = 4)
  Clock Path Skew:      1.480ns (2.994 - 1.514)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y60.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X11Y60.C2      net (fanout=1)        0.450   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X11Y60.C       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X11Y60.B4      net (fanout=1)        0.099   N12
    SLICE_X11Y60.B       Tilo                  0.156   N12
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X8Y56.A6       net (fanout=5)        0.264   RLINK/RLB_DI<6>
    SLICE_X8Y56.A        Tilo                  0.142   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.D3       net (fanout=6)        0.403   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_25_o
    SLICE_X9Y59.CLK      Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      2.380ns (1.164ns logic, 1.216ns route)
                                                       (48.9% logic, 51.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.778ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.728ns (Levels of Logic = 1)
  Clock Path Skew:      -0.492ns (2.044 - 2.536)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.442ns

  Clock Uncertainty:          0.442ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.512ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y59.BMUX    Tshcko                0.495   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM1/DP
    SLICE_X15Y58.A4      net (fanout=1)        0.596   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<6>
    SLICE_X15Y58.AMUX    Tilo                  0.203   RLINK/CORE/RL/R_LREGS_state_proc_lnext.n_nakcode<1>4
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB71
    OLOGIC_X0Y52.D1      net (fanout=1)        1.024   RLINK/FX2CNTL/TXFIFO_DO<6>
    OLOGIC_X0Y52.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<6>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    -------------------------------------------------  ---------------------------
    Total                                      2.728ns (1.108ns logic, 1.620ns route)
                                                       (40.6% logic, 59.4% route)

--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_I_CLK100
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_I_CLK100                    |     10.000ns|      5.340ns|      9.758ns|            0|            0|            0|      7370960|
| TS_GEN_CLKSYS_USEDCM_CLKOUT0  |     15.625ns|     15.247ns|          N/A|            0|            0|      7370960|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock I_CLK100
---------------+------------+------------+------------+------------+------------------+--------+
               |Max Setup to|  Process   |Max Hold to |  Process   |                  | Clock  |
Source         | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s) | Phase  |
---------------+------------+------------+------------+------------+------------------+--------+
IO_MEM_DATA<0> |   -0.562(R)|      FAST  |    4.327(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<1> |   -0.615(R)|      FAST  |    4.380(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<2> |   -0.646(R)|      FAST  |    4.446(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<3> |   -0.611(R)|      FAST  |    4.376(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<4> |   -0.642(R)|      FAST  |    4.442(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<5> |   -0.557(R)|      FAST  |    4.322(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<6> |   -0.588(R)|      FAST  |    4.388(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<7> |   -0.551(R)|      FAST  |    4.316(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<8> |   -0.559(R)|      FAST  |    4.324(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<9> |   -0.590(R)|      FAST  |    4.390(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<10>|   -0.583(R)|      FAST  |    4.383(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<11>|   -0.612(R)|      FAST  |    4.377(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<12>|   -0.643(R)|      FAST  |    4.443(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<13>|   -0.570(R)|      FAST  |    4.335(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<14>|   -0.513(R)|      FAST  |    4.278(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<15>|   -0.544(R)|      FAST  |    4.344(R)|      SLOW  |CLK               |   0.000|
I_BTN<0>       |   -1.130(R)|      FAST  |    4.852(R)|      SLOW  |CLK               |   0.000|
I_BTN<1>       |   -1.034(R)|      FAST  |    4.721(R)|      SLOW  |CLK               |   0.000|
I_BTN<2>       |   -1.065(R)|      FAST  |    4.787(R)|      SLOW  |CLK               |   0.000|
I_BTN<3>       |   -1.111(R)|      FAST  |    4.833(R)|      SLOW  |CLK               |   0.000|
I_BTN<4>       |   -1.099(R)|      FAST  |    4.786(R)|      SLOW  |CLK               |   0.000|
I_FUSP_CTS_N   |   -0.583(R)|      FAST  |    4.383(R)|      SLOW  |CLK               |   0.000|
I_FUSP_RXD     |   -0.556(R)|      FAST  |    4.226(R)|      SLOW  |CLK               |   0.000|
I_RXD          |   -0.626(R)|      FAST  |    4.296(R)|      SLOW  |CLK               |   0.000|
I_SWI<0>       |   -0.541(R)|      FAST  |    4.341(R)|      SLOW  |CLK               |   0.000|
I_SWI<1>       |   -0.573(R)|      FAST  |    4.338(R)|      SLOW  |CLK               |   0.000|
I_SWI<2>       |   -0.604(R)|      FAST  |    4.404(R)|      SLOW  |CLK               |   0.000|
I_SWI<3>       |   -0.518(R)|      FAST  |    4.283(R)|      SLOW  |CLK               |   0.000|
I_SWI<4>       |   -0.549(R)|      FAST  |    4.349(R)|      SLOW  |CLK               |   0.000|
I_SWI<5>       |   -0.578(R)|      FAST  |    4.343(R)|      SLOW  |CLK               |   0.000|
I_SWI<6>       |   -0.609(R)|      FAST  |    4.409(R)|      SLOW  |CLK               |   0.000|
I_SWI<7>       |   -0.582(R)|      FAST  |    4.382(R)|      SLOW  |CLK               |   0.000|
---------------+------------+------------+------------+------------+------------------+--------+

Setup/Hold to clock I_FX2_IFCLK
--------------+------------+------------+------------+------------+------------------+--------+
              |Max Setup to|  Process   |Max Hold to |  Process   |                  | Clock  |
Source        | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s) | Phase  |
--------------+------------+------------+------------+------------+------------------+--------+
IO_FX2_DATA<0>|    0.976(R)|      SLOW  |    0.576(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<1>|    0.979(R)|      SLOW  |    0.573(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<2>|    0.979(R)|      SLOW  |    0.573(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<3>|    0.981(R)|      SLOW  |    0.571(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<4>|    0.981(R)|      SLOW  |    0.571(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<5>|    0.981(R)|      SLOW  |    0.571(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<6>|    0.981(R)|      SLOW  |    0.571(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<7>|    0.976(R)|      SLOW  |    0.576(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
I_FX2_FLAG<0> |    0.972(R)|      SLOW  |    0.580(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
I_FX2_FLAG<1> |    0.971(R)|      SLOW  |    0.581(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
I_FX2_FLAG<2> |    0.971(R)|      SLOW  |    0.581(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
--------------+------------+------------+------------+------------+------------------+--------+

Clock I_CLK100 to Pad
---------------+-----------------+------------+-----------------+------------+------------------+--------+
               |Max (slowest) clk|  Process   |Min (fastest) clk|  Process   |                  | Clock  |
Destination    |  (edge) to PAD  |   Corner   |  (edge) to PAD  |   Corner   |Internal Clock(s) | Phase  |
---------------+-----------------+------------+-----------------+------------+------------------+--------+
IO_MEM_DATA<0> |        11.711(R)|      SLOW  |         4.458(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<1> |        11.754(R)|      SLOW  |         4.501(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<2> |        11.754(R)|      SLOW  |         4.501(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<3> |        11.750(R)|      SLOW  |         4.497(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<4> |        11.750(R)|      SLOW  |         4.497(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<5> |        11.706(R)|      SLOW  |         4.453(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<6> |        11.706(R)|      SLOW  |         4.453(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<7> |        11.699(R)|      SLOW  |         4.446(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<8> |        11.707(R)|      SLOW  |         4.454(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<9> |        11.707(R)|      SLOW  |         4.454(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<10>|        11.700(R)|      SLOW  |         4.447(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<11>|        11.751(R)|      SLOW  |         4.498(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<12>|        11.751(R)|      SLOW  |         4.498(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<13>|        11.709(R)|      SLOW  |         4.456(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<14>|        11.661(R)|      SLOW  |         4.408(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<15>|        11.661(R)|      SLOW  |         4.408(R)|      FAST  |CLK               |   0.000|
O_ANO_N<0>     |        11.440(R)|      SLOW  |         4.306(R)|      FAST  |CLK               |   0.000|
O_ANO_N<1>     |        11.440(R)|      SLOW  |         4.306(R)|      FAST  |CLK               |   0.000|
O_ANO_N<2>     |        11.445(R)|      SLOW  |         4.311(R)|      FAST  |CLK               |   0.000|
O_ANO_N<3>     |        11.445(R)|      SLOW  |         4.311(R)|      FAST  |CLK               |   0.000|
O_FUSP_RTS_N   |        12.019(R)|      SLOW  |         4.851(R)|      FAST  |CLK               |   0.000|
O_FUSP_TXD     |        12.024(R)|      SLOW  |         4.856(R)|      FAST  |CLK               |   0.000|
O_LED<0>       |        11.572(R)|      SLOW  |         4.438(R)|      FAST  |CLK               |   0.000|
O_LED<1>       |        11.572(R)|      SLOW  |         4.438(R)|      FAST  |CLK               |   0.000|
O_LED<2>       |        11.571(R)|      SLOW  |         4.437(R)|      FAST  |CLK               |   0.000|
O_LED<3>       |        11.571(R)|      SLOW  |         4.437(R)|      FAST  |CLK               |   0.000|
O_LED<4>       |        11.499(R)|      SLOW  |         4.365(R)|      FAST  |CLK               |   0.000|
O_LED<5>       |        11.499(R)|      SLOW  |         4.365(R)|      FAST  |CLK               |   0.000|
O_LED<6>       |        11.549(R)|      SLOW  |         4.415(R)|      FAST  |CLK               |   0.000|
O_LED<7>       |        11.549(R)|      SLOW  |         4.415(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<0>  |        11.367(R)|      SLOW  |         4.237(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<1>  |        11.367(R)|      SLOW  |         4.237(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<2>  |        11.374(R)|      SLOW  |         4.244(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<3>  |        11.374(R)|      SLOW  |         4.244(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<4>  |        11.367(R)|      SLOW  |         4.237(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<5>  |        11.367(R)|      SLOW  |         4.237(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<6>  |        11.365(R)|      SLOW  |         4.235(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<7>  |        11.365(R)|      SLOW  |         4.235(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<8>  |        11.362(R)|      SLOW  |         4.232(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<9>  |        11.362(R)|      SLOW  |         4.232(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<10> |        11.371(R)|      SLOW  |         4.241(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<11> |        11.371(R)|      SLOW  |         4.241(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<12> |        11.368(R)|      SLOW  |         4.238(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<13> |        11.368(R)|      SLOW  |         4.238(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<14> |        11.365(R)|      SLOW  |         4.235(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<15> |        11.365(R)|      SLOW  |         4.235(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<16> |        11.363(R)|      SLOW  |         4.233(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<17> |        11.363(R)|      SLOW  |         4.233(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<18> |        11.363(R)|      SLOW  |         4.233(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<19> |        11.363(R)|      SLOW  |         4.233(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<20> |        11.367(R)|      SLOW  |         4.237(R)|      FAST  |CLK               |   0.000|
O_MEM_BE_N<0>  |        10.704(R)|      SLOW  |         3.613(R)|      FAST  |CLK               |   0.000|
O_MEM_BE_N<1>  |        10.704(R)|      SLOW  |         3.613(R)|      FAST  |CLK               |   0.000|
O_MEM_CE_N     |        10.705(R)|      SLOW  |         3.614(R)|      FAST  |CLK               |   0.000|
O_MEM_OE_N     |        10.692(R)|      SLOW  |         3.601(R)|      FAST  |CLK               |   0.000|
O_MEM_WE_N     |        18.512(F)|      SLOW  |        11.421(F)|      FAST  |CLK               |   7.812|
O_SEG_N<0>     |        11.433(R)|      SLOW  |         4.299(R)|      FAST  |CLK               |   0.000|
O_SEG_N<1>     |        11.433(R)|      SLOW  |         4.299(R)|      FAST  |CLK               |   0.000|
O_SEG_N<2>     |        11.438(R)|      SLOW  |         4.304(R)|      FAST  |CLK               |   0.000|
O_SEG_N<3>     |        11.438(R)|      SLOW  |         4.304(R)|      FAST  |CLK               |   0.000|
O_SEG_N<4>     |        11.440(R)|      SLOW  |         4.306(R)|      FAST  |CLK               |   0.000|
O_SEG_N<5>     |        11.440(R)|      SLOW  |         4.306(R)|      FAST  |CLK               |   0.000|
O_SEG_N<6>     |        11.442(R)|      SLOW  |         4.308(R)|      FAST  |CLK               |   0.000|
O_SEG_N<7>     |        11.442(R)|      SLOW  |         4.308(R)|      FAST  |CLK               |   0.000|
O_TXD          |        11.444(R)|      SLOW  |         4.310(R)|      FAST  |CLK               |   0.000|
---------------+-----------------+------------+-----------------+------------+------------------+--------+

Clock I_FX2_IFCLK to Pad
--------------+-----------------+------------+-----------------+------------+------------------+--------+
              |Max (slowest) clk|  Process   |Min (fastest) clk|  Process   |                  | Clock  |
Destination   |  (edge) to PAD  |   Corner   |  (edge) to PAD  |   Corner   |Internal Clock(s) | Phase  |
--------------+-----------------+------------+-----------------+------------+------------------+--------+
IO_FX2_DATA<0>|         7.865(R)|      SLOW  |         2.792(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<1>|         7.862(R)|      SLOW  |         2.789(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<2>|         7.862(R)|      SLOW  |         2.789(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<3>|         7.860(R)|      SLOW  |         2.787(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<4>|         7.860(R)|      SLOW  |         2.787(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<5>|         7.859(R)|      SLOW  |         2.786(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<6>|         7.859(R)|      SLOW  |         2.786(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<7>|         7.864(R)|      SLOW  |         2.791(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_FIFO<0> |         7.867(R)|      SLOW  |         2.902(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_FIFO<1> |         7.865(R)|      SLOW  |         2.900(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_PKTEND_N|         7.864(R)|      SLOW  |         2.899(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_SLOE_N  |         7.867(R)|      SLOW  |         2.902(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_SLRD_N  |         7.872(R)|      SLOW  |         2.907(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_SLWR_N  |         7.872(R)|      SLOW  |         2.907(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
--------------+-----------------+------------+-----------------+------------+------------------+--------+

Clock to Setup on destination clock I_CLK100
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
I_CLK100       |   15.247|         |    3.588|         |
I_FX2_IFCLK    |    6.330|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock I_FX2_IFCLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
I_CLK100       |    8.343|         |         |         |
I_FX2_IFCLK    |    9.034|         |         |         |
---------------+---------+---------+---------+---------+

OFFSET = IN 2 ns VALID 33 ns BEFORE COMP "I_FX2_IFCLK";
Worst Case Data Window 1.562; Ideal Clock Offset To Actual Clock 14.700; 
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
IO_FX2_DATA<0>    |    0.976(R)|      SLOW  |    0.576(R)|      SLOW  |    1.024|   30.424|      -14.700|
IO_FX2_DATA<1>    |    0.979(R)|      SLOW  |    0.573(R)|      SLOW  |    1.021|   30.427|      -14.703|
IO_FX2_DATA<2>    |    0.979(R)|      SLOW  |    0.573(R)|      SLOW  |    1.021|   30.427|      -14.703|
IO_FX2_DATA<3>    |    0.981(R)|      SLOW  |    0.571(R)|      SLOW  |    1.019|   30.429|      -14.705|
IO_FX2_DATA<4>    |    0.981(R)|      SLOW  |    0.571(R)|      SLOW  |    1.019|   30.429|      -14.705|
IO_FX2_DATA<5>    |    0.981(R)|      SLOW  |    0.571(R)|      SLOW  |    1.019|   30.429|      -14.705|
IO_FX2_DATA<6>    |    0.981(R)|      SLOW  |    0.571(R)|      SLOW  |    1.019|   30.429|      -14.705|
IO_FX2_DATA<7>    |    0.976(R)|      SLOW  |    0.576(R)|      SLOW  |    1.024|   30.424|      -14.700|
I_FX2_FLAG<0>     |    0.972(R)|      SLOW  |    0.580(R)|      SLOW  |    1.028|   30.420|      -14.696|
I_FX2_FLAG<1>     |    0.971(R)|      SLOW  |    0.581(R)|      SLOW  |    1.029|   30.419|      -14.695|
I_FX2_FLAG<2>     |    0.971(R)|      SLOW  |    0.581(R)|      SLOW  |    1.029|   30.419|      -14.695|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|       0.981|         -  |       0.581|         -  |    1.019|   30.419|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

OFFSET = OUT 20 ns AFTER COMP "I_CLK100";
Bus Skew: 7.820 ns; 
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
                                               |Max (slowest)|  Process   |Min (fastest)|  Process   |              |
PAD                                            | Delay (ns)  |   Corner   | Delay (ns)  |   Corner   |Edge Skew (ns)|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
IO_MEM_DATA<0>                                 |       11.711|      SLOW  |        4.458|      FAST  |         1.019|
IO_MEM_DATA<1>                                 |       11.754|      SLOW  |        4.501|      FAST  |         1.062|
IO_MEM_DATA<2>                                 |       11.754|      SLOW  |        4.501|      FAST  |         1.062|
IO_MEM_DATA<3>                                 |       11.750|      SLOW  |        4.497|      FAST  |         1.058|
IO_MEM_DATA<4>                                 |       11.750|      SLOW  |        4.497|      FAST  |         1.058|
IO_MEM_DATA<5>                                 |       11.706|      SLOW  |        4.453|      FAST  |         1.014|
IO_MEM_DATA<6>                                 |       11.706|      SLOW  |        4.453|      FAST  |         1.014|
IO_MEM_DATA<7>                                 |       11.699|      SLOW  |        4.446|      FAST  |         1.007|
IO_MEM_DATA<8>                                 |       11.707|      SLOW  |        4.454|      FAST  |         1.015|
IO_MEM_DATA<9>                                 |       11.707|      SLOW  |        4.454|      FAST  |         1.015|
IO_MEM_DATA<10>                                |       11.700|      SLOW  |        4.447|      FAST  |         1.008|
IO_MEM_DATA<11>                                |       11.751|      SLOW  |        4.498|      FAST  |         1.059|
IO_MEM_DATA<12>                                |       11.751|      SLOW  |        4.498|      FAST  |         1.059|
IO_MEM_DATA<13>                                |       11.709|      SLOW  |        4.456|      FAST  |         1.017|
IO_MEM_DATA<14>                                |       11.661|      SLOW  |        4.408|      FAST  |         0.969|
IO_MEM_DATA<15>                                |       11.661|      SLOW  |        4.408|      FAST  |         0.969|
O_ANO_N<0>                                     |       11.440|      SLOW  |        4.306|      FAST  |         0.748|
O_ANO_N<1>                                     |       11.440|      SLOW  |        4.306|      FAST  |         0.748|
O_ANO_N<2>                                     |       11.445|      SLOW  |        4.311|      FAST  |         0.753|
O_ANO_N<3>                                     |       11.445|      SLOW  |        4.311|      FAST  |         0.753|
O_FUSP_RTS_N                                   |       12.019|      SLOW  |        4.851|      FAST  |         1.327|
O_FUSP_TXD                                     |       12.024|      SLOW  |        4.856|      FAST  |         1.332|
O_LED<0>                                       |       11.572|      SLOW  |        4.438|      FAST  |         0.880|
O_LED<1>                                       |       11.572|      SLOW  |        4.438|      FAST  |         0.880|
O_LED<2>                                       |       11.571|      SLOW  |        4.437|      FAST  |         0.879|
O_LED<3>                                       |       11.571|      SLOW  |        4.437|      FAST  |         0.879|
O_LED<4>                                       |       11.499|      SLOW  |        4.365|      FAST  |         0.807|
O_LED<5>                                       |       11.499|      SLOW  |        4.365|      FAST  |         0.807|
O_LED<6>                                       |       11.549|      SLOW  |        4.415|      FAST  |         0.857|
O_LED<7>                                       |       11.549|      SLOW  |        4.415|      FAST  |         0.857|
O_MEM_ADDR<0>                                  |       11.367|      SLOW  |        4.237|      FAST  |         0.675|
O_MEM_ADDR<1>                                  |       11.367|      SLOW  |        4.237|      FAST  |         0.675|
O_MEM_ADDR<2>                                  |       11.374|      SLOW  |        4.244|      FAST  |         0.682|
O_MEM_ADDR<3>                                  |       11.374|      SLOW  |        4.244|      FAST  |         0.682|
O_MEM_ADDR<4>                                  |       11.367|      SLOW  |        4.237|      FAST  |         0.675|
O_MEM_ADDR<5>                                  |       11.367|      SLOW  |        4.237|      FAST  |         0.675|
O_MEM_ADDR<6>                                  |       11.365|      SLOW  |        4.235|      FAST  |         0.673|
O_MEM_ADDR<7>                                  |       11.365|      SLOW  |        4.235|      FAST  |         0.673|
O_MEM_ADDR<8>                                  |       11.362|      SLOW  |        4.232|      FAST  |         0.670|
O_MEM_ADDR<9>                                  |       11.362|      SLOW  |        4.232|      FAST  |         0.670|
O_MEM_ADDR<10>                                 |       11.371|      SLOW  |        4.241|      FAST  |         0.679|
O_MEM_ADDR<11>                                 |       11.371|      SLOW  |        4.241|      FAST  |         0.679|
O_MEM_ADDR<12>                                 |       11.368|      SLOW  |        4.238|      FAST  |         0.676|
O_MEM_ADDR<13>                                 |       11.368|      SLOW  |        4.238|      FAST  |         0.676|
O_MEM_ADDR<14>                                 |       11.365|      SLOW  |        4.235|      FAST  |         0.673|
O_MEM_ADDR<15>                                 |       11.365|      SLOW  |        4.235|      FAST  |         0.673|
O_MEM_ADDR<16>                                 |       11.363|      SLOW  |        4.233|      FAST  |         0.671|
O_MEM_ADDR<17>                                 |       11.363|      SLOW  |        4.233|      FAST  |         0.671|
O_MEM_ADDR<18>                                 |       11.363|      SLOW  |        4.233|      FAST  |         0.671|
O_MEM_ADDR<19>                                 |       11.363|      SLOW  |        4.233|      FAST  |         0.671|
O_MEM_ADDR<20>                                 |       11.367|      SLOW  |        4.237|      FAST  |         0.675|
O_MEM_BE_N<0>                                  |       10.704|      SLOW  |        3.613|      FAST  |         0.012|
O_MEM_BE_N<1>                                  |       10.704|      SLOW  |        3.613|      FAST  |         0.012|
O_MEM_CE_N                                     |       10.705|      SLOW  |        3.614|      FAST  |         0.013|
O_MEM_OE_N                                     |       10.692|      SLOW  |        3.601|      FAST  |         0.000|
O_MEM_WE_N                                     |       18.512|      SLOW  |       11.421|      FAST  |         7.820|
O_SEG_N<0>                                     |       11.433|      SLOW  |        4.299|      FAST  |         0.741|
O_SEG_N<1>                                     |       11.433|      SLOW  |        4.299|      FAST  |         0.741|
O_SEG_N<2>                                     |       11.438|      SLOW  |        4.304|      FAST  |         0.746|
O_SEG_N<3>                                     |       11.438|      SLOW  |        4.304|      FAST  |         0.746|
O_SEG_N<4>                                     |       11.440|      SLOW  |        4.306|      FAST  |         0.748|
O_SEG_N<5>                                     |       11.440|      SLOW  |        4.306|      FAST  |         0.748|
O_SEG_N<6>                                     |       11.442|      SLOW  |        4.308|      FAST  |         0.750|
O_SEG_N<7>                                     |       11.442|      SLOW  |        4.308|      FAST  |         0.750|
O_TXD                                          |       11.444|      SLOW  |        4.310|      FAST  |         0.752|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+

OFFSET = OUT 10 ns VALID 33 ns AFTER COMP "I_FX2_IFCLK";
Bus Skew: 0.013 ns; 
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
                                               |Max (slowest)|  Process   |Min (fastest)|  Process   |              |
PAD                                            | Delay (ns)  |   Corner   | Delay (ns)  |   Corner   |Edge Skew (ns)|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
IO_FX2_DATA<0>                                 |        7.865|      SLOW  |        2.792|      FAST  |         0.006|
IO_FX2_DATA<1>                                 |        7.862|      SLOW  |        2.789|      FAST  |         0.003|
IO_FX2_DATA<2>                                 |        7.862|      SLOW  |        2.789|      FAST  |         0.003|
IO_FX2_DATA<3>                                 |        7.860|      SLOW  |        2.787|      FAST  |         0.001|
IO_FX2_DATA<4>                                 |        7.860|      SLOW  |        2.787|      FAST  |         0.001|
IO_FX2_DATA<5>                                 |        7.859|      SLOW  |        2.786|      FAST  |         0.000|
IO_FX2_DATA<6>                                 |        7.859|      SLOW  |        2.786|      FAST  |         0.000|
IO_FX2_DATA<7>                                 |        7.864|      SLOW  |        2.791|      FAST  |         0.005|
O_FX2_FIFO<0>                                  |        7.867|      SLOW  |        2.902|      FAST  |         0.008|
O_FX2_FIFO<1>                                  |        7.865|      SLOW  |        2.900|      FAST  |         0.006|
O_FX2_PKTEND_N                                 |        7.864|      SLOW  |        2.899|      FAST  |         0.005|
O_FX2_SLOE_N                                   |        7.867|      SLOW  |        2.902|      FAST  |         0.008|
O_FX2_SLRD_N                                   |        7.872|      SLOW  |        2.907|      FAST  |         0.013|
O_FX2_SLWR_N                                   |        7.872|      SLOW  |        2.907|      FAST  |         0.013|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+


Timing summary:
---------------

Timing errors: 14  Score: 3607  (Setup/Max: 0, Hold: 3607)

Constraints cover 7375944 paths, 0 nets, and 31600 connections

Design statistics:
   Minimum period:  15.247ns{1}   (Maximum frequency:  65.587MHz)
   Maximum path delay from/to any node:   6.912ns
   Minimum input required time before clock:   0.981ns
   Minimum output required time after clock:  18.512ns


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Sat Mar 19 14:59:10 2016 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 510 MB



