Release 14.7 par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

athome::  Sat Mar 19 14:57:57 2016

par -w -ol high -xe n -intstyle xflow -mt 2 sys_w11a_n3_map.ncd sys_w11a_n3.ncd
sys_w11a_n3.pcf 


Constraints file: sys_w11a_n3.pcf.
Loading device for application Rf_Device from file '6slx16.nph' in environment
/mnt/data/opt/Xilinx/ISE/14.7/ISE_DS/ISE/.
   "sys_w11a_n3" is an NCD, version 3.2, device xc6slx16, package csg324, speed -2
WARNING:ConstraintSystem - The Offset constraint <OFFSET = IN 10 ns BEFORE COMP "I_CLK100";> [sys_w11a_n3.pcf(5088)], is
   specified without a duration.  This will result in a lack of hold time checks in timing reports.  If hold time checks
   are desired a duration value should be specified following the 'VALID' keyword.


Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.23 2013-10-13".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                 2,568 out of  18,224   14%
    Number used as Flip Flops:               2,566
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                2
  Number of Slice LUTs:                      5,304 out of   9,112   58%
    Number used as logic:                    5,101 out of   9,112   55%
      Number using O6 output only:           3,946
      Number using O5 output only:              97
      Number using O5 and O6:                1,058
      Number used as ROM:                        0
    Number used as Memory:                     181 out of   2,176    8%
      Number used as Dual Port RAM:            116
        Number using O6 output only:             8
        Number using O5 output only:             0
        Number using O5 and O6:                108
      Number used as Single Port RAM:           65
        Number using O6 output only:            30
        Number using O5 output only:             2
        Number using O5 and O6:                 33
      Number used as Shift Register:             0
    Number used exclusively as route-thrus:     22
      Number with same-slice register load:     12
      Number with same-slice carry load:        10
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                 1,818 out of   2,278   79%
  Number of MUXCYs used:                       560 out of   4,556   12%
  Number of LUT Flip Flop pairs used:        5,561
    Number with an unused Flip Flop:         3,181 out of   5,561   57%
    Number with an unused LUT:                 257 out of   5,561    4%
    Number of fully used LUT-FF pairs:       2,123 out of   5,561   38%
    Number of slice register sites lost
      to control set restrictions:               0 out of  18,224    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                       108 out of     232   46%
    Number of LOCed IOBs:                      108 out of     108  100%
    IOB Flip Flops:                            146

Specific Feature Utilization:
  Number of RAMB16BWERs:                        15 out of      32   46%
  Number of RAMB8BWERs:                          0 out of      64    0%
  Number of BUFIO2/BUFIO2_2CLKs:                 1 out of      32    3%
    Number used as BUFIO2s:                      1
    Number used as BUFIO2_2CLKs:                 0
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       2 out of      16   12%
    Number used as BUFGs:                        2
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     1 out of       4   25%
    Number used as DCMs:                         1
    Number used as DCM_CLKGENs:                  0
  Number of ILOGIC2/ISERDES2s:                  43 out of     248   17%
    Number used as ILOGIC2s:                    43
    Number used as ISERDES2s:                    0
  Number of IODELAY2/IODRP2/IODRP2_MCBs:        11 out of     248    4%
    Number used as IODELAY2s:                   11
    Number used as IODRP2s:                      0
    Number used as IODRP2_MCBs:                  0
  Number of OLOGIC2/OSERDES2s:                  79 out of     248   31%
    Number used as OLOGIC2s:                    79
    Number used as OSERDES2s:                    0
  Number of BSCANs:                              0 out of       4    0%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            1 out of      32    3%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

PAR will use up to 2 processors
WARNING:Timing:3402 - The Clock Modifying COMP, GEN_CLKSYS/USEDCM.DCM, has the attribute CLK_FEEDBACK set to NONE.  No phase relationship
   exists between the input and output clocks of this Clock Modifying COMP. Data paths between these clock domains must be constrained using
   FROM/TO constraints.
WARNING:Par:288 - The signal I_MEM_WAIT_IBUF has no load.  PAR will not attempt to route this signal.
Starting Multi-threaded Router


Phase  1  : 33341 unrouted;      REAL time: 14 secs 

Phase  2  : 30396 unrouted;      REAL time: 15 secs 

Phase  3  : 16291 unrouted;      REAL time: 25 secs 

Phase  4  : 16291 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 26 secs 

Updating file: sys_w11a_n3.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 

Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 39 secs 

Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 43 secs 
Total REAL time to Router completion: 43 secs 
Total CPU time to Router completion (all processors): 56 secs 

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 CLK |  BUFGMUX_X2Y3| No   | 1212 |  0.705     |  1.778      |
+---------------------+--------------+------+------+------------+-------------+
|   I_FX2_IFCLK_BUFGP |  BUFGMUX_X2Y9| No   |   51 |  0.634     |  1.710      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Number of Timing Constraints that were not applied: 1

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_GEN_CLKSYS_USEDCM_CLKOUT0 = PERIOD TIM | SETUP       |     0.378ns|    15.247ns|       0|           0
  EGRP "GEN_CLKSYS_USEDCM_CLKOUT0"          | HOLD        |     0.219ns|            |       0|           0
  TS_I_CLK100 / 0.64 HIGH 50%               |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  OFFSET = IN 2 ns VALID 33 ns BEFORE COMP  | SETUP       |     1.019ns|     0.981ns|       0|           0
  "I_FX2_IFCLK"                             | HOLD        |    30.419ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  OFFSET = OUT 20 ns AFTER COMP "I_CLK100"  | MAXDELAY    |     1.488ns|    18.512ns|       0|           0
----------------------------------------------------------------------------------------------------------
  OFFSET = OUT 10 ns VALID 33 ns AFTER COMP | MAXDELAY    |     2.128ns|     7.872ns|       0|           0
   "I_FX2_IFCLK"                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_CDC_FIFO = MAXDELAY FROM TIMEGRP "FFS( | SETUP       |     2.387ns|     2.613ns|       0|           0
  \"*FIFO/GC?/GRAY_*.CNT/R_DATA*\")" TO     | HOLD        |     0.491ns|            |       0|           0
       TIMEGRP "FFS(\"*FIFO/R_REG?_?addr_c* |             |            |            |        |            
  \")" 5 ns DATAPATHONLY                    |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_PAD_CLK = MAXDELAY FROM TIMEGRP "PADS( | MAXDELAY    |     3.088ns|     6.912ns|       0|           0
  I_CLK100)" TO TIMEGRP "TNM_CLK" 10        |             |            |            |        |            
    ns                                      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_I_CLK100 = PERIOD TIMEGRP "I_CLK100" 1 | MINLOWPULSE |     4.660ns|     5.340ns|       0|           0
  0 ns HIGH 50%                             |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_PAD_IFCLK = MAXDELAY FROM TIMEGRP "PAD | MAXDELAY    |     5.518ns|     4.482ns|       0|           0
  S(I_FX2_IFCLK)" TO TIMEGRP         "TNM_I |             |            |            |        |            
  FCLK" 10 ns                               |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  OFFSET = IN 10 ns BEFORE COMP "I_CLK100"  | SETUP       |    10.513ns|    -0.513ns|       0|           0
----------------------------------------------------------------------------------------------------------
  TS_I_FX2_IFCLK = PERIOD TIMEGRP "I_FX2_IF | SETUP       |    24.306ns|     9.034ns|       0|           0
  CLK" 33.34 ns HIGH 50%                    | HOLD        |     0.413ns|            |       0|           0
----------------------------------------------------------------------------------------------------------


Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_I_CLK100
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_I_CLK100                    |     10.000ns|      5.340ns|      9.758ns|            0|            0|            0|      7370960|
| TS_GEN_CLKSYS_USEDCM_CLKOUT0  |     15.625ns|     15.247ns|          N/A|            0|            0|      7370960|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 46 secs 
Total CPU time to PAR completion (all processors): 1 mins 

Peak Memory Usage:  876 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 5
Number of info messages: 0

Writing design to file sys_w11a_n3.ncd



PAR done!
