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Release 14.7 Trace  (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
 
/mnt/data/opt/Xilinx/ISE/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 3
-fastpaths -u 100 -intstyle xflow -xml sys_w11a_n3.twx -tsi sys_w11a_n3.tsi
sys_w11a_n3.ncd sys_w11a_n3.pcf


Design file:              sys_w11a_n3.ncd
Physical constraint file: sys_w11a_n3.pcf
Report level:             timespec interaction report
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********************************************************************************
*                                                                              *
* This timing constraint interaction report can be used to understand which    *
* timing constraints take precedence when two or more timing constraints cover *
* a common set of timing paths.                                                *
*                                                                              *
* Constraint coverage over a set of paths is based on the following precedence *
* order (lowest to highest precedence):                                        *
*                                                                              *
*   Unconstrained path analysis                                                *
*   PERIOD or FREQUENCY, allclocknets                                          *
*   PERIOD or FREQUENCY, time group                                            *
*   PERIOD or FREQUENCY, net                                                   *
*   OFFSET IN/OUT, global                                                      *
*   OFFSET IN/OUT, time group                                                  *
*   OFFSET IN/OUT, pad                                                         *
*   MAXDELAY path, with pre-defined FROM and TO groups                         *
*   MAXDELAY path, with user-defined FROM or TO group                          *
*   MAXDELAY path, with user-defined FROM and TO groups                        *
*   MAXDELAY path, with intermediate (THRU) points                             *
*   PATH definition                                                            *
*   TIG path                                                                   *
*                                                                              *
* When two or more timing constraints have the same precedence, an optional    *
* PRIORITY qualifier can be used to identify the constraint that should take   *
* precedence for path coverage. If no PRIORITY qualifier exists, the last      *
* constraint encountered in the constraint file will take precedence.          *
*                                                                              *
* The following report lists constraints interactions, where lower-priority    *
* constraints had paths removed due to higher-priority constraints. For each   *
* interaction, the higher-priority constraint and number of paths removed are  *
* listed.                                                                      *
*                                                                              *
* In addition, if two or more interacting constraints have a similar type, a   *
* set of potential constraint consolidations may be reported. It may be        *
* possible to reduce the memory and runtime required for timing analysis by    *
* combining similar constraints.                                               *
*                                                                              *
* A clock domain overlap report will be produced when multiple                 *
* period/frequency constraints are defined to cover the same synchronous       *
* destination elements. This overlap report displays the set of overlapping    *
* constraints in precedence order (lowest to highest precedence) along with    *
* the list of synchronous destination elements shared by those constraints.    *
* The destination elements are listed using their logical resource name        *
* followed parenthetically by their physical resource name and physical clock  *
* pin name.                                                                    *
*                                                                              *
* The clock domain overlap report can be used to detect and correct            *
* overlapping constraint specifications that may be unintentionally altering   *
* the desired clock domain membership and resultant timing analysis of a       *
* design.                                                                      *
*                                                                              *
********************************************************************************

Constraint Interaction Report
=============================

Constraint interactions for Unconstrained path analysis 
         32 paths removed by OFFSET = IN 10 ns BEFORE COMP "I_CLK100";
         11 paths removed by OFFSET = IN 2 ns VALID 33 ns BEFORE COMP "I_FX2_IFCLK";
         22 paths removed by OFFSET = OUT 10 ns VALID 33 ns AFTER COMP "I_FX2_IFCLK";
         81 paths removed by OFFSET = OUT 20 ns AFTER COMP "I_CLK100";
         20 paths removed by TS_CDC_FIFO = MAXDELAY FROM TIMEGRP "FFS(\"*FIFO/GC?/GRAY_*.CNT/R_DATA*\")" TO         TIMEGRP "FFS(\"*FIFO/R_REG?_?addr_c*\")" 5 ns DATAPATHONLY;
    7370956 paths removed by TS_GEN_CLKSYS_USEDCM_CLKOUT0 = PERIOD TIMEGRP "GEN_CLKSYS_USEDCM_CLKOUT0"         TS_I_CLK100 / 0.64 HIGH 50%;
       1534 paths removed by TS_I_FX2_IFCLK = PERIOD TIMEGRP "I_FX2_IFCLK" 33.34 ns HIGH 50%;
       2912 paths removed by TS_PAD_CLK = MAXDELAY FROM TIMEGRP "PADS(I_CLK100)" TO TIMEGRP "TNM_CLK" 10         ns;

  Consolidating the following similar constraints may reduce the memory and runtime required for timing analysis:
    OFFSET = IN 10 ns BEFORE COMP "I_CLK100";
    OFFSET = OUT 10 ns VALID 33 ns AFTER COMP "I_FX2_IFCLK";


Clock Domain Overlap Report
===========================

No overlap to report.


Timespec interaction analysis completed Sat Mar 19 14:59:10 2016
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