# 1 "sys_w11a_n2.ucf_cpp"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "/usr/include/stdc-predef.h" 1 3 4
# 1 "<command-line>" 2
# 1 "sys_w11a_n2.ucf_cpp"
## $Id: sys_w11a_n2.ucf_cpp 540 2013-10-13 18:42:50Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-10-13 540 1.1 add pad->clk constraints
## 2013-04-20 509 1.1 add fx2 support
## 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
## 2010-05-26 295 1.0 Initial version
##

NET "I_CLK50" TNM_NET = "I_CLK50";
TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns AFTER "I_CLK50";

## constrain pad->net clock delay
NET CLK TNM = TNM_CLK;
TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK50) TO TNM_CLK 10 ns;
NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK;
TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns;

## std board
##
# 1 "/home/walter/tmp/octest/trunk/rtl/bplib/nexys2/nexys2_pins.ucf" 1
## $Id: nexys2_pins.ucf 444 2011-12-25 10:04:58Z mueller $
##
## Pin locks for Nexys 2 core functionality (for 1200k FPGA)
## - internal RS232
## - human I/O (switches, buttons, leds, display)
## - cram
##
## Revision History:
## Date Rev Version Comment
## 2011-11-23 444 1.1 remove clksys output hack
## 2010-11-13 338 1.0.3 add O_CLKSYS (for DCM derived system clock)
## 2010-11-06 336 1.0.2 Rename CLK -> I_CLK50
## 2010-05-23 294 1.0.1 use ADV_N rather ADV
## 2010-05-16 291 1.0 Initial version
##
## Note: default is DRIVE=12 | SLEW=SLOW
##
## clocks --------------------------------------------------------------------
NET "I_CLK50" LOC = "b8" | IOSTANDARD=LVCMOS33;
##
## RS232 interface -----------------------------------------------------------
NET "I_RXD" LOC = "u6" | IOSTANDARD=LVCMOS33;
NET "O_TXD" LOC = "p9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW;
##
## switches and buttons ------------------------------------------------------
NET "I_SWI<0>" LOC = "g18" | IOSTANDARD=LVCMOS33;
NET "I_SWI<1>" LOC = "h18" | IOSTANDARD=LVCMOS33;
NET "I_SWI<2>" LOC = "k18" | IOSTANDARD=LVCMOS33;
NET "I_SWI<3>" LOC = "k17" | IOSTANDARD=LVCMOS33;
NET "I_SWI<4>" LOC = "l14" | IOSTANDARD=LVCMOS33;
NET "I_SWI<5>" LOC = "l13" | IOSTANDARD=LVCMOS33;
NET "I_SWI<6>" LOC = "n17" | IOSTANDARD=LVCMOS33;
NET "I_SWI<7>" LOC = "r17" | IOSTANDARD=LVCMOS33;
##
NET "I_BTN<0>" LOC = "b18" | IOSTANDARD=LVCMOS33;
NET "I_BTN<1>" LOC = "d18" | IOSTANDARD=LVCMOS33;
NET "I_BTN<2>" LOC = "e18" | IOSTANDARD=LVCMOS33;
NET "I_BTN<3>" LOC = "h13" | IOSTANDARD=LVCMOS33;
##
## LEDs ----------------------------------------------------------------------
NET "O_LED<0>" LOC = "j14" | IOSTANDARD=LVCMOS33;
NET "O_LED<1>" LOC = "j15" | IOSTANDARD=LVCMOS33;
NET "O_LED<2>" LOC = "k15" | IOSTANDARD=LVCMOS33;
NET "O_LED<3>" LOC = "k14" | IOSTANDARD=LVCMOS33;
NET "O_LED<4>" LOC = "e16" | IOSTANDARD=LVCMOS33;
NET "O_LED<5>" LOC = "p16" | IOSTANDARD=LVCMOS33;
NET "O_LED<6>" LOC = "e4" | IOSTANDARD=LVCMOS33;
NET "O_LED<7>" LOC = "p4" | IOSTANDARD=LVCMOS33;
NET "O_LED<*>" DRIVE=12 | SLEW=SLOW;
##
## 7 segment display ---------------------------------------------------------
NET "O_ANO_N<0>" LOC = "f17" | IOSTANDARD=LVCMOS33;
NET "O_ANO_N<1>" LOC = "h17" | IOSTANDARD=LVCMOS33;
NET "O_ANO_N<2>" LOC = "c18" | IOSTANDARD=LVCMOS33;
NET "O_ANO_N<3>" LOC = "f15" | IOSTANDARD=LVCMOS33;
NET "O_ANO_N<*>" DRIVE=12 | SLEW=SLOW;
##
NET "O_SEG_N<0>" LOC = "l18" | IOSTANDARD=LVCMOS33;
NET "O_SEG_N<1>" LOC = "f18" | IOSTANDARD=LVCMOS33;
NET "O_SEG_N<2>" LOC = "d17" | IOSTANDARD=LVCMOS33;
NET "O_SEG_N<3>" LOC = "d16" | IOSTANDARD=LVCMOS33;
NET "O_SEG_N<4>" LOC = "g14" | IOSTANDARD=LVCMOS33;
NET "O_SEG_N<5>" LOC = "j17" | IOSTANDARD=LVCMOS33;
NET "O_SEG_N<6>" LOC = "h14" | IOSTANDARD=LVCMOS33;
NET "O_SEG_N<7>" LOC = "c17" | IOSTANDARD=LVCMOS33;
NET "O_SEG_N<*>" DRIVE=12 | SLEW=SLOW;
##
## CRAM ----------------------------------------------------------------------
NET "O_MEM_CE_N" LOC = "r6" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_WE_N" LOC = "n7" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_OE_N" LOC = "t2" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_MEM_BE_N<0>" LOC = "k5" | IOSTANDARD=LVCMOS33;
NET "O_MEM_BE_N<1>" LOC = "k4" | IOSTANDARD=LVCMOS33;
NET "O_MEM_BE_N<*>" DRIVE=12 | SLEW=FAST;
##
NET "O_MEM_ADV_N" LOC = "j4" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_CLK" LOC = "h5" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_CRE" LOC = "p7" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "I_MEM_WAIT" LOC = "f5" | IOSTANDARD=LVCMOS33 | PULLDOWN;
##
NET "O_MEM_ADDR<0>" LOC = "j1" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<1>" LOC = "j2" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<2>" LOC = "h4" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<3>" LOC = "h1" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<4>" LOC = "h2" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<5>" LOC = "j5" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<6>" LOC = "h3" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<7>" LOC = "h6" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<8>" LOC = "f1" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<9>" LOC = "g3" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<10>" LOC = "g6" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<11>" LOC = "g5" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<12>" LOC = "g4" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<13>" LOC = "f2" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<14>" LOC = "e1" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<15>" LOC = "m5" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<16>" LOC = "e2" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<17>" LOC = "c2" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<18>" LOC = "c1" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<19>" LOC = "d2" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<20>" LOC = "k3" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<21>" LOC = "d1" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<22>" LOC = "k6" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<*>" DRIVE=6 | SLEW=FAST;
##
NET "IO_MEM_DATA<0>" LOC = "l1" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<1>" LOC = "l4" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<2>" LOC = "l6" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<3>" LOC = "m4" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<4>" LOC = "n5" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<5>" LOC = "p1" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<6>" LOC = "p2" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<7>" LOC = "r2" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<8>" LOC = "l3" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<9>" LOC = "l5" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<10>" LOC = "m3" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<11>" LOC = "m6" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<12>" LOC = "l2" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<13>" LOC = "n4" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<14>" LOC = "r3" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<15>" LOC = "t1" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER;
##
## Flash ---------------------------------------------------------------------
NET "O_FLA_CE_N" LOC = "r5" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW;
##
# 25 "sys_w11a_n2.ucf_cpp" 2
##
## Pmod B0 - RS232
##
# 1 "/home/walter/tmp/octest/trunk/rtl/bplib/nexys2/nexys2_pins_pmb0_rs232.ucf" 1
## $Id: nexys2_pins_pmb0_rs232.ucf 297 2010-05-30 20:10:16Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2010-05-28 295 1.0 Initial version
##
## Pmod connector B top / usage RS232 for FTDI USB serport -------------------
##
NET "O_FUSP_RTS_N" LOC = "m13" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
NET "I_FUSP_CTS_N" LOC = "r18" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "I_FUSP_RXD" LOC = "r15" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "O_FUSP_TXD" LOC = "t17" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
# 29 "sys_w11a_n2.ucf_cpp" 2
##
## Cypress FX2
##
# 1 "/home/walter/tmp/octest/trunk/rtl/bplib/nexys2/nexys2_pins_fx2.ucf" 1
## $Id: nexys2_pins_fx2.ucf 397 2011-07-24 09:43:07Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-07-05 389 1.0 Initial version
##
## Cypress EZ-USB FX2 Interface ----------------------------------------------
##
##
NET "I_FX2_IFCLK" LOC = "t15" | IOSTANDARD=LVCMOS33;
##
NET "IO_FX2_DATA<0>" LOC = "r14" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<1>" LOC = "r13" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<2>" LOC = "p13" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<3>" LOC = "t12" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<4>" LOC = "n11" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<5>" LOC = "r11" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<6>" LOC = "p10" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<7>" LOC = "r10" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER;
##
NET "O_FX2_SLWR_N" LOC = "v9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_FX2_SLRD_N" LOC = "n9" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_FX2_SLOE_N" LOC = "v15" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_FX2_PKTEND_N" LOC = "v12" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_FX2_FIFO<0>" LOC = "t14" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_FX2_FIFO<1>" LOC = "v13" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
## assume that PA.7 is used a FLAGD (and not as SLCS#)
NET "I_FX2_FLAG<0>" LOC = "v14" | IOSTANDARD=LVCMOS33; ## flag a (program)
NET "I_FX2_FLAG<1>" LOC = "u14" | IOSTANDARD=LVCMOS33; ## flag b (full)
NET "I_FX2_FLAG<2>" LOC = "v16" | IOSTANDARD=LVCMOS33; ## flag c (empty)
NET "I_FX2_FLAG<3>" LOC = "t16" | IOSTANDARD=LVCMOS33; ## flag d (slcs)
##
# 33 "sys_w11a_n2.ucf_cpp" 2
# 1 "/home/walter/tmp/octest/trunk/rtl/bplib/nexys2/nexys2_time_fx2_ic.ucf" 1
## $Id: nexys2_time_fx2_ic.ucf 537 2013-10-06 09:06:23Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-10-05 537 1.1 add VALID for hold time check
## 2012-01-01 448 1.0 Initial version
##
## timing rules for a 30 MHz internal clock design:
## Period: 30 MHz
## clk->out: longest setup time in FX2 is t_SRD (clk->SLRD) of 18.7 ns
## clk->out < 33.3-18.7 = 14.6 ns
## --> use 10 ns
##

## The nexys2 board has unfortunately the FX2 IFCLK *not* connected to a
## clock capable pin -> not ok when FX2 uses internal clock. So allow par
## to route from a 'normal' pin to a clock net. Not nice, compromizes the
## timing, but unavoidable on nexys2 (Note: nexys3 and atlys are ok).
## In practice IFCLK to pad times are quite similar on nexys2 and nexys3...

NET "I_FX2_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE;

##
NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK";
TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %;
OFFSET = IN 2.5 ns VALID 33 ns BEFORE "I_FX2_IFCLK";
OFFSET = OUT 10 ns VALID 33 ns AFTER "I_FX2_IFCLK";
# 33 "sys_w11a_n2.ucf_cpp" 2
