--------------------------------------------------------------------------------
Release 14.7 Trace  (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

/mnt/data/opt/Xilinx/ISE/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 3
-fastpaths -u 25 -intstyle xflow -xml sys_w11a_n2.twx -tsi sys_w11a_n2.tsi
sys_w11a_n2.ncd sys_w11a_n2.pcf

Design file:              sys_w11a_n2.ncd
Physical constraint file: sys_w11a_n2.pcf
Device,package,speed:     xc3s1200e,fg320,-4 (PRODUCTION 1.27 2013-10-13)
Report level:             verbose report
                          unconstrained path report, limited to 25 items

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

WARNING:Timing:3391 - Timing constraint OFFSET = IN 10 ns BEFORE COMP 
   "I_CLK50"; does not specify a data valid duration and will not be hold 
   checked. To enable hold checking on this offset constraint please specify a 
   data valid duration using the VALID <duration> option.
INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more 
   information, see the TSI report.  Please consult the Xilinx Command Line 
   Tools User Guide for information on generating a TSI report.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter 
   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock 
   Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 
   'Phase Error' calculations, these terms will be zero in the Clock 
   Uncertainty calculation.  Please make appropriate modification to 
   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase 
   Error.

================================================================================
Timing constraint: TS_I_CLK50 = PERIOD TIMEGRP "I_CLK50" 20 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   6.000ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_I_CLK50 = PERIOD TIMEGRP "I_CLK50" 20 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 14.000ns (period - (min low pulse limit / (low pulse / period)))
  Period: 20.000ns
  Low pulse: 10.000ns
  Low pulse limit: 3.000ns (Tdcmpw_CLKIN_50_100)
  Physical resource: DCM/DCM1.DCM/CLKIN
  Logical resource: DCM/DCM1.DCM/CLKIN
  Location pin: DCM_X1Y3.CLKIN
  Clock network: I_CLK50_IBUFG
--------------------------------------------------------------------------------
Slack: 14.000ns (period - (min high pulse limit / (high pulse / period)))
  Period: 20.000ns
  High pulse: 10.000ns
  High pulse limit: 3.000ns (Tdcmpw_CLKIN_50_100)
  Physical resource: DCM/DCM1.DCM/CLKIN
  Logical resource: DCM/DCM1.DCM/CLKIN
  Location pin: DCM_X1Y3.CLKIN
  Clock network: I_CLK50_IBUFG
--------------------------------------------------------------------------------
Slack: 16.164ns (period - min period limit)
  Period: 19.231ns
  Min period limit: 3.067ns (326.052MHz) (Tdcmpfx)
  Physical resource: DCM/DCM1.DCM/CLKFX
  Logical resource: DCM/DCM1.DCM/CLKFX
  Location pin: DCM_X1Y3.CLKFX
  Clock network: CLK1
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_PAD_CLK = MAXDELAY FROM TIMEGRP "PADS(I_CLK50)" TO 
TIMEGRP "TNM_CLK" 10 ns;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 3365 paths analyzed, 3365 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   4.698ns.
--------------------------------------------------------------------------------
Slack (slowest paths):  5.302ns (requirement - data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/HIO/IOB_SWI/R_DI_6 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.698ns (Levels of Logic = 3)

  Maximum Data Path: I_CLK50 to HIO/HIO/HIO/IOB_SWI/R_DI_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.721   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.017   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.398   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.457   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    N17.ICLK1            net (fanout=2225)     0.379   CLK
    -------------------------------------------------  ---------------------------
    Total                                      4.698ns (3.200ns logic, 1.498ns route)
                                                       (68.1% logic, 31.9% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  5.303ns (requirement - data path)
  Source:               I_CLK50 (PAD)
  Destination:          SRAM_CTL/IOB_MEM_DATA/R_DO_5 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.697ns (Levels of Logic = 3)

  Maximum Data Path: I_CLK50 to SRAM_CTL/IOB_MEM_DATA/R_DO_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.721   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.017   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.398   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.457   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    P1.OTCLK1            net (fanout=2225)     0.378   CLK
    -------------------------------------------------  ---------------------------
    Total                                      4.697ns (3.200ns logic, 1.497ns route)
                                                       (68.1% logic, 31.9% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  5.303ns (requirement - data path)
  Source:               I_CLK50 (PAD)
  Destination:          SRAM_CTL/IOB_MEM_DATA/R_DI_5 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.697ns (Levels of Logic = 3)

  Maximum Data Path: I_CLK50 to SRAM_CTL/IOB_MEM_DATA/R_DI_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.721   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.017   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.398   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.457   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    P1.ICLK1             net (fanout=2225)     0.378   CLK
    -------------------------------------------------  ---------------------------
    Total                                      4.697ns (3.200ns logic, 1.497ns route)
                                                       (68.1% logic, 31.9% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_PAD_CLK = MAXDELAY FROM TIMEGRP "PADS(I_CLK50)" TO TIMEGRP "TNM_CLK" 10 ns;
--------------------------------------------------------------------------------
Delay (hold path):      3.686ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          IBDR_SYS/DL11_1.I0/R_REGS.xbuf_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.686ns (Levels of Logic = 3)

  Minimum Data Path: I_CLK50 to IBDR_SYS/DL11_1.I0/R_REGS.xbuf_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.577   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.014   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.319   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.166   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    SLICE_X63Y75.CLK     net (fanout=2225)     0.144   CLK
    -------------------------------------------------  ---------------------------
    Total                                      3.686ns (2.646ns logic, 1.040ns route)
                                                       (71.8% logic, 28.2% route)

--------------------------------------------------------------------------------
Delay (hold path):      3.686ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          IBDR_SYS/DL11_1.I0/R_REGS.xbuf_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.686ns (Levels of Logic = 3)

  Minimum Data Path: I_CLK50 to IBDR_SYS/DL11_1.I0/R_REGS.xbuf_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.577   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.014   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.319   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.166   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    SLICE_X63Y75.CLK     net (fanout=2225)     0.144   CLK
    -------------------------------------------------  ---------------------------
    Total                                      3.686ns (2.646ns logic, 1.040ns route)
                                                       (71.8% logic, 28.2% route)

--------------------------------------------------------------------------------
Delay (hold path):      3.686ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          SYS70/W11A/DPATH/GPR/R_PC_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      3.686ns (Levels of Logic = 3)

  Minimum Data Path: I_CLK50 to SYS70/W11A/DPATH/GPR/R_PC_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.577   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.014   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.319   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.166   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    SLICE_X28Y44.CLK     net (fanout=2225)     0.144   CLK
    -------------------------------------------------  ---------------------------
    Total                                      3.686ns (2.646ns logic, 1.040ns route)
                                                       (71.8% logic, 28.2% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_PAD_IFCLK = MAXDELAY FROM TIMEGRP "PADS(I_FX2_IFCLK)" TO 
TIMEGRP         "TNM_IFCLK" 10 ns;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 144 paths analyzed, 144 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   4.931ns.
--------------------------------------------------------------------------------
Slack (slowest paths):  5.069ns (requirement - data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.931ns (Levels of Logic = 2)

  Maximum Data Path: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.726   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.378   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.457   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    V16.ICLK1            net (fanout=84)       0.370   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.931ns (3.183ns logic, 1.748ns route)
                                                       (64.6% logic, 35.4% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  5.071ns (requirement - data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_G (RAM)
  Requirement:          10.000ns
  Data Path Delay:      4.929ns (Levels of Logic = 2)

  Maximum Data Path: I_FX2_IFCLK to RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_G
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.726   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.378   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.457   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    SLICE_X88Y2.CLK      net (fanout=84)       0.368   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.929ns (3.183ns logic, 1.746ns route)
                                                       (64.6% logic, 35.4% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  5.071ns (requirement - data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F (RAM)
  Requirement:          10.000ns
  Data Path Delay:      4.929ns (Levels of Logic = 2)

  Maximum Data Path: I_FX2_IFCLK to RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.726   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.378   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.457   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    SLICE_X88Y2.CLK      net (fanout=84)       0.368   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.929ns (3.183ns logic, 1.746ns route)
                                                       (64.6% logic, 35.4% route)

--------------------------------------------------------------------------------

Fastest Paths: TS_PAD_IFCLK = MAXDELAY FROM TIMEGRP "PADS(I_FX2_IFCLK)" TO TIMEGRP
        "TNM_IFCLK" 10 ns;
--------------------------------------------------------------------------------
Delay (hold path):      3.947ns (data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0.SLICEM_G (RAM)
  Requirement:          0.000ns
  Data Path Delay:      3.947ns (Levels of Logic = 2)

  Minimum Data Path: I_FX2_IFCLK to RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0.SLICEM_G
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.466   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.103   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.166   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    SLICE_X62Y4.CLK      net (fanout=84)       0.212   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.947ns (2.632ns logic, 1.315ns route)
                                                       (66.7% logic, 33.3% route)

--------------------------------------------------------------------------------
Delay (hold path):      3.947ns (data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0.SLICEM_F (RAM)
  Requirement:          0.000ns
  Data Path Delay:      3.947ns (Levels of Logic = 2)

  Minimum Data Path: I_FX2_IFCLK to RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0.SLICEM_F
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.466   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.103   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.166   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    SLICE_X62Y4.CLK      net (fanout=84)       0.212   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.947ns (2.632ns logic, 1.315ns route)
                                                       (66.7% logic, 33.3% route)

--------------------------------------------------------------------------------
Delay (hold path):      3.947ns (data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0.WE (RAM)
  Requirement:          0.000ns
  Data Path Delay:      3.947ns (Levels of Logic = 2)

  Minimum Data Path: I_FX2_IFCLK to RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0.WE
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.466   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.103   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.166   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    SLICE_X62Y4.CLK      net (fanout=84)       0.212   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.947ns (2.632ns logic, 1.315ns route)
                                                       (66.7% logic, 33.3% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_I_FX2_IFCLK = PERIOD TIMEGRP "I_FX2_IFCLK" 33.34 ns HIGH 
50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 1699 paths analyzed, 432 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   8.719ns.
--------------------------------------------------------------------------------
Slack (setup path):     24.621ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RLINK/FX2CNTL/R_REGS.ccnt_2 (FF)
  Destination:          RLINK/FX2CNTL/R_REGS.ccnt_1 (FF)
  Requirement:          33.340ns
  Data Path Delay:      8.719ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/R_REGS.ccnt_2 to RLINK/FX2CNTL/R_REGS.ccnt_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X70Y0.YQ       Tcko                  0.652   RLINK/FX2CNTL/R_REGS.ccnt_3
                                                       RLINK/FX2CNTL/R_REGS.ccnt_2
    SLICE_X68Y1.G4       net (fanout=6)        1.673   RLINK/FX2CNTL/R_REGS.ccnt_2
    SLICE_X68Y1.X        Tif5x                 1.152   RLINK/FX2CNTL/cc_done_cmp_eq0000
                                                       RLINK/FX2CNTL/cc_done_cmp_eq00001
                                                       RLINK/FX2CNTL/cc_done_cmp_eq0000_f5
    SLICE_X67Y2.G2       net (fanout=9)        0.720   RLINK/FX2CNTL/cc_done_cmp_eq0000
    SLICE_X67Y2.Y        Tilo                  0.704   RLINK/FX2CNTL/FX2_SLWR_N
                                                       RLINK/FX2CNTL/TXFIFO_HOLD_SW0
    SLICE_X67Y2.F3       net (fanout=2)        0.044   N801
    SLICE_X67Y2.X        Tilo                  0.704   RLINK/FX2CNTL/FX2_SLWR_N
                                                       RLINK/FX2CNTL/TXFIFO_HOLD
    SLICE_X70Y1.F4       net (fanout=10)       0.619   RLINK/FX2CNTL/FX2_SLWR_N
    SLICE_X70Y1.X        Tilo                  0.759   RLINK/FX2CNTL/R_REGS.rxpipe2
                                                       RLINK/FX2CNTL/R_REGS_ccnt_and0000
    SLICE_X71Y1.CE       net (fanout=3)        1.137   RLINK/FX2CNTL/R_REGS_ccnt_and0000
    SLICE_X71Y1.CLK      Tceck                 0.555   RLINK/FX2CNTL/R_REGS.ccnt_1
                                                       RLINK/FX2CNTL/R_REGS.ccnt_1
    -------------------------------------------------  ---------------------------
    Total                                      8.719ns (4.526ns logic, 4.193ns route)
                                                       (51.9% logic, 48.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     24.621ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RLINK/FX2CNTL/R_REGS.ccnt_2 (FF)
  Destination:          RLINK/FX2CNTL/R_REGS.ccnt_4 (FF)
  Requirement:          33.340ns
  Data Path Delay:      8.719ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/R_REGS.ccnt_2 to RLINK/FX2CNTL/R_REGS.ccnt_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X70Y0.YQ       Tcko                  0.652   RLINK/FX2CNTL/R_REGS.ccnt_3
                                                       RLINK/FX2CNTL/R_REGS.ccnt_2
    SLICE_X68Y1.G4       net (fanout=6)        1.673   RLINK/FX2CNTL/R_REGS.ccnt_2
    SLICE_X68Y1.X        Tif5x                 1.152   RLINK/FX2CNTL/cc_done_cmp_eq0000
                                                       RLINK/FX2CNTL/cc_done_cmp_eq00001
                                                       RLINK/FX2CNTL/cc_done_cmp_eq0000_f5
    SLICE_X67Y2.G2       net (fanout=9)        0.720   RLINK/FX2CNTL/cc_done_cmp_eq0000
    SLICE_X67Y2.Y        Tilo                  0.704   RLINK/FX2CNTL/FX2_SLWR_N
                                                       RLINK/FX2CNTL/TXFIFO_HOLD_SW0
    SLICE_X67Y2.F3       net (fanout=2)        0.044   N801
    SLICE_X67Y2.X        Tilo                  0.704   RLINK/FX2CNTL/FX2_SLWR_N
                                                       RLINK/FX2CNTL/TXFIFO_HOLD
    SLICE_X70Y1.F4       net (fanout=10)       0.619   RLINK/FX2CNTL/FX2_SLWR_N
    SLICE_X70Y1.X        Tilo                  0.759   RLINK/FX2CNTL/R_REGS.rxpipe2
                                                       RLINK/FX2CNTL/R_REGS_ccnt_and0000
    SLICE_X71Y0.CE       net (fanout=3)        1.137   RLINK/FX2CNTL/R_REGS_ccnt_and0000
    SLICE_X71Y0.CLK      Tceck                 0.555   RLINK/FX2CNTL/R_REGS.ccnt_4
                                                       RLINK/FX2CNTL/R_REGS.ccnt_4
    -------------------------------------------------  ---------------------------
    Total                                      8.719ns (4.526ns logic, 4.193ns route)
                                                       (51.9% logic, 48.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     24.621ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RLINK/FX2CNTL/R_REGS.ccnt_2 (FF)
  Destination:          RLINK/FX2CNTL/R_REGS.ccnt_0 (FF)
  Requirement:          33.340ns
  Data Path Delay:      8.719ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/R_REGS.ccnt_2 to RLINK/FX2CNTL/R_REGS.ccnt_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X70Y0.YQ       Tcko                  0.652   RLINK/FX2CNTL/R_REGS.ccnt_3
                                                       RLINK/FX2CNTL/R_REGS.ccnt_2
    SLICE_X68Y1.G4       net (fanout=6)        1.673   RLINK/FX2CNTL/R_REGS.ccnt_2
    SLICE_X68Y1.X        Tif5x                 1.152   RLINK/FX2CNTL/cc_done_cmp_eq0000
                                                       RLINK/FX2CNTL/cc_done_cmp_eq00001
                                                       RLINK/FX2CNTL/cc_done_cmp_eq0000_f5
    SLICE_X67Y2.G2       net (fanout=9)        0.720   RLINK/FX2CNTL/cc_done_cmp_eq0000
    SLICE_X67Y2.Y        Tilo                  0.704   RLINK/FX2CNTL/FX2_SLWR_N
                                                       RLINK/FX2CNTL/TXFIFO_HOLD_SW0
    SLICE_X67Y2.F3       net (fanout=2)        0.044   N801
    SLICE_X67Y2.X        Tilo                  0.704   RLINK/FX2CNTL/FX2_SLWR_N
                                                       RLINK/FX2CNTL/TXFIFO_HOLD
    SLICE_X70Y1.F4       net (fanout=10)       0.619   RLINK/FX2CNTL/FX2_SLWR_N
    SLICE_X70Y1.X        Tilo                  0.759   RLINK/FX2CNTL/R_REGS.rxpipe2
                                                       RLINK/FX2CNTL/R_REGS_ccnt_and0000
    SLICE_X71Y1.CE       net (fanout=3)        1.137   RLINK/FX2CNTL/R_REGS_ccnt_and0000
    SLICE_X71Y1.CLK      Tceck                 0.555   RLINK/FX2CNTL/R_REGS.ccnt_1
                                                       RLINK/FX2CNTL/R_REGS.ccnt_0
    -------------------------------------------------  ---------------------------
    Total                                      8.719ns (4.526ns logic, 4.193ns route)
                                                       (51.9% logic, 48.1% route)

--------------------------------------------------------------------------------

Hold Paths: TS_I_FX2_IFCLK = PERIOD TIMEGRP "I_FX2_IFCLK" 33.34 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.930ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_1 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_s_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.930ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 33.340ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_1 to RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_s_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X55Y4.XQ       Tcko                  0.473   RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_1
                                                       RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_1
    SLICE_X55Y5.BX       net (fanout=1)        0.364   RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_1
    SLICE_X55Y5.CLK      Tckdi       (-Th)    -0.093   RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_s_1
                                                       RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_s_1
    -------------------------------------------------  ---------------------------
    Total                                      0.930ns (0.566ns logic, 0.364ns route)
                                                       (60.9% logic, 39.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.931ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_1 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_s_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.931ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 33.340ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_1 to RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_s_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X74Y7.XQ       Tcko                  0.474   RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_1
                                                       RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_1
    SLICE_X75Y6.BX       net (fanout=1)        0.364   RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_1
    SLICE_X75Y6.CLK      Tckdi       (-Th)    -0.093   RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_s_1
                                                       RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_s_1
    -------------------------------------------------  ---------------------------
    Total                                      0.931ns (0.567ns logic, 0.364ns route)
                                                       (60.9% logic, 39.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.989ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_4 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_s_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.999ns (Levels of Logic = 0)
  Clock Path Skew:      0.010ns (0.059 - 0.049)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 33.340ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_4 to RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_s_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X71Y4.YQ       Tcko                  0.470   RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_4
                                                       RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_4
    SLICE_X72Y7.BY       net (fanout=1)        0.377   RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_4
    SLICE_X72Y7.CLK      Tckdi       (-Th)    -0.152   RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_s_4
                                                       RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_s_4
    -------------------------------------------------  ---------------------------
    Total                                      0.999ns (0.622ns logic, 0.377ns route)
                                                       (62.3% logic, 37.7% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_I_FX2_IFCLK = PERIOD TIMEGRP "I_FX2_IFCLK" 33.34 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 31.326ns (period - (min low pulse limit / (low pulse / period)))
  Period: 33.340ns
  Low pulse: 16.670ns
  Low pulse limit: 1.007ns (Twpl)
  Physical resource: RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>/CLK
  Logical resource: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F/WS
  Location pin: SLICE_X88Y2.CLK
  Clock network: I_FX2_IFCLK_BUFGP
--------------------------------------------------------------------------------
Slack: 31.326ns (period - (min high pulse limit / (high pulse / period)))
  Period: 33.340ns
  High pulse: 16.670ns
  High pulse limit: 1.007ns (Twph)
  Physical resource: RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>/CLK
  Logical resource: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F/WS
  Location pin: SLICE_X88Y2.CLK
  Clock network: I_FX2_IFCLK_BUFGP
--------------------------------------------------------------------------------
Slack: 31.326ns (period - min period limit)
  Period: 33.340ns
  Min period limit: 2.014ns (496.524MHz) (Tcp)
  Physical resource: RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>/CLK
  Logical resource: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F/WS
  Location pin: SLICE_X88Y2.CLK
  Clock network: I_FX2_IFCLK_BUFGP
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_CLK1 = PERIOD TIMEGRP "CLK1" TS_I_CLK50 / 1.04 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 3146961 paths analyzed, 13973 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is  19.190ns.
--------------------------------------------------------------------------------
Slack (setup path):     0.040ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SYS70/W11A/DPATH/R_IREG_3 (FF)
  Destination:          SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[0].MEM/F.S0 (RAM)
  Requirement:          19.230ns
  Data Path Delay:      19.190ns (Levels of Logic = 16)
  Clock Path Skew:      0.000ns
  Source Clock:         CLK rising at 0.000ns
  Destination Clock:    CLK rising at 19.230ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: SYS70/W11A/DPATH/R_IREG_3 to SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[0].MEM/F.S0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y57.XQ      Tcko                  0.592   SYS70/W11A/DPATH/R_IREG<3>
                                                       SYS70/W11A/DPATH/R_IREG_3
    SLICE_X27Y64.F2      net (fanout=36)       1.190   SYS70/W11A/DPATH/R_IREG<3>
    SLICE_X27Y64.X       Tilo                  0.704   SYS70/W11A/SEQ/VM_CNTL_dspace40
                                                       SYS70/W11A/SEQ/VM_CNTL_dspace40
    SLICE_X29Y64.F2      net (fanout=1)        0.383   SYS70/W11A/SEQ/VM_CNTL_dspace40
    SLICE_X29Y64.X       Tilo                  0.704   SYS70/W11A/SEQ/VM_CNTL_dspace51
                                                       SYS70/W11A/SEQ/VM_CNTL_dspace51
    SLICE_X33Y66.F2      net (fanout=1)        0.687   SYS70/W11A/SEQ/VM_CNTL_dspace51
    SLICE_X33Y66.X       Tilo                  0.704   SYS70/DMCMON.I0/R_REGS.vm_dspace
                                                       SYS70/W11A/SEQ/VM_CNTL_dspace115
    SLICE_X43Y56.G2      net (fanout=9)        1.326   SYS70/W11A/VM_CNTL_dspace
    SLICE_X43Y56.Y       Tilo                  0.704   SYS70/W11A/VMBOX/MMU/R_SSR0.dspace
                                                       SYS70/W11A/VMBOX/MMU/ASN<3>
    SLICE_X43Y56.F4      net (fanout=1)        0.343   SYS70/W11A/VMBOX/MMU/ASN<3>
    SLICE_X43Y56.X       Tilo                  0.704   SYS70/W11A/VMBOX/MMU/R_SSR0.dspace
                                                       SYS70/W11A/VMBOX/MMU/SADR/eaddr_3_mux00001
    SLICE_X46Y55.G4      net (fanout=116)      2.014   SYS70/W11A/VMBOX/MMU/SADR/SADR_ADDR<3>
    SLICE_X46Y55.F5      Tif5                  1.033   SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[0].MEM/F5.S1
                                                       SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[0].MEM/G.S1
                                                       SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[0].MEM/F5.S1
    SLICE_X46Y54.FXINB   net (fanout=1)        0.000   SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[0].MEM/F5.S1
    SLICE_X46Y54.Y       Tif6y                 0.409   SYS70/W11A/VMBOX/MMU/SARSDR_slf<0>
                                                       SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[0].MEM/F6.S0
    SLICE_X55Y44.F2      net (fanout=3)        1.185   SYS70/W11A/VMBOX/MMU/SARSDR_slf<0>
    SLICE_X55Y44.COUT    Topcyf                1.162   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<1>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_lut<0>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<0>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<1>
    SLICE_X55Y45.CIN     net (fanout=1)        0.000   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<1>
    SLICE_X55Y45.COUT    Tbyp                  0.118   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<3>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<2>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<3>
    SLICE_X55Y46.CIN     net (fanout=1)        0.000   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<3>
    SLICE_X55Y46.COUT    Tbyp                  0.118   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<5>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<4>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<5>
    SLICE_X55Y47.CIN     net (fanout=1)        0.000   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<5>
    SLICE_X55Y47.XB      Tcinxb                0.404   SYS70/W11A/VMBOX/is_stackred_mux000237
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<6>
    SLICE_X46Y47.G2      net (fanout=1)        1.010   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<6>
    SLICE_X46Y47.Y       Tilo                  0.759   SYS70/W11A/VMBOX/MMU/AIB_SETA_or0000
                                                       SYS70/W11A/VMBOX/MMU/abo_length_mux00021
    SLICE_X46Y47.F3      net (fanout=2)        0.024   SYS70/W11A/VMBOX/MMU/abo_length_mux0002
    SLICE_X46Y47.X       Tilo                  0.759   SYS70/W11A/VMBOX/MMU/AIB_SETA_or0000
                                                       SYS70/W11A/VMBOX/MMU/AIB_SETA_or00001
    SLICE_X45Y49.F1      net (fanout=4)        0.523   SYS70/W11A/VMBOX/MMU/AIB_SETA_or0000
    SLICE_X45Y49.X       Tilo                  0.704   SYS70/W11A/VMBOX/MMU/SADR/N_AIB<0>
                                                       SYS70/W11A/VMBOX/MMU/SADR/N_AIB_0_mux00001
    SLICE_X44Y49.BY      net (fanout=1)        0.441   SYS70/W11A/VMBOX/MMU/SADR/N_AIB<0>
    SLICE_X44Y49.DIG     Tbydig                0.274   SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[0].MEM/F5.S1
                                                       SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[0].MEM/$1I125
    SLICE_X44Y48.ALTDIG  net (fanout=1)        0.000   SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[0].MEM/ALTD
    SLICE_X44Y48.CLK     Tds                   0.212   SYS70/W11A/VMBOX/MMU/SADR/AIB<0>
                                                       SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[0].MEM/F.S0
    -------------------------------------------------  ---------------------------
    Total                                     19.190ns (10.064ns logic, 9.126ns route)
                                                       (52.4% logic, 47.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.040ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SYS70/W11A/DPATH/R_IREG_3 (FF)
  Destination:          SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[0].MEM/F.S0 (RAM)
  Requirement:          19.230ns
  Data Path Delay:      19.190ns (Levels of Logic = 16)
  Clock Path Skew:      0.000ns
  Source Clock:         CLK rising at 0.000ns
  Destination Clock:    CLK rising at 19.230ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: SYS70/W11A/DPATH/R_IREG_3 to SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[0].MEM/F.S0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y57.XQ      Tcko                  0.592   SYS70/W11A/DPATH/R_IREG<3>
                                                       SYS70/W11A/DPATH/R_IREG_3
    SLICE_X27Y64.F2      net (fanout=36)       1.190   SYS70/W11A/DPATH/R_IREG<3>
    SLICE_X27Y64.X       Tilo                  0.704   SYS70/W11A/SEQ/VM_CNTL_dspace40
                                                       SYS70/W11A/SEQ/VM_CNTL_dspace40
    SLICE_X29Y64.F2      net (fanout=1)        0.383   SYS70/W11A/SEQ/VM_CNTL_dspace40
    SLICE_X29Y64.X       Tilo                  0.704   SYS70/W11A/SEQ/VM_CNTL_dspace51
                                                       SYS70/W11A/SEQ/VM_CNTL_dspace51
    SLICE_X33Y66.F2      net (fanout=1)        0.687   SYS70/W11A/SEQ/VM_CNTL_dspace51
    SLICE_X33Y66.X       Tilo                  0.704   SYS70/DMCMON.I0/R_REGS.vm_dspace
                                                       SYS70/W11A/SEQ/VM_CNTL_dspace115
    SLICE_X43Y56.G2      net (fanout=9)        1.326   SYS70/W11A/VM_CNTL_dspace
    SLICE_X43Y56.Y       Tilo                  0.704   SYS70/W11A/VMBOX/MMU/R_SSR0.dspace
                                                       SYS70/W11A/VMBOX/MMU/ASN<3>
    SLICE_X43Y56.F4      net (fanout=1)        0.343   SYS70/W11A/VMBOX/MMU/ASN<3>
    SLICE_X43Y56.X       Tilo                  0.704   SYS70/W11A/VMBOX/MMU/R_SSR0.dspace
                                                       SYS70/W11A/VMBOX/MMU/SADR/eaddr_3_mux00001
    SLICE_X46Y54.G4      net (fanout=116)      2.014   SYS70/W11A/VMBOX/MMU/SADR/SADR_ADDR<3>
    SLICE_X46Y54.F5      Tif5                  1.033   SYS70/W11A/VMBOX/MMU/SARSDR_slf<0>
                                                       SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[0].MEM/G.S0
                                                       SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[0].MEM/F5.S0
    SLICE_X46Y54.FXINA   net (fanout=1)        0.000   SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[0].MEM/F5.S0
    SLICE_X46Y54.Y       Tif6y                 0.409   SYS70/W11A/VMBOX/MMU/SARSDR_slf<0>
                                                       SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[0].MEM/F6.S0
    SLICE_X55Y44.F2      net (fanout=3)        1.185   SYS70/W11A/VMBOX/MMU/SARSDR_slf<0>
    SLICE_X55Y44.COUT    Topcyf                1.162   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<1>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_lut<0>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<0>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<1>
    SLICE_X55Y45.CIN     net (fanout=1)        0.000   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<1>
    SLICE_X55Y45.COUT    Tbyp                  0.118   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<3>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<2>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<3>
    SLICE_X55Y46.CIN     net (fanout=1)        0.000   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<3>
    SLICE_X55Y46.COUT    Tbyp                  0.118   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<5>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<4>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<5>
    SLICE_X55Y47.CIN     net (fanout=1)        0.000   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<5>
    SLICE_X55Y47.XB      Tcinxb                0.404   SYS70/W11A/VMBOX/is_stackred_mux000237
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<6>
    SLICE_X46Y47.G2      net (fanout=1)        1.010   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<6>
    SLICE_X46Y47.Y       Tilo                  0.759   SYS70/W11A/VMBOX/MMU/AIB_SETA_or0000
                                                       SYS70/W11A/VMBOX/MMU/abo_length_mux00021
    SLICE_X46Y47.F3      net (fanout=2)        0.024   SYS70/W11A/VMBOX/MMU/abo_length_mux0002
    SLICE_X46Y47.X       Tilo                  0.759   SYS70/W11A/VMBOX/MMU/AIB_SETA_or0000
                                                       SYS70/W11A/VMBOX/MMU/AIB_SETA_or00001
    SLICE_X45Y49.F1      net (fanout=4)        0.523   SYS70/W11A/VMBOX/MMU/AIB_SETA_or0000
    SLICE_X45Y49.X       Tilo                  0.704   SYS70/W11A/VMBOX/MMU/SADR/N_AIB<0>
                                                       SYS70/W11A/VMBOX/MMU/SADR/N_AIB_0_mux00001
    SLICE_X44Y49.BY      net (fanout=1)        0.441   SYS70/W11A/VMBOX/MMU/SADR/N_AIB<0>
    SLICE_X44Y49.DIG     Tbydig                0.274   SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[0].MEM/F5.S1
                                                       SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[0].MEM/$1I125
    SLICE_X44Y48.ALTDIG  net (fanout=1)        0.000   SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[0].MEM/ALTD
    SLICE_X44Y48.CLK     Tds                   0.212   SYS70/W11A/VMBOX/MMU/SADR/AIB<0>
                                                       SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[0].MEM/F.S0
    -------------------------------------------------  ---------------------------
    Total                                     19.190ns (10.064ns logic, 9.126ns route)
                                                       (52.4% logic, 47.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.053ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SYS70/W11A/DPATH/R_IREG_3 (FF)
  Destination:          SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[1].MEM/F.S0 (RAM)
  Requirement:          19.230ns
  Data Path Delay:      19.177ns (Levels of Logic = 16)
  Clock Path Skew:      0.000ns
  Source Clock:         CLK rising at 0.000ns
  Destination Clock:    CLK rising at 19.230ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: SYS70/W11A/DPATH/R_IREG_3 to SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[1].MEM/F.S0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X24Y57.XQ      Tcko                  0.592   SYS70/W11A/DPATH/R_IREG<3>
                                                       SYS70/W11A/DPATH/R_IREG_3
    SLICE_X27Y64.F2      net (fanout=36)       1.190   SYS70/W11A/DPATH/R_IREG<3>
    SLICE_X27Y64.X       Tilo                  0.704   SYS70/W11A/SEQ/VM_CNTL_dspace40
                                                       SYS70/W11A/SEQ/VM_CNTL_dspace40
    SLICE_X29Y64.F2      net (fanout=1)        0.383   SYS70/W11A/SEQ/VM_CNTL_dspace40
    SLICE_X29Y64.X       Tilo                  0.704   SYS70/W11A/SEQ/VM_CNTL_dspace51
                                                       SYS70/W11A/SEQ/VM_CNTL_dspace51
    SLICE_X33Y66.F2      net (fanout=1)        0.687   SYS70/W11A/SEQ/VM_CNTL_dspace51
    SLICE_X33Y66.X       Tilo                  0.704   SYS70/DMCMON.I0/R_REGS.vm_dspace
                                                       SYS70/W11A/SEQ/VM_CNTL_dspace115
    SLICE_X43Y56.G2      net (fanout=9)        1.326   SYS70/W11A/VM_CNTL_dspace
    SLICE_X43Y56.Y       Tilo                  0.704   SYS70/W11A/VMBOX/MMU/R_SSR0.dspace
                                                       SYS70/W11A/VMBOX/MMU/ASN<3>
    SLICE_X43Y56.F4      net (fanout=1)        0.343   SYS70/W11A/VMBOX/MMU/ASN<3>
    SLICE_X43Y56.X       Tilo                  0.704   SYS70/W11A/VMBOX/MMU/R_SSR0.dspace
                                                       SYS70/W11A/VMBOX/MMU/SADR/eaddr_3_mux00001
    SLICE_X46Y55.G4      net (fanout=116)      2.014   SYS70/W11A/VMBOX/MMU/SADR/SADR_ADDR<3>
    SLICE_X46Y55.F5      Tif5                  1.033   SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[0].MEM/F5.S1
                                                       SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[0].MEM/G.S1
                                                       SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[0].MEM/F5.S1
    SLICE_X46Y54.FXINB   net (fanout=1)        0.000   SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[0].MEM/F5.S1
    SLICE_X46Y54.Y       Tif6y                 0.409   SYS70/W11A/VMBOX/MMU/SARSDR_slf<0>
                                                       SYS70/W11A/VMBOX/MMU/SADR/SDR_SLF/AW_6.GL[0].MEM/F6.S0
    SLICE_X55Y44.F2      net (fanout=3)        1.185   SYS70/W11A/VMBOX/MMU/SARSDR_slf<0>
    SLICE_X55Y44.COUT    Topcyf                1.162   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<1>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_lut<0>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<0>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<1>
    SLICE_X55Y45.CIN     net (fanout=1)        0.000   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<1>
    SLICE_X55Y45.COUT    Tbyp                  0.118   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<3>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<2>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<3>
    SLICE_X55Y46.CIN     net (fanout=1)        0.000   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<3>
    SLICE_X55Y46.COUT    Tbyp                  0.118   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<5>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<4>
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<5>
    SLICE_X55Y47.CIN     net (fanout=1)        0.000   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<5>
    SLICE_X55Y47.XB      Tcinxb                0.404   SYS70/W11A/VMBOX/is_stackred_mux000237
                                                       SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<6>
    SLICE_X46Y47.G2      net (fanout=1)        1.010   SYS70/W11A/VMBOX/MMU/Mcompar_abo_length_cmp_gt0000_cy<6>
    SLICE_X46Y47.Y       Tilo                  0.759   SYS70/W11A/VMBOX/MMU/AIB_SETA_or0000
                                                       SYS70/W11A/VMBOX/MMU/abo_length_mux00021
    SLICE_X46Y47.F3      net (fanout=2)        0.024   SYS70/W11A/VMBOX/MMU/abo_length_mux0002
    SLICE_X46Y47.X       Tilo                  0.759   SYS70/W11A/VMBOX/MMU/AIB_SETA_or0000
                                                       SYS70/W11A/VMBOX/MMU/AIB_SETA_or00001
    SLICE_X45Y46.F2      net (fanout=4)        0.510   SYS70/W11A/VMBOX/MMU/AIB_SETA_or0000
    SLICE_X45Y46.X       Tilo                  0.704   SYS70/W11A/VMBOX/R_REGS.vaok
                                                       SYS70/W11A/VMBOX/MMU/SADR/N_AIB_1_mux00001
    SLICE_X44Y47.BY      net (fanout=1)        0.441   SYS70/W11A/VMBOX/MMU/SADR/N_AIB<1>
    SLICE_X44Y47.DIG     Tbydig                0.274   SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[1].MEM/F5.S1
                                                       SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[1].MEM/$1I125
    SLICE_X44Y46.ALTDIG  net (fanout=1)        0.000   SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[1].MEM/ALTD
    SLICE_X44Y46.CLK     Tds                   0.212   SYS70/W11A/VMBOX/MMU/SADR/AIB<1>
                                                       SYS70/W11A/VMBOX/MMU/SADR/SDR_AIB/AW_6.GL[1].MEM/F.S0
    -------------------------------------------------  ---------------------------
    Total                                     19.177ns (10.064ns logic, 9.113ns route)
                                                       (52.5% logic, 47.5% route)

--------------------------------------------------------------------------------

Hold Paths: TS_CLK1 = PERIOD TIMEGRP "CLK1" TS_I_CLK50 / 1.04 HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.721ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/SERPORT/XONRX/R_REGS.rxdata_7 (FF)
  Destination:          RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[7].MEM0.SLICEM_G (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.717ns (Levels of Logic = 1)
  Clock Path Skew:      -0.004ns (0.005 - 0.009)
  Source Clock:         CLK rising at 0.000ns
  Destination Clock:    CLK rising at 0.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/SERPORT/XONRX/R_REGS.rxdata_7 to RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[7].MEM0.SLICEM_G
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X72Y17.XQ      Tcko                  0.474   RLINK/SERPORT/XONRX/R_REGS.rxdata_7
                                                       RLINK/SERPORT/XONRX/R_REGS.rxdata_7
    SLICE_X72Y15.BY      net (fanout=2)        0.370   RLINK/SERPORT/XONRX/R_REGS.rxdata_7
    SLICE_X72Y15.CLK     Tdh         (-Th)     0.127   RLINK/SERPORT/RXFIFO/FIFO/RAM/DOB0<7>
                                                       RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[7].MEM0.SLICEM_G
    -------------------------------------------------  ---------------------------
    Total                                      0.717ns (0.347ns logic, 0.370ns route)
                                                       (48.4% logic, 51.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.736ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/SERPORT/XONRX/R_REGS.rxdata_7 (FF)
  Destination:          RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[7].MEM0.SLICEM_F (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.732ns (Levels of Logic = 1)
  Clock Path Skew:      -0.004ns (0.005 - 0.009)
  Source Clock:         CLK rising at 0.000ns
  Destination Clock:    CLK rising at 0.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/SERPORT/XONRX/R_REGS.rxdata_7 to RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[7].MEM0.SLICEM_F
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X72Y17.XQ      Tcko                  0.474   RLINK/SERPORT/XONRX/R_REGS.rxdata_7
                                                       RLINK/SERPORT/XONRX/R_REGS.rxdata_7
    SLICE_X72Y15.BY      net (fanout=2)        0.370   RLINK/SERPORT/XONRX/R_REGS.rxdata_7
    SLICE_X72Y15.CLK     Tdh         (-Th)     0.112   RLINK/SERPORT/RXFIFO/FIFO/RAM/DOB0<7>
                                                       RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[7].MEM0.SLICEM_F
    -------------------------------------------------  ---------------------------
    Total                                      0.732ns (0.362ns logic, 0.370ns route)
                                                       (49.5% logic, 50.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.854ns (requirement - (clock path skew + uncertainty - data path))
  Source:               SYS70/DMCMON.I0/R_REGS.dp_ireg_1 (FF)
  Destination:          SYS70/DMCMON.I0/BRAM1/UMEM/AW_09_S36.GL[0].MEM.A (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.914ns (Levels of Logic = 0)
  Clock Path Skew:      0.060ns (0.143 - 0.083)
  Source Clock:         CLK rising at 0.000ns
  Destination Clock:    CLK rising at 0.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: SYS70/DMCMON.I0/R_REGS.dp_ireg_1 to SYS70/DMCMON.I0/BRAM1/UMEM/AW_09_S36.GL[0].MEM.A
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X17Y30.XQ      Tcko                  0.473   SYS70/DMCMON.I0/R_REGS.dp_ireg_1
                                                       SYS70/DMCMON.I0/R_REGS.dp_ireg_1
    RAMB16_X0Y3.DIA25    net (fanout=2)        0.567   SYS70/DMCMON.I0/R_REGS.dp_ireg_1
    RAMB16_X0Y3.CLKA     Tbckd       (-Th)     0.126   SYS70/DMCMON.I0/BRAM1/UMEM/AW_09_S36.GL[0].MEM
                                                       SYS70/DMCMON.I0/BRAM1/UMEM/AW_09_S36.GL[0].MEM.A
    -------------------------------------------------  ---------------------------
    Total                                      0.914ns (0.347ns logic, 0.567ns route)
                                                       (38.0% logic, 62.0% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_CLK1 = PERIOD TIMEGRP "CLK1" TS_I_CLK50 / 1.04 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 15.063ns (period - min period limit)
  Period: 19.230ns
  Min period limit: 4.167ns (239.981MHz) (Tmsper_B)
  Physical resource: SYS70/W11A/DPATH/MUNIT/Mmult_prod_mult0000/CLK
  Logical resource: SYS70/W11A/DPATH/MUNIT/Mmult_prod_mult0000/CLK
  Location pin: MULT18X18_X0Y5.CLK
  Clock network: CLK
--------------------------------------------------------------------------------
Slack: 15.064ns (period - (min low pulse limit / (low pulse / period)))
  Period: 19.230ns
  Low pulse: 9.615ns
  Low pulse limit: 2.083ns (Tmspwl_B)
  Physical resource: SYS70/W11A/DPATH/MUNIT/Mmult_prod_mult0000/CLK
  Logical resource: SYS70/W11A/DPATH/MUNIT/Mmult_prod_mult0000/CLK
  Location pin: MULT18X18_X0Y5.CLK
  Clock network: CLK
--------------------------------------------------------------------------------
Slack: 15.064ns (period - (min high pulse limit / (high pulse / period)))
  Period: 19.230ns
  High pulse: 9.615ns
  High pulse limit: 2.083ns (Tmspwh_B)
  Physical resource: SYS70/W11A/DPATH/MUNIT/Mmult_prod_mult0000/CLK
  Logical resource: SYS70/W11A/DPATH/MUNIT/Mmult_prod_mult0000/CLK
  Location pin: MULT18X18_X0Y5.CLK
  Clock network: CLK
--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = IN 10 ns BEFORE COMP "I_CLK50";
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 31 paths analyzed, 31 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   2.453ns.
--------------------------------------------------------------------------------
Slack (setup path):     7.547ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               I_RXD (PAD)
  Destination:          IOB_RS232/P0/IOB_RXD/IOB/R_DI_0 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      6.222ns (Levels of Logic = 0)
  Clock Path Delay:     3.769ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: I_RXD to IOB_RS232/P0/IOB_RXD/IOB/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    U6.ICLK1             Tiopickd              6.222   I_RXD
                                                       I_RXD
                                                       I_RXD_IBUF
                                                       I_RXD.IFD_DELAY
                                                       IOB_RS232/P0/IOB_RXD/IOB/R_DI_0
    -------------------------------------------------  ---------------------------
    Total                                      6.222ns (6.222ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: I_CLK50 to IOB_RS232/P0/IOB_RXD/IOB/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.577   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.014   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.319   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.166   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    U6.ICLK1             net (fanout=2225)     0.227   CLK
    -------------------------------------------------  ---------------------------
    Total                                      3.769ns (2.646ns logic, 1.123ns route)
                                                       (70.2% logic, 29.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     7.568ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               IO_MEM_DATA<9> (PAD)
  Destination:          SRAM_CTL/IOB_MEM_DATA/R_DI_9 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      6.222ns (Levels of Logic = 0)
  Clock Path Delay:     3.790ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: IO_MEM_DATA<9> to SRAM_CTL/IOB_MEM_DATA/R_DI_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    L5.ICLK1             Tiopickd              6.222   IO_MEM_DATA<9>
                                                       IO_MEM_DATA<9>
                                                       IO_MEM_DATA_9_IOBUF/IBUF
                                                       IO_MEM_DATA<9>.IFD_DELAY
                                                       SRAM_CTL/IOB_MEM_DATA/R_DI_9
    -------------------------------------------------  ---------------------------
    Total                                      6.222ns (6.222ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: I_CLK50 to SRAM_CTL/IOB_MEM_DATA/R_DI_9
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.577   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.014   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.319   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.166   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    L5.ICLK1             net (fanout=2225)     0.248   CLK
    -------------------------------------------------  ---------------------------
    Total                                      3.790ns (2.646ns logic, 1.144ns route)
                                                       (69.8% logic, 30.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     7.568ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               IO_MEM_DATA<2> (PAD)
  Destination:          SRAM_CTL/IOB_MEM_DATA/R_DI_2 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      6.222ns (Levels of Logic = 0)
  Clock Path Delay:     3.790ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: IO_MEM_DATA<2> to SRAM_CTL/IOB_MEM_DATA/R_DI_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    L6.ICLK1             Tiopickd              6.222   IO_MEM_DATA<2>
                                                       IO_MEM_DATA<2>
                                                       IO_MEM_DATA_2_IOBUF/IBUF
                                                       IO_MEM_DATA<2>.IFD_DELAY
                                                       SRAM_CTL/IOB_MEM_DATA/R_DI_2
    -------------------------------------------------  ---------------------------
    Total                                      6.222ns (6.222ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: I_CLK50 to SRAM_CTL/IOB_MEM_DATA/R_DI_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.577   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.014   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.319   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.166   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    L6.ICLK1             net (fanout=2225)     0.248   CLK
    -------------------------------------------------  ---------------------------
    Total                                      3.790ns (2.646ns logic, 1.144ns route)
                                                       (69.8% logic, 30.2% route)

--------------------------------------------------------------------------------

Hold Paths: OFFSET = IN 10 ns BEFORE COMP "I_CLK50";
--------------------------------------------------------------------------------
Offset (hold paths):    -0.993ns (data path - clock path + uncertainty)
  Source:               I_SWI<6> (PAD)
  Destination:          HIO/HIO/HIO/IOB_SWI/R_DI_6 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Data Path Delay:      3.705ns (Levels of Logic = 0)
  Clock Path Delay:     4.698ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Minimum Data Path: I_SWI<6> to HIO/HIO/HIO/IOB_SWI/R_DI_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    N17.ICLK1            Tioickpd    (-Th)    -3.705   I_SWI<6>
                                                       I_SWI<6>
                                                       I_SWI_6_IBUF
                                                       I_SWI<6>.IFD_DELAY
                                                       HIO/HIO/HIO/IOB_SWI/R_DI_6
    -------------------------------------------------  ---------------------------
    Total                                      3.705ns (3.705ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Maximum Clock Path: I_CLK50 to HIO/HIO/HIO/IOB_SWI/R_DI_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.721   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.017   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.398   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.457   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    N17.ICLK1            net (fanout=2225)     0.379   CLK
    -------------------------------------------------  ---------------------------
    Total                                      4.698ns (3.200ns logic, 1.498ns route)
                                                       (68.1% logic, 31.9% route)

--------------------------------------------------------------------------------
Offset (hold paths):    -0.992ns (data path - clock path + uncertainty)
  Source:               IO_MEM_DATA<6> (PAD)
  Destination:          SRAM_CTL/IOB_MEM_DATA/R_DI_6 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Data Path Delay:      3.705ns (Levels of Logic = 0)
  Clock Path Delay:     4.697ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Minimum Data Path: IO_MEM_DATA<6> to SRAM_CTL/IOB_MEM_DATA/R_DI_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P2.ICLK1             Tioickpd    (-Th)    -3.705   IO_MEM_DATA<6>
                                                       IO_MEM_DATA<6>
                                                       IO_MEM_DATA_6_IOBUF/IBUF
                                                       IO_MEM_DATA<6>.IFD_DELAY
                                                       SRAM_CTL/IOB_MEM_DATA/R_DI_6
    -------------------------------------------------  ---------------------------
    Total                                      3.705ns (3.705ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Maximum Clock Path: I_CLK50 to SRAM_CTL/IOB_MEM_DATA/R_DI_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.721   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.017   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.398   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.457   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    P2.ICLK1             net (fanout=2225)     0.378   CLK
    -------------------------------------------------  ---------------------------
    Total                                      4.697ns (3.200ns logic, 1.497ns route)
                                                       (68.1% logic, 31.9% route)

--------------------------------------------------------------------------------
Offset (hold paths):    -0.992ns (data path - clock path + uncertainty)
  Source:               IO_MEM_DATA<5> (PAD)
  Destination:          SRAM_CTL/IOB_MEM_DATA/R_DI_5 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Data Path Delay:      3.705ns (Levels of Logic = 0)
  Clock Path Delay:     4.697ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Minimum Data Path: IO_MEM_DATA<5> to SRAM_CTL/IOB_MEM_DATA/R_DI_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P1.ICLK1             Tioickpd    (-Th)    -3.705   IO_MEM_DATA<5>
                                                       IO_MEM_DATA<5>
                                                       IO_MEM_DATA_5_IOBUF/IBUF
                                                       IO_MEM_DATA<5>.IFD_DELAY
                                                       SRAM_CTL/IOB_MEM_DATA/R_DI_5
    -------------------------------------------------  ---------------------------
    Total                                      3.705ns (3.705ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Maximum Clock Path: I_CLK50 to SRAM_CTL/IOB_MEM_DATA/R_DI_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.721   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.017   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.398   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.457   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    P1.ICLK1             net (fanout=2225)     0.378   CLK
    -------------------------------------------------  ---------------------------
    Total                                      4.697ns (3.200ns logic, 1.497ns route)
                                                       (68.1% logic, 31.9% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = OUT 20 ns AFTER COMP "I_CLK50";
For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612).

 81 paths analyzed, 65 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
 Minimum allowable offset is  16.983ns.
--------------------------------------------------------------------------------
Slack (slowest paths):  3.017ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               SRAM_CTL/IOB_MEM_WE/IOB/R_DO_0 (FF)
  Destination:          O_MEM_WE_N (PAD)
  Source Clock:         CLK falling at 9.615ns
  Requirement:          20.000ns
  Data Path Delay:      2.792ns (Levels of Logic = 0)
  Clock Path Delay:     4.576ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: I_CLK50 to SRAM_CTL/IOB_MEM_WE/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.721   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.017   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.398   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.457   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    N7.OTCLK1            net (fanout=2225)     0.257   CLK
    -------------------------------------------------  ---------------------------
    Total                                      4.576ns (3.200ns logic, 1.376ns route)
                                                       (69.9% logic, 30.1% route)

  Maximum Data Path: SRAM_CTL/IOB_MEM_WE/IOB/R_DO_0 to O_MEM_WE_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    N7.PAD               Tiockp                2.792   O_MEM_WE_N
                                                       SRAM_CTL/IOB_MEM_WE/IOB/R_DO_0
                                                       O_MEM_WE_N_OBUF
                                                       O_MEM_WE_N
    -------------------------------------------------  ---------------------------
    Total                                      2.792ns (2.792ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  10.918ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               IOB_RS232/P1/IOB_TXD/IOB/R_DO_0 (FF)
  Destination:          O_FUSP_TXD (PAD)
  Source Clock:         CLK rising at 0.000ns
  Requirement:          20.000ns
  Data Path Delay:      4.388ns (Levels of Logic = 0)
  Clock Path Delay:     4.694ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: I_CLK50 to IOB_RS232/P1/IOB_TXD/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.721   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.017   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.398   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.457   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    T17.OTCLK1           net (fanout=2225)     0.375   CLK
    -------------------------------------------------  ---------------------------
    Total                                      4.694ns (3.200ns logic, 1.494ns route)
                                                       (68.2% logic, 31.8% route)

  Maximum Data Path: IOB_RS232/P1/IOB_TXD/IOB/R_DO_0 to O_FUSP_TXD
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T17.PAD              Tiockp                4.388   O_FUSP_TXD
                                                       IOB_RS232/P1/IOB_TXD/IOB/R_DO_0
                                                       O_FUSP_TXD_OBUF
                                                       O_FUSP_TXD
    -------------------------------------------------  ---------------------------
    Total                                      4.388ns (4.388ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  10.987ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               IOB_RS232/P1/IOB_RTS/IOB/R_DO_0 (FF)
  Destination:          O_FUSP_RTS_N (PAD)
  Source Clock:         CLK rising at 0.000ns
  Requirement:          20.000ns
  Data Path Delay:      4.388ns (Levels of Logic = 0)
  Clock Path Delay:     4.625ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: I_CLK50 to IOB_RS232/P1/IOB_RTS/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.721   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.017   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.398   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.457   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    M13.OTCLK1           net (fanout=2225)     0.306   CLK
    -------------------------------------------------  ---------------------------
    Total                                      4.625ns (3.200ns logic, 1.425ns route)
                                                       (69.2% logic, 30.8% route)

  Maximum Data Path: IOB_RS232/P1/IOB_RTS/IOB/R_DO_0 to O_FUSP_RTS_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    M13.PAD              Tiockp                4.388   O_FUSP_RTS_N
                                                       IOB_RS232/P1/IOB_RTS/IOB/R_DO_0
                                                       O_FUSP_RTS_N_OBUF
                                                       O_FUSP_RTS_N
    -------------------------------------------------  ---------------------------
    Total                                      4.388ns (4.388ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------

Fastest Paths: OFFSET = OUT 20 ns AFTER COMP "I_CLK50";
--------------------------------------------------------------------------------
Delay (fastest paths):  6.095ns (clock arrival + clock path + data path - uncertainty)
  Source:               SRAM_CTL/IOB_MEM_BE/R_DO_1 (FF)
  Destination:          O_MEM_BE_N<1> (PAD)
  Source Clock:         CLK rising at 0.000ns
  Data Path Delay:      2.292ns (Levels of Logic = 0)
  Clock Path Delay:     3.803ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Minimum Clock Path: I_CLK50 to SRAM_CTL/IOB_MEM_BE/R_DO_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.577   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.014   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.319   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.166   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    K4.OTCLK1            net (fanout=2225)     0.261   CLK
    -------------------------------------------------  ---------------------------
    Total                                      3.803ns (2.646ns logic, 1.157ns route)
                                                       (69.6% logic, 30.4% route)

  Minimum Data Path: SRAM_CTL/IOB_MEM_BE/R_DO_1 to O_MEM_BE_N<1>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    K4.PAD               Tiockp                2.292   O_MEM_BE_N<1>
                                                       SRAM_CTL/IOB_MEM_BE/R_DO_1
                                                       O_MEM_BE_N_1_OBUF
                                                       O_MEM_BE_N<1>
    -------------------------------------------------  ---------------------------
    Total                                      2.292ns (2.292ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  6.093ns (clock arrival + clock path + data path - uncertainty)
  Source:               SRAM_CTL/IOB_MEM_BE/R_DO_0 (FF)
  Destination:          O_MEM_BE_N<0> (PAD)
  Source Clock:         CLK rising at 0.000ns
  Data Path Delay:      2.292ns (Levels of Logic = 0)
  Clock Path Delay:     3.801ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Minimum Clock Path: I_CLK50 to SRAM_CTL/IOB_MEM_BE/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.577   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.014   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.319   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.166   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    K5.OTCLK1            net (fanout=2225)     0.259   CLK
    -------------------------------------------------  ---------------------------
    Total                                      3.801ns (2.646ns logic, 1.155ns route)
                                                       (69.6% logic, 30.4% route)

  Minimum Data Path: SRAM_CTL/IOB_MEM_BE/R_DO_0 to O_MEM_BE_N<0>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    K5.PAD               Tiockp                2.292   O_MEM_BE_N<0>
                                                       SRAM_CTL/IOB_MEM_BE/R_DO_0
                                                       O_MEM_BE_N_0_OBUF
                                                       O_MEM_BE_N<0>
    -------------------------------------------------  ---------------------------
    Total                                      2.292ns (2.292ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  6.088ns (clock arrival + clock path + data path - uncertainty)
  Source:               SRAM_CTL/IOB_MEM_CE/IOB/R_DO_0 (FF)
  Destination:          O_MEM_CE_N (PAD)
  Source Clock:         CLK rising at 0.000ns
  Data Path Delay:      2.292ns (Levels of Logic = 0)
  Clock Path Delay:     3.796ns (Levels of Logic = 3)
  Clock Uncertainty:    0.000ns

  Minimum Clock Path: I_CLK50 to SRAM_CTL/IOB_MEM_CE/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_IBUFG
    DCM_X1Y3.CLKIN       net (fanout=1)        0.577   I_CLK50_IBUFG
    DCM_X1Y3.CLKFX       Tdcmino               0.014   DCM/DCM1.DCM
                                                       DCM/DCM1.DCM
    BUFGMUX_X2Y10.I0     net (fanout=1)        0.319   CLK1
    BUFGMUX_X2Y10.O      Tgi0o                 1.166   CLK_BUFG
                                                       CLK_BUFG.GCLKMUX
                                                       CLK_BUFG
    R6.OTCLK1            net (fanout=2225)     0.254   CLK
    -------------------------------------------------  ---------------------------
    Total                                      3.796ns (2.646ns logic, 1.150ns route)
                                                       (69.7% logic, 30.3% route)

  Minimum Data Path: SRAM_CTL/IOB_MEM_CE/IOB/R_DO_0 to O_MEM_CE_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R6.PAD               Tiockp                2.292   O_MEM_CE_N
                                                       SRAM_CTL/IOB_MEM_CE/IOB/R_DO_0
                                                       O_MEM_CE_N_OBUF
                                                       O_MEM_CE_N
    -------------------------------------------------  ---------------------------
    Total                                      2.292ns (2.292ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = IN 2.5 ns VALID 33 ns BEFORE COMP "I_FX2_IFCLK";
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 11 paths analyzed, 11 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   2.261ns.
--------------------------------------------------------------------------------
Slack (setup path):     0.239ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               IO_FX2_DATA<5> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          2.500ns
  Data Path Delay:      6.222ns (Levels of Logic = 0)
  Clock Path Delay:     3.961ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: IO_FX2_DATA<5> to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R11.ICLK1            Tiopickd              6.222   IO_FX2_DATA<5>
                                                       IO_FX2_DATA<5>
                                                       IO_FX2_DATA_5_IOBUF/IBUF
                                                       IO_FX2_DATA<5>.IFD_DELAY
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5
    -------------------------------------------------  ---------------------------
    Total                                      6.222ns (6.222ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.466   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.103   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.166   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    R11.ICLK1            net (fanout=84)       0.226   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.961ns (2.632ns logic, 1.329ns route)
                                                       (66.4% logic, 33.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.241ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               IO_FX2_DATA<3> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          2.500ns
  Data Path Delay:      6.222ns (Levels of Logic = 0)
  Clock Path Delay:     3.963ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: IO_FX2_DATA<3> to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T12.ICLK1            Tiopickd              6.222   IO_FX2_DATA<3>
                                                       IO_FX2_DATA<3>
                                                       IO_FX2_DATA_3_IOBUF/IBUF
                                                       IO_FX2_DATA<3>.IFD_DELAY
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3
    -------------------------------------------------  ---------------------------
    Total                                      6.222ns (6.222ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.466   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.103   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.166   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    T12.ICLK1            net (fanout=84)       0.228   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.963ns (2.632ns logic, 1.331ns route)
                                                       (66.4% logic, 33.6% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.246ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               IO_FX2_DATA<4> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          2.500ns
  Data Path Delay:      6.222ns (Levels of Logic = 0)
  Clock Path Delay:     3.968ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: IO_FX2_DATA<4> to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    N11.ICLK1            Tiopickd              6.222   IO_FX2_DATA<4>
                                                       IO_FX2_DATA<4>
                                                       IO_FX2_DATA_4_IOBUF/IBUF
                                                       IO_FX2_DATA<4>.IFD_DELAY
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4
    -------------------------------------------------  ---------------------------
    Total                                      6.222ns (6.222ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.466   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.103   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.166   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    N11.ICLK1            net (fanout=84)       0.233   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.968ns (2.632ns logic, 1.336ns route)
                                                       (66.3% logic, 33.7% route)

--------------------------------------------------------------------------------

Hold Paths: OFFSET = IN 2.5 ns VALID 33 ns BEFORE COMP "I_FX2_IFCLK";
--------------------------------------------------------------------------------
Slack (hold path):      29.274ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               I_FX2_FLAG<2> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          30.500ns
  Data Path Delay:      3.705ns (Levels of Logic = 0)
  Clock Path Delay:     4.931ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Minimum Data Path: I_FX2_FLAG<2> to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V16.ICLK1            Tioickpd    (-Th)    -3.705   I_FX2_FLAG<2>
                                                       I_FX2_FLAG<2>
                                                       I_FX2_FLAG_2_IBUF
                                                       I_FX2_FLAG<2>.IFD_DELAY
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2
    -------------------------------------------------  ---------------------------
    Total                                      3.705ns (3.705ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Maximum Clock Path: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.726   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.378   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.457   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    V16.ICLK1            net (fanout=84)       0.370   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.931ns (3.183ns logic, 1.748ns route)
                                                       (64.6% logic, 35.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      29.298ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               I_FX2_FLAG<1> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          30.500ns
  Data Path Delay:      3.705ns (Levels of Logic = 0)
  Clock Path Delay:     4.907ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Minimum Data Path: I_FX2_FLAG<1> to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    U14.ICLK1            Tioickpd    (-Th)    -3.705   I_FX2_FLAG<1>
                                                       I_FX2_FLAG<1>
                                                       I_FX2_FLAG_1_IBUF
                                                       I_FX2_FLAG<1>.IFD_DELAY
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1
    -------------------------------------------------  ---------------------------
    Total                                      3.705ns (3.705ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Maximum Clock Path: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.726   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.378   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.457   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    U14.ICLK1            net (fanout=84)       0.346   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.907ns (3.183ns logic, 1.724ns route)
                                                       (64.9% logic, 35.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      29.298ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               I_FX2_FLAG<0> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          30.500ns
  Data Path Delay:      3.705ns (Levels of Logic = 0)
  Clock Path Delay:     4.907ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Minimum Data Path: I_FX2_FLAG<0> to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V14.ICLK1            Tioickpd    (-Th)    -3.705   I_FX2_FLAG<0>
                                                       I_FX2_FLAG<0>
                                                       I_FX2_FLAG_0_IBUF
                                                       I_FX2_FLAG<0>.IFD_DELAY
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0
    -------------------------------------------------  ---------------------------
    Total                                      3.705ns (3.705ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Maximum Clock Path: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.726   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.378   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.457   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    V14.ICLK1            net (fanout=84)       0.346   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.907ns (3.183ns logic, 1.724ns route)
                                                       (64.9% logic, 35.1% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = OUT 10 ns VALID 33 ns AFTER COMP "I_FX2_IFCLK";
For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612).

 22 paths analyzed, 14 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
 Minimum allowable offset is   8.501ns.
--------------------------------------------------------------------------------
Slack (slowest paths):  1.499ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               RLINK/FX2CNTL/IOB_FX2_DATA/R_TE_8 (FF)
  Destination:          IO_FX2_DATA<0> (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      3.595ns (Levels of Logic = 0)
  Clock Path Delay:     4.906ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_TE_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.726   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.378   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.457   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    R14.OTCLK1           net (fanout=84)       0.345   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.906ns (3.183ns logic, 1.723ns route)
                                                       (64.9% logic, 35.1% route)

  Maximum Data Path: RLINK/FX2CNTL/IOB_FX2_DATA/R_TE_8 to IO_FX2_DATA<0>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R14.PAD              Tiockon               3.595   IO_FX2_DATA<0>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_TE_8
                                                       IO_FX2_DATA_0_IOBUF/OBUFT
                                                       IO_FX2_DATA<0>
    -------------------------------------------------  ---------------------------
    Total                                      3.595ns (3.595ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  1.529ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               RLINK/FX2CNTL/IOB_FX2_DATA/R_TE_7 (FF)
  Destination:          IO_FX2_DATA<1> (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      3.595ns (Levels of Logic = 0)
  Clock Path Delay:     4.876ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_TE_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.726   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.378   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.457   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    R13.OTCLK1           net (fanout=84)       0.315   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.876ns (3.183ns logic, 1.693ns route)
                                                       (65.3% logic, 34.7% route)

  Maximum Data Path: RLINK/FX2CNTL/IOB_FX2_DATA/R_TE_7 to IO_FX2_DATA<1>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R13.PAD              Tiockon               3.595   IO_FX2_DATA<1>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_TE_7
                                                       IO_FX2_DATA_1_IOBUF/OBUFT
                                                       IO_FX2_DATA<1>
    -------------------------------------------------  ---------------------------
    Total                                      3.595ns (3.595ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  1.529ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               RLINK/FX2CNTL/IOB_FX2_DATA/R_TE_6 (FF)
  Destination:          IO_FX2_DATA<2> (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      3.595ns (Levels of Logic = 0)
  Clock Path Delay:     4.876ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_TE_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.726   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.378   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.457   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    P13.OTCLK1           net (fanout=84)       0.315   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.876ns (3.183ns logic, 1.693ns route)
                                                       (65.3% logic, 34.7% route)

  Maximum Data Path: RLINK/FX2CNTL/IOB_FX2_DATA/R_TE_6 to IO_FX2_DATA<2>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P13.PAD              Tiockon               3.595   IO_FX2_DATA<2>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_TE_6
                                                       IO_FX2_DATA_2_IOBUF/OBUFT
                                                       IO_FX2_DATA<2>
    -------------------------------------------------  ---------------------------
    Total                                      3.595ns (3.595ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------

Fastest Paths: OFFSET = OUT 10 ns VALID 33 ns AFTER COMP "I_FX2_IFCLK";
--------------------------------------------------------------------------------
Delay (fastest paths):  6.273ns (clock arrival + clock path + data path - uncertainty)
  Source:               RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0 (FF)
  Destination:          O_FX2_SLRD_N (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Data Path Delay:      2.292ns (Levels of Logic = 0)
  Clock Path Delay:     3.981ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Minimum Clock Path: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.466   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.103   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.166   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    N9.OTCLK1            net (fanout=84)       0.246   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.981ns (2.632ns logic, 1.349ns route)
                                                       (66.1% logic, 33.9% route)

  Minimum Data Path: RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0 to O_FX2_SLRD_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    N9.PAD               Tiockp                2.292   O_FX2_SLRD_N
                                                       RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0
                                                       O_FX2_SLRD_N_OBUF
                                                       O_FX2_SLRD_N
    -------------------------------------------------  ---------------------------
    Total                                      2.292ns (2.292ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  6.247ns (clock arrival + clock path + data path - uncertainty)
  Source:               RLINK/FX2CNTL/IOB_FX2_PKTEND/IOB/R_DO_0 (FF)
  Destination:          O_FX2_PKTEND_N (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Data Path Delay:      2.292ns (Levels of Logic = 0)
  Clock Path Delay:     3.955ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Minimum Clock Path: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_PKTEND/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.466   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.103   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.166   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    V12.OTCLK1           net (fanout=84)       0.220   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.955ns (2.632ns logic, 1.323ns route)
                                                       (66.5% logic, 33.5% route)

  Minimum Data Path: RLINK/FX2CNTL/IOB_FX2_PKTEND/IOB/R_DO_0 to O_FX2_PKTEND_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V12.PAD              Tiockp                2.292   O_FX2_PKTEND_N
                                                       RLINK/FX2CNTL/IOB_FX2_PKTEND/IOB/R_DO_0
                                                       O_FX2_PKTEND_N_OBUF
                                                       O_FX2_PKTEND_N
    -------------------------------------------------  ---------------------------
    Total                                      2.292ns (2.292ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  6.247ns (clock arrival + clock path + data path - uncertainty)
  Source:               RLINK/FX2CNTL/IOB_FX2_FIFO/R_DO_1 (FF)
  Destination:          O_FX2_FIFO<1> (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Data Path Delay:      2.292ns (Levels of Logic = 0)
  Clock Path Delay:     3.955ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Minimum Clock Path: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FIFO/R_DO_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T15.I                Tiopi                 1.466   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.I0      net (fanout=1)        1.103   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y0.O       Tgi0o                 1.166   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG.GCLKMUX
                                                       I_FX2_IFCLK_BUFGP/BUFG
    V13.OTCLK1           net (fanout=84)       0.220   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.955ns (2.632ns logic, 1.323ns route)
                                                       (66.5% logic, 33.5% route)

  Minimum Data Path: RLINK/FX2CNTL/IOB_FX2_FIFO/R_DO_1 to O_FX2_FIFO<1>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V13.PAD              Tiockp                2.292   O_FX2_FIFO<1>
                                                       RLINK/FX2CNTL/IOB_FX2_FIFO/R_DO_1
                                                       O_FX2_FIFO_1_OBUF
                                                       O_FX2_FIFO<1>
    -------------------------------------------------  ---------------------------
    Total                                      2.292ns (2.292ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: Unconstrained path analysis 

 320 paths analyzed, 83 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   9.738ns.
--------------------------------------------------------------------------------
Delay (setup path):     9.738ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_3 (FF)
  Data Path Delay:      9.391ns (Levels of Logic = 4)
  Clock Path Skew:      -0.347ns (4.582 - 4.929)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X88Y3.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<0>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F
    SLICE_X78Y16.F1      net (fanout=1)        1.029   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<0>
    SLICE_X78Y16.X       Tif5x                 1.152   RLINK/RLB_DI<0>
                                                       RLINK/RLBMUX/RLB_DI<0>28_G
                                                       RLINK/RLBMUX/RLB_DI<0>28
    SLICE_X66Y16.F2      net (fanout=7)        1.508   RLINK/RLB_DI<0>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X65Y17.F2      net (fanout=6)        0.600   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X65Y17.X       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS_data_and0000
                                                       RLINK/CORE/B2CD/R_REGS_data_and000055
    SLICE_X66Y17.F2      net (fanout=1)        0.398   RLINK/CORE/B2CD/R_REGS_data_and0000
    SLICE_X66Y17.CLK     Tfck                  1.285   RLINK/CORE/B2CD/R_REGS.data_3
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<5>1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<5>_f5
                                                       RLINK/CORE/B2CD/R_REGS.data_3
    -------------------------------------------------  ---------------------------
    Total                                      9.391ns (5.856ns logic, 3.535ns route)
                                                       (62.4% logic, 37.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     9.727ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_3 (FF)
  Data Path Delay:      9.380ns (Levels of Logic = 4)
  Clock Path Skew:      -0.347ns (4.582 - 4.929)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X88Y2.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F
    SLICE_X78Y16.F4      net (fanout=1)        1.018   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>
    SLICE_X78Y16.X       Tif5x                 1.152   RLINK/RLB_DI<0>
                                                       RLINK/RLBMUX/RLB_DI<0>28_G
                                                       RLINK/RLBMUX/RLB_DI<0>28
    SLICE_X66Y16.F2      net (fanout=7)        1.508   RLINK/RLB_DI<0>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X65Y17.F2      net (fanout=6)        0.600   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X65Y17.X       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS_data_and0000
                                                       RLINK/CORE/B2CD/R_REGS_data_and000055
    SLICE_X66Y17.F2      net (fanout=1)        0.398   RLINK/CORE/B2CD/R_REGS_data_and0000
    SLICE_X66Y17.CLK     Tfck                  1.285   RLINK/CORE/B2CD/R_REGS.data_3
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<5>1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<5>_f5
                                                       RLINK/CORE/B2CD/R_REGS.data_3
    -------------------------------------------------  ---------------------------
    Total                                      9.380ns (5.856ns logic, 3.524ns route)
                                                       (62.4% logic, 37.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     9.446ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_1 (FF)
  Data Path Delay:      9.099ns (Levels of Logic = 4)
  Clock Path Skew:      -0.347ns (4.582 - 4.929)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X88Y3.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<0>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F
    SLICE_X78Y16.F1      net (fanout=1)        1.029   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<0>
    SLICE_X78Y16.X       Tif5x                 1.152   RLINK/RLB_DI<0>
                                                       RLINK/RLBMUX/RLB_DI<0>28_G
                                                       RLINK/RLBMUX/RLB_DI<0>28
    SLICE_X66Y16.F2      net (fanout=7)        1.508   RLINK/RLB_DI<0>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X64Y17.G3      net (fanout=6)        0.522   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X64Y17.Y       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_6
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>11
    SLICE_X67Y17.F1      net (fanout=4)        0.577   RLINK/CORE/B2CD/N11
    SLICE_X67Y17.CLK     Tfck                  0.837   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>1
                                                       RLINK/CORE/B2CD/R_REGS.data_1
    -------------------------------------------------  ---------------------------
    Total                                      9.099ns (5.463ns logic, 3.636ns route)
                                                       (60.0% logic, 40.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     9.435ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_1 (FF)
  Data Path Delay:      9.088ns (Levels of Logic = 4)
  Clock Path Skew:      -0.347ns (4.582 - 4.929)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X88Y2.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F
    SLICE_X78Y16.F4      net (fanout=1)        1.018   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>
    SLICE_X78Y16.X       Tif5x                 1.152   RLINK/RLB_DI<0>
                                                       RLINK/RLBMUX/RLB_DI<0>28_G
                                                       RLINK/RLBMUX/RLB_DI<0>28
    SLICE_X66Y16.F2      net (fanout=7)        1.508   RLINK/RLB_DI<0>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X64Y17.G3      net (fanout=6)        0.522   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X64Y17.Y       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_6
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>11
    SLICE_X67Y17.F1      net (fanout=4)        0.577   RLINK/CORE/B2CD/N11
    SLICE_X67Y17.CLK     Tfck                  0.837   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>1
                                                       RLINK/CORE/B2CD/R_REGS.data_1
    -------------------------------------------------  ---------------------------
    Total                                      9.088ns (5.463ns logic, 3.625ns route)
                                                       (60.1% logic, 39.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     9.433ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_0 (FF)
  Data Path Delay:      9.086ns (Levels of Logic = 4)
  Clock Path Skew:      -0.347ns (4.582 - 4.929)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X88Y3.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<0>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F
    SLICE_X78Y16.F1      net (fanout=1)        1.029   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<0>
    SLICE_X78Y16.X       Tif5x                 1.152   RLINK/RLB_DI<0>
                                                       RLINK/RLBMUX/RLB_DI<0>28_G
                                                       RLINK/RLBMUX/RLB_DI<0>28
    SLICE_X66Y16.F2      net (fanout=7)        1.508   RLINK/RLB_DI<0>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X64Y17.G3      net (fanout=6)        0.522   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X64Y17.Y       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_6
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>11
    SLICE_X66Y16.G4      net (fanout=4)        0.509   RLINK/CORE/B2CD/N11
    SLICE_X66Y16.CLK     Tgck                  0.892   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<8>1
                                                       RLINK/CORE/B2CD/R_REGS.data_0
    -------------------------------------------------  ---------------------------
    Total                                      9.086ns (5.518ns logic, 3.568ns route)
                                                       (60.7% logic, 39.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     9.422ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_0 (FF)
  Data Path Delay:      9.075ns (Levels of Logic = 4)
  Clock Path Skew:      -0.347ns (4.582 - 4.929)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X88Y2.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F
    SLICE_X78Y16.F4      net (fanout=1)        1.018   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>
    SLICE_X78Y16.X       Tif5x                 1.152   RLINK/RLB_DI<0>
                                                       RLINK/RLBMUX/RLB_DI<0>28_G
                                                       RLINK/RLBMUX/RLB_DI<0>28
    SLICE_X66Y16.F2      net (fanout=7)        1.508   RLINK/RLB_DI<0>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X64Y17.G3      net (fanout=6)        0.522   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X64Y17.Y       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_6
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>11
    SLICE_X66Y16.G4      net (fanout=4)        0.509   RLINK/CORE/B2CD/N11
    SLICE_X66Y16.CLK     Tgck                  0.892   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<8>1
                                                       RLINK/CORE/B2CD/R_REGS.data_0
    -------------------------------------------------  ---------------------------
    Total                                      9.075ns (5.518ns logic, 3.557ns route)
                                                       (60.8% logic, 39.2% route)

--------------------------------------------------------------------------------
Delay (setup path):     9.256ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_1 (FF)
  Data Path Delay:      8.909ns (Levels of Logic = 4)
  Clock Path Skew:      -0.347ns (4.582 - 4.929)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X88Y3.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<0>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F
    SLICE_X78Y16.F1      net (fanout=1)        1.029   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<0>
    SLICE_X78Y16.X       Tif5x                 1.152   RLINK/RLB_DI<0>
                                                       RLINK/RLBMUX/RLB_DI<0>28_G
                                                       RLINK/RLBMUX/RLB_DI<0>28
    SLICE_X66Y16.F2      net (fanout=7)        1.508   RLINK/RLB_DI<0>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X67Y17.G4      net (fanout=6)        0.072   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X67Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>21
    SLICE_X67Y17.F2      net (fanout=2)        0.892   RLINK/CORE/B2CD/N2
    SLICE_X67Y17.CLK     Tfck                  0.837   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>1
                                                       RLINK/CORE/B2CD/R_REGS.data_1
    -------------------------------------------------  ---------------------------
    Total                                      8.909ns (5.408ns logic, 3.501ns route)
                                                       (60.7% logic, 39.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     9.245ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_1 (FF)
  Data Path Delay:      8.898ns (Levels of Logic = 4)
  Clock Path Skew:      -0.347ns (4.582 - 4.929)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X88Y2.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F
    SLICE_X78Y16.F4      net (fanout=1)        1.018   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>
    SLICE_X78Y16.X       Tif5x                 1.152   RLINK/RLB_DI<0>
                                                       RLINK/RLBMUX/RLB_DI<0>28_G
                                                       RLINK/RLBMUX/RLB_DI<0>28
    SLICE_X66Y16.F2      net (fanout=7)        1.508   RLINK/RLB_DI<0>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X67Y17.G4      net (fanout=6)        0.072   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X67Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>21
    SLICE_X67Y17.F2      net (fanout=2)        0.892   RLINK/CORE/B2CD/N2
    SLICE_X67Y17.CLK     Tfck                  0.837   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>1
                                                       RLINK/CORE/B2CD/R_REGS.data_1
    -------------------------------------------------  ---------------------------
    Total                                      8.898ns (5.408ns logic, 3.490ns route)
                                                       (60.8% logic, 39.2% route)

--------------------------------------------------------------------------------
Delay (setup path):     9.233ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_0 (FF)
  Data Path Delay:      8.886ns (Levels of Logic = 4)
  Clock Path Skew:      -0.347ns (4.582 - 4.929)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X88Y3.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<0>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F
    SLICE_X78Y16.F1      net (fanout=1)        1.029   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<0>
    SLICE_X78Y16.X       Tif5x                 1.152   RLINK/RLB_DI<0>
                                                       RLINK/RLBMUX/RLB_DI<0>28_G
                                                       RLINK/RLBMUX/RLB_DI<0>28
    SLICE_X66Y16.F2      net (fanout=7)        1.508   RLINK/RLB_DI<0>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X67Y17.G4      net (fanout=6)        0.072   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X67Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>21
    SLICE_X66Y16.G3      net (fanout=2)        0.814   RLINK/CORE/B2CD/N2
    SLICE_X66Y16.CLK     Tgck                  0.892   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<8>1
                                                       RLINK/CORE/B2CD/R_REGS.data_0
    -------------------------------------------------  ---------------------------
    Total                                      8.886ns (5.463ns logic, 3.423ns route)
                                                       (61.5% logic, 38.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     9.222ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_0 (FF)
  Data Path Delay:      8.875ns (Levels of Logic = 4)
  Clock Path Skew:      -0.347ns (4.582 - 4.929)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X88Y2.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F
    SLICE_X78Y16.F4      net (fanout=1)        1.018   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>
    SLICE_X78Y16.X       Tif5x                 1.152   RLINK/RLB_DI<0>
                                                       RLINK/RLBMUX/RLB_DI<0>28_G
                                                       RLINK/RLBMUX/RLB_DI<0>28
    SLICE_X66Y16.F2      net (fanout=7)        1.508   RLINK/RLB_DI<0>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X67Y17.G4      net (fanout=6)        0.072   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X67Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>21
    SLICE_X66Y16.G3      net (fanout=2)        0.814   RLINK/CORE/B2CD/N2
    SLICE_X66Y16.CLK     Tgck                  0.892   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<8>1
                                                       RLINK/CORE/B2CD/R_REGS.data_0
    -------------------------------------------------  ---------------------------
    Total                                      8.875ns (5.463ns logic, 3.412ns route)
                                                       (61.6% logic, 38.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     9.010ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_1 (FF)
  Data Path Delay:      8.720ns (Levels of Logic = 4)
  Clock Path Skew:      -0.290ns (4.582 - 4.872)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X74Y4.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<2>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0.SLICEM_F
    SLICE_X75Y13.F1      net (fanout=1)        0.660   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<2>
    SLICE_X75Y13.X       Tif5x                 1.025   RLINK/RLB_DI<2>
                                                       RLINK/RLBMUX/RLB_DI<2>28_G
                                                       RLINK/RLBMUX/RLB_DI<2>28
    SLICE_X65Y17.G1      net (fanout=9)        1.508   RLINK/RLB_DI<2>
    SLICE_X65Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS_data_and0000
                                                       RLINK/CORE/B2CD/R_REGS_data_and000054
    SLICE_X67Y17.G2      net (fanout=6)        0.434   RLINK/CORE/B2CD/R_REGS_data_and000054
    SLICE_X67Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>21
    SLICE_X67Y17.F2      net (fanout=2)        0.892   RLINK/CORE/B2CD/N2
    SLICE_X67Y17.CLK     Tfck                  0.837   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>1
                                                       RLINK/CORE/B2CD/R_REGS.data_1
    -------------------------------------------------  ---------------------------
    Total                                      8.720ns (5.226ns logic, 3.494ns route)
                                                       (59.9% logic, 40.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.991ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_6 (FF)
  Data Path Delay:      8.634ns (Levels of Logic = 4)
  Clock Path Skew:      -0.357ns (4.572 - 4.929)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X88Y3.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<0>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F
    SLICE_X78Y16.F1      net (fanout=1)        1.029   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<0>
    SLICE_X78Y16.X       Tif5x                 1.152   RLINK/RLB_DI<0>
                                                       RLINK/RLBMUX/RLB_DI<0>28_G
                                                       RLINK/RLBMUX/RLB_DI<0>28
    SLICE_X66Y16.F2      net (fanout=7)        1.508   RLINK/RLB_DI<0>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X64Y17.G3      net (fanout=6)        0.522   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X64Y17.Y       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_6
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>11
    SLICE_X64Y17.F3      net (fanout=4)        0.057   RLINK/CORE/B2CD/N11
    SLICE_X64Y17.CLK     Tfck                  0.892   RLINK/CORE/B2CD/R_REGS.data_6
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<2>1
                                                       RLINK/CORE/B2CD/R_REGS.data_6
    -------------------------------------------------  ---------------------------
    Total                                      8.634ns (5.518ns logic, 3.116ns route)
                                                       (63.9% logic, 36.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.991ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_7 (FF)
  Data Path Delay:      8.634ns (Levels of Logic = 4)
  Clock Path Skew:      -0.357ns (4.572 - 4.929)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X88Y3.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<0>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1.SLICEM_F
    SLICE_X78Y16.F1      net (fanout=1)        1.029   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<0>
    SLICE_X78Y16.X       Tif5x                 1.152   RLINK/RLB_DI<0>
                                                       RLINK/RLBMUX/RLB_DI<0>28_G
                                                       RLINK/RLBMUX/RLB_DI<0>28
    SLICE_X66Y16.F2      net (fanout=7)        1.508   RLINK/RLB_DI<0>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X64Y17.G3      net (fanout=6)        0.522   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X64Y17.Y       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_6
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>11
    SLICE_X64Y16.G3      net (fanout=4)        0.057   RLINK/CORE/B2CD/N11
    SLICE_X64Y16.CLK     Tgck                  0.892   RLINK/CORE/B2CD/R_REGS.data_7
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<1>1
                                                       RLINK/CORE/B2CD/R_REGS.data_7
    -------------------------------------------------  ---------------------------
    Total                                      8.634ns (5.518ns logic, 3.116ns route)
                                                       (63.9% logic, 36.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.987ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_0 (FF)
  Data Path Delay:      8.697ns (Levels of Logic = 4)
  Clock Path Skew:      -0.290ns (4.582 - 4.872)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X74Y4.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<2>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0.SLICEM_F
    SLICE_X75Y13.F1      net (fanout=1)        0.660   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<2>
    SLICE_X75Y13.X       Tif5x                 1.025   RLINK/RLB_DI<2>
                                                       RLINK/RLBMUX/RLB_DI<2>28_G
                                                       RLINK/RLBMUX/RLB_DI<2>28
    SLICE_X65Y17.G1      net (fanout=9)        1.508   RLINK/RLB_DI<2>
    SLICE_X65Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS_data_and0000
                                                       RLINK/CORE/B2CD/R_REGS_data_and000054
    SLICE_X67Y17.G2      net (fanout=6)        0.434   RLINK/CORE/B2CD/R_REGS_data_and000054
    SLICE_X67Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>21
    SLICE_X66Y16.G3      net (fanout=2)        0.814   RLINK/CORE/B2CD/N2
    SLICE_X66Y16.CLK     Tgck                  0.892   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<8>1
                                                       RLINK/CORE/B2CD/R_REGS.data_0
    -------------------------------------------------  ---------------------------
    Total                                      8.697ns (5.281ns logic, 3.416ns route)
                                                       (60.7% logic, 39.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.980ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_6 (FF)
  Data Path Delay:      8.623ns (Levels of Logic = 4)
  Clock Path Skew:      -0.357ns (4.572 - 4.929)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X88Y2.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F
    SLICE_X78Y16.F4      net (fanout=1)        1.018   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>
    SLICE_X78Y16.X       Tif5x                 1.152   RLINK/RLB_DI<0>
                                                       RLINK/RLBMUX/RLB_DI<0>28_G
                                                       RLINK/RLBMUX/RLB_DI<0>28
    SLICE_X66Y16.F2      net (fanout=7)        1.508   RLINK/RLB_DI<0>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X64Y17.G3      net (fanout=6)        0.522   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X64Y17.Y       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_6
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>11
    SLICE_X64Y17.F3      net (fanout=4)        0.057   RLINK/CORE/B2CD/N11
    SLICE_X64Y17.CLK     Tfck                  0.892   RLINK/CORE/B2CD/R_REGS.data_6
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<2>1
                                                       RLINK/CORE/B2CD/R_REGS.data_6
    -------------------------------------------------  ---------------------------
    Total                                      8.623ns (5.518ns logic, 3.105ns route)
                                                       (64.0% logic, 36.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.980ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_7 (FF)
  Data Path Delay:      8.623ns (Levels of Logic = 4)
  Clock Path Skew:      -0.357ns (4.572 - 4.929)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X88Y2.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0.SLICEM_F
    SLICE_X78Y16.F4      net (fanout=1)        1.018   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<0>
    SLICE_X78Y16.X       Tif5x                 1.152   RLINK/RLB_DI<0>
                                                       RLINK/RLBMUX/RLB_DI<0>28_G
                                                       RLINK/RLBMUX/RLB_DI<0>28
    SLICE_X66Y16.F2      net (fanout=7)        1.508   RLINK/RLB_DI<0>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X64Y17.G3      net (fanout=6)        0.522   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X64Y17.Y       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_6
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>11
    SLICE_X64Y16.G3      net (fanout=4)        0.057   RLINK/CORE/B2CD/N11
    SLICE_X64Y16.CLK     Tgck                  0.892   RLINK/CORE/B2CD/R_REGS.data_7
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<1>1
                                                       RLINK/CORE/B2CD/R_REGS.data_7
    -------------------------------------------------  ---------------------------
    Total                                      8.623ns (5.518ns logic, 3.105ns route)
                                                       (64.0% logic, 36.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.878ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_1 (FF)
  Data Path Delay:      8.588ns (Levels of Logic = 4)
  Clock Path Skew:      -0.290ns (4.582 - 4.872)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X74Y5.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<2>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1.SLICEM_F
    SLICE_X75Y13.F4      net (fanout=1)        0.528   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<2>
    SLICE_X75Y13.X       Tif5x                 1.025   RLINK/RLB_DI<2>
                                                       RLINK/RLBMUX/RLB_DI<2>28_G
                                                       RLINK/RLBMUX/RLB_DI<2>28
    SLICE_X65Y17.G1      net (fanout=9)        1.508   RLINK/RLB_DI<2>
    SLICE_X65Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS_data_and0000
                                                       RLINK/CORE/B2CD/R_REGS_data_and000054
    SLICE_X67Y17.G2      net (fanout=6)        0.434   RLINK/CORE/B2CD/R_REGS_data_and000054
    SLICE_X67Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>21
    SLICE_X67Y17.F2      net (fanout=2)        0.892   RLINK/CORE/B2CD/N2
    SLICE_X67Y17.CLK     Tfck                  0.837   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>1
                                                       RLINK/CORE/B2CD/R_REGS.data_1
    -------------------------------------------------  ---------------------------
    Total                                      8.588ns (5.226ns logic, 3.362ns route)
                                                       (60.9% logic, 39.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.855ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_0 (FF)
  Data Path Delay:      8.565ns (Levels of Logic = 4)
  Clock Path Skew:      -0.290ns (4.582 - 4.872)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X74Y5.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<2>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1.SLICEM_F
    SLICE_X75Y13.F4      net (fanout=1)        0.528   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<2>
    SLICE_X75Y13.X       Tif5x                 1.025   RLINK/RLB_DI<2>
                                                       RLINK/RLBMUX/RLB_DI<2>28_G
                                                       RLINK/RLBMUX/RLB_DI<2>28
    SLICE_X65Y17.G1      net (fanout=9)        1.508   RLINK/RLB_DI<2>
    SLICE_X65Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS_data_and0000
                                                       RLINK/CORE/B2CD/R_REGS_data_and000054
    SLICE_X67Y17.G2      net (fanout=6)        0.434   RLINK/CORE/B2CD/R_REGS_data_and000054
    SLICE_X67Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>21
    SLICE_X66Y16.G3      net (fanout=2)        0.814   RLINK/CORE/B2CD/N2
    SLICE_X66Y16.CLK     Tgck                  0.892   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<8>1
                                                       RLINK/CORE/B2CD/R_REGS.data_0
    -------------------------------------------------  ---------------------------
    Total                                      8.565ns (5.281ns logic, 3.284ns route)
                                                       (61.7% logic, 38.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.701ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_1 (FF)
  Data Path Delay:      8.472ns (Levels of Logic = 4)
  Clock Path Skew:      -0.229ns (4.582 - 4.811)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X62Y4.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<6>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0.SLICEM_F
    SLICE_X68Y14.F1      net (fanout=1)        1.089   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<6>
    SLICE_X68Y14.X       Tif5x                 1.152   RLINK/RLB_DI<6>
                                                       RLINK/RLBMUX/RLB_DI<6>28_G
                                                       RLINK/RLBMUX/RLB_DI<6>28
    SLICE_X65Y17.G2      net (fanout=3)        0.704   RLINK/RLB_DI<6>
    SLICE_X65Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS_data_and0000
                                                       RLINK/CORE/B2CD/R_REGS_data_and000054
    SLICE_X67Y17.G2      net (fanout=6)        0.434   RLINK/CORE/B2CD/R_REGS_data_and000054
    SLICE_X67Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>21
    SLICE_X67Y17.F2      net (fanout=2)        0.892   RLINK/CORE/B2CD/N2
    SLICE_X67Y17.CLK     Tfck                  0.837   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>1
                                                       RLINK/CORE/B2CD/R_REGS.data_1
    -------------------------------------------------  ---------------------------
    Total                                      8.472ns (5.353ns logic, 3.119ns route)
                                                       (63.2% logic, 36.8% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.697ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_3 (FF)
  Data Path Delay:      8.398ns (Levels of Logic = 4)
  Clock Path Skew:      -0.299ns (4.582 - 4.881)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X76Y7.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0.SLICEM_F
    SLICE_X75Y10.F2      net (fanout=1)        0.663   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<3>
    SLICE_X75Y10.X       Tif5x                 1.025   RLINK/RLB_DI<3>
                                                       RLINK/RLBMUX/RLB_DI<3>28_G
                                                       RLINK/RLBMUX/RLB_DI<3>28
    SLICE_X66Y16.F3      net (fanout=3)        1.008   RLINK/RLB_DI<3>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X65Y17.F2      net (fanout=6)        0.600   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X65Y17.X       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS_data_and0000
                                                       RLINK/CORE/B2CD/R_REGS_data_and000055
    SLICE_X66Y17.F2      net (fanout=1)        0.398   RLINK/CORE/B2CD/R_REGS_data_and0000
    SLICE_X66Y17.CLK     Tfck                  1.285   RLINK/CORE/B2CD/R_REGS.data_3
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<5>1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<5>_f5
                                                       RLINK/CORE/B2CD/R_REGS.data_3
    -------------------------------------------------  ---------------------------
    Total                                      8.398ns (5.729ns logic, 2.669ns route)
                                                       (68.2% logic, 31.8% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.678ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_0 (FF)
  Data Path Delay:      8.449ns (Levels of Logic = 4)
  Clock Path Skew:      -0.229ns (4.582 - 4.811)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X62Y4.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<6>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0.SLICEM_F
    SLICE_X68Y14.F1      net (fanout=1)        1.089   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<6>
    SLICE_X68Y14.X       Tif5x                 1.152   RLINK/RLB_DI<6>
                                                       RLINK/RLBMUX/RLB_DI<6>28_G
                                                       RLINK/RLBMUX/RLB_DI<6>28
    SLICE_X65Y17.G2      net (fanout=3)        0.704   RLINK/RLB_DI<6>
    SLICE_X65Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS_data_and0000
                                                       RLINK/CORE/B2CD/R_REGS_data_and000054
    SLICE_X67Y17.G2      net (fanout=6)        0.434   RLINK/CORE/B2CD/R_REGS_data_and000054
    SLICE_X67Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>21
    SLICE_X66Y16.G3      net (fanout=2)        0.814   RLINK/CORE/B2CD/N2
    SLICE_X66Y16.CLK     Tgck                  0.892   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<8>1
                                                       RLINK/CORE/B2CD/R_REGS.data_0
    -------------------------------------------------  ---------------------------
    Total                                      8.449ns (5.408ns logic, 3.041ns route)
                                                       (64.0% logic, 36.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.655ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_3 (FF)
  Data Path Delay:      8.342ns (Levels of Logic = 4)
  Clock Path Skew:      -0.313ns (4.582 - 4.895)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X78Y3.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<1>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0.SLICEM_F
    SLICE_X79Y12.F1      net (fanout=1)        0.776   RLINK/FX2CNTL/RXFIFO/RAM/DOB0<1>
    SLICE_X79Y12.X       Tif5x                 1.025   RLINK/RLB_DI<1>
                                                       RLINK/RLBMUX/RLB_DI<1>28_G
                                                       RLINK/RLBMUX/RLB_DI<1>28
    SLICE_X66Y16.F1      net (fanout=9)        0.839   RLINK/RLB_DI<1>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X65Y17.F2      net (fanout=6)        0.600   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X65Y17.X       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS_data_and0000
                                                       RLINK/CORE/B2CD/R_REGS_data_and000055
    SLICE_X66Y17.F2      net (fanout=1)        0.398   RLINK/CORE/B2CD/R_REGS_data_and0000
    SLICE_X66Y17.CLK     Tfck                  1.285   RLINK/CORE/B2CD/R_REGS.data_3
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<5>1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<5>_f5
                                                       RLINK/CORE/B2CD/R_REGS.data_3
    -------------------------------------------------  ---------------------------
    Total                                      8.342ns (5.729ns logic, 2.613ns route)
                                                       (68.7% logic, 31.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.645ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_1 (FF)
  Data Path Delay:      8.413ns (Levels of Logic = 4)
  Clock Path Skew:      -0.232ns (4.582 - 4.814)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X62Y1.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<6>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1.SLICEM_F
    SLICE_X68Y14.F2      net (fanout=1)        1.030   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<6>
    SLICE_X68Y14.X       Tif5x                 1.152   RLINK/RLB_DI<6>
                                                       RLINK/RLBMUX/RLB_DI<6>28_G
                                                       RLINK/RLBMUX/RLB_DI<6>28
    SLICE_X65Y17.G2      net (fanout=3)        0.704   RLINK/RLB_DI<6>
    SLICE_X65Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS_data_and0000
                                                       RLINK/CORE/B2CD/R_REGS_data_and000054
    SLICE_X67Y17.G2      net (fanout=6)        0.434   RLINK/CORE/B2CD/R_REGS_data_and000054
    SLICE_X67Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>21
    SLICE_X67Y17.F2      net (fanout=2)        0.892   RLINK/CORE/B2CD/N2
    SLICE_X67Y17.CLK     Tfck                  0.837   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>1
                                                       RLINK/CORE/B2CD/R_REGS.data_1
    -------------------------------------------------  ---------------------------
    Total                                      8.413ns (5.353ns logic, 3.060ns route)
                                                       (63.6% logic, 36.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.622ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_0 (FF)
  Data Path Delay:      8.390ns (Levels of Logic = 4)
  Clock Path Skew:      -0.232ns (4.582 - 4.814)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X62Y1.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<6>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1.SLICEM_F
    SLICE_X68Y14.F2      net (fanout=1)        1.030   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<6>
    SLICE_X68Y14.X       Tif5x                 1.152   RLINK/RLB_DI<6>
                                                       RLINK/RLBMUX/RLB_DI<6>28_G
                                                       RLINK/RLBMUX/RLB_DI<6>28
    SLICE_X65Y17.G2      net (fanout=3)        0.704   RLINK/RLB_DI<6>
    SLICE_X65Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS_data_and0000
                                                       RLINK/CORE/B2CD/R_REGS_data_and000054
    SLICE_X67Y17.G2      net (fanout=6)        0.434   RLINK/CORE/B2CD/R_REGS_data_and000054
    SLICE_X67Y17.Y       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS.data_1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<7>21
    SLICE_X66Y16.G3      net (fanout=2)        0.814   RLINK/CORE/B2CD/N2
    SLICE_X66Y16.CLK     Tgck                  0.892   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<8>1
                                                       RLINK/CORE/B2CD/R_REGS.data_0
    -------------------------------------------------  ---------------------------
    Total                                      8.390ns (5.408ns logic, 2.982ns route)
                                                       (64.5% logic, 35.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.619ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1.SLICEM_F (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS.data_3 (FF)
  Data Path Delay:      8.320ns (Levels of Logic = 4)
  Clock Path Skew:      -0.299ns (4.582 - 4.881)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1.SLICEM_F to RLINK/CORE/B2CD/R_REGS.data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X76Y6.X        Tshcko                1.956   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1.WE
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1.SLICEM_F
    SLICE_X75Y10.F3      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/DOB1<3>
    SLICE_X75Y10.X       Tif5x                 1.025   RLINK/RLB_DI<3>
                                                       RLINK/RLBMUX/RLB_DI<3>28_G
                                                       RLINK/RLBMUX/RLB_DI<3>28
    SLICE_X66Y16.F3      net (fanout=3)        1.008   RLINK/RLB_DI<3>
    SLICE_X66Y16.X       Tilo                  0.759   RLINK/CORE/B2CD/R_REGS.data_0
                                                       RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X65Y17.F2      net (fanout=6)        0.600   RLINK/CORE/B2CD/R_REGS_data_and000032
    SLICE_X65Y17.X       Tilo                  0.704   RLINK/CORE/B2CD/R_REGS_data_and0000
                                                       RLINK/CORE/B2CD/R_REGS_data_and000055
    SLICE_X66Y17.F2      net (fanout=1)        0.398   RLINK/CORE/B2CD/R_REGS_data_and0000
    SLICE_X66Y17.CLK     Tfck                  1.285   RLINK/CORE/B2CD/R_REGS.data_3
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<5>1
                                                       RLINK/CORE/B2CD/R_REGS_data_mux0001<5>_f5
                                                       RLINK/CORE/B2CD/R_REGS.data_3
    -------------------------------------------------  ---------------------------
    Total                                      8.320ns (5.729ns logic, 2.591ns route)
                                                       (68.9% logic, 31.1% route)

--------------------------------------------------------------------------------

Hold Paths: Unconstrained path analysis

--------------------------------------------------------------------------------
Delay (hold path):      0.863ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_4 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_4 (FF)
  Data Path Delay:      1.107ns (Levels of Logic = 0)
  Clock Path Skew:      0.244ns (4.845 - 4.601)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_4 to RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X71Y7.XQ       Tcko                  0.473   RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_4
    SLICE_X71Y4.BY       net (fanout=17)       0.499   RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
    SLICE_X71Y4.CLK      Tckdi       (-Th)    -0.135   RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_4
                                                       RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_4
    -------------------------------------------------  ---------------------------
    Total                                      1.107ns (0.608ns logic, 0.499ns route)
                                                       (54.9% logic, 45.1% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.002ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_1 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_1 (FF)
  Data Path Delay:      1.247ns (Levels of Logic = 0)
  Clock Path Skew:      0.245ns (4.839 - 4.594)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_1 to RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X52Y10.XQ      Tcko                  0.474   RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA<1>
                                                       RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_1
    SLICE_X55Y4.BX       net (fanout=24)       0.680   RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA<1>
    SLICE_X55Y4.CLK      Tckdi       (-Th)    -0.093   RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_1
                                                       RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_1
    -------------------------------------------------  ---------------------------
    Total                                      1.247ns (0.567ns logic, 0.680ns route)
                                                       (45.5% logic, 54.5% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.543ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_3 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_3 (FF)
  Data Path Delay:      1.296ns (Levels of Logic = 0)
  Clock Path Skew:      -0.247ns (4.598 - 4.845)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_3 to RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X70Y5.XQ       Tcko                  0.474   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<3>
                                                       RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_3
    SLICE_X70Y8.BX       net (fanout=24)       0.688   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<3>
    SLICE_X70Y8.CLK      Tckdi       (-Th)    -0.134   RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_3
                                                       RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_3
    -------------------------------------------------  ---------------------------
    Total                                      1.296ns (0.608ns logic, 0.688ns route)
                                                       (46.9% logic, 53.1% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.058ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_0 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_0 (FF)
  Data Path Delay:      1.326ns (Levels of Logic = 0)
  Clock Path Skew:      0.268ns (4.869 - 4.601)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_0 to RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X70Y6.YQ       Tcko                  0.522   RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA<1>
                                                       RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_0
    SLICE_X74Y7.BY       net (fanout=21)       0.652   RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA<0>
    SLICE_X74Y7.CLK      Tckdi       (-Th)    -0.152   RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_1
                                                       RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_0
    -------------------------------------------------  ---------------------------
    Total                                      1.326ns (0.674ns logic, 0.652ns route)
                                                       (50.8% logic, 49.2% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.592ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_2 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_2 (FF)
  Data Path Delay:      1.359ns (Levels of Logic = 0)
  Clock Path Skew:      -0.233ns (4.603 - 4.836)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_2 to RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X54Y6.XQ       Tcko                  0.474   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<2>
                                                       RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_2
    SLICE_X48Y8.BY       net (fanout=24)       0.733   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<2>
    SLICE_X48Y8.CLK      Tckdi       (-Th)    -0.152   RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_3
                                                       RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_2
    -------------------------------------------------  ---------------------------
    Total                                      1.359ns (0.626ns logic, 0.733ns route)
                                                       (46.1% logic, 53.9% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.104ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_0 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_0 (FF)
  Data Path Delay:      1.349ns (Levels of Logic = 0)
  Clock Path Skew:      0.245ns (4.839 - 4.594)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_0 to RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X52Y11.YQ      Tcko                  0.522   RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA<3>
                                                       RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_0
    SLICE_X55Y4.BY       net (fanout=22)       0.692   RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA<0>
    SLICE_X55Y4.CLK      Tckdi       (-Th)    -0.135   RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_1
                                                       RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_0
    -------------------------------------------------  ---------------------------
    Total                                      1.349ns (0.657ns logic, 0.692ns route)
                                                       (48.7% logic, 51.3% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.602ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_4 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_4 (FF)
  Data Path Delay:      1.374ns (Levels of Logic = 0)
  Clock Path Skew:      -0.228ns (4.601 - 4.829)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_4 to RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X56Y6.XQ       Tcko                  0.474   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_4
    SLICE_X51Y8.BY       net (fanout=17)       0.765   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
    SLICE_X51Y8.CLK      Tckdi       (-Th)    -0.135   RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_4
                                                       RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_4
    -------------------------------------------------  ---------------------------
    Total                                      1.374ns (0.609ns logic, 0.765ns route)
                                                       (44.3% logic, 55.7% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.655ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_2 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_2 (FF)
  Data Path Delay:      1.416ns (Levels of Logic = 0)
  Clock Path Skew:      -0.239ns (4.598 - 4.837)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_2 to RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X69Y2.XQ       Tcko                  0.473   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<2>
                                                       RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_2
    SLICE_X70Y8.BY       net (fanout=23)       0.791   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<2>
    SLICE_X70Y8.CLK      Tckdi       (-Th)    -0.152   RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_3
                                                       RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_2
    -------------------------------------------------  ---------------------------
    Total                                      1.416ns (0.625ns logic, 0.791ns route)
                                                       (44.1% logic, 55.9% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.216ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_3 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_3 (FF)
  Data Path Delay:      1.487ns (Levels of Logic = 0)
  Clock Path Skew:      0.271ns (4.869 - 4.598)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_3 to RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X70Y9.YQ       Tcko                  0.522   RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA<3>
                                                       RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_3
    SLICE_X74Y6.BX       net (fanout=24)       0.831   RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA<3>
    SLICE_X74Y6.CLK      Tckdi       (-Th)    -0.134   RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_3
                                                       RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_3
    -------------------------------------------------  ---------------------------
    Total                                      1.487ns (0.656ns logic, 0.831ns route)
                                                       (44.1% logic, 55.9% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.221ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_1 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_1 (FF)
  Data Path Delay:      1.489ns (Levels of Logic = 0)
  Clock Path Skew:      0.268ns (4.869 - 4.601)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_1 to RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X70Y6.XQ       Tcko                  0.474   RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA<1>
                                                       RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_1
    SLICE_X74Y7.BX       net (fanout=23)       0.881   RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA<1>
    SLICE_X74Y7.CLK      Tckdi       (-Th)    -0.134   RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_1
                                                       RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_1
    -------------------------------------------------  ---------------------------
    Total                                      1.489ns (0.608ns logic, 0.881ns route)
                                                       (40.8% logic, 59.2% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.265ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_2 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_2 (FF)
  Data Path Delay:      1.510ns (Levels of Logic = 0)
  Clock Path Skew:      0.245ns (4.839 - 4.594)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_2 to RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X53Y10.XQ      Tcko                  0.473   RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA<2>
                                                       RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_2
    SLICE_X54Y4.BY       net (fanout=23)       0.885   RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA<2>
    SLICE_X54Y4.CLK      Tckdi       (-Th)    -0.152   RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_3
                                                       RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_2
    -------------------------------------------------  ---------------------------
    Total                                      1.510ns (0.625ns logic, 0.885ns route)
                                                       (41.4% logic, 58.6% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.299ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_3 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_3 (FF)
  Data Path Delay:      1.544ns (Levels of Logic = 0)
  Clock Path Skew:      0.245ns (4.839 - 4.594)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_3 to RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X52Y11.XQ      Tcko                  0.474   RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA<3>
                                                       RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_3
    SLICE_X54Y4.BX       net (fanout=24)       0.936   RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA<3>
    SLICE_X54Y4.CLK      Tckdi       (-Th)    -0.134   RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_3
                                                       RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_3
    -------------------------------------------------  ---------------------------
    Total                                      1.544ns (0.608ns logic, 0.936ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.807ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_0 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_0 (FF)
  Data Path Delay:      1.572ns (Levels of Logic = 0)
  Clock Path Skew:      -0.235ns (4.601 - 4.836)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_0 to RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X55Y6.YQ       Tcko                  0.470   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<1>
                                                       RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_0
    SLICE_X50Y8.BY       net (fanout=21)       0.950   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<0>
    SLICE_X50Y8.CLK      Tckdi       (-Th)    -0.152   RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_1
                                                       RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_0
    -------------------------------------------------  ---------------------------
    Total                                      1.572ns (0.622ns logic, 0.950ns route)
                                                       (39.6% logic, 60.4% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.789ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_1 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_1 (FF)
  Data Path Delay:      1.561ns (Levels of Logic = 0)
  Clock Path Skew:      -0.228ns (4.609 - 4.837)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_1 to RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X68Y3.XQ       Tcko                  0.474   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<1>
                                                       RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_1
    SLICE_X72Y8.BX       net (fanout=24)       0.953   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<1>
    SLICE_X72Y8.CLK      Tckdi       (-Th)    -0.134   RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_1
                                                       RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_1
    -------------------------------------------------  ---------------------------
    Total                                      1.561ns (0.608ns logic, 0.953ns route)
                                                       (38.9% logic, 61.1% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.836ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_4 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_4 (FF)
  Data Path Delay:      1.586ns (Levels of Logic = 0)
  Clock Path Skew:      -0.250ns (4.585 - 4.835)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_4 to RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X69Y4.XQ       Tcko                  0.473   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_4
    SLICE_X69Y11.BY      net (fanout=10)       0.978   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<4>
    SLICE_X69Y11.CLK     Tckdi       (-Th)    -0.135   RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_4
                                                       RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_4
    -------------------------------------------------  ---------------------------
    Total                                      1.586ns (0.608ns logic, 0.978ns route)
                                                       (38.3% logic, 61.7% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.854ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_3 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_3 (FF)
  Data Path Delay:      1.628ns (Levels of Logic = 0)
  Clock Path Skew:      -0.226ns (4.603 - 4.829)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_3 to RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X56Y7.XQ       Tcko                  0.474   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<3>
                                                       RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_3
    SLICE_X48Y8.BX       net (fanout=24)       1.020   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<3>
    SLICE_X48Y8.CLK      Tckdi       (-Th)    -0.134   RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_3
                                                       RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_3
    -------------------------------------------------  ---------------------------
    Total                                      1.628ns (0.608ns logic, 1.020ns route)
                                                       (37.3% logic, 62.7% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.488ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_4 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_4 (FF)
  Data Path Delay:      1.711ns (Levels of Logic = 0)
  Clock Path Skew:      0.223ns (4.817 - 4.594)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_4 to RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X53Y11.XQ      Tcko                  0.473   RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_4
    SLICE_X61Y4.BY       net (fanout=10)       1.103   RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA<4>
    SLICE_X61Y4.CLK      Tckdi       (-Th)    -0.135   RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_4
                                                       RLINK/FX2CNTL/TXFIFO/R_REGR.waddr_c_4
    -------------------------------------------------  ---------------------------
    Total                                      1.711ns (0.608ns logic, 1.103ns route)
                                                       (35.5% logic, 64.5% route)

--------------------------------------------------------------------------------
Delay (hold path):      1.540ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_2 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_2 (FF)
  Data Path Delay:      1.808ns (Levels of Logic = 0)
  Clock Path Skew:      0.268ns (4.869 - 4.601)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_2 to RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X71Y6.XQ       Tcko                  0.473   RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA<2>
                                                       RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA_2
    SLICE_X74Y6.BY       net (fanout=24)       1.183   RLINK/FX2CNTL/RXFIFO/GCR/GRAY_5.CNT/R_DATA<2>
    SLICE_X74Y6.CLK      Tckdi       (-Th)    -0.152   RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_3
                                                       RLINK/FX2CNTL/RXFIFO/R_REGW.raddr_c_2
    -------------------------------------------------  ---------------------------
    Total                                      1.808ns (0.625ns logic, 1.183ns route)
                                                       (34.6% logic, 65.4% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.027ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_1 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_1 (FF)
  Data Path Delay:      1.792ns (Levels of Logic = 0)
  Clock Path Skew:      -0.235ns (4.601 - 4.836)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_1 to RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X55Y6.XQ       Tcko                  0.473   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<1>
                                                       RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_1
    SLICE_X50Y8.BX       net (fanout=23)       1.185   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<1>
    SLICE_X50Y8.CLK      Tckdi       (-Th)    -0.134   RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_1
                                                       RLINK/FX2CNTL/TXFIFO/R_REGW.raddr_c_1
    -------------------------------------------------  ---------------------------
    Total                                      1.792ns (0.607ns logic, 1.185ns route)
                                                       (33.9% logic, 66.1% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.099ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_0 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_0 (FF)
  Data Path Delay:      1.863ns (Levels of Logic = 0)
  Clock Path Skew:      -0.236ns (4.609 - 4.845)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_0 to RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X70Y5.YQ       Tcko                  0.522   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<3>
                                                       RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_0
    SLICE_X72Y8.BY       net (fanout=22)       1.189   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<0>
    SLICE_X72Y8.CLK      Tckdi       (-Th)    -0.152   RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_1
                                                       RLINK/FX2CNTL/RXFIFO/R_REGR.waddr_c_0
    -------------------------------------------------  ---------------------------
    Total                                      1.863ns (0.674ns logic, 1.189ns route)
                                                       (36.2% logic, 63.8% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.856ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM0.SLICEM_F (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6 (FF)
  Data Path Delay:      3.105ns (Levels of Logic = 1)
  Clock Path Skew:      0.249ns (4.854 - 4.605)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM0.SLICEM_F to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X46Y8.X        Tshcko                1.565   RLINK/FX2CNTL/TXFIFO/RAM/DOB0<6>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM0.WE
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM0.SLICEM_F
    SLICE_X47Y9.G4       net (fanout=1)        0.019   RLINK/FX2CNTL/TXFIFO/RAM/DOB0<6>
    SLICE_X47Y9.Y        Tilo                  0.563   RLINK/FX2CNTL/TXFIFO_DO<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/DOB<6>1
    P10.O1               net (fanout=1)        0.675   RLINK/FX2CNTL/TXFIFO_DO<6>
    P10.OTCLK1           Tiocko      (-Th)    -0.283   IO_FX2_DATA<6>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    -------------------------------------------------  ---------------------------
    Total                                      3.105ns (2.411ns logic, 0.694ns route)
                                                       (77.6% logic, 22.4% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.881ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM1.SLICEM_F (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6 (FF)
  Data Path Delay:      3.130ns (Levels of Logic = 1)
  Clock Path Skew:      0.249ns (4.854 - 4.605)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM1.SLICEM_F to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X46Y9.X        Tshcko                1.565   RLINK/FX2CNTL/TXFIFO/RAM/DOB1<6>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM1.WE
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM1.SLICEM_F
    SLICE_X47Y9.G3       net (fanout=1)        0.044   RLINK/FX2CNTL/TXFIFO/RAM/DOB1<6>
    SLICE_X47Y9.Y        Tilo                  0.563   RLINK/FX2CNTL/TXFIFO_DO<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/DOB<6>1
    P10.O1               net (fanout=1)        0.675   RLINK/FX2CNTL/TXFIFO_DO<6>
    P10.OTCLK1           Tiocko      (-Th)    -0.283   IO_FX2_DATA<6>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    -------------------------------------------------  ---------------------------
    Total                                      3.130ns (2.411ns logic, 0.719ns route)
                                                       (77.0% logic, 23.0% route)

--------------------------------------------------------------------------------
Delay (hold path):      3.122ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM0.SLICEM_F (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7 (FF)
  Data Path Delay:      3.379ns (Levels of Logic = 1)
  Clock Path Skew:      0.257ns (4.854 - 4.597)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM0.SLICEM_F to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X52Y8.X        Tshcko                1.565   RLINK/FX2CNTL/TXFIFO/RAM/DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM0.WE
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM0.SLICEM_F
    SLICE_X47Y9.F4       net (fanout=1)        0.478   RLINK/FX2CNTL/TXFIFO/RAM/DOB0<7>
    SLICE_X47Y9.X        Tilo                  0.563   RLINK/FX2CNTL/TXFIFO_DO<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/DOB<7>1
    R10.O1               net (fanout=1)        0.490   RLINK/FX2CNTL/TXFIFO_DO<7>
    R10.OTCLK1           Tiocko      (-Th)    -0.283   IO_FX2_DATA<7>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    -------------------------------------------------  ---------------------------
    Total                                      3.379ns (2.411ns logic, 0.968ns route)
                                                       (71.4% logic, 28.6% route)

--------------------------------------------------------------------------------
Delay (hold path):      3.147ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM1.SLICEM_F (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3 (FF)
  Data Path Delay:      3.397ns (Levels of Logic = 1)
  Clock Path Skew:      0.250ns (4.829 - 4.579)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM1.SLICEM_F to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X58Y6.X        Tshcko                1.565   RLINK/FX2CNTL/TXFIFO/RAM/DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM1.WE
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM1.SLICEM_F
    SLICE_X59Y6.F4       net (fanout=1)        0.018   RLINK/FX2CNTL/TXFIFO/RAM/DOB1<3>
    SLICE_X59Y6.X        Tilo                  0.563   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/DOB<3>1
    T12.O1               net (fanout=1)        0.968   RLINK/FX2CNTL/TXFIFO_DO<3>
    T12.OTCLK1           Tiocko      (-Th)    -0.283   IO_FX2_DATA<3>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    -------------------------------------------------  ---------------------------
    Total                                      3.397ns (2.411ns logic, 0.986ns route)
                                                       (71.0% logic, 29.0% route)

--------------------------------------------------------------------------------
Delay (hold path):      3.197ns (datapath - clock path skew - uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM0.SLICEM_F (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5 (FF)
  Data Path Delay:      3.419ns (Levels of Logic = 1)
  Clock Path Skew:      0.222ns (4.827 - 4.605)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM0.SLICEM_F to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X44Y8.X        Tshcko                1.565   RLINK/FX2CNTL/TXFIFO/RAM/DOB0<5>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM0.WE
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM0.SLICEM_F
    SLICE_X47Y8.F4       net (fanout=1)        0.274   RLINK/FX2CNTL/TXFIFO/RAM/DOB0<5>
    SLICE_X47Y8.X        Tilo                  0.563   RLINK/FX2CNTL/TXFIFO_DO<5>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/DOB<5>1
    R11.O1               net (fanout=1)        0.734   RLINK/FX2CNTL/TXFIFO_DO<5>
    R11.OTCLK1           Tiocko      (-Th)    -0.283   IO_FX2_DATA<5>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    -------------------------------------------------  ---------------------------
    Total                                      3.419ns (2.411ns logic, 1.008ns route)
                                                       (70.5% logic, 29.5% route)

--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_I_CLK50
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_I_CLK50                     |     20.000ns|      6.000ns|     19.958ns|            0|            0|            0|      3146961|
| TS_CLK1                       |     19.231ns|     19.190ns|          N/A|            0|            0|      3146961|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock I_CLK50
---------------+------------+------------+------------------+--------+
               |Max Setup to|Max Hold to |                  | Clock  |
Source         | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
---------------+------------+------------+------------------+--------+
IO_MEM_DATA<0> |    2.424(R)|    0.915(R)|CLK               |   0.000|
IO_MEM_DATA<1> |    2.430(R)|    0.908(R)|CLK               |   0.000|
IO_MEM_DATA<2> |    2.432(R)|    0.906(R)|CLK               |   0.000|
IO_MEM_DATA<3> |    2.427(R)|    0.912(R)|CLK               |   0.000|
IO_MEM_DATA<4> |    2.419(R)|    0.921(R)|CLK               |   0.000|
IO_MEM_DATA<5> |    2.359(R)|    0.992(R)|CLK               |   0.000|
IO_MEM_DATA<6> |    2.359(R)|    0.992(R)|CLK               |   0.000|
IO_MEM_DATA<7> |    2.366(R)|    0.984(R)|CLK               |   0.000|
IO_MEM_DATA<8> |    2.430(R)|    0.908(R)|CLK               |   0.000|
IO_MEM_DATA<9> |    2.432(R)|    0.906(R)|CLK               |   0.000|
IO_MEM_DATA<10>|    2.427(R)|    0.912(R)|CLK               |   0.000|
IO_MEM_DATA<11>|    2.422(R)|    0.918(R)|CLK               |   0.000|
IO_MEM_DATA<12>|    2.424(R)|    0.915(R)|CLK               |   0.000|
IO_MEM_DATA<13>|    2.419(R)|    0.921(R)|CLK               |   0.000|
IO_MEM_DATA<14>|    2.366(R)|    0.984(R)|CLK               |   0.000|
IO_MEM_DATA<15>|    2.362(R)|    0.988(R)|CLK               |   0.000|
I_BTN<0>       |    2.361(R)|    0.989(R)|CLK               |   0.000|
I_BTN<1>       |    2.370(R)|    0.978(R)|CLK               |   0.000|
I_BTN<2>       |    2.420(R)|    0.920(R)|CLK               |   0.000|
I_BTN<3>       |    2.425(R)|    0.914(R)|CLK               |   0.000|
I_FUSP_CTS_N   |    2.364(R)|    0.986(R)|CLK               |   0.000|
I_FUSP_RXD     |    2.369(R)|    0.980(R)|CLK               |   0.000|
I_RXD          |    2.453(R)|    0.881(R)|CLK               |   0.000|
I_SWI<0>       |    2.432(R)|    0.905(R)|CLK               |   0.000|
I_SWI<1>       |    2.423(R)|    0.917(R)|CLK               |   0.000|
I_SWI<2>       |    2.420(R)|    0.920(R)|CLK               |   0.000|
I_SWI<3>       |    2.425(R)|    0.914(R)|CLK               |   0.000|
I_SWI<4>       |    2.423(R)|    0.916(R)|CLK               |   0.000|
I_SWI<5>       |    2.432(R)|    0.905(R)|CLK               |   0.000|
I_SWI<6>       |    2.358(R)|    0.993(R)|CLK               |   0.000|
I_SWI<7>       |    2.366(R)|    0.983(R)|CLK               |   0.000|
---------------+------------+------------+------------------+--------+

Setup/Hold to clock I_FX2_IFCLK
--------------+------------+------------+------------------+--------+
              |Max Setup to|Max Hold to |                  | Clock  |
Source        | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
--------------+------------+------------+------------------+--------+
IO_FX2_DATA<0>|    2.194(R)|    1.201(R)|I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<1>|    2.219(R)|    1.171(R)|I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<2>|    2.219(R)|    1.171(R)|I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<3>|    2.259(R)|    1.124(R)|I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<4>|    2.254(R)|    1.130(R)|I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<5>|    2.261(R)|    1.122(R)|I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<6>|    2.238(R)|    1.149(R)|I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<7>|    2.238(R)|    1.149(R)|I_FX2_IFCLK_BUFGP |   0.000|
I_FX2_FLAG<0> |    2.193(R)|    1.202(R)|I_FX2_IFCLK_BUFGP |   0.000|
I_FX2_FLAG<1> |    2.193(R)|    1.202(R)|I_FX2_IFCLK_BUFGP |   0.000|
I_FX2_FLAG<2> |    2.173(R)|    1.226(R)|I_FX2_IFCLK_BUFGP |   0.000|
--------------+------------+------------+------------------+--------+

Clock I_CLK50 to Pad
---------------+------------+------------------+--------+
               | clk (edge) |                  | Clock  |
Destination    |   to PAD   |Internal Clock(s) | Phase  |
---------------+------------+------------------+--------+
IO_MEM_DATA<0> |    8.215(R)|CLK               |   0.000|
IO_MEM_DATA<1> |    8.208(R)|CLK               |   0.000|
IO_MEM_DATA<2> |    8.206(R)|CLK               |   0.000|
IO_MEM_DATA<3> |    8.212(R)|CLK               |   0.000|
IO_MEM_DATA<4> |    8.221(R)|CLK               |   0.000|
IO_MEM_DATA<5> |    8.292(R)|CLK               |   0.000|
IO_MEM_DATA<6> |    8.292(R)|CLK               |   0.000|
IO_MEM_DATA<7> |    8.284(R)|CLK               |   0.000|
IO_MEM_DATA<8> |    8.208(R)|CLK               |   0.000|
IO_MEM_DATA<9> |    8.206(R)|CLK               |   0.000|
IO_MEM_DATA<10>|    8.212(R)|CLK               |   0.000|
IO_MEM_DATA<11>|    8.218(R)|CLK               |   0.000|
IO_MEM_DATA<12>|    8.215(R)|CLK               |   0.000|
IO_MEM_DATA<13>|    8.221(R)|CLK               |   0.000|
IO_MEM_DATA<14>|    8.284(R)|CLK               |   0.000|
IO_MEM_DATA<15>|    8.288(R)|CLK               |   0.000|
O_ANO_N<0>     |    7.534(R)|CLK               |   0.000|
O_ANO_N<1>     |    7.525(R)|CLK               |   0.000|
O_ANO_N<2>     |    7.605(R)|CLK               |   0.000|
O_ANO_N<3>     |    7.608(R)|CLK               |   0.000|
O_FUSP_RTS_N   |    9.013(R)|CLK               |   0.000|
O_FUSP_TXD     |    9.082(R)|CLK               |   0.000|
O_LED<0>       |    7.535(R)|CLK               |   0.000|
O_LED<1>       |    7.535(R)|CLK               |   0.000|
O_LED<2>       |    7.537(R)|CLK               |   0.000|
O_LED<3>       |    7.537(R)|CLK               |   0.000|
O_LED<4>       |    7.595(R)|CLK               |   0.000|
O_LED<5>       |    7.601(R)|CLK               |   0.000|
O_LED<6>       |    7.606(R)|CLK               |   0.000|
O_LED<7>       |    7.604(R)|CLK               |   0.000|
O_MEM_ADDR<0>  |    7.513(R)|CLK               |   0.000|
O_MEM_ADDR<1>  |    7.513(R)|CLK               |   0.000|
O_MEM_ADDR<2>  |    7.498(R)|CLK               |   0.000|
O_MEM_ADDR<3>  |    7.504(R)|CLK               |   0.000|
O_MEM_ADDR<4>  |    7.504(R)|CLK               |   0.000|
O_MEM_ADDR<5>  |    7.510(R)|CLK               |   0.000|
O_MEM_ADDR<6>  |    7.498(R)|CLK               |   0.000|
O_MEM_ADDR<7>  |    7.501(R)|CLK               |   0.000|
O_MEM_ADDR<8>  |    7.514(R)|CLK               |   0.000|
O_MEM_ADDR<9>  |    7.512(R)|CLK               |   0.000|
O_MEM_ADDR<10> |    7.508(R)|CLK               |   0.000|
O_MEM_ADDR<11> |    7.508(R)|CLK               |   0.000|
O_MEM_ADDR<12> |    7.512(R)|CLK               |   0.000|
O_MEM_ADDR<13> |    7.514(R)|CLK               |   0.000|
O_MEM_ADDR<14> |    7.571(R)|CLK               |   0.000|
O_MEM_ADDR<15> |    7.511(R)|CLK               |   0.000|
O_MEM_ADDR<16> |    7.571(R)|CLK               |   0.000|
O_MEM_ADDR<17> |    7.581(R)|CLK               |   0.000|
O_MEM_ADDR<18> |    7.581(R)|CLK               |   0.000|
O_MEM_ADDR<19> |    7.579(R)|CLK               |   0.000|
O_MEM_ADDR<20> |    7.514(R)|CLK               |   0.000|
O_MEM_BE_N<0>  |    7.416(R)|CLK               |   0.000|
O_MEM_BE_N<1>  |    7.418(R)|CLK               |   0.000|
O_MEM_CE_N     |    7.410(R)|CLK               |   0.000|
O_MEM_OE_N     |    7.485(R)|CLK               |   0.000|
O_MEM_WE_N     |   16.983(F)|CLK               |   9.615|
O_SEG_N<0>     |    7.528(R)|CLK               |   0.000|
O_SEG_N<1>     |    7.534(R)|CLK               |   0.000|
O_SEG_N<2>     |    7.601(R)|CLK               |   0.000|
O_SEG_N<3>     |    7.601(R)|CLK               |   0.000|
O_SEG_N<4>     |    7.537(R)|CLK               |   0.000|
O_SEG_N<5>     |    7.537(R)|CLK               |   0.000|
O_SEG_N<6>     |    7.522(R)|CLK               |   0.000|
O_SEG_N<7>     |    7.605(R)|CLK               |   0.000|
O_TXD          |    7.505(R)|CLK               |   0.000|
---------------+------------+------------------+--------+

Clock I_FX2_IFCLK to Pad
--------------+------------+------------------+--------+
              | clk (edge) |                  | Clock  |
Destination   |   to PAD   |Internal Clock(s) | Phase  |
--------------+------------+------------------+--------+
IO_FX2_DATA<0>|    8.501(R)|I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<1>|    8.471(R)|I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<2>|    8.471(R)|I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<3>|    8.424(R)|I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<4>|    8.430(R)|I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<5>|    8.422(R)|I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<6>|    8.449(R)|I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<7>|    8.449(R)|I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_FIFO<0> |    7.698(R)|I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_FIFO<1> |    7.612(R)|I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_PKTEND_N|    7.612(R)|I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_SLOE_N  |    7.710(R)|I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_SLRD_N  |    7.643(R)|I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_SLWR_N  |    7.647(R)|I_FX2_IFCLK_BUFGP |   0.000|
--------------+------------+------------------+--------+

Clock to Setup on destination clock I_CLK50
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
I_CLK50        |   19.190|         |    6.500|         |
I_FX2_IFCLK    |    9.738|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock I_FX2_IFCLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
I_CLK50        |    5.313|         |         |         |
I_FX2_IFCLK    |    8.719|         |         |         |
---------------+---------+---------+---------+---------+

OFFSET = IN 2.5 ns VALID 33 ns BEFORE COMP "I_FX2_IFCLK";
Worst Case Data Window 3.487; Ideal Clock Offset To Actual Clock 14.518; 
------------------+------------+------------+---------+---------+-------------+
                  |            |            |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |    Hold    |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+---------+---------+-------------+
IO_FX2_DATA<0>    |    2.194(R)|    1.201(R)|    0.306|   29.299|      -14.497|
IO_FX2_DATA<1>    |    2.219(R)|    1.171(R)|    0.281|   29.329|      -14.524|
IO_FX2_DATA<2>    |    2.219(R)|    1.171(R)|    0.281|   29.329|      -14.524|
IO_FX2_DATA<3>    |    2.259(R)|    1.124(R)|    0.241|   29.376|      -14.568|
IO_FX2_DATA<4>    |    2.254(R)|    1.130(R)|    0.246|   29.370|      -14.562|
IO_FX2_DATA<5>    |    2.261(R)|    1.122(R)|    0.239|   29.378|      -14.570|
IO_FX2_DATA<6>    |    2.238(R)|    1.149(R)|    0.262|   29.351|      -14.545|
IO_FX2_DATA<7>    |    2.238(R)|    1.149(R)|    0.262|   29.351|      -14.545|
I_FX2_FLAG<0>     |    2.193(R)|    1.202(R)|    0.307|   29.298|      -14.496|
I_FX2_FLAG<1>     |    2.193(R)|    1.202(R)|    0.307|   29.298|      -14.496|
I_FX2_FLAG<2>     |    2.173(R)|    1.226(R)|    0.327|   29.274|      -14.474|
------------------+------------+------------+---------+---------+-------------+
Worst Case Summary|       2.261|       1.226|    0.239|   29.274|             |
------------------+------------+------------+---------+---------+-------------+

OFFSET = OUT 20 ns AFTER COMP "I_CLK50";
Bus Skew: 9.573 ns; 
-----------------------------------------------+-------------+--------------+
PAD                                            | Delay (ns)  |Edge Skew (ns)|
-----------------------------------------------+-------------+--------------+
IO_MEM_DATA<0>                                 |        8.215|         0.805|
IO_MEM_DATA<1>                                 |        8.208|         0.798|
IO_MEM_DATA<2>                                 |        8.206|         0.796|
IO_MEM_DATA<3>                                 |        8.212|         0.802|
IO_MEM_DATA<4>                                 |        8.221|         0.811|
IO_MEM_DATA<5>                                 |        8.292|         0.882|
IO_MEM_DATA<6>                                 |        8.292|         0.882|
IO_MEM_DATA<7>                                 |        8.284|         0.874|
IO_MEM_DATA<8>                                 |        8.208|         0.798|
IO_MEM_DATA<9>                                 |        8.206|         0.796|
IO_MEM_DATA<10>                                |        8.212|         0.802|
IO_MEM_DATA<11>                                |        8.218|         0.808|
IO_MEM_DATA<12>                                |        8.215|         0.805|
IO_MEM_DATA<13>                                |        8.221|         0.811|
IO_MEM_DATA<14>                                |        8.284|         0.874|
IO_MEM_DATA<15>                                |        8.288|         0.878|
O_ANO_N<0>                                     |        7.534|         0.124|
O_ANO_N<1>                                     |        7.525|         0.115|
O_ANO_N<2>                                     |        7.605|         0.195|
O_ANO_N<3>                                     |        7.608|         0.198|
O_FUSP_RTS_N                                   |        9.013|         1.603|
O_FUSP_TXD                                     |        9.082|         1.672|
O_LED<0>                                       |        7.535|         0.125|
O_LED<1>                                       |        7.535|         0.125|
O_LED<2>                                       |        7.537|         0.127|
O_LED<3>                                       |        7.537|         0.127|
O_LED<4>                                       |        7.595|         0.185|
O_LED<5>                                       |        7.601|         0.191|
O_LED<6>                                       |        7.606|         0.196|
O_LED<7>                                       |        7.604|         0.194|
O_MEM_ADDR<0>                                  |        7.513|         0.103|
O_MEM_ADDR<1>                                  |        7.513|         0.103|
O_MEM_ADDR<2>                                  |        7.498|         0.088|
O_MEM_ADDR<3>                                  |        7.504|         0.094|
O_MEM_ADDR<4>                                  |        7.504|         0.094|
O_MEM_ADDR<5>                                  |        7.510|         0.100|
O_MEM_ADDR<6>                                  |        7.498|         0.088|
O_MEM_ADDR<7>                                  |        7.501|         0.091|
O_MEM_ADDR<8>                                  |        7.514|         0.104|
O_MEM_ADDR<9>                                  |        7.512|         0.102|
O_MEM_ADDR<10>                                 |        7.508|         0.098|
O_MEM_ADDR<11>                                 |        7.508|         0.098|
O_MEM_ADDR<12>                                 |        7.512|         0.102|
O_MEM_ADDR<13>                                 |        7.514|         0.104|
O_MEM_ADDR<14>                                 |        7.571|         0.161|
O_MEM_ADDR<15>                                 |        7.511|         0.101|
O_MEM_ADDR<16>                                 |        7.571|         0.161|
O_MEM_ADDR<17>                                 |        7.581|         0.171|
O_MEM_ADDR<18>                                 |        7.581|         0.171|
O_MEM_ADDR<19>                                 |        7.579|         0.169|
O_MEM_ADDR<20>                                 |        7.514|         0.104|
O_MEM_BE_N<0>                                  |        7.416|         0.006|
O_MEM_BE_N<1>                                  |        7.418|         0.008|
O_MEM_CE_N                                     |        7.410|         0.000|
O_MEM_OE_N                                     |        7.485|         0.075|
O_MEM_WE_N                                     |       16.983|         9.573|
O_SEG_N<0>                                     |        7.528|         0.118|
O_SEG_N<1>                                     |        7.534|         0.124|
O_SEG_N<2>                                     |        7.601|         0.191|
O_SEG_N<3>                                     |        7.601|         0.191|
O_SEG_N<4>                                     |        7.537|         0.127|
O_SEG_N<5>                                     |        7.537|         0.127|
O_SEG_N<6>                                     |        7.522|         0.112|
O_SEG_N<7>                                     |        7.605|         0.195|
O_TXD                                          |        7.505|         0.095|
-----------------------------------------------+-------------+--------------+

OFFSET = OUT 10 ns VALID 33 ns AFTER COMP "I_FX2_IFCLK";
Bus Skew: 0.889 ns; 
-----------------------------------------------+-------------+--------------+
PAD                                            | Delay (ns)  |Edge Skew (ns)|
-----------------------------------------------+-------------+--------------+
IO_FX2_DATA<0>                                 |        8.501|         0.889|
IO_FX2_DATA<1>                                 |        8.471|         0.859|
IO_FX2_DATA<2>                                 |        8.471|         0.859|
IO_FX2_DATA<3>                                 |        8.424|         0.812|
IO_FX2_DATA<4>                                 |        8.430|         0.818|
IO_FX2_DATA<5>                                 |        8.422|         0.810|
IO_FX2_DATA<6>                                 |        8.449|         0.837|
IO_FX2_DATA<7>                                 |        8.449|         0.837|
O_FX2_FIFO<0>                                  |        7.698|         0.086|
O_FX2_FIFO<1>                                  |        7.612|         0.000|
O_FX2_PKTEND_N                                 |        7.612|         0.000|
O_FX2_SLOE_N                                   |        7.710|         0.098|
O_FX2_SLRD_N                                   |        7.643|         0.031|
O_FX2_SLWR_N                                   |        7.647|         0.035|
-----------------------------------------------+-------------+--------------+


Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

Constraints cover 3152634 paths, 0 nets, and 36063 connections

Design statistics:
   Minimum period:  19.190ns{1}   (Maximum frequency:  52.110MHz)
   Maximum path delay from/to any node:   4.931ns
   Minimum input required time before clock:   2.453ns
   Minimum output required time after clock:  16.983ns


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Sat Mar 19 14:47:49 2016 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 489 MB



