Release 14.7 par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

athome::  Sat Mar 19 14:44:40 2016

par -w -ol high -xe n -intstyle xflow sys_w11a_n2_map.ncd sys_w11a_n2.ncd
sys_w11a_n2.pcf 


Constraints file: sys_w11a_n2.pcf.
Loading device for application Rf_Device from file '3s1200e.nph' in environment
/mnt/data/opt/Xilinx/ISE/14.7/ISE_DS/ISE/.
   "sys_w11a_n2" is an NCD, version 3.2, device xc3s1200e, package fg320, speed -4
WARNING:ConstraintSystem - The Offset constraint <OFFSET = IN 10 ns BEFORE COMP "I_CLK50";> [sys_w11a_n2.pcf(5514)], is
   specified without a duration.  This will result in a lack of hold time checks in timing reports.  If hold time checks
   are desired a duration value should be specified following the 'VALID' keyword.


Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)


Device speed data version:  "PRODUCTION 1.27 2013-10-13".


Design Summary Report:

 Number of External IOBs                         106 out of 250    42%

   Number of External Input IOBs                 21

      Number of External Input IBUFs             21
        Number of LOCed External Input IBUFs     21 out of 21    100%


   Number of External Output IOBs                61

      Number of External Output IOBs             61
        Number of LOCed External Output IOBs     61 out of 61    100%


   Number of External Bidir IOBs                 24

      Number of External Bidir IOBs              24
        Number of LOCed External Bidir IOBs      24 out of 24    100%


   Number of BUFGMUXs                        2 out of 24      8%
   Number of DCMs                            1 out of 8      12%
   Number of MULT18X18SIOs                   1 out of 28      3%
   Number of RAMB16s                        14 out of 28     50%
   Number of Slices                       4818 out of 8672   55%
      Number of SLICEMs                    224 out of 4336    5%



Overall effort level (-ol):   High 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    High 
Extra effort level (-xe):     Normal 

Starting initial Timing Analysis.  REAL time: 14 secs 
Finished initial Timing Analysis.  REAL time: 15 secs 

WARNING:Par:288 - The signal I_MEM_WAIT_IBUF has no load.  PAR will not attempt to route this signal.

Starting Placer
Total REAL time at the beginning of Placer: 15 secs 
Total CPU  time at the beginning of Placer: 7 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:9af58805) REAL time: 19 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:9af58805) REAL time: 19 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:9af58805) REAL time: 19 secs 

Phase 4.2  Initial Clock and IO Placement

...........
WARNING:Place:1019 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
   clock site pair. The clock component <I_FX2_IFCLK_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y0>. The IO component
   <I_FX2_IFCLK> is placed at site <T15>.  This will not allow the use of the fast path between the IO and the Clock
   buffer. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <I_FX2_IFCLK.PAD>
   allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN.
   The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that
   this error condition be corrected in the design.
Phase 4.2  Initial Clock and IO Placement (Checksum:1743a1b0) REAL time: 30 secs 

Phase 5.30  Global Clock Region Assignment
Phase 5.30  Global Clock Region Assignment (Checksum:1743a1b0) REAL time: 30 secs 

Phase 6.36  Local Placement Optimization
Phase 6.36  Local Placement Optimization (Checksum:1743a1b0) REAL time: 30 secs 

Phase 7.8  Global Placement
............................
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......................................................................................................................................
.............................................................................................
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.................
Phase 7.8  Global Placement (Checksum:ff0b3e75) REAL time: 1 mins 17 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:ff0b3e75) REAL time: 1 mins 17 secs 

Phase 9.18  Placement Optimization
Phase 9.18  Placement Optimization (Checksum:8ad3e338) REAL time: 1 mins 41 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:8ad3e338) REAL time: 1 mins 41 secs 

Total REAL time to Placer completion: 1 mins 42 secs 
Total CPU  time to Placer completion: 1 mins 13 secs 
Writing design to file sys_w11a_n2.ncd



Starting Router


Phase  1  : 36095 unrouted;      REAL time: 1 mins 56 secs 

Phase  2  : 33626 unrouted;      REAL time: 1 mins 56 secs 

Phase  3  : 11420 unrouted;      REAL time: 2 mins 5 secs 

Phase  4  : 11637 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 9 secs 

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 25 secs 

Updating file: sys_w11a_n2.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 33 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 34 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 2 mins 37 secs 

Total REAL time to Router completion: 2 mins 37 secs 
Total CPU time to Router completion: 1 mins 50 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|                 CLK | BUFGMUX_X2Y10| No   | 2225 |  0.210     |  0.379      |
+---------------------+--------------+------+------+------------+-------------+
|   I_FX2_IFCLK_BUFGP |  BUFGMUX_X2Y0| No   |   84 |  0.120     |  0.370      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Number of Timing Constraints that were not applied: 1

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_CLK1 = PERIOD TIMEGRP "CLK1" TS_I_CLK5 | SETUP       |     0.040ns|    19.190ns|       0|           0
  0 / 1.04 HIGH 50%                         | HOLD        |     0.721ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  OFFSET = IN 2.5 ns VALID 33 ns BEFORE COM | SETUP       |     0.239ns|     2.261ns|       0|           0
  P "I_FX2_IFCLK"                           | HOLD        |    29.274ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  OFFSET = OUT 10 ns VALID 33 ns AFTER COMP | MAXDELAY    |     1.499ns|     8.501ns|       0|           0
   "I_FX2_IFCLK"                            |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  OFFSET = OUT 20 ns AFTER COMP "I_CLK50"   | MAXDELAY    |     3.017ns|    16.983ns|       0|           0
----------------------------------------------------------------------------------------------------------
  TS_PAD_IFCLK = MAXDELAY FROM TIMEGRP "PAD | MAXDELAY    |     5.069ns|     4.931ns|       0|           0
  S(I_FX2_IFCLK)" TO TIMEGRP         "TNM_I |             |            |            |        |            
  FCLK" 10 ns                               |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_PAD_CLK = MAXDELAY FROM TIMEGRP "PADS( | MAXDELAY    |     5.302ns|     4.698ns|       0|           0
  I_CLK50)" TO TIMEGRP "TNM_CLK" 10 ns      |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  OFFSET = IN 10 ns BEFORE COMP "I_CLK50"   | SETUP       |     7.547ns|     2.453ns|       0|           0
----------------------------------------------------------------------------------------------------------
  TS_I_CLK50 = PERIOD TIMEGRP "I_CLK50" 20  | MINLOWPULSE |    14.000ns|     6.000ns|       0|           0
  ns HIGH 50%                               |             |            |            |        |            
----------------------------------------------------------------------------------------------------------
  TS_I_FX2_IFCLK = PERIOD TIMEGRP "I_FX2_IF | SETUP       |    24.621ns|     8.719ns|       0|           0
  CLK" 33.34 ns HIGH 50%                    | HOLD        |     0.930ns|            |       0|           0
----------------------------------------------------------------------------------------------------------


Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_I_CLK50
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_I_CLK50                     |     20.000ns|      6.000ns|     19.958ns|            0|            0|            0|      3146961|
| TS_CLK1                       |     19.231ns|     19.190ns|          N/A|            0|            0|      3146961|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

All constraints were met.


Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 2 mins 40 secs 
Total CPU time to PAR completion: 1 mins 53 secs 

Peak Memory Usage:  744 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 5
Number of info messages: 0

Writing design to file sys_w11a_n2.ncd



PAR done!
