
*** Running vivado
    with args -log sys_tst_rlink_b3.vdi -applog -m64 -messageDb vivado.pb -mode batch -source sys_tst_rlink_b3.tcl -notrace


****** Vivado v2014.4 (64-bit)
  **** SW Build 1071353 on Tue Nov 18 16:48:31 MST 2014
  **** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014
    ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.

source sys_tst_rlink_b3.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 151 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2014.4
Loading clock regions from /mnt/data/opt/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/artix7/xc7a35t/ClockRegion.xml
Loading clock buffers from /mnt/data/opt/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/artix7/xc7a35t/ClockBuffers.xml
Loading clock placement rules from /mnt/data/opt/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/ClockPlacerRules.xml
Loading package pin functions from /mnt/data/opt/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/PinFunctions.xml...
Loading package from /mnt/data/opt/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/artix7/xc7a35t/cpg236/Package.xml
Loading io standards from /mnt/data/opt/Xilinx/Vivado/2014.4/data/./parts/xilinx/artix7/IOStandards.xml
Loading device configuration modes from /mnt/data/opt/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/ConfigModes.xml
INFO: [Project 1-570] Preparing netlist for logic optimization
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
Parsing XDC File [/home/walter/tmp/octest/trunk/rtl/bplib/basys3/basys3_pclk.xdc]
Finished Parsing XDC File [/home/walter/tmp/octest/trunk/rtl/bplib/basys3/basys3_pclk.xdc]
Parsing XDC File [/home/walter/tmp/octest/trunk/rtl/bplib/basys3/basys3_pins.xdc]
Finished Parsing XDC File [/home/walter/tmp/octest/trunk/rtl/bplib/basys3/basys3_pins.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 64 instances were transformed.
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 64 instances

link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1069.590 ; gain = 233.543 ; free physical = 997 ; free virtual = 9649
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.16 . Memory (MB): peak = 1071.594 ; gain = 2.004 ; free physical = 996 ; free virtual = 9649
INFO: [Timing 38-35] Done setting XDC timing constraints.

Starting Logic Optimization Task

Phase 1 Retarget

INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 223ac61d4

Time (s): cpu = 00:00:00.21 ; elapsed = 00:00:00.29 . Memory (MB): peak = 1496.031 ; gain = 0.000 ; free physical = 649 ; free virtual = 9303

Phase 2 Constant Propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-10] Eliminated 87 cells.
Phase 2 Constant Propagation | Checksum: 1631123dc

Time (s): cpu = 00:00:00.37 ; elapsed = 00:00:00.45 . Memory (MB): peak = 1496.031 ; gain = 0.000 ; free physical = 648 ; free virtual = 9303

Phase 3 Sweep
INFO: [Opt 31-12] Eliminated 328 unconnected nets.
INFO: [Opt 31-140] Inserted 0 IBUFs to IO ports without IO buffers.
INFO: [Opt 31-141] Inserted 0 OBUFs to IO ports without IO buffers.
INFO: [Opt 31-11] Eliminated 0 unconnected cells.
Phase 3 Sweep | Checksum: 1b1056a79

Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.60 . Memory (MB): peak = 1496.031 ; gain = 0.000 ; free physical = 648 ; free virtual = 9302
Ending Logic Optimization Task | Checksum: 1b1056a79

Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.62 . Memory (MB): peak = 1496.031 ; gain = 0.000 ; free physical = 648 ; free virtual = 9302
Implement Debug Cores | Checksum: 17321dbd4
Logic Optimization | Checksum: 17321dbd4

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 3.12 ns.
INFO: [Pwropt 34-9] Applying IDT optimizations ...
INFO: [Pwropt 34-10] Applying ODC optimizations ...


Starting PowerOpt Patch Enables Task
INFO: [Pwropt 34-162] WRITE_MODE attribute of 1 BRAM(s) out of a total of 6 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated.
INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports
Number of BRAM Ports augmented: 0 newly gated: 0 Total Ports: 12
Ending PowerOpt Patch Enables Task | Checksum: 1b1056a79

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1540.086 ; gain = 0.000 ; free physical = 580 ; free virtual = 9240
Ending Power Optimization Task | Checksum: 1b1056a79

Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1540.086 ; gain = 44.055 ; free physical = 580 ; free virtual = 9240
INFO: [Common 17-83] Releasing license: Implementation
27 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:18 . Memory (MB): peak = 1540.086 ; gain = 470.496 ; free physical = 580 ; free virtual = 9240
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1544.094 ; gain = 0.000 ; free physical = 578 ; free virtual = 9240
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/basys3/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_b3_drc_opted.rpt.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Runtime Estimator
Phase 1 Placer Runtime Estimator | Checksum: eb0e7501

Time (s): cpu = 00:00:00.19 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1544.098 ; gain = 0.000 ; free physical = 577 ; free virtual = 9238

Phase 2 Placer Initialization

Phase 2.1 Placer Initialization Core
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1544.098 ; gain = 0.000 ; free physical = 577 ; free virtual = 9238
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1544.098 ; gain = 0.000 ; free physical = 577 ; free virtual = 9238

Phase 2.1.1 IO Placement/ Clock Placement/ Build Placer Device

Phase 2.1.1.1 Pre-Place Cells
Phase 2.1.1.1 Pre-Place Cells | Checksum: 70201c0e

Time (s): cpu = 00:00:00.24 ; elapsed = 00:00:00.31 . Memory (MB): peak = 1544.098 ; gain = 0.000 ; free physical = 577 ; free virtual = 9239
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 2.1.1.2 IO & Clk Clean Up
Phase 2.1.1.2 IO & Clk Clean Up | Checksum: 70201c0e

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1544.098 ; gain = 0.000 ; free physical = 574 ; free virtual = 9239

Phase 2.1.1.3 Implementation Feasibility check On IDelay
Phase 2.1.1.3 Implementation Feasibility check On IDelay | Checksum: 70201c0e

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1544.098 ; gain = 0.000 ; free physical = 574 ; free virtual = 9239

Phase 2.1.1.4 Commit IO Placement
Phase 2.1.1.4 Commit IO Placement | Checksum: cf47eefb

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1544.098 ; gain = 0.000 ; free physical = 574 ; free virtual = 9239
Phase 2.1.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: d682284b

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1544.098 ; gain = 0.000 ; free physical = 574 ; free virtual = 9239

Phase 2.1.2 Build Placer Netlist Model

Phase 2.1.2.1 Place Init Design

Phase 2.1.2.1.1 Init Lut Pin Assignment
Phase 2.1.2.1.1 Init Lut Pin Assignment | Checksum: 1cdac6354

Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1544.098 ; gain = 0.000 ; free physical = 573 ; free virtual = 9239
Phase 2.1.2.1 Place Init Design | Checksum: 166964fbd

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1544.098 ; gain = 0.000 ; free physical = 572 ; free virtual = 9239
Phase 2.1.2 Build Placer Netlist Model | Checksum: 166964fbd

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1544.098 ; gain = 0.000 ; free physical = 572 ; free virtual = 9239

Phase 2.1.3 Constrain Clocks/Macros

Phase 2.1.3.1 Constrain Global/Regional Clocks
Phase 2.1.3.1 Constrain Global/Regional Clocks | Checksum: 166964fbd

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1544.098 ; gain = 0.000 ; free physical = 572 ; free virtual = 9239
Phase 2.1.3 Constrain Clocks/Macros | Checksum: 166964fbd

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1544.098 ; gain = 0.000 ; free physical = 572 ; free virtual = 9239
Phase 2.1 Placer Initialization Core | Checksum: 166964fbd

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1544.098 ; gain = 0.000 ; free physical = 572 ; free virtual = 9239
Phase 2 Placer Initialization | Checksum: 166964fbd

Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 1544.098 ; gain = 0.000 ; free physical = 572 ; free virtual = 9239

Phase 3 Global Placement
Phase 3 Global Placement | Checksum: 16d83f7ac

Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 572 ; free virtual = 9239

Phase 4 Detail Placement

Phase 4.1 Commit Multi Column Macros
Phase 4.1 Commit Multi Column Macros | Checksum: 16d83f7ac

Time (s): cpu = 00:00:06 ; elapsed = 00:00:05 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 572 ; free virtual = 9239

Phase 4.2 Commit Most Macros & LUTRAMs
Phase 4.2 Commit Most Macros & LUTRAMs | Checksum: b6278f37

Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 567 ; free virtual = 9234

Phase 4.3 Area Swap Optimization
Phase 4.3 Area Swap Optimization | Checksum: cf8660bc

Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 567 ; free virtual = 9234

Phase 4.4 updateClock Trees: DP
Phase 4.4 updateClock Trees: DP | Checksum: cf8660bc

Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 566 ; free virtual = 9234

Phase 4.5 Timing Path Optimizer
Phase 4.5 Timing Path Optimizer | Checksum: df2641bf

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 566 ; free virtual = 9234

Phase 4.6 Small Shape Detail Placement

Phase 4.6.1 Commit Small Macros & Core Logic

Phase 4.6.1.1 setBudgets
Phase 4.6.1.1 setBudgets | Checksum: 7b804004

Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 566 ; free virtual = 9234

Phase 4.6.1.2 Commit Slice Clusters
Phase 4.6.1.2 Commit Slice Clusters | Checksum: b12a8d6f

Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9233
Phase 4.6.1 Commit Small Macros & Core Logic | Checksum: b12a8d6f

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9233

Phase 4.6.2 Clock Restriction Legalization for Leaf Columns
Phase 4.6.2 Clock Restriction Legalization for Leaf Columns | Checksum: b12a8d6f

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9233

Phase 4.6.3 Clock Restriction Legalization for Non-Clock Pins
Phase 4.6.3 Clock Restriction Legalization for Non-Clock Pins | Checksum: b12a8d6f

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9233
Phase 4.6 Small Shape Detail Placement | Checksum: b12a8d6f

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9233

Phase 4.7 Re-assign LUT pins
Phase 4.7 Re-assign LUT pins | Checksum: b12a8d6f

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9233
Phase 4 Detail Placement | Checksum: b12a8d6f

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9233

Phase 5 Post Placement Optimization and Clean-Up

Phase 5.1 PCOPT Shape updates
Phase 5.1 PCOPT Shape updates | Checksum: 182894375

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9233

Phase 5.2 Post Commit Optimization

Phase 5.2.1 updateClock Trees: PCOPT
Phase 5.2.1 updateClock Trees: PCOPT | Checksum: 182894375

Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9233

Phase 5.2.2 Post Placement Optimization

Phase 5.2.2.1 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=0.642. For the most accurate timing information please run report_timing.
Phase 5.2.2.1 Post Placement Timing Optimization | Checksum: 13a7a3a98

Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9232
Phase 5.2.2 Post Placement Optimization | Checksum: 13a7a3a98

Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9232
Phase 5.2 Post Commit Optimization | Checksum: 13a7a3a98

Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9232

Phase 5.3 Sweep Clock Roots: Post-Placement
Phase 5.3 Sweep Clock Roots: Post-Placement | Checksum: 13a7a3a98

Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9232

Phase 5.4 Post Placement Cleanup
Phase 5.4 Post Placement Cleanup | Checksum: 13a7a3a98

Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9232

Phase 5.5 Placer Reporting

Phase 5.5.1 Restore STA
Phase 5.5.1 Restore STA | Checksum: 13a7a3a98

Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9232
Phase 5.5 Placer Reporting | Checksum: 13a7a3a98

Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9232

Phase 5.6 Final Placement Cleanup
Phase 5.6 Final Placement Cleanup | Checksum: 16f1f8c3a

Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9232
Phase 5 Post Placement Optimization and Clean-Up | Checksum: 16f1f8c3a

Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9232
Ending Placer Task | Checksum: e9c74852

Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9232
INFO: [Common 17-83] Releasing license: Implementation
40 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:08 . Memory (MB): peak = 1546.098 ; gain = 2.000 ; free physical = 564 ; free virtual = 9232
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.28 . Memory (MB): peak = 1546.102 ; gain = 0.000 ; free physical = 560 ; free virtual = 9232
report_io: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.20 . Memory (MB): peak = 1546.102 ; gain = 0.000 ; free physical = 561 ; free virtual = 9231
report_utilization: Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.50 . Memory (MB): peak = 1546.102 ; gain = 0.000 ; free physical = 561 ; free virtual = 9231
report_control_sets: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.13 . Memory (MB): peak = 1546.102 ; gain = 0.000 ; free physical = 561 ; free virtual = 9231
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command route_design
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: bae868af

Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1600.770 ; gain = 54.668 ; free physical = 469 ; free virtual = 9141

Phase 2 Router Initialization

Phase 2.1 Create Timer
Phase 2.1 Create Timer | Checksum: bae868af

Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1605.770 ; gain = 59.668 ; free physical = 468 ; free virtual = 9141

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: bae868af

Time (s): cpu = 00:00:23 ; elapsed = 00:00:20 . Memory (MB): peak = 1612.770 ; gain = 66.668 ; free physical = 462 ; free virtual = 9134
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 1226b03b0

Time (s): cpu = 00:00:25 ; elapsed = 00:00:21 . Memory (MB): peak = 1630.770 ; gain = 84.668 ; free physical = 443 ; free virtual = 9116
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.14   | TNS=0      | WHS=-0.302 | THS=-85.9  |

Phase 2 Router Initialization | Checksum: 12c1d9626

Time (s): cpu = 00:00:25 ; elapsed = 00:00:22 . Memory (MB): peak = 1630.770 ; gain = 84.668 ; free physical = 443 ; free virtual = 9115

Phase 3 Initial Routing
Phase 3 Initial Routing | Checksum: 1d6f974d7

Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 1630.770 ; gain = 84.668 ; free physical = 443 ; free virtual = 9115

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 365
 Number of Nodes with overlaps = 40
 Number of Nodes with overlaps = 15
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 0

Phase 4.1.1 Update Timing
Phase 4.1.1 Update Timing | Checksum: 195192111

Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1630.770 ; gain = 84.668 ; free physical = 443 ; free virtual = 9116
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.907  | TNS=0      | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 25c55f847

Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1630.770 ; gain = 84.668 ; free physical = 443 ; free virtual = 9116
Phase 4 Rip-up And Reroute | Checksum: 25c55f847

Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 1630.770 ; gain = 84.668 ; free physical = 443 ; free virtual = 9116

Phase 5 Delay CleanUp

Phase 5.1 Update Timing
Phase 5.1 Update Timing | Checksum: 291aeaf1f

Time (s): cpu = 00:00:28 ; elapsed = 00:00:24 . Memory (MB): peak = 1630.770 ; gain = 84.668 ; free physical = 443 ; free virtual = 9116
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.907  | TNS=0      | WHS=N/A    | THS=N/A    |

Phase 5 Delay CleanUp | Checksum: 291aeaf1f

Time (s): cpu = 00:00:28 ; elapsed = 00:00:24 . Memory (MB): peak = 1630.770 ; gain = 84.668 ; free physical = 443 ; free virtual = 9116

Phase 6 Clock Skew Optimization
Phase 6 Clock Skew Optimization | Checksum: 291aeaf1f

Time (s): cpu = 00:00:28 ; elapsed = 00:00:24 . Memory (MB): peak = 1630.770 ; gain = 84.668 ; free physical = 443 ; free virtual = 9116

Phase 7 Post Hold Fix

Phase 7.1 Update Timing
Phase 7.1 Update Timing | Checksum: 2b0d57d49

Time (s): cpu = 00:00:28 ; elapsed = 00:00:24 . Memory (MB): peak = 1630.770 ; gain = 84.668 ; free physical = 443 ; free virtual = 9116
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.907  | TNS=0      | WHS=0.009  | THS=0      |

Phase 7 Post Hold Fix | Checksum: 24b649d5f

Time (s): cpu = 00:00:28 ; elapsed = 00:00:24 . Memory (MB): peak = 1630.770 ; gain = 84.668 ; free physical = 443 ; free virtual = 9116

Phase 8 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.64243 %
  Global Horizontal Routing Utilization  = 0.888339 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 8 Route finalize | Checksum: 26b67e455

Time (s): cpu = 00:00:28 ; elapsed = 00:00:24 . Memory (MB): peak = 1630.770 ; gain = 84.668 ; free physical = 443 ; free virtual = 9116

Phase 9 Verifying routed nets

 Verification completed successfully
Phase 9 Verifying routed nets | Checksum: 26b67e455

Time (s): cpu = 00:00:28 ; elapsed = 00:00:24 . Memory (MB): peak = 1630.770 ; gain = 84.668 ; free physical = 443 ; free virtual = 9116

Phase 10 Depositing Routes
Phase 10 Depositing Routes | Checksum: 1a83e34c5

Time (s): cpu = 00:00:29 ; elapsed = 00:00:24 . Memory (MB): peak = 1630.770 ; gain = 84.668 ; free physical = 443 ; free virtual = 9116

Phase 11 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=0.907  | TNS=0      | WHS=0.009  | THS=0      |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 11 Post Router Timing | Checksum: 1a83e34c5

Time (s): cpu = 00:00:29 ; elapsed = 00:00:24 . Memory (MB): peak = 1630.770 ; gain = 84.668 ; free physical = 443 ; free virtual = 9116
INFO: [Route 35-16] Router Completed Successfully

Routing Is Done.

Time (s): cpu = 00:00:29 ; elapsed = 00:00:24 . Memory (MB): peak = 1630.883 ; gain = 84.781 ; free physical = 443 ; free virtual = 9116
INFO: [Common 17-83] Releasing license: Implementation
53 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:25 . Memory (MB): peak = 1630.883 ; gain = 84.781 ; free physical = 443 ; free virtual = 9116
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.31 . Memory (MB): peak = 1630.883 ; gain = 0.000 ; free physical = 439 ; free virtual = 9116
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file /home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/basys3/project_mflow/project_mflow.runs/impl_1/sys_tst_rlink_b3_drc_routed.rpt.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
INFO: [Common 17-206] Exiting Vivado at Thu May 14 17:44:08 2015...

*** Running vivado
    with args -log sys_tst_rlink_b3.vdi -applog -m64 -messageDb vivado.pb -mode batch -source sys_tst_rlink_b3.tcl -notrace


****** Vivado v2014.4 (64-bit)
  **** SW Build 1071353 on Tue Nov 18 16:48:31 MST 2014
  **** IP Build 1070531 on Tue Nov 18 01:10:18 MST 2014
    ** Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.

source sys_tst_rlink_b3.tcl -notrace
Command: open_checkpoint sys_tst_rlink_b3_routed.dcp
INFO: [Netlist 29-17] Analyzing 151 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2014.4
Loading clock regions from /mnt/data/opt/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/artix7/xc7a35t/ClockRegion.xml
Loading clock buffers from /mnt/data/opt/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/artix7/xc7a35t/ClockBuffers.xml
Loading clock placement rules from /mnt/data/opt/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/ClockPlacerRules.xml
Loading package pin functions from /mnt/data/opt/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/PinFunctions.xml...
Loading package from /mnt/data/opt/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/artix7/xc7a35t/cpg236/Package.xml
Loading io standards from /mnt/data/opt/Xilinx/Vivado/2014.4/data/./parts/xilinx/artix7/IOStandards.xml
Loading device configuration modes from /mnt/data/opt/Xilinx/Vivado/2014.4/data/parts/xilinx/artix7/ConfigModes.xml
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/basys3/project_mflow/project_mflow.runs/impl_1/.Xil/Vivado-4467-athome/dcp/sys_tst_rlink_b3.xdc]
Finished Parsing XDC File [/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/basys3/project_mflow/project_mflow.runs/impl_1/.Xil/Vivado-4467-athome/dcp/sys_tst_rlink_b3.xdc]
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:00.45 ; elapsed = 00:00:00.46 . Memory (MB): peak = 1072.625 ; gain = 4.000 ; free physical = 368 ; free virtual = 9050
Restored from archive | CPU: 0.450000 secs | Memory: 2.741386 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:00.46 ; elapsed = 00:00:00.46 . Memory (MB): peak = 1072.625 ; gain = 4.000 ; free physical = 368 ; free virtual = 9050
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 64 instances were transformed.
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 64 instances

INFO: [Project 1-484] Checkpoint was created with build 1071353
open_checkpoint: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1072.625 ; gain = 251.590 ; free physical = 371 ; free virtual = 9049
Attempting to get a license for feature 'Implementation' and/or device 'xc7a35t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a35t'
Running DRC as a precondition to command write_bitstream
INFO: [Drc 23-27] Running DRC with 2 threads
INFO: [Vivado 12-3199] DRC finished with 0 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./sys_tst_rlink_b3.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-120] WebTalk data collection is mandatory for users of free Webpack licenses. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-186] '/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/basys3/project_mflow/project_mflow.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Thu May 14 17:45:06 2015. For additional details about this file, please refer to the WebTalk help file at /mnt/data/opt/Xilinx/Vivado/2014.4/doc/webtalk_introduction.html.
INFO: [Common 17-83] Releasing license: Implementation
write_bitstream: Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 1429.641 ; gain = 357.016 ; free physical = 137 ; free virtual = 8701
INFO: [Common 17-206] Exiting Vivado at Thu May 14 17:45:06 2015...
