Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
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| Tool Version      : Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:48:31 MST 2014
| Date              : Thu May 14 17:44:05 2015
| Host              : athome running 64-bit Ubuntu 14.04.2 LTS
| Command           : report_timing_summary -warn_on_violation -max_paths 10 -file sys_tst_rlink_b3_timing_summary_routed.rpt -rpx sys_tst_rlink_b3_timing_summary_routed.rpx
| Design            : sys_tst_rlink_b3
| Device            : 7a35t-cpg236
| Speed File        : -1  PRODUCTION 1.14 2014-09-11
| Temperature Grade : C
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        



check_timing report

Table of Contents
-----------------
1. checking no_clock
2. checking constant_clock
3. checking pulse_width_clock
4. checking unconstrained_internal_endpoints
5. checking no_input_delay
6. checking no_output_delay
7. checking multiple_clock
8. checking generated_clocks
9. checking loops
10. checking partial_input_delay
11. checking partial_output_delay
12. checking unexpandable_clocks
13. checking latch_loops

1. checking no_clock
--------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock
--------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock
-----------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints
--------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay
--------------------------
 There are 22 input ports with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay
---------------------------
 There are 29 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock
--------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks
----------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops
-----------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay
--------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay
---------------------------------
 There are 0 ports with partial output delay specified.


12. checking unexpandable_clocks
--------------------------------
 There are 0 unexpandable clock pairs.


13. checking latch_loops
------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      0.909        0.000                      0                 2907        0.011        0.000                      0                 2907        3.750        0.000                       0                  1133  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock     Waveform(ns)       Period(ns)      Frequency(MHz)
-----     ------------       ----------      --------------
I_CLK100  {0.000 5.000}      10.000          100.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
I_CLK100            0.909        0.000                      0                 2907        0.011        0.000                      0                 2907        3.750        0.000                       0                  1133  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  I_CLK100
  To Clock:  I_CLK100

Setup :            0  Failing Endpoints,  Worst Slack        0.909ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.011ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        3.750ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.909ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][13]/D
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (I_CLK100 rise@10.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        8.753ns  (logic 2.022ns (23.101%)  route 6.731ns (76.899%))
  Logic Levels:           7  (CARRY4=4 LUT2=1 LUT6=2)
  Clock Path Skew:        -0.411ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.778ns = ( 14.778 - 10.000 ) 
    Source Clock Delay      (SCD):    5.370ns
    Clock Pessimism Removal (CPR):    0.180ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.849     5.370    IOB_RS232/IOB_RXD/IOB/I_CLK100_IBUF_BUFG
    ILOGIC_X0Y112                                                     r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517     5.887 r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=30, routed)          4.293    10.180    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X48Y24         LUT2 (Prop_lut2_I1_O)        0.180    10.360 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.860    11.221    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_11
    SLICE_X50Y24         LUT6 (Prop_lut6_I0_O)        0.124    11.345 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=29, routed)          1.008    12.353    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_10
    SLICE_X53Y20         LUT6 (Prop_lut6_I1_O)        0.124    12.477 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_4/O
                         net (fo=1, routed)           0.569    13.046    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_4
    SLICE_X52Y20         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520    13.566 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000    13.566    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][0]_i_1
    SLICE_X52Y21         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117    13.683 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1__0/CO[3]
                         net (fo=1, routed)           0.000    13.683    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][4]_i_1__0
    SLICE_X52Y22         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117    13.800 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1__0/CO[3]
                         net (fo=1, routed)           0.000    13.800    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][8]_i_1__0
    SLICE_X52Y23         CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323    14.123 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][12]_i_1/O[1]
                         net (fo=1, routed)           0.000    14.123    RLINK/SERPORT/UART/RXTX/RX/n_6_R_REGS_reg[ccnt][12]_i_1
    SLICE_X52Y23         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][13]/D
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                     10.000    10.000 r  
    W5                                                0.000    10.000 r  I_CLK100
                         net (fo=0)                   0.000    10.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.437    14.778    RLINK/SERPORT/UART/RXTX/RX/I_CLK100_IBUF_BUFG
    SLICE_X52Y23                                                      r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][13]/C
                         clock pessimism              0.180    14.958    
                         clock uncertainty           -0.035    14.923    
    SLICE_X52Y23         FDRE (Setup_fdre_C_D)        0.109    15.032    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][13]
  -------------------------------------------------------------------
                         required time                         15.032    
                         arrival time                         -14.123    
  -------------------------------------------------------------------
                         slack                                  0.909    

Slack (MET) :             0.993ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][14]/D
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (I_CLK100 rise@10.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        8.669ns  (logic 1.938ns (22.356%)  route 6.731ns (77.644%))
  Logic Levels:           7  (CARRY4=4 LUT2=1 LUT6=2)
  Clock Path Skew:        -0.411ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.778ns = ( 14.778 - 10.000 ) 
    Source Clock Delay      (SCD):    5.370ns
    Clock Pessimism Removal (CPR):    0.180ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.849     5.370    IOB_RS232/IOB_RXD/IOB/I_CLK100_IBUF_BUFG
    ILOGIC_X0Y112                                                     r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517     5.887 r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=30, routed)          4.293    10.180    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X48Y24         LUT2 (Prop_lut2_I1_O)        0.180    10.360 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.860    11.221    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_11
    SLICE_X50Y24         LUT6 (Prop_lut6_I0_O)        0.124    11.345 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=29, routed)          1.008    12.353    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_10
    SLICE_X53Y20         LUT6 (Prop_lut6_I1_O)        0.124    12.477 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_4/O
                         net (fo=1, routed)           0.569    13.046    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_4
    SLICE_X52Y20         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520    13.566 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000    13.566    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][0]_i_1
    SLICE_X52Y21         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117    13.683 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1__0/CO[3]
                         net (fo=1, routed)           0.000    13.683    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][4]_i_1__0
    SLICE_X52Y22         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117    13.800 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1__0/CO[3]
                         net (fo=1, routed)           0.000    13.800    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][8]_i_1__0
    SLICE_X52Y23         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239    14.039 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][12]_i_1/O[2]
                         net (fo=1, routed)           0.000    14.039    RLINK/SERPORT/UART/RXTX/RX/n_5_R_REGS_reg[ccnt][12]_i_1
    SLICE_X52Y23         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][14]/D
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                     10.000    10.000 r  
    W5                                                0.000    10.000 r  I_CLK100
                         net (fo=0)                   0.000    10.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.437    14.778    RLINK/SERPORT/UART/RXTX/RX/I_CLK100_IBUF_BUFG
    SLICE_X52Y23                                                      r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][14]/C
                         clock pessimism              0.180    14.958    
                         clock uncertainty           -0.035    14.923    
    SLICE_X52Y23         FDRE (Setup_fdre_C_D)        0.109    15.032    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][14]
  -------------------------------------------------------------------
                         required time                         15.032    
                         arrival time                         -14.039    
  -------------------------------------------------------------------
                         slack                                  0.993    

Slack (MET) :             1.014ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][12]/D
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (I_CLK100 rise@10.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        8.648ns  (logic 1.917ns (22.167%)  route 6.731ns (77.833%))
  Logic Levels:           7  (CARRY4=4 LUT2=1 LUT6=2)
  Clock Path Skew:        -0.411ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.778ns = ( 14.778 - 10.000 ) 
    Source Clock Delay      (SCD):    5.370ns
    Clock Pessimism Removal (CPR):    0.180ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.849     5.370    IOB_RS232/IOB_RXD/IOB/I_CLK100_IBUF_BUFG
    ILOGIC_X0Y112                                                     r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517     5.887 r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=30, routed)          4.293    10.180    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X48Y24         LUT2 (Prop_lut2_I1_O)        0.180    10.360 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.860    11.221    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_11
    SLICE_X50Y24         LUT6 (Prop_lut6_I0_O)        0.124    11.345 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=29, routed)          1.008    12.353    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_10
    SLICE_X53Y20         LUT6 (Prop_lut6_I1_O)        0.124    12.477 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_4/O
                         net (fo=1, routed)           0.569    13.046    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_4
    SLICE_X52Y20         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520    13.566 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000    13.566    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][0]_i_1
    SLICE_X52Y21         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117    13.683 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1__0/CO[3]
                         net (fo=1, routed)           0.000    13.683    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][4]_i_1__0
    SLICE_X52Y22         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117    13.800 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1__0/CO[3]
                         net (fo=1, routed)           0.000    13.800    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][8]_i_1__0
    SLICE_X52Y23         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.218    14.018 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][12]_i_1/O[0]
                         net (fo=1, routed)           0.000    14.018    RLINK/SERPORT/UART/RXTX/RX/n_7_R_REGS_reg[ccnt][12]_i_1
    SLICE_X52Y23         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][12]/D
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                     10.000    10.000 r  
    W5                                                0.000    10.000 r  I_CLK100
                         net (fo=0)                   0.000    10.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.437    14.778    RLINK/SERPORT/UART/RXTX/RX/I_CLK100_IBUF_BUFG
    SLICE_X52Y23                                                      r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][12]/C
                         clock pessimism              0.180    14.958    
                         clock uncertainty           -0.035    14.923    
    SLICE_X52Y23         FDRE (Setup_fdre_C_D)        0.109    15.032    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][12]
  -------------------------------------------------------------------
                         required time                         15.032    
                         arrival time                         -14.018    
  -------------------------------------------------------------------
                         slack                                  1.014    

Slack (MET) :             1.027ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][9]/D
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (I_CLK100 rise@10.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        8.636ns  (logic 1.905ns (22.059%)  route 6.731ns (77.941%))
  Logic Levels:           6  (CARRY4=3 LUT2=1 LUT6=2)
  Clock Path Skew:        -0.410ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.779ns = ( 14.779 - 10.000 ) 
    Source Clock Delay      (SCD):    5.370ns
    Clock Pessimism Removal (CPR):    0.180ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.849     5.370    IOB_RS232/IOB_RXD/IOB/I_CLK100_IBUF_BUFG
    ILOGIC_X0Y112                                                     r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517     5.887 r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=30, routed)          4.293    10.180    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X48Y24         LUT2 (Prop_lut2_I1_O)        0.180    10.360 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.860    11.221    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_11
    SLICE_X50Y24         LUT6 (Prop_lut6_I0_O)        0.124    11.345 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=29, routed)          1.008    12.353    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_10
    SLICE_X53Y20         LUT6 (Prop_lut6_I1_O)        0.124    12.477 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_4/O
                         net (fo=1, routed)           0.569    13.046    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_4
    SLICE_X52Y20         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520    13.566 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000    13.566    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][0]_i_1
    SLICE_X52Y21         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117    13.683 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1__0/CO[3]
                         net (fo=1, routed)           0.000    13.683    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][4]_i_1__0
    SLICE_X52Y22         CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323    14.006 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1__0/O[1]
                         net (fo=1, routed)           0.000    14.006    RLINK/SERPORT/UART/RXTX/RX/n_6_R_REGS_reg[ccnt][8]_i_1__0
    SLICE_X52Y22         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][9]/D
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                     10.000    10.000 r  
    W5                                                0.000    10.000 r  I_CLK100
                         net (fo=0)                   0.000    10.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.438    14.779    RLINK/SERPORT/UART/RXTX/RX/I_CLK100_IBUF_BUFG
    SLICE_X52Y22                                                      r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][9]/C
                         clock pessimism              0.180    14.959    
                         clock uncertainty           -0.035    14.924    
    SLICE_X52Y22         FDRE (Setup_fdre_C_D)        0.109    15.033    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][9]
  -------------------------------------------------------------------
                         required time                         15.033    
                         arrival time                         -14.006    
  -------------------------------------------------------------------
                         slack                                  1.027    

Slack (MET) :             1.036ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][11]/D
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (I_CLK100 rise@10.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        8.627ns  (logic 1.896ns (21.978%)  route 6.731ns (78.022%))
  Logic Levels:           6  (CARRY4=3 LUT2=1 LUT6=2)
  Clock Path Skew:        -0.410ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.779ns = ( 14.779 - 10.000 ) 
    Source Clock Delay      (SCD):    5.370ns
    Clock Pessimism Removal (CPR):    0.180ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.849     5.370    IOB_RS232/IOB_RXD/IOB/I_CLK100_IBUF_BUFG
    ILOGIC_X0Y112                                                     r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517     5.887 r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=30, routed)          4.293    10.180    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X48Y24         LUT2 (Prop_lut2_I1_O)        0.180    10.360 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.860    11.221    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_11
    SLICE_X50Y24         LUT6 (Prop_lut6_I0_O)        0.124    11.345 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=29, routed)          1.008    12.353    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_10
    SLICE_X53Y20         LUT6 (Prop_lut6_I1_O)        0.124    12.477 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_4/O
                         net (fo=1, routed)           0.569    13.046    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_4
    SLICE_X52Y20         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520    13.566 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000    13.566    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][0]_i_1
    SLICE_X52Y21         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117    13.683 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1__0/CO[3]
                         net (fo=1, routed)           0.000    13.683    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][4]_i_1__0
    SLICE_X52Y22         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.314    13.997 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1__0/O[3]
                         net (fo=1, routed)           0.000    13.997    RLINK/SERPORT/UART/RXTX/RX/n_4_R_REGS_reg[ccnt][8]_i_1__0
    SLICE_X52Y22         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][11]/D
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                     10.000    10.000 r  
    W5                                                0.000    10.000 r  I_CLK100
                         net (fo=0)                   0.000    10.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.438    14.779    RLINK/SERPORT/UART/RXTX/RX/I_CLK100_IBUF_BUFG
    SLICE_X52Y22                                                      r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][11]/C
                         clock pessimism              0.180    14.959    
                         clock uncertainty           -0.035    14.924    
    SLICE_X52Y22         FDRE (Setup_fdre_C_D)        0.109    15.033    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][11]
  -------------------------------------------------------------------
                         required time                         15.033    
                         arrival time                         -13.997    
  -------------------------------------------------------------------
                         slack                                  1.036    

Slack (MET) :             1.111ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][10]/D
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (I_CLK100 rise@10.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        8.552ns  (logic 1.821ns (21.294%)  route 6.731ns (78.706%))
  Logic Levels:           6  (CARRY4=3 LUT2=1 LUT6=2)
  Clock Path Skew:        -0.410ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.779ns = ( 14.779 - 10.000 ) 
    Source Clock Delay      (SCD):    5.370ns
    Clock Pessimism Removal (CPR):    0.180ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.849     5.370    IOB_RS232/IOB_RXD/IOB/I_CLK100_IBUF_BUFG
    ILOGIC_X0Y112                                                     r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517     5.887 r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=30, routed)          4.293    10.180    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X48Y24         LUT2 (Prop_lut2_I1_O)        0.180    10.360 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.860    11.221    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_11
    SLICE_X50Y24         LUT6 (Prop_lut6_I0_O)        0.124    11.345 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=29, routed)          1.008    12.353    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_10
    SLICE_X53Y20         LUT6 (Prop_lut6_I1_O)        0.124    12.477 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_4/O
                         net (fo=1, routed)           0.569    13.046    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_4
    SLICE_X52Y20         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520    13.566 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000    13.566    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][0]_i_1
    SLICE_X52Y21         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117    13.683 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1__0/CO[3]
                         net (fo=1, routed)           0.000    13.683    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][4]_i_1__0
    SLICE_X52Y22         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239    13.922 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1__0/O[2]
                         net (fo=1, routed)           0.000    13.922    RLINK/SERPORT/UART/RXTX/RX/n_5_R_REGS_reg[ccnt][8]_i_1__0
    SLICE_X52Y22         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][10]/D
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                     10.000    10.000 r  
    W5                                                0.000    10.000 r  I_CLK100
                         net (fo=0)                   0.000    10.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.438    14.779    RLINK/SERPORT/UART/RXTX/RX/I_CLK100_IBUF_BUFG
    SLICE_X52Y22                                                      r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][10]/C
                         clock pessimism              0.180    14.959    
                         clock uncertainty           -0.035    14.924    
    SLICE_X52Y22         FDRE (Setup_fdre_C_D)        0.109    15.033    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][10]
  -------------------------------------------------------------------
                         required time                         15.033    
                         arrival time                         -13.922    
  -------------------------------------------------------------------
                         slack                                  1.111    

Slack (MET) :             1.132ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]/D
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (I_CLK100 rise@10.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        8.531ns  (logic 1.800ns (21.100%)  route 6.731ns (78.900%))
  Logic Levels:           6  (CARRY4=3 LUT2=1 LUT6=2)
  Clock Path Skew:        -0.410ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.779ns = ( 14.779 - 10.000 ) 
    Source Clock Delay      (SCD):    5.370ns
    Clock Pessimism Removal (CPR):    0.180ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.849     5.370    IOB_RS232/IOB_RXD/IOB/I_CLK100_IBUF_BUFG
    ILOGIC_X0Y112                                                     r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517     5.887 r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=30, routed)          4.293    10.180    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X48Y24         LUT2 (Prop_lut2_I1_O)        0.180    10.360 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.860    11.221    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_11
    SLICE_X50Y24         LUT6 (Prop_lut6_I0_O)        0.124    11.345 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=29, routed)          1.008    12.353    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_10
    SLICE_X53Y20         LUT6 (Prop_lut6_I1_O)        0.124    12.477 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_4/O
                         net (fo=1, routed)           0.569    13.046    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_4
    SLICE_X52Y20         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520    13.566 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000    13.566    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][0]_i_1
    SLICE_X52Y21         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.117    13.683 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1__0/CO[3]
                         net (fo=1, routed)           0.000    13.683    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][4]_i_1__0
    SLICE_X52Y22         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.218    13.901 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]_i_1__0/O[0]
                         net (fo=1, routed)           0.000    13.901    RLINK/SERPORT/UART/RXTX/RX/n_7_R_REGS_reg[ccnt][8]_i_1__0
    SLICE_X52Y22         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]/D
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                     10.000    10.000 r  
    W5                                                0.000    10.000 r  I_CLK100
                         net (fo=0)                   0.000    10.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.438    14.779    RLINK/SERPORT/UART/RXTX/RX/I_CLK100_IBUF_BUFG
    SLICE_X52Y22                                                      r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]/C
                         clock pessimism              0.180    14.959    
                         clock uncertainty           -0.035    14.924    
    SLICE_X52Y22         FDRE (Setup_fdre_C_D)        0.109    15.033    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][8]
  -------------------------------------------------------------------
                         required time                         15.033    
                         arrival time                         -13.901    
  -------------------------------------------------------------------
                         slack                                  1.132    

Slack (MET) :             1.146ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][5]/D
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (I_CLK100 rise@10.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        8.519ns  (logic 1.788ns (20.989%)  route 6.731ns (79.011%))
  Logic Levels:           5  (CARRY4=2 LUT2=1 LUT6=2)
  Clock Path Skew:        -0.408ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.781ns = ( 14.781 - 10.000 ) 
    Source Clock Delay      (SCD):    5.370ns
    Clock Pessimism Removal (CPR):    0.180ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.849     5.370    IOB_RS232/IOB_RXD/IOB/I_CLK100_IBUF_BUFG
    ILOGIC_X0Y112                                                     r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517     5.887 r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=30, routed)          4.293    10.180    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X48Y24         LUT2 (Prop_lut2_I1_O)        0.180    10.360 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.860    11.221    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_11
    SLICE_X50Y24         LUT6 (Prop_lut6_I0_O)        0.124    11.345 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=29, routed)          1.008    12.353    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_10
    SLICE_X53Y20         LUT6 (Prop_lut6_I1_O)        0.124    12.477 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_4/O
                         net (fo=1, routed)           0.569    13.046    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_4
    SLICE_X52Y20         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520    13.566 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000    13.566    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][0]_i_1
    SLICE_X52Y21         CARRY4 (Prop_carry4_CI_O[1])
                                                      0.323    13.889 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1__0/O[1]
                         net (fo=1, routed)           0.000    13.889    RLINK/SERPORT/UART/RXTX/RX/n_6_R_REGS_reg[ccnt][4]_i_1__0
    SLICE_X52Y21         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][5]/D
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                     10.000    10.000 r  
    W5                                                0.000    10.000 r  I_CLK100
                         net (fo=0)                   0.000    10.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.440    14.781    RLINK/SERPORT/UART/RXTX/RX/I_CLK100_IBUF_BUFG
    SLICE_X52Y21                                                      r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][5]/C
                         clock pessimism              0.180    14.961    
                         clock uncertainty           -0.035    14.926    
    SLICE_X52Y21         FDRE (Setup_fdre_C_D)        0.109    15.035    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][5]
  -------------------------------------------------------------------
                         required time                         15.035    
                         arrival time                         -13.889    
  -------------------------------------------------------------------
                         slack                                  1.146    

Slack (MET) :             1.155ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][7]/D
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (I_CLK100 rise@10.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        8.510ns  (logic 1.779ns (20.905%)  route 6.731ns (79.095%))
  Logic Levels:           5  (CARRY4=2 LUT2=1 LUT6=2)
  Clock Path Skew:        -0.408ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.781ns = ( 14.781 - 10.000 ) 
    Source Clock Delay      (SCD):    5.370ns
    Clock Pessimism Removal (CPR):    0.180ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.849     5.370    IOB_RS232/IOB_RXD/IOB/I_CLK100_IBUF_BUFG
    ILOGIC_X0Y112                                                     r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517     5.887 r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=30, routed)          4.293    10.180    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X48Y24         LUT2 (Prop_lut2_I1_O)        0.180    10.360 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.860    11.221    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_11
    SLICE_X50Y24         LUT6 (Prop_lut6_I0_O)        0.124    11.345 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=29, routed)          1.008    12.353    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_10
    SLICE_X53Y20         LUT6 (Prop_lut6_I1_O)        0.124    12.477 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_4/O
                         net (fo=1, routed)           0.569    13.046    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_4
    SLICE_X52Y20         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520    13.566 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000    13.566    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][0]_i_1
    SLICE_X52Y21         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.314    13.880 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1__0/O[3]
                         net (fo=1, routed)           0.000    13.880    RLINK/SERPORT/UART/RXTX/RX/n_4_R_REGS_reg[ccnt][4]_i_1__0
    SLICE_X52Y21         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][7]/D
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                     10.000    10.000 r  
    W5                                                0.000    10.000 r  I_CLK100
                         net (fo=0)                   0.000    10.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.440    14.781    RLINK/SERPORT/UART/RXTX/RX/I_CLK100_IBUF_BUFG
    SLICE_X52Y21                                                      r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][7]/C
                         clock pessimism              0.180    14.961    
                         clock uncertainty           -0.035    14.926    
    SLICE_X52Y21         FDRE (Setup_fdre_C_D)        0.109    15.035    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][7]
  -------------------------------------------------------------------
                         required time                         15.035    
                         arrival time                         -13.880    
  -------------------------------------------------------------------
                         slack                                  1.155    

Slack (MET) :             1.230ns  (required time - arrival time)
  Source:                 IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][6]/D
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (I_CLK100 rise@10.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        8.435ns  (logic 1.704ns (20.202%)  route 6.731ns (79.798%))
  Logic Levels:           5  (CARRY4=2 LUT2=1 LUT6=2)
  Clock Path Skew:        -0.408ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.781ns = ( 14.781 - 10.000 ) 
    Source Clock Delay      (SCD):    5.370ns
    Clock Pessimism Removal (CPR):    0.180ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.849     5.370    IOB_RS232/IOB_RXD/IOB/I_CLK100_IBUF_BUFG
    ILOGIC_X0Y112                                                     r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/C
  -------------------------------------------------------------------    -------------------
    ILOGIC_X0Y112        FDRE (Prop_fdre_C_Q)         0.517     5.887 r  IOB_RS232/IOB_RXD/IOB/R_DI_reg[0]/Q
                         net (fo=30, routed)          4.293    10.180    RLINK/SERPORT/UART/RXTX/RX/RXD
    SLICE_X48Y24         LUT2 (Prop_lut2_I1_O)        0.180    10.360 f  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_11/O
                         net (fo=1, routed)           0.860    11.221    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_11
    SLICE_X50Y24         LUT6 (Prop_lut6_I0_O)        0.124    11.345 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_10/O
                         net (fo=29, routed)          1.008    12.353    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_10
    SLICE_X53Y20         LUT6 (Prop_lut6_I1_O)        0.124    12.477 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS[ccnt][0]_i_4/O
                         net (fo=1, routed)           0.569    13.046    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[ccnt][0]_i_4
    SLICE_X52Y20         CARRY4 (Prop_carry4_DI[1]_CO[3])
                                                      0.520    13.566 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][0]_i_1/CO[3]
                         net (fo=1, routed)           0.000    13.566    RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS_reg[ccnt][0]_i_1
    SLICE_X52Y21         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239    13.805 r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][4]_i_1__0/O[2]
                         net (fo=1, routed)           0.000    13.805    RLINK/SERPORT/UART/RXTX/RX/n_5_R_REGS_reg[ccnt][4]_i_1__0
    SLICE_X52Y21         FDRE                                         r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][6]/D
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                     10.000    10.000 r  
    W5                                                0.000    10.000 r  I_CLK100
                         net (fo=0)                   0.000    10.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        1.440    14.781    RLINK/SERPORT/UART/RXTX/RX/I_CLK100_IBUF_BUFG
    SLICE_X52Y21                                                      r  RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][6]/C
                         clock pessimism              0.180    14.961    
                         clock uncertainty           -0.035    14.926    
    SLICE_X52Y21         FDRE (Setup_fdre_C_D)        0.109    15.035    RLINK/SERPORT/UART/RXTX/RX/R_REGS_reg[ccnt][6]
  -------------------------------------------------------------------
                         required time                         15.035    
                         arrival time                         -13.805    
  -------------------------------------------------------------------
                         slack                                  1.230    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.011ns  (arrival time - required time)
  Source:                 RBDTST/MON/R_REGS_reg[rbdata][5]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM/DIADI[21]
                            (rising edge-triggered cell RAMB36E1 clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (I_CLK100 rise@0.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        0.386ns  (logic 0.141ns (36.501%)  route 0.245ns (63.499%))
  Logic Levels:           0  
  Clock Path Skew:        0.079ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.006ns
    Source Clock Delay      (SCD):    1.448ns
    Clock Pessimism Removal (CPR):    0.478ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.565     1.448    RBDTST/MON/I_CLK100_IBUF_BUFG
    SLICE_X51Y8                                                       r  RBDTST/MON/R_REGS_reg[rbdata][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X51Y8          FDRE (Prop_fdre_C_Q)         0.141     1.589 r  RBDTST/MON/R_REGS_reg[rbdata][5]/Q
                         net (fo=1, routed)           0.245     1.834    RBDTST/MON/BRAM0/UMEM/DI[21]
    RAMB36_X2Y1          RAMB36E1                                     r  RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM/DIADI[21]
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.878     2.006    RBDTST/MON/BRAM0/UMEM/I_CLK100_IBUF_BUFG
    RAMB36_X2Y1                                                       r  RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM/CLKARDCLK
                         clock pessimism             -0.478     1.528    
    RAMB36_X2Y1          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[21])
                                                      0.296     1.824    RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM
  -------------------------------------------------------------------
                         required time                         -1.824    
                         arrival time                           1.834    
  -------------------------------------------------------------------
                         slack                                  0.011    

Slack (MET) :             0.048ns  (arrival time - required time)
  Source:                 RBDTST/MON/R_REGS_reg[rbdata][9]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM/DIADI[25]
                            (rising edge-triggered cell RAMB36E1 clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (I_CLK100 rise@0.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        0.423ns  (logic 0.164ns (38.748%)  route 0.259ns (61.252%))
  Logic Levels:           0  
  Clock Path Skew:        0.079ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.006ns
    Source Clock Delay      (SCD):    1.448ns
    Clock Pessimism Removal (CPR):    0.478ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.565     1.448    RBDTST/MON/I_CLK100_IBUF_BUFG
    SLICE_X52Y9                                                       r  RBDTST/MON/R_REGS_reg[rbdata][9]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X52Y9          FDRE (Prop_fdre_C_Q)         0.164     1.612 r  RBDTST/MON/R_REGS_reg[rbdata][9]/Q
                         net (fo=1, routed)           0.259     1.871    RBDTST/MON/BRAM0/UMEM/DI[25]
    RAMB36_X2Y1          RAMB36E1                                     r  RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM/DIADI[25]
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.878     2.006    RBDTST/MON/BRAM0/UMEM/I_CLK100_IBUF_BUFG
    RAMB36_X2Y1                                                       r  RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM/CLKARDCLK
                         clock pessimism             -0.478     1.528    
    RAMB36_X2Y1          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[25])
                                                      0.296     1.824    RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM
  -------------------------------------------------------------------
                         required time                         -1.824    
                         arrival time                           1.871    
  -------------------------------------------------------------------
                         slack                                  0.048    

Slack (MET) :             0.081ns  (arrival time - required time)
  Source:                 RBDTST/MON/R_REGS_reg[rbdata][12]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM/DIADI[28]
                            (rising edge-triggered cell RAMB36E1 clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (I_CLK100 rise@0.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        0.458ns  (logic 0.164ns (35.812%)  route 0.294ns (64.188%))
  Logic Levels:           0  
  Clock Path Skew:        0.080ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.006ns
    Source Clock Delay      (SCD):    1.447ns
    Clock Pessimism Removal (CPR):    0.478ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.564     1.447    RBDTST/MON/I_CLK100_IBUF_BUFG
    SLICE_X54Y10                                                      r  RBDTST/MON/R_REGS_reg[rbdata][12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X54Y10         FDRE (Prop_fdre_C_Q)         0.164     1.611 r  RBDTST/MON/R_REGS_reg[rbdata][12]/Q
                         net (fo=1, routed)           0.294     1.905    RBDTST/MON/BRAM0/UMEM/DI[28]
    RAMB36_X2Y1          RAMB36E1                                     r  RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM/DIADI[28]
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.878     2.006    RBDTST/MON/BRAM0/UMEM/I_CLK100_IBUF_BUFG
    RAMB36_X2Y1                                                       r  RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM/CLKARDCLK
                         clock pessimism             -0.478     1.528    
    RAMB36_X2Y1          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[28])
                                                      0.296     1.824    RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM
  -------------------------------------------------------------------
                         required time                         -1.824    
                         arrival time                           1.905    
  -------------------------------------------------------------------
                         slack                                  0.081    

Slack (MET) :             0.084ns  (arrival time - required time)
  Source:                 RLINK/CORE/RL/R_LREGS_reg[arpend]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RLINK/CORE/RL/R_LREGS_reg[atocnt][4]/D
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (I_CLK100 rise@0.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        0.440ns  (logic 0.186ns (42.301%)  route 0.254ns (57.699%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.265ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.958ns
    Source Clock Delay      (SCD):    1.444ns
    Clock Pessimism Removal (CPR):    0.249ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.561     1.444    RLINK/CORE/RL/I_CLK100_IBUF_BUFG
    SLICE_X33Y11                                                      r  RLINK/CORE/RL/R_LREGS_reg[arpend]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X33Y11         FDRE (Prop_fdre_C_Q)         0.141     1.585 r  RLINK/CORE/RL/R_LREGS_reg[arpend]/Q
                         net (fo=13, routed)          0.254     1.839    RLINK/CORE/RL/n_0_R_LREGS_reg[arpend]
    SLICE_X39Y7          LUT5 (Prop_lut5_I2_O)        0.045     1.884 r  RLINK/CORE/RL/R_LREGS[atocnt][4]_i_1/O
                         net (fo=1, routed)           0.000     1.884    RLINK/CORE/RL/N_LREGS[atocnt][4]
    SLICE_X39Y7          FDRE                                         r  RLINK/CORE/RL/R_LREGS_reg[atocnt][4]/D
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.831     1.958    RLINK/CORE/RL/I_CLK100_IBUF_BUFG
    SLICE_X39Y7                                                       r  RLINK/CORE/RL/R_LREGS_reg[atocnt][4]/C
                         clock pessimism             -0.249     1.709    
    SLICE_X39Y7          FDRE (Hold_fdre_C_D)         0.091     1.800    RLINK/CORE/RL/R_LREGS_reg[atocnt][4]
  -------------------------------------------------------------------
                         required time                         -1.800    
                         arrival time                           1.884    
  -------------------------------------------------------------------
                         slack                                  0.084    

Slack (MET) :             0.086ns  (arrival time - required time)
  Source:                 RLINK/CORE/B2CD/R_REGS_reg[data][5]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RLINK/CORE/RL/ICRC/R_CRC_reg[1]/D
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (I_CLK100 rise@0.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        0.479ns  (logic 0.229ns (47.848%)  route 0.250ns (52.152%))
  Logic Levels:           1  (LUT4=1)
  Clock Path Skew:        0.262ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.947ns
    Source Clock Delay      (SCD):    1.436ns
    Clock Pessimism Removal (CPR):    0.249ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.553     1.436    RLINK/CORE/B2CD/I_CLK100_IBUF_BUFG
    SLICE_X37Y21                                                      r  RLINK/CORE/B2CD/R_REGS_reg[data][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y21         FDRE (Prop_fdre_C_Q)         0.128     1.564 r  RLINK/CORE/B2CD/R_REGS_reg[data][5]/Q
                         net (fo=16, routed)          0.250     1.814    RLINK/CORE/RL/ICRC/Q[5]
    SLICE_X34Y20         LUT4 (Prop_lut4_I3_O)        0.101     1.915 r  RLINK/CORE/RL/ICRC/R_CRC[1]_i_1/O
                         net (fo=1, routed)           0.000     1.915    RLINK/CORE/RL/ICRC/p_13_in
    SLICE_X34Y20         FDRE                                         r  RLINK/CORE/RL/ICRC/R_CRC_reg[1]/D
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.820     1.947    RLINK/CORE/RL/ICRC/I_CLK100_IBUF_BUFG
    SLICE_X34Y20                                                      r  RLINK/CORE/RL/ICRC/R_CRC_reg[1]/C
                         clock pessimism             -0.249     1.698    
    SLICE_X34Y20         FDRE (Hold_fdre_C_D)         0.131     1.829    RLINK/CORE/RL/ICRC/R_CRC_reg[1]
  -------------------------------------------------------------------
                         required time                         -1.829    
                         arrival time                           1.915    
  -------------------------------------------------------------------
                         slack                                  0.086    

Slack (MET) :             0.090ns  (arrival time - required time)
  Source:                 RBDTST/MON/R_REGS_reg[rbdata][0]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM/DIADI[16]
                            (rising edge-triggered cell RAMB36E1 clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (I_CLK100 rise@0.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        0.465ns  (logic 0.141ns (30.319%)  route 0.324ns (69.681%))
  Logic Levels:           0  
  Clock Path Skew:        0.079ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.006ns
    Source Clock Delay      (SCD):    1.448ns
    Clock Pessimism Removal (CPR):    0.478ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.565     1.448    RBDTST/MON/I_CLK100_IBUF_BUFG
    SLICE_X48Y8                                                       r  RBDTST/MON/R_REGS_reg[rbdata][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y8          FDRE (Prop_fdre_C_Q)         0.141     1.589 r  RBDTST/MON/R_REGS_reg[rbdata][0]/Q
                         net (fo=1, routed)           0.324     1.913    RBDTST/MON/BRAM0/UMEM/DI[16]
    RAMB36_X2Y1          RAMB36E1                                     r  RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM/DIADI[16]
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.878     2.006    RBDTST/MON/BRAM0/UMEM/I_CLK100_IBUF_BUFG
    RAMB36_X2Y1                                                       r  RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM/CLKARDCLK
                         clock pessimism             -0.478     1.528    
    RAMB36_X2Y1          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[16])
                                                      0.296     1.824    RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM
  -------------------------------------------------------------------
                         required time                         -1.824    
                         arrival time                           1.913    
  -------------------------------------------------------------------
                         slack                                  0.090    

Slack (MET) :             0.094ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][6]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[6].MEM1/SP/I
                            (rising edge-triggered cell RAMD32 clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (I_CLK100 rise@0.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        0.273ns  (logic 0.141ns (51.743%)  route 0.132ns (48.257%))
  Logic Levels:           0  
  Clock Path Skew:        0.033ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.947ns
    Source Clock Delay      (SCD):    1.436ns
    Clock Pessimism Removal (CPR):    0.478ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.553     1.436    RLINK/SERPORT/XONRX/I_CLK100_IBUF_BUFG
    SLICE_X40Y21                                                      r  RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y21         FDRE (Prop_fdre_C_Q)         0.141     1.577 r  RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][6]/Q
                         net (fo=4, routed)           0.132     1.709    RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[6].MEM1/D
    SLICE_X38Y21         RAMD32                                       r  RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[6].MEM1/SP/I
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.820     1.947    RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[6].MEM1/WCLK
    SLICE_X38Y21                                                      r  RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[6].MEM1/SP/CLK
                         clock pessimism             -0.478     1.469    
    SLICE_X38Y21         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.146     1.615    RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[6].MEM1/SP
  -------------------------------------------------------------------
                         required time                         -1.615    
                         arrival time                           1.709    
  -------------------------------------------------------------------
                         slack                                  0.094    

Slack (MET) :             0.094ns  (arrival time - required time)
  Source:                 RLINK/CORE/B2CD/R_REGS_reg[data][5]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RLINK/CORE/RL/ICRC/R_CRC_reg[13]/D
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (I_CLK100 rise@0.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        0.477ns  (logic 0.227ns (47.630%)  route 0.250ns (52.370%))
  Logic Levels:           1  (LUT5=1)
  Clock Path Skew:        0.262ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.947ns
    Source Clock Delay      (SCD):    1.436ns
    Clock Pessimism Removal (CPR):    0.249ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.553     1.436    RLINK/CORE/B2CD/I_CLK100_IBUF_BUFG
    SLICE_X37Y21                                                      r  RLINK/CORE/B2CD/R_REGS_reg[data][5]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X37Y21         FDRE (Prop_fdre_C_Q)         0.128     1.564 r  RLINK/CORE/B2CD/R_REGS_reg[data][5]/Q
                         net (fo=16, routed)          0.250     1.814    RLINK/CORE/RL/ICRC/Q[5]
    SLICE_X34Y20         LUT5 (Prop_lut5_I1_O)        0.099     1.913 r  RLINK/CORE/RL/ICRC/R_CRC[13]_i_1/O
                         net (fo=1, routed)           0.000     1.913    RLINK/CORE/RL/ICRC/crc16_update[13]
    SLICE_X34Y20         FDRE                                         r  RLINK/CORE/RL/ICRC/R_CRC_reg[13]/D
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.820     1.947    RLINK/CORE/RL/ICRC/I_CLK100_IBUF_BUFG
    SLICE_X34Y20                                                      r  RLINK/CORE/RL/ICRC/R_CRC_reg[13]/C
                         clock pessimism             -0.249     1.698    
    SLICE_X34Y20         FDRE (Hold_fdre_C_D)         0.121     1.819    RLINK/CORE/RL/ICRC/R_CRC_reg[13]
  -------------------------------------------------------------------
                         required time                         -1.819    
                         arrival time                           1.913    
  -------------------------------------------------------------------
                         slack                                  0.094    

Slack (MET) :             0.096ns  (arrival time - required time)
  Source:                 RBDTST/MON/R_REGS_reg[rbdata][2]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM/DIADI[18]
                            (rising edge-triggered cell RAMB36E1 clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (I_CLK100 rise@0.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        0.471ns  (logic 0.141ns (29.923%)  route 0.330ns (70.077%))
  Logic Levels:           0  
  Clock Path Skew:        0.079ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    2.006ns
    Source Clock Delay      (SCD):    1.448ns
    Clock Pessimism Removal (CPR):    0.478ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.565     1.448    RBDTST/MON/I_CLK100_IBUF_BUFG
    SLICE_X48Y8                                                       r  RBDTST/MON/R_REGS_reg[rbdata][2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X48Y8          FDRE (Prop_fdre_C_Q)         0.141     1.589 r  RBDTST/MON/R_REGS_reg[rbdata][2]/Q
                         net (fo=1, routed)           0.330     1.919    RBDTST/MON/BRAM0/UMEM/DI[18]
    RAMB36_X2Y1          RAMB36E1                                     r  RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM/DIADI[18]
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.878     2.006    RBDTST/MON/BRAM0/UMEM/I_CLK100_IBUF_BUFG
    RAMB36_X2Y1                                                       r  RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM/CLKARDCLK
                         clock pessimism             -0.478     1.528    
    RAMB36_X2Y1          RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[18])
                                                      0.296     1.824    RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM
  -------------------------------------------------------------------
                         required time                         -1.824    
                         arrival time                           1.919    
  -------------------------------------------------------------------
                         slack                                  0.096    

Slack (MET) :             0.096ns  (arrival time - required time)
  Source:                 RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][0]/C
                            (rising edge-triggered cell FDRE clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[0].MEM0/SP/I
                            (rising edge-triggered cell RAMD32 clocked by I_CLK100  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             I_CLK100
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (I_CLK100 rise@0.000ns - I_CLK100 rise@0.000ns)
  Data Path Delay:        0.274ns  (logic 0.141ns (51.400%)  route 0.133ns (48.600%))
  Logic Levels:           0  
  Clock Path Skew:        0.034ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.946ns
    Source Clock Delay      (SCD):    1.434ns
    Clock Pessimism Removal (CPR):    0.478ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.551     1.434    RLINK/SERPORT/XONRX/I_CLK100_IBUF_BUFG
    SLICE_X40Y23                                                      r  RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][0]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X40Y23         FDRE (Prop_fdre_C_Q)         0.141     1.575 r  RLINK/SERPORT/XONRX/R_REGS_reg[rxdata][0]/Q
                         net (fo=4, routed)           0.133     1.708    RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[0].MEM0/D
    SLICE_X38Y22         RAMD32                                       r  RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[0].MEM0/SP/I
  -------------------------------------------------------------------    -------------------

                         (clock I_CLK100 rise edge)
                                                      0.000     0.000 r  
    W5                                                0.000     0.000 r  I_CLK100
                         net (fo=0)                   0.000     0.000    I_CLK100
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  I_CLK100_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    I_CLK100_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  I_CLK100_IBUF_BUFG_inst/O
                         net (fo=1132, routed)        0.819     1.946    RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[0].MEM0/WCLK
    SLICE_X38Y22                                                      r  RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[0].MEM0/SP/CLK
                         clock pessimism             -0.478     1.468    
    SLICE_X38Y22         RAMD32 (Hold_ramd32_CLK_I)
                                                      0.144     1.612    RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[0].MEM0/SP
  -------------------------------------------------------------------
                         required time                         -1.612    
                         arrival time                           1.708    
  -------------------------------------------------------------------
                         slack                                  0.096    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         I_CLK100
Waveform:           { 0 5 }
Period:             10.000
Sources:            { I_CLK100 }

Check Type        Corner  Lib Pin             Reference Pin  Required  Actual  Slack  Location       Pin                                                    
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.944     10.000  7.056  RAMB18_X1Y6    RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[0].MEM/CLKARDCLK  
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.944     10.000  7.056  RAMB18_X1Y6    RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[0].MEM/CLKBWRCLK  
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.944     10.000  7.056  RAMB18_X1Y7    RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[1].MEM/CLKARDCLK  
Min Period        n/a     RAMB18E1/CLKBWRCLK  n/a            2.944     10.000  7.056  RAMB18_X1Y7    RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[1].MEM/CLKBWRCLK  
Min Period        n/a     RAMB18E1/CLKARDCLK  n/a            2.576     10.000  7.424  RAMB18_X1Y2    RBDTST/BRAM/BRAM/UMEM/AW_10_S18.GL[0].MEM/CLKARDCLK    
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.576     10.000  7.424  RAMB36_X1Y2    RBDTST/EMON/BRAM/UMEM/AW_09_S32.GL[0].MEM/CLKARDCLK    
Min Period        n/a     RAMB36E1/CLKBWRCLK  n/a            2.576     10.000  7.424  RAMB36_X1Y2    RBDTST/EMON/BRAM/UMEM/AW_09_S32.GL[0].MEM/CLKBWRCLK    
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.576     10.000  7.424  RAMB36_X2Y1    RBDTST/MON/BRAM0/UMEM/AW_09_S32.GL[0].MEM/CLKARDCLK    
Min Period        n/a     RAMB36E1/CLKARDCLK  n/a            2.576     10.000  7.424  RAMB36_X2Y2    RBDTST/MON/BRAM1/UMEM/AW_09_S32.GL[0].MEM/CLKARDCLK    
Min Period        n/a     BUFG/I              n/a            2.155     10.000  7.845  BUFGCTRL_X0Y0  I_CLK100_IBUF_BUFG_inst/I                              
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X50Y13   RBDTST/TEST/FIFO/RAM/AW_4.GL[2].MEM/DP/CLK             
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X50Y13   RBDTST/TEST/FIFO/RAM/AW_4.GL[2].MEM/SP/CLK             
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X50Y13   RBDTST/TEST/FIFO/RAM/AW_4.GL[3].MEM/DP/CLK             
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X50Y13   RBDTST/TEST/FIFO/RAM/AW_4.GL[3].MEM/SP/CLK             
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X50Y13   RBDTST/TEST/FIFO/RAM/AW_4.GL[4].MEM/DP/CLK             
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X50Y13   RBDTST/TEST/FIFO/RAM/AW_4.GL[4].MEM/SP/CLK             
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X50Y13   RBDTST/TEST/FIFO/RAM/AW_4.GL[5].MEM/DP/CLK             
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X50Y13   RBDTST/TEST/FIFO/RAM/AW_4.GL[5].MEM/SP/CLK             
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X52Y13   RBDTST/TEST/FIFO/RAM/AW_4.GL[6].MEM/DP/CLK             
Low Pulse Width   Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X52Y13   RBDTST/TEST/FIFO/RAM/AW_4.GL[6].MEM/SP/CLK             
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X52Y12   RBDTST/TEST/FIFO/RAM/AW_4.GL[0].MEM/DP/CLK             
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X52Y12   RBDTST/TEST/FIFO/RAM/AW_4.GL[0].MEM/SP/CLK             
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X52Y12   RBDTST/TEST/FIFO/RAM/AW_4.GL[10].MEM/DP/CLK            
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X52Y12   RBDTST/TEST/FIFO/RAM/AW_4.GL[10].MEM/SP/CLK            
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X52Y12   RBDTST/TEST/FIFO/RAM/AW_4.GL[11].MEM/DP/CLK            
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X52Y12   RBDTST/TEST/FIFO/RAM/AW_4.GL[11].MEM/SP/CLK            
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X52Y12   RBDTST/TEST/FIFO/RAM/AW_4.GL[12].MEM/DP/CLK            
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X52Y12   RBDTST/TEST/FIFO/RAM/AW_4.GL[12].MEM/SP/CLK            
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X50Y12   RBDTST/TEST/FIFO/RAM/AW_4.GL[13].MEM/DP/CLK            
High Pulse Width  Slow    RAMD32/CLK          n/a            1.250     5.000   3.750  SLICE_X50Y12   RBDTST/TEST/FIFO/RAM/AW_4.GL[13].MEM/SP/CLK            



