Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
---------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2014.4 (lin64) Build 1071353 Tue Nov 18 16:48:31 MST 2014
| Date         : Thu May 14 17:43:38 2015
| Host         : athome running 64-bit Ubuntu 14.04.2 LTS
| Command      : report_control_sets -verbose -file sys_tst_rlink_b3_control_sets_placed.rpt
| Design       : sys_tst_rlink_b3
| Device       : xc7a35t
---------------------------------------------------------------------------------------------

Control Set Information

Table of Contents
-----------------
1. Summary
2. Flip-Flop Distribution
3. Detailed Control Set Information

1. Summary
----------

+-------------------------------------------------------------------+-------+
|                               Status                              | Count |
+-------------------------------------------------------------------+-------+
| Number of unique control sets                                     |    84 |
| Minimum Number of register sites lost to control set restrictions |   200 |
+-------------------------------------------------------------------+-------+


2. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |             229 |           87 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |              40 |           21 |
| Yes          | No                    | No                     |             477 |          196 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |             198 |           62 |
+--------------+-----------------------+------------------------+-----------------+--------------+


3. Detailed Control Set Information
-----------------------------------

+---------------------+-------------------------------------------------------+-------------------------------------------------------+------------------+----------------+
|     Clock Signal    |                     Enable Signal                     |                    Set/Reset Signal                   | Slice Load Count | Bel Load Count |
+---------------------+-------------------------------------------------------+-------------------------------------------------------+------------------+----------------+
|  I_CLK100_IBUF_BUFG | RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[bcnt][3]_i_2    | RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[bcnt][3]_i_1__0 |                1 |              4 |
|  I_CLK100_IBUF_BUFG | CLKDIV/CE_MSEC                                        |                                                       |                2 |              4 |
|  I_CLK100_IBUF_BUFG | RBDTST/TEST/FIFO/E[0]                                 | RLINK/CORE/RL/I91[0]                                  |                2 |              4 |
|  I_CLK100_IBUF_BUFG | RLINK/SERPORT/UART/AB/n_0_R_REGS[mcnt][6]_i_2         | RLINK/SERPORT/UART/AB/n_0_R_REGS[mcnt][6]_i_1         |                2 |              4 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/iram_we                                 | RLINK/CORE/RL/I91[0]                                  |                3 |              4 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/n_0_R_BREGS[stat][3]_i_1                |                                                       |                1 |              4 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/n_0_R_BREGS[state][3]_i_1               |                                                       |                3 |              4 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/O16                                     |                                                       |                1 |              4 |
|  I_CLK100_IBUF_BUFG | RLINK/SERPORT/UART/RXTX/TX/ld_ccnt                    | RLINK/SERPORT/UART/RXTX/TX/n_0_R_REGS[bcnt][3]_i_1    |                1 |              4 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/I83[0]                                  | RLINK/CORE/RL/O85[0]                                  |                2 |              4 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/N_REGS[empty]_0                         | RLINK/SERPORT/UART/AB/O1                              |                1 |              5 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/DOFIFO/FIFO/RAM/N_REGS[full]            |                                                       |                2 |              5 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/n[swi_en]                               |                                                       |                4 |              5 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/DOFIFO/FIFO/N_REGS[empty]               |                                                       |                2 |              5 |
|  I_CLK100_IBUF_BUFG | RLINK/SERPORT/XONTX/n[oval]12_out                     | RLINK/SERPORT/XONTX/n_0_R_REGS[obuf][7]_i_1           |                1 |              5 |
|  I_CLK100_IBUF_BUFG |                                                       | HIO/HIO/HIO/DEB.DEB_BTN/n_0_R_REGS[dref][4]_i_1       |                3 |              5 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/CD2B/E[0]                                  | RLINK/SERPORT/UART/AB/O1                              |                2 |              5 |
|  I_CLK100_IBUF_BUFG |                                                       | HIO/n_0_R_REGS[ledeff][6]_i_1                         |                5 |              5 |
|  I_CLK100_IBUF_BUFG | HIO/HIO/HIO/DEB.DEB_BTN/n_0_R_REGS[dref][4]_i_1       |                                                       |                3 |              5 |
|  I_CLK100_IBUF_BUFG | RLINK/SERPORT/XONRX/E[0]                              | RLINK/SERPORT/UART/AB/O1                              |                3 |              5 |
|  I_CLK100_IBUF_BUFG | RLINK/SERPORT/UART/AB/n_0_R_REGS[ccnt][12]_i_2__0     | RLINK/SERPORT/UART/AB/n_0_R_REGS[ccnt][12]_i_1        |                3 |              6 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/O141                                    |                                                       |                3 |              6 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/O86                                     |                                                       |                3 |              6 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/DOFIFO/FIFO/O10                         |                                                       |                5 |              6 |
|  I_CLK100_IBUF_BUFG |                                                       | RLINK/CORE/RL/n_0_R_BREGS[btocnt][5]_i_1              |                1 |              6 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/n_0_R_LREGS[rcmd][7]_i_1                |                                                       |                3 |              8 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/O64                                     |                                                       |                4 |              8 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/n_0_R_LREGS[lcmd][7]_i_1                |                                                       |                3 |              8 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/n_0_R_LREGS[addr][7]_i_1                |                                                       |                2 |              8 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/n_0_R_LREGS[dinl][7]_i_1                |                                                       |                3 |              8 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/n_0_R_LREGS[cnt][7]_i_1                 |                                                       |                5 |              8 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/n_0_R_LREGS[cnt][15]_i_1                |                                                       |                5 |              8 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/n_0_R_LREGS[atocnt][7]_i_1              |                                                       |                4 |              8 |
|  I_CLK100_IBUF_BUFG | RBDTST/EMON/n_0_R_REGS[rdivcnt][7]_i_1                |                                                       |                4 |              8 |
|  I_CLK100_IBUF_BUFG | RLINK/SERPORT/UART/RXTX/RX/E[0]                       | RLINK/SERPORT/UART/AB/O1                              |                3 |              8 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/n_0_R_LREGS[addr][15]_i_1               |                                                       |                2 |              8 |
|  I_CLK100_IBUF_BUFG | RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[sreg][7]_i_1__0 |                                                       |                2 |              8 |
|  I_CLK100_IBUF_BUFG | RLINK/SERPORT/UART/RXTX/TX/n_0_R_REGS[sreg][7]_i_1    |                                                       |                1 |              8 |
|  I_CLK100_IBUF_BUFG |                                                       | RLINK/SERPORT/UART/AB/O1                              |                5 |              8 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/n[din][15]                              |                                                       |                3 |              8 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/n[din][1]                               |                                                       |                6 |              8 |
|  I_CLK100_IBUF_BUFG | RBDTST/EMON/n_0_R_REGS[laddr][8]_i_1                  |                                                       |                4 |              9 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/O17                                     |                                                       |                3 |              9 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/O83                                     |                                                       |                4 |              9 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/CD2B/n[ecodeval]3_out                      |                                                       |                4 |              9 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/E[0]                                    |                                                       |                4 |             10 |
|  I_CLK100_IBUF_BUFG | CLKDIV/n_0_R_REGS[mcnt][9]_i_1                        |                                                       |                3 |             10 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/O71                                     |                                                       |                3 |             10 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/O102[0]                                 | RLINK/CORE/RL/O85[0]                                  |                4 |             10 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/O87                                     | RLINK/CORE/RL/O145                                    |                3 |             10 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/R_REGS_reg[ncyc]0                       |                                                       |                2 |             10 |
|  I_CLK100_IBUF_BUFG | RBDTST/MON/n_0_R_REGS[rbnbusy][9]_i_2                 | RLINK/CORE/RL/I94[0]                                  |                2 |             10 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/SEL/n[anena]                            |                                                       |                4 |             10 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/O103                                    |                                                       |                5 |             10 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/n_0_R_BREGS[cnt][10]_i_1                |                                                       |                4 |             11 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/n_0_R_BREGS[dcnt][10]_i_2               | RLINK/CORE/RL/cnt_load                                |                3 |             11 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/DOFIFO/FIFO/sel                         | RLINK/CORE/RL/addra_clear                             |                3 |             12 |
|  I_CLK100_IBUF_BUFG | RLINK/SERPORT/UART/AB/n_0_R_REGS[ccnt][12]_i_2__0     |                                                       |                3 |             12 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/ICRC/O11                                |                                                       |                3 |             12 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/ICRC/O13                                | RLINK/CORE/RL/ICRC/n[rtaddrb_red]16_out               |                3 |             12 |
|  I_CLK100_IBUF_BUFG | RLINK/SERPORT/XONTX/E[0]                              | RLINK/SERPORT/UART/AB/O1                              |                3 |             13 |
|  I_CLK100_IBUF_BUFG | RBDTST/MON/n_0_R_REGS[rbndly][0]_i_2                  | RLINK/CORE/RL/O140                                    |                4 |             14 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/p_1_out[0]                              |                                                       |                4 |             16 |
|  I_CLK100_IBUF_BUFG | RLINK/SERPORT/UART/RXTX/RX/n_0_R_REGS[dcnt][0]_i_1    |                                                       |                4 |             16 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/I82[0]                                  | RLINK/CORE/RL/I81[0]                                  |                5 |             16 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/ICRC/icrcena                            | RLINK/CORE/RL/ICRC/O10                                |                4 |             16 |
|  I_CLK100_IBUF_BUFG |                                                       | HIO/HIO/HIO/DEB.DEB_SWI/n_0_R_REGS[dref][15]_i_1      |                7 |             16 |
|  I_CLK100_IBUF_BUFG | RLINK/SERPORT/RXFIFO/FIFO/RAM/WE1                     |                                                       |                2 |             16 |
|  I_CLK100_IBUF_BUFG | HIO/HIO/HIO/DEB.DEB_SWI/n_0_R_REGS[dref][15]_i_1      |                                                       |                7 |             16 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/DOFIFO/FIFO/E[0]                        | RLINK/CORE/RL/ICRC/O10                                |                4 |             16 |
|  I_CLK100_IBUF_BUFG | RLINK/SERPORT/RXFIFO/FIFO/RAM/WE0                     |                                                       |                2 |             16 |
|  I_CLK100_IBUF_BUFG | RLINK/SERPORT/TXFIFO/FIFO/RAM/WE1                     |                                                       |                2 |             16 |
|  I_CLK100_IBUF_BUFG | RLINK/SERPORT/TXFIFO/FIFO/RAM/WE0                     |                                                       |                2 |             16 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/O15                                     |                                                       |                9 |             16 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/O62                                     |                                                       |                7 |             16 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/O63                                     |                                                       |                5 |             16 |
|  I_CLK100_IBUF_BUFG | RBDTST/TIM0/n_0_R_REGS[timer][15]_i_1                 |                                                       |                5 |             16 |
|  I_CLK100_IBUF_BUFG | RBDTST/TIM1/n_0_R_REGS[timer][15]_i_1__0              |                                                       |                8 |             16 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/DOFIFO/FIFO/RAM/WE1                     |                                                       |                2 |             16 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/n_0_R_BREGS[rbdout][15]_i_1             |                                                       |                7 |             16 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/DOFIFO/FIFO/RAM/WE0                     |                                                       |                2 |             16 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/iram_we                                 |                                                       |                4 |             32 |
|  I_CLK100_IBUF_BUFG | RLINK/CORE/RL/O101                                    |                                                       |               18 |             36 |
|  I_CLK100_IBUF_BUFG |                                                       |                                                       |               87 |            229 |
+---------------------+-------------------------------------------------------+-------------------------------------------------------+------------------+----------------+


