--------------------------------------------------------------------------------
Release 14.7 Trace  (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

/mnt/data/opt/Xilinx/ISE/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 3
-fastpaths -u 100 -intstyle xflow -xml sys_w11a_n3.twx -tsi sys_w11a_n3.tsi
sys_w11a_n3.ncd sys_w11a_n3.pcf

Design file:              sys_w11a_n3.ncd
Physical constraint file: sys_w11a_n3.pcf
Device,package,speed:     xc6slx16,csg324,C,-2 (PRODUCTION 1.23 2013-10-13)
Report level:             verbose report
                          unconstrained path report, limited to 100 items

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

WARNING:Timing:3391 - Timing constraint OFFSET = IN 10 ns BEFORE COMP 
   "I_CLK100"; does not specify a data valid duration and will not be hold 
   checked. To enable hold checking on this offset constraint please specify a 
   data valid duration using the VALID <duration> option.
INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more 
   information, see the TSI report.  Please consult the Xilinx Command Line 
   Tools User Guide for information on generating a TSI report.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: TS_I_CLK100 = PERIOD TIMEGRP "I_CLK100" 10 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 component switching limit errors)
 Minimum period is   5.340ns.
--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_I_CLK100 = PERIOD TIMEGRP "I_CLK100" 10 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 4.660ns (period - (min low pulse limit / (low pulse / period)))
  Period: 10.000ns
  Low pulse: 5.000ns
  Low pulse limit: 2.670ns (Tdcmpw_CLKIN_100_150)
  Physical resource: GEN_CLKSYS/USEDCM.DCM/CLKIN
  Logical resource: GEN_CLKSYS/USEDCM.DCM/CLKIN
  Location pin: DCM_X0Y1.CLKIN
  Clock network: GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
--------------------------------------------------------------------------------
Slack: 4.660ns (period - (min high pulse limit / (high pulse / period)))
  Period: 10.000ns
  High pulse: 5.000ns
  High pulse limit: 2.670ns (Tdcmpw_CLKIN_100_150)
  Physical resource: GEN_CLKSYS/USEDCM.DCM/CLKIN
  Logical resource: GEN_CLKSYS/USEDCM.DCM/CLKIN
  Location pin: DCM_X0Y1.CLKIN
  Clock network: GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
--------------------------------------------------------------------------------
Slack: 7.000ns (period - min period limit)
  Period: 10.000ns
  Min period limit: 3.000ns (333.333MHz) (Tdcmper_CLKIN)
  Physical resource: GEN_CLKSYS/USEDCM.DCM/CLKIN
  Logical resource: GEN_CLKSYS/USEDCM.DCM/CLKIN
  Location pin: DCM_X0Y1.CLKIN
  Clock network: GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_PAD_CLK = MAXDELAY FROM TIMEGRP "PADS(I_CLK100)" TO 
TIMEGRP "TNM_CLK" 10         ns;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 2434 paths analyzed, 2434 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   6.912ns.
--------------------------------------------------------------------------------
Slack (slowest paths):  3.088ns (requirement - data path)
  Source:               I_CLK100 (PAD)
  Destination:          IOB_RS232/P0/IOB_RXD/IOB/R_DI_0 (FF)
  Requirement:          10.000ns
  Data Path Delay:      6.912ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to IOB_RS232/P0/IOB_RXD/IOB/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X18Y19.CLK0   net (fanout=1029)     1.778   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.912ns (2.356ns logic, 4.556ns route)
                                                       (34.1% logic, 65.9% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  3.089ns (requirement - data path)
  Source:               I_CLK100 (PAD)
  Destination:          SRAM_CTL/IOB_MEM_DATA/R_DI_0 (FF)
  Requirement:          10.000ns
  Data Path Delay:      6.911ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SRAM_CTL/IOB_MEM_DATA/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X16Y1.CLK0    net (fanout=1029)     1.777   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.911ns (2.356ns logic, 4.555ns route)
                                                       (34.1% logic, 65.9% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  3.092ns (requirement - data path)
  Source:               I_CLK100 (PAD)
  Destination:          SRAM_CTL/IOB_MEM_DATA/R_DI_8 (FF)
  Requirement:          10.000ns
  Data Path Delay:      6.908ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SRAM_CTL/IOB_MEM_DATA/R_DI_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X1Y1.CLK0     net (fanout=1029)     1.774   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.908ns (2.356ns logic, 4.552ns route)
                                                       (34.1% logic, 65.9% route)

--------------------------------------------------------------------------------
Hold Paths: TS_PAD_CLK = MAXDELAY FROM TIMEGRP "PADS(I_CLK100)" TO TIMEGRP "TNM_CLK" 10         ns;
--------------------------------------------------------------------------------
Delay (fastest path):   2.527ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          IBDR_SYS/DL11_1.I0/R_REGS_xie (FF)
  Data Path Delay:      2.527ns (Levels of Logic = 4)

  Minimum Data Path at Fast Process Corner: I_CLK100 to IBDR_SYS/DL11_1.I0/R_REGS_xie
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    SLICE_X19Y40.CLK     net (fanout=1029)     0.395   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.527ns (1.274ns logic, 1.253ns route)
                                                       (50.4% logic, 49.6% route)
--------------------------------------------------------------------------------
Delay (fastest path):   2.527ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          IBDR_SYS/DL11_1.I0/R_REGS_xmaint (FF)
  Data Path Delay:      2.527ns (Levels of Logic = 4)

  Minimum Data Path at Fast Process Corner: I_CLK100 to IBDR_SYS/DL11_1.I0/R_REGS_xmaint
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    SLICE_X19Y40.CLK     net (fanout=1029)     0.395   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.527ns (1.274ns logic, 1.253ns route)
                                                       (50.4% logic, 49.6% route)
--------------------------------------------------------------------------------
Delay (fastest path):   2.528ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/W11A/SEQ/R_STATE_2_1 (FF)
  Data Path Delay:      2.528ns (Levels of Logic = 4)

  Minimum Data Path at Fast Process Corner: I_CLK100 to SYS70/W11A/SEQ/R_STATE_2_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    SLICE_X18Y8.CLK      net (fanout=1029)     0.396   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.528ns (1.274ns logic, 1.254ns route)
                                                       (50.4% logic, 49.6% route)
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_PAD_IFCLK = MAXDELAY FROM TIMEGRP "PADS(I_FX2_IFCLK)" TO 
TIMEGRP         "TNM_IFCLK" 10 ns;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 122 paths analyzed, 122 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   4.482ns.
--------------------------------------------------------------------------------
Slack (slowest paths):  5.518ns (requirement - data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.482ns (Levels of Logic = 2)

  Maximum Data Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y31.CLK0    net (fanout=49)       1.710   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.482ns (1.766ns logic, 2.716ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  5.519ns (requirement - data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.481ns (Levels of Logic = 2)

  Maximum Data Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y56.CLK0    net (fanout=49)       1.709   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.481ns (1.766ns logic, 2.715ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  5.519ns (requirement - data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0 (FF)
  Requirement:          10.000ns
  Data Path Delay:      4.481ns (Levels of Logic = 2)

  Maximum Data Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y28.CLK0    net (fanout=49)       1.709   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.481ns (1.766ns logic, 2.715ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------
Hold Paths: TS_PAD_IFCLK = MAXDELAY FROM TIMEGRP "PADS(I_FX2_IFCLK)" TO TIMEGRP         "TNM_IFCLK" 10 ns;
--------------------------------------------------------------------------------
Delay (fastest path):   1.498ns (data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Data Path Delay:      1.498ns (Levels of Logic = 2)

  Minimum Data Path at Fast Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 0.763   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.272   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.059   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    SLICE_X14Y54.CLK     net (fanout=49)       0.404   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      1.498ns (0.822ns logic, 0.676ns route)
                                                       (54.9% logic, 45.1% route)
--------------------------------------------------------------------------------
Delay (fastest path):   1.498ns (data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Data Path Delay:      1.498ns (Levels of Logic = 2)

  Minimum Data Path at Fast Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 0.763   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.272   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.059   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    SLICE_X14Y54.CLK     net (fanout=49)       0.404   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      1.498ns (0.822ns logic, 0.676ns route)
                                                       (54.9% logic, 45.1% route)
--------------------------------------------------------------------------------
Delay (fastest path):   1.498ns (data path)
  Source:               I_FX2_IFCLK (PAD)
  Destination:          RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Data Path Delay:      1.498ns (Levels of Logic = 2)

  Minimum Data Path at Fast Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 0.763   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.272   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.059   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    SLICE_X14Y54.CLK     net (fanout=49)       0.404   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      1.498ns (0.822ns logic, 0.676ns route)
                                                       (54.9% logic, 45.1% route)
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_CDC_FIFO = MAXDELAY FROM TIMEGRP 
"FFS(\"*FIFO/GC?/GRAY_*.CNT/R_DATA*\")" TO         TIMEGRP 
"FFS(\"*FIFO/R_REG?_?addr_c*\")" 5 ns DATAPATHONLY;
For more information, see From:To (Multicycle) Analysis in the Timing Closure User Guide (UG612).

 20 paths analyzed, 20 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   2.188ns.
--------------------------------------------------------------------------------
Slack (setup paths):    2.812ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_1 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c_1 (FF)
  Requirement:          5.000ns
  Data Path Delay:      2.188ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_1 to RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y58.AMUX    Tshcko                0.576   RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_1
    SLICE_X13Y60.BX      net (fanout=12)       1.498   RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA<1>
    SLICE_X13Y60.CLK     Tdick                 0.114   RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c_1
    -------------------------------------------------  ---------------------------
    Total                                      2.188ns (0.690ns logic, 1.498ns route)
                                                       (31.5% logic, 68.5% route)

--------------------------------------------------------------------------------
Slack (setup paths):    3.048ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_3 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c_3 (FF)
  Requirement:          5.000ns
  Data Path Delay:      1.952ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_3 to RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y58.BMUX    Tshcko                0.576   RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_3
    SLICE_X13Y60.DX      net (fanout=15)       1.262   RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA<3>
    SLICE_X13Y60.CLK     Tdick                 0.114   RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c_3
    -------------------------------------------------  ---------------------------
    Total                                      1.952ns (0.690ns logic, 1.262ns route)
                                                       (35.3% logic, 64.7% route)

--------------------------------------------------------------------------------
Slack (setup paths):    3.074ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_2 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c_2 (FF)
  Requirement:          5.000ns
  Data Path Delay:      1.926ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.000ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_2 to RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X18Y58.AQ      Tcko                  0.525   RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA_2
    SLICE_X13Y60.CX      net (fanout=14)       1.287   RLINK/FX2CNTL/TXFIFO/GCW/GRAY_5.CNT/R_DATA<2>
    SLICE_X13Y60.CLK     Tdick                 0.114   RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c_2
    -------------------------------------------------  ---------------------------
    Total                                      1.926ns (0.639ns logic, 1.287ns route)
                                                       (33.2% logic, 66.8% route)

--------------------------------------------------------------------------------
Hold Paths: TS_CDC_FIFO = MAXDELAY FROM TIMEGRP "FFS(\"*FIFO/GC?/GRAY_*.CNT/R_DATA*\")" TO         TIMEGRP "FFS(\"*FIFO/R_REG?_?addr_c*\")" 5 ns DATAPATHONLY;
--------------------------------------------------------------------------------
Slack (hold path):      0.600ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_4 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.600ns (Levels of Logic = 0)
  Positive Clock Path Skew: 0.000ns
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_4 to RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X5Y59.BQ       Tcko                  0.198   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_4
    SLICE_X7Y60.AX       net (fanout=7)        0.343   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<4>
    SLICE_X7Y60.CLK      Tckdi       (-Th)    -0.059   RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c<4>
                                                       RLINK/FX2CNTL/RXFIFO/R_REGR_waddr_c_4
    -------------------------------------------------  ---------------------------
    Total                                      0.600ns (0.257ns logic, 0.343ns route)
                                                       (42.8% logic, 57.2% route)
--------------------------------------------------------------------------------
Slack (hold path):      0.668ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_1 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.668ns (Levels of Logic = 0)
  Positive Clock Path Skew: 0.000ns
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_1 to RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y59.AMUX    Tshcko                0.238   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_1
    SLICE_X15Y61.BX      net (fanout=14)       0.371   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<1>
    SLICE_X15Y61.CLK     Tckdi       (-Th)    -0.059   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c_1
    -------------------------------------------------  ---------------------------
    Total                                      0.668ns (0.297ns logic, 0.371ns route)
                                                       (44.5% logic, 55.5% route)
--------------------------------------------------------------------------------
Slack (hold path):      0.671ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_4 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.671ns (Levels of Logic = 0)
  Positive Clock Path Skew: 0.000ns
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_4 to RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y59.BQ      Tcko                  0.200   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA_4
    SLICE_X17Y60.BX      net (fanout=11)       0.412   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
    SLICE_X17Y60.CLK     Tckdi       (-Th)    -0.059   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<4>
                                                       RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c_4
    -------------------------------------------------  ---------------------------
    Total                                      0.671ns (0.259ns logic, 0.412ns route)
                                                       (38.6% logic, 61.4% route)
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_I_FX2_IFCLK = PERIOD TIMEGRP "I_FX2_IFCLK" 33.34 ns HIGH 
50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 1530 paths analyzed, 433 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   9.510ns.
--------------------------------------------------------------------------------
Slack (setup path):     23.830ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1 (FF)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0 (FF)
  Requirement:          33.340ns
  Data Path Delay:      9.352ns (Levels of Logic = 2)
  Clock Path Skew:      -0.123ns (1.036 - 1.159)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1 to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    ILOGIC_X0Y31.Q4      Tickq                 1.778   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<1>
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1
    SLICE_X10Y57.C6      net (fanout=7)        3.035   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<1>
    SLICE_X10Y57.C       Tilo                  0.255   RLINK/FX2CNTL/R_REGS_pepend
                                                       RLINK/FX2CNTL/R_REGS_state_FSM_FFd4-In31
    SLICE_X10Y57.D3      net (fanout=6)        0.495   RLINK/FX2CNTL/R_REGS_state_FSM_FFd4-In3
    SLICE_X10Y57.D       Tilo                  0.254   RLINK/FX2CNTL/R_REGS_pepend
                                                       RLINK/FX2CNTL/Mmux_proc_next.idata_ceo11
    OLOGIC_X0Y46.OCE     net (fanout=8)        2.526   RLINK/FX2CNTL/proc_next.idata_ceo
    OLOGIC_X0Y46.CLK0    Tooceck               1.009   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<0>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    -------------------------------------------------  ---------------------------
    Total                                      9.352ns (3.296ns logic, 6.056ns route)
                                                       (35.2% logic, 64.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     23.887ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1 (FF)
  Destination:          RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO_0 (FF)
  Requirement:          33.340ns
  Data Path Delay:      9.302ns (Levels of Logic = 2)
  Clock Path Skew:      -0.116ns (1.043 - 1.159)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1 to RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    ILOGIC_X0Y31.Q4      Tickq                 1.778   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<1>
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1
    SLICE_X10Y57.C6      net (fanout=7)        3.035   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<1>
    SLICE_X10Y57.C       Tilo                  0.255   RLINK/FX2CNTL/R_REGS_pepend
                                                       RLINK/FX2CNTL/R_REGS_state_FSM_FFd4-In31
    SLICE_X10Y57.D3      net (fanout=6)        0.495   RLINK/FX2CNTL/R_REGS_state_FSM_FFd4-In3
    SLICE_X10Y57.DMUX    Tilo                  0.326   RLINK/FX2CNTL/R_REGS_pepend
                                                       RLINK/FX2CNTL/FX2_SLWR_N1
    OLOGIC_X0Y60.D1      net (fanout=9)        2.235   RLINK/FX2CNTL/FX2_SLWR_N
    OLOGIC_X0Y60.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO
                                                       RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO_0
    -------------------------------------------------  ---------------------------
    Total                                      9.302ns (3.537ns logic, 5.765ns route)
                                                       (38.0% logic, 62.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     24.098ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1 (FF)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1 (FF)
  Requirement:          33.340ns
  Data Path Delay:      9.081ns (Levels of Logic = 2)
  Clock Path Skew:      -0.126ns (1.033 - 1.159)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1 to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    ILOGIC_X0Y31.Q4      Tickq                 1.778   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<1>
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1
    SLICE_X10Y57.C6      net (fanout=7)        3.035   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<1>
    SLICE_X10Y57.C       Tilo                  0.255   RLINK/FX2CNTL/R_REGS_pepend
                                                       RLINK/FX2CNTL/R_REGS_state_FSM_FFd4-In31
    SLICE_X10Y57.D3      net (fanout=6)        0.495   RLINK/FX2CNTL/R_REGS_state_FSM_FFd4-In3
    SLICE_X10Y57.D       Tilo                  0.254   RLINK/FX2CNTL/R_REGS_pepend
                                                       RLINK/FX2CNTL/Mmux_proc_next.idata_ceo11
    OLOGIC_X0Y49.OCE     net (fanout=8)        2.255   RLINK/FX2CNTL/proc_next.idata_ceo
    OLOGIC_X0Y49.CLK0    Tooceck               1.009   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<1>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    -------------------------------------------------  ---------------------------
    Total                                      9.081ns (3.296ns logic, 5.785ns route)
                                                       (36.3% logic, 63.7% route)

--------------------------------------------------------------------------------

Hold Paths: TS_I_FX2_IFCLK = PERIOD TIMEGRP "I_FX2_IFCLK" 33.34 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.381ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c_2 (FF)
  Destination:          RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_s_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.383ns (Levels of Logic = 0)
  Clock Path Skew:      0.002ns (0.040 - 0.038)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 33.340ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c_2 to RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_s_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X13Y60.CQ      Tcko                  0.198   RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c_2
    SLICE_X12Y60.CX      net (fanout=1)        0.137   RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_c<2>
    SLICE_X12Y60.CLK     Tckdi       (-Th)    -0.048   RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_s<3>
                                                       RLINK/FX2CNTL/TXFIFO/R_REGR_waddr_s_2
    -------------------------------------------------  ---------------------------
    Total                                      0.383ns (0.246ns logic, 0.137ns route)
                                                       (64.2% logic, 35.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.438ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/R_REGS_petocnt_4 (FF)
  Destination:          RLINK/FX2CNTL/R_REGS_petocnt_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.438ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 33.340ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/R_REGS_petocnt_4 to RLINK/FX2CNTL/R_REGS_petocnt_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X11Y57.AQ      Tcko                  0.198   RLINK/FX2CNTL/R_REGS_petocnt<7>
                                                       RLINK/FX2CNTL/R_REGS_petocnt_4
    SLICE_X11Y57.A6      net (fanout=4)        0.025   RLINK/FX2CNTL/R_REGS_petocnt<4>
    SLICE_X11Y57.CLK     Tah         (-Th)    -0.215   RLINK/FX2CNTL/R_REGS_petocnt<7>
                                                       RLINK/FX2CNTL/R_REGS_petocnt_4_glue_set
                                                       RLINK/FX2CNTL/R_REGS_petocnt_4
    -------------------------------------------------  ---------------------------
    Total                                      0.438ns (0.413ns logic, 0.025ns route)
                                                       (94.3% logic, 5.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.440ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_2 (FF)
  Destination:          RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.435ns (Levels of Logic = 0)
  Clock Path Skew:      -0.005ns (0.104 - 0.109)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 33.340ns
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 33.340ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_2 to RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X5Y59.AQ       Tcko                  0.198   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA_2
    SLICE_X6Y57.D4       net (fanout=12)       0.365   RLINK/FX2CNTL/RXFIFO/GCW/GRAY_5.CNT/R_DATA<2>
    SLICE_X6Y57.CLK      Tah         (-Th)     0.128   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    -------------------------------------------------  ---------------------------
    Total                                      0.435ns (0.070ns logic, 0.365ns route)
                                                       (16.1% logic, 83.9% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_I_FX2_IFCLK = PERIOD TIMEGRP "I_FX2_IFCLK" 33.34 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 30.674ns (period - min period limit)
  Period: 33.340ns
  Min period limit: 2.666ns (375.094MHz) (Tbcper_I)
  Physical resource: I_FX2_IFCLK_BUFGP/BUFG/I0
  Logical resource: I_FX2_IFCLK_BUFGP/BUFG/I0
  Location pin: BUFGMUX_X2Y9.I0
  Clock network: I_FX2_IFCLK_BUFGP/IBUFG
--------------------------------------------------------------------------------
Slack: 31.091ns (period - min period limit)
  Period: 33.340ns
  Min period limit: 2.249ns (444.642MHz) (Tockper)
  Physical resource: RLINK/FX2CNTL/IOB_FX2_SLOE/IOB/R_DO/CLK0
  Logical resource: RLINK/FX2CNTL/IOB_FX2_SLOE/IOB/R_DO_0/CK0
  Location pin: OLOGIC_X0Y45.CLK0
  Clock network: I_FX2_IFCLK_BUFGP
--------------------------------------------------------------------------------
Slack: 31.091ns (period - min period limit)
  Period: 33.340ns
  Min period limit: 2.249ns (444.642MHz) (Tockper)
  Physical resource: RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO/CLK0
  Logical resource: RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0/CK0
  Location pin: OLOGIC_X0Y61.CLK0
  Clock network: I_FX2_IFCLK_BUFGP
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_GEN_CLKSYS_USEDCM_CLKOUT0 = PERIOD TIMEGRP 
"GEN_CLKSYS_USEDCM_CLKOUT0"         TS_I_CLK100 / 0.68 HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 12817577 paths analyzed, 13405 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is  14.472ns.
--------------------------------------------------------------------------------
Slack (setup path):     0.233ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SYS70/W11A/SEQ/R_STATE_4_1 (FF)
  Destination:          SYS70/W11A/DPATH/MUNIT/Mmult_proc_omux.prod (DSP)
  Requirement:          14.705ns
  Data Path Delay:      14.203ns (Levels of Logic = 8)
  Clock Path Skew:      0.013ns (0.447 - 0.434)
  Source Clock:         CLK rising at 0.000ns
  Destination Clock:    CLK rising at 14.705ns
  Clock Uncertainty:    0.282ns

  Clock Uncertainty:          0.282ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: SYS70/W11A/SEQ/R_STATE_4_1 to SYS70/W11A/DPATH/MUNIT/Mmult_proc_omux.prod
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y9.BQ       Tcko                  0.476   SYS70/W11A/SEQ/R_STATE_4_1
                                                       SYS70/W11A/SEQ/R_STATE_4_1
    SLICE_X15Y5.A5       net (fanout=6)        0.931   SYS70/W11A/SEQ/R_STATE_4_1
    SLICE_X15Y5.A        Tilo                  0.259   SYS70/W11A/DPATH/GPR/WE1
                                                       SYS70/W11A/SEQ/_n2298_inv41_1
    SLICE_X15Y5.B4       net (fanout=6)        0.569   SYS70/W11A/SEQ/_n2298_inv41
    SLICE_X15Y5.B        Tilo                  0.259   SYS70/W11A/DPATH/GPR/WE1
                                                       SYS70/W11A/SEQ/_n6576<6>1
    SLICE_X17Y14.C2      net (fanout=8)        2.177   SYS70/W11A/SEQ/_n6576
    SLICE_X17Y14.C       Tilo                  0.259   SYS70/W11A/VMBOX/R_REGS_kstack
                                                       SYS70/W11A/SEQ/_n5001<6>2
    SLICE_X13Y12.A2      net (fanout=1)        1.465   SYS70/W11A/SEQ/_n5001<6>2
    SLICE_X13Y12.A       Tilo                  0.259   N1137
                                                       SYS70/W11A/SEQ/_n5001<6>3
    SLICE_X9Y14.B2       net (fanout=8)        1.282   SYS70/W11A/SEQ/_n5001
    SLICE_X9Y14.B        Tilo                  0.259   SYS70/W11A/DP_CNTL_dres_sel<2>
                                                       SYS70/W11A/SEQ/Mmux_proc_next.ndpcntl_dres_sel42
    SLICE_X7Y21.D6       net (fanout=59)       1.551   SYS70/W11A/DP_CNTL_dres_sel<1>
    SLICE_X7Y21.D        Tilo                  0.259   N1082
                                                       SYS70/W11A/DPATH/Mmux_DRES54_SW1
    SLICE_X6Y16.A3       net (fanout=1)        1.260   N1082
    SLICE_X6Y16.A        Tilo                  0.254   SYS70/W11A/DPATH/R_CPDOUT<15>
                                                       SYS70/W11A/DPATH/Mmux_DRES55
    SLICE_X5Y19.B2       net (fanout=4)        1.713   SYS70/W11A/VM_DIN<13>
    SLICE_X5Y19.B        Tilo                  0.259   SYS70/W11A/DPATH/R_DDST<15>
                                                       SYS70/W11A/DPATH/Mmux_DRES[15]_GPR_DDST[15]_mux_6_OUT51
    DSP48_X0Y4.A13       net (fanout=1)        0.551   SYS70/W11A/DPATH/DRES[15]_GPR_DDST[15]_mux_6_OUT<13>
    DSP48_X0Y4.CLK       Tdspdck_A_A1REG       0.161   SYS70/W11A/DPATH/MUNIT/Mmult_proc_omux.prod
                                                       SYS70/W11A/DPATH/MUNIT/Mmult_proc_omux.prod
    -------------------------------------------------  ---------------------------
    Total                                     14.203ns (2.704ns logic, 11.499ns route)
                                                       (19.0% logic, 81.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.257ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SYS70/W11A/SEQ/R_STATE_4_1 (FF)
  Destination:          SYS70/W11A/DPATH/MUNIT/Mmult_proc_omux.prod (DSP)
  Requirement:          14.705ns
  Data Path Delay:      14.179ns (Levels of Logic = 8)
  Clock Path Skew:      0.013ns (0.447 - 0.434)
  Source Clock:         CLK rising at 0.000ns
  Destination Clock:    CLK rising at 14.705ns
  Clock Uncertainty:    0.282ns

  Clock Uncertainty:          0.282ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: SYS70/W11A/SEQ/R_STATE_4_1 to SYS70/W11A/DPATH/MUNIT/Mmult_proc_omux.prod
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X16Y9.BQ       Tcko                  0.476   SYS70/W11A/SEQ/R_STATE_4_1
                                                       SYS70/W11A/SEQ/R_STATE_4_1
    SLICE_X15Y5.A5       net (fanout=6)        0.931   SYS70/W11A/SEQ/R_STATE_4_1
    SLICE_X15Y5.A        Tilo                  0.259   SYS70/W11A/DPATH/GPR/WE1
                                                       SYS70/W11A/SEQ/_n2298_inv41_1
    SLICE_X15Y5.B4       net (fanout=6)        0.569   SYS70/W11A/SEQ/_n2298_inv41
    SLICE_X15Y5.B        Tilo                  0.259   SYS70/W11A/DPATH/GPR/WE1
                                                       SYS70/W11A/SEQ/_n6576<6>1
    SLICE_X17Y14.C2      net (fanout=8)        2.177   SYS70/W11A/SEQ/_n6576
    SLICE_X17Y14.C       Tilo                  0.259   SYS70/W11A/VMBOX/R_REGS_kstack
                                                       SYS70/W11A/SEQ/_n5001<6>2
    SLICE_X13Y12.A2      net (fanout=1)        1.465   SYS70/W11A/SEQ/_n5001<6>2
    SLICE_X13Y12.A       Tilo                  0.259   N1137
                                                       SYS70/W11A/SEQ/_n5001<6>3
    SLICE_X9Y14.B2       net (fanout=8)        1.282   SYS70/W11A/SEQ/_n5001
    SLICE_X9Y14.B        Tilo                  0.259   SYS70/W11A/DP_CNTL_dres_sel<2>
                                                       SYS70/W11A/SEQ/Mmux_proc_next.ndpcntl_dres_sel42
    SLICE_X6Y24.A1       net (fanout=59)       1.986   SYS70/W11A/DP_CNTL_dres_sel<1>
    SLICE_X6Y24.A        Tilo                  0.254   SYS70/W11A/VMBOX/MMU/SARSDR_saf<4>
                                                       SYS70/W11A/DPATH/Mmux_DRES54_SW0
    SLICE_X6Y16.A6       net (fanout=1)        0.806   N1081
    SLICE_X6Y16.A        Tilo                  0.254   SYS70/W11A/DPATH/R_CPDOUT<15>
                                                       SYS70/W11A/DPATH/Mmux_DRES55
    SLICE_X5Y19.B2       net (fanout=4)        1.713   SYS70/W11A/VM_DIN<13>
    SLICE_X5Y19.B        Tilo                  0.259   SYS70/W11A/DPATH/R_DDST<15>
                                                       SYS70/W11A/DPATH/Mmux_DRES[15]_GPR_DDST[15]_mux_6_OUT51
    DSP48_X0Y4.A13       net (fanout=1)        0.551   SYS70/W11A/DPATH/DRES[15]_GPR_DDST[15]_mux_6_OUT<13>
    DSP48_X0Y4.CLK       Tdspdck_A_A1REG       0.161   SYS70/W11A/DPATH/MUNIT/Mmult_proc_omux.prod
                                                       SYS70/W11A/DPATH/MUNIT/Mmult_proc_omux.prod
    -------------------------------------------------  ---------------------------
    Total                                     14.179ns (2.699ns logic, 11.480ns route)
                                                       (19.0% logic, 81.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     0.282ns (requirement - (data path - clock path skew + uncertainty))
  Source:               SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Destination:          SYS70/W11A/DPATH/MUNIT/Mmult_proc_omux.prod (DSP)
  Requirement:          14.705ns
  Data Path Delay:      14.115ns (Levels of Logic = 9)
  Clock Path Skew:      -0.026ns (0.327 - 0.353)
  Source Clock:         CLK rising at 0.000ns
  Destination Clock:    CLK rising at 14.705ns
  Clock Uncertainty:    0.282ns

  Clock Uncertainty:          0.282ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM to SYS70/W11A/DPATH/MUNIT/Mmult_proc_omux.prod
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB16_X0Y10.DOA2    Trcko_DOA             2.100   SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM
                                                       SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM
    SLICE_X11Y6.B3       net (fanout=2)        2.807   SYS70/CACHE/CMEM_DOA_1<2>
    SLICE_X11Y6.B        Tilo                  0.259   SYS70/W11A/DPATH/R_IREG<0>
                                                       SYS70/W11A/VMBOX/Mmux_proc_next.ivm_dout11
    SLICE_X11Y6.A3       net (fanout=2)        1.352   SYS70/W11A/VMBOX/Mmux_proc_next.ivm_dout1
    SLICE_X11Y6.A        Tilo                  0.259   SYS70/W11A/DPATH/R_IREG<0>
                                                       SYS70/W11A/VMBOX/Mmux_proc_next.ivm_dout<0>123
    SLICE_X12Y8.A4       net (fanout=4)        0.748   SYS70/W11A/VM_DOUT<2>
    SLICE_X12Y8.AMUX     Tilo                  0.298   SYS70/W11A/DPATH/OUNIT/ma<1>_mand
                                                       SYS70/W11A/DPATH/OUNIT/Mmux_mb91_SW1
    SLICE_X12Y9.C1       net (fanout=1)        0.833   N800
    SLICE_X12Y9.COUT     Topcyc                0.325   SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<3>
                                                       SYS70/W11A/DPATH/OUNIT/Maddsub_sum_lut<2>
                                                       SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<3>
    SLICE_X12Y10.CIN     net (fanout=1)        0.003   SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<3>
    SLICE_X12Y10.COUT    Tbyp                  0.091   SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<7>
                                                       SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<7>
    SLICE_X12Y11.CIN     net (fanout=1)        0.003   SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<7>
    SLICE_X12Y11.BMUX    Tcinb                 0.277   SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<11>
                                                       SYS70/W11A/DPATH/OUNIT/Maddsub_sum_cy<11>
    SLICE_X7Y17.B6       net (fanout=2)        1.166   SYS70/W11A/DPATH/OUNIT_DOUT<9>
    SLICE_X7Y17.B        Tilo                  0.259   SYS70/CACHE/R_REGS_di<11>
                                                       SYS70/W11A/DPATH/Mmux_DRES164
    SLICE_X6Y14.A5       net (fanout=4)        0.665   SYS70/W11A/DPATH/Mmux_DRES163
    SLICE_X6Y14.A        Tilo                  0.254   SYS70/W11A/DPATH/R_CPDOUT<10>
                                                       SYS70/W11A/DPATH/Mmux_DRES165
    SLICE_X7Y19.C6       net (fanout=4)        1.649   SYS70/W11A/VM_DIN<9>
    SLICE_X7Y19.C        Tilo                  0.259   SYS70/W11A/DPATH/R_DDST<11>
                                                       SYS70/W11A/DPATH/Mmux_DRES[15]_GPR_DDST[15]_mux_6_OUT161
    DSP48_X0Y4.A9        net (fanout=1)        0.347   SYS70/W11A/DPATH/DRES[15]_GPR_DDST[15]_mux_6_OUT<9>
    DSP48_X0Y4.CLK       Tdspdck_A_A1REG       0.161   SYS70/W11A/DPATH/MUNIT/Mmult_proc_omux.prod
                                                       SYS70/W11A/DPATH/MUNIT/Mmult_proc_omux.prod
    -------------------------------------------------  ---------------------------
    Total                                     14.115ns (4.542ns logic, 9.573ns route)
                                                       (32.2% logic, 67.8% route)

--------------------------------------------------------------------------------

Hold Paths: TS_GEN_CLKSYS_USEDCM_CLKOUT0 = PERIOD TIMEGRP "GEN_CLKSYS_USEDCM_CLKOUT0"
        TS_I_CLK100 / 0.68 HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.227ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/SERPORT/XONRX/R_REGS_rxdata_3 (FF)
  Destination:          RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[3].MEM1/SP (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.229ns (Levels of Logic = 0)
  Clock Path Skew:      0.002ns (0.042 - 0.040)
  Source Clock:         CLK rising at 0.000ns
  Destination Clock:    CLK rising at 0.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: RLINK/SERPORT/XONRX/R_REGS_rxdata_3 to RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[3].MEM1/SP
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X19Y51.DQ      Tcko                  0.198   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
                                                       RLINK/SERPORT/XONRX/R_REGS_rxdata_3
    SLICE_X18Y51.DI      net (fanout=4)        0.033   RLINK/SERPORT/XONRX/R_REGS_rxdata<3>
    SLICE_X18Y51.CLK     Tdh         (-Th)     0.002   RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[3].MEM1/SP
    -------------------------------------------------  ---------------------------
    Total                                      0.229ns (0.196ns logic, 0.033ns route)
                                                       (85.6% logic, 14.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.263ns (requirement - (clock path skew + uncertainty - data path))
  Source:               SYS70/IBMON.I0/R_REGS_ibaddr_8 (FF)
  Destination:          SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.270ns (Levels of Logic = 0)
  Clock Path Skew:      0.007ns (0.125 - 0.118)
  Source Clock:         CLK rising at 0.000ns
  Destination Clock:    CLK rising at 0.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: SYS70/IBMON.I0/R_REGS_ibaddr_8 to SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X33Y28.DQ      Tcko                  0.198   SYS70/IBMON.I0/R_REGS_ibaddr_8
                                                       SYS70/IBMON.I0/R_REGS_ibaddr_8
    RAMB16_X1Y14.DIA8    net (fanout=1)        0.125   SYS70/IBMON.I0/R_REGS_ibaddr_8
    RAMB16_X1Y14.CLKA    Trckd_DIA   (-Th)     0.053   SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
                                                       SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
    -------------------------------------------------  ---------------------------
    Total                                      0.270ns (0.145ns logic, 0.125ns route)
                                                       (53.7% logic, 46.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.265ns (requirement - (clock path skew + uncertainty - data path))
  Source:               SYS70/IBMON.I0/R_REGS_ibaddr_2 (FF)
  Destination:          SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.272ns (Levels of Logic = 0)
  Clock Path Skew:      0.007ns (0.125 - 0.118)
  Source Clock:         CLK rising at 0.000ns
  Destination Clock:    CLK rising at 0.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: SYS70/IBMON.I0/R_REGS_ibaddr_2 to SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X32Y28.BQ      Tcko                  0.200   SYS70/IBMON.I0/R_REGS_ibaddr_4
                                                       SYS70/IBMON.I0/R_REGS_ibaddr_2
    RAMB16_X1Y14.DIA2    net (fanout=1)        0.125   SYS70/IBMON.I0/R_REGS_ibaddr_2
    RAMB16_X1Y14.CLKA    Trckd_DIA   (-Th)     0.053   SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
                                                       SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
    -------------------------------------------------  ---------------------------
    Total                                      0.272ns (0.147ns logic, 0.125ns route)
                                                       (54.0% logic, 46.0% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_GEN_CLKSYS_USEDCM_CLKOUT0 = PERIOD TIMEGRP "GEN_CLKSYS_USEDCM_CLKOUT0"
        TS_I_CLK100 / 0.68 HIGH 50%;
--------------------------------------------------------------------------------
Slack: 11.135ns (period - min period limit)
  Period: 14.705ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM/CLKA
  Logical resource: SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM/CLKA
  Location pin: RAMB16_X0Y10.CLKA
  Clock network: CLK
--------------------------------------------------------------------------------
Slack: 11.135ns (period - min period limit)
  Period: 14.705ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKB(Fmax))
  Physical resource: SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM/CLKB
  Logical resource: SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM/CLKB
  Location pin: RAMB16_X0Y10.CLKB
  Clock network: CLK
--------------------------------------------------------------------------------
Slack: 11.135ns (period - min period limit)
  Period: 14.705ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/CLKA
  Logical resource: SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM/CLKA
  Location pin: RAMB16_X0Y12.CLKA
  Clock network: CLK
--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = IN 10 ns BEFORE COMP "I_CLK100";
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 32 paths analyzed, 32 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Offset is  -0.522ns.
--------------------------------------------------------------------------------
Slack (setup path):     10.522ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               IO_MEM_DATA<14> (PAD)
  Destination:          SRAM_CTL/IOB_MEM_DATA/R_DI_14 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      1.834ns (Levels of Logic = 2)
  Clock Path Delay:     2.778ns (Levels of Logic = 4)
  Clock Uncertainty:    0.422ns

  Clock Uncertainty:          0.422ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Fast Process Corner: IO_MEM_DATA<14> to SRAM_CTL/IOB_MEM_DATA/R_DI_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R8.I                 Tiopi                 0.887   IO_MEM_DATA<14>
                                                       IO_MEM_DATA<14>
                                                       IO_MEM_DATA_14_IOBUF/IBUF
                                                       ProtoComp1909.IMUX.14
    ILOGIC_X8Y1.D        net (fanout=1)        0.190   N616
    ILOGIC_X8Y1.CLK0     Tidock                0.757   SRAM_CTL/IOB_MEM_DATA/R_DI<14>
                                                       ProtoComp1914.D2OFFBYP_SRC.14
                                                       SRAM_CTL/IOB_MEM_DATA/R_DI_14
    -------------------------------------------------  ---------------------------
    Total                                      1.834ns (1.644ns logic, 0.190ns route)
                                                       (89.6% logic, 10.4% route)

  Minimum Clock Path at Fast Process Corner: I_CLK100 to SRAM_CTL/IOB_MEM_DATA/R_DI_14
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X8Y1.CLK0     net (fanout=1029)     0.646   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.778ns (1.274ns logic, 1.504ns route)
                                                       (45.9% logic, 54.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     10.527ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               I_SWI<3> (PAD)
  Destination:          HIO/HIO/HIO/IOB_SWI/R_DI_3 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      1.834ns (Levels of Logic = 2)
  Clock Path Delay:     2.783ns (Levels of Logic = 4)
  Clock Uncertainty:    0.422ns

  Clock Uncertainty:          0.422ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Fast Process Corner: I_SWI<3> to HIO/HIO/HIO/IOB_SWI/R_DI_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    M8.I                 Tiopi                 0.887   I_SWI<3>
                                                       I_SWI<3>
                                                       I_SWI_3_IBUF
                                                       ProtoComp1910.IMUX.3
    ILOGIC_X7Y1.D        net (fanout=1)        0.190   I_SWI_3_IBUF
    ILOGIC_X7Y1.CLK0     Tidock                0.757   HIO/HIO/HIO/IOB_SWI/R_DI<3>
                                                       ProtoComp1914.D2OFFBYP_SRC.19
                                                       HIO/HIO/HIO/IOB_SWI/R_DI_3
    -------------------------------------------------  ---------------------------
    Total                                      1.834ns (1.644ns logic, 0.190ns route)
                                                       (89.6% logic, 10.4% route)

  Minimum Clock Path at Fast Process Corner: I_CLK100 to HIO/HIO/HIO/IOB_SWI/R_DI_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X7Y1.CLK0     net (fanout=1029)     0.651   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.783ns (1.274ns logic, 1.509ns route)
                                                       (45.8% logic, 54.2% route)

--------------------------------------------------------------------------------
Slack (setup path):     10.550ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               I_SWI<0> (PAD)
  Destination:          HIO/HIO/HIO/IOB_SWI/R_DI_0 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      1.803ns (Levels of Logic = 2)
  Clock Path Delay:     2.775ns (Levels of Logic = 4)
  Clock Uncertainty:    0.422ns

  Clock Uncertainty:          0.422ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Fast Process Corner: I_SWI<0> to HIO/HIO/HIO/IOB_SWI/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T10.I                Tiopi                 0.887   I_SWI<0>
                                                       I_SWI<0>
                                                       I_SWI_0_IBUF
                                                       ProtoComp1910.IMUX
    ILOGIC_X9Y0.D        net (fanout=1)        0.159   I_SWI_0_IBUF
    ILOGIC_X9Y0.CLK0     Tidock                0.757   HIO/HIO/HIO/IOB_SWI/R_DI<0>
                                                       ProtoComp1914.D2OFFBYP_SRC.16
                                                       HIO/HIO/HIO/IOB_SWI/R_DI_0
    -------------------------------------------------  ---------------------------
    Total                                      1.803ns (1.644ns logic, 0.159ns route)
                                                       (91.2% logic, 8.8% route)

  Minimum Clock Path at Fast Process Corner: I_CLK100 to HIO/HIO/HIO/IOB_SWI/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X9Y0.CLK0     net (fanout=1029)     0.643   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.775ns (1.274ns logic, 1.501ns route)
                                                       (45.9% logic, 54.1% route)

--------------------------------------------------------------------------------

Hold Paths: OFFSET = IN 10 ns BEFORE COMP "I_CLK100";
--------------------------------------------------------------------------------
Offset (hold paths):    -3.999ns (data path - clock path + uncertainty)
  Source:               I_BTN<0> (PAD)
  Destination:          HIO/HIO/HIO/IOB_BTN/R_DI_0 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Data Path Delay:      2.445ns (Levels of Logic = 2)
  Clock Path Delay:     6.866ns (Levels of Logic = 4)
  Clock Uncertainty:    0.422ns

  Clock Uncertainty:          0.422ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Slow Process Corner: I_BTN<0> to HIO/HIO/HIO/IOB_BTN/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    A8.I                 Tiopi                 0.902   I_BTN<0>
                                                       I_BTN<0>
                                                       I_BTN_0_IBUF
                                                       ProtoComp1910.IMUX.14
    ILOGIC_X7Y60.D       net (fanout=1)        0.164   I_BTN_0_IBUF
    ILOGIC_X7Y60.CLK0    Tiockd      (-Th)    -1.379   HIO/HIO/HIO/IOB_BTN/R_DI<0>
                                                       ProtoComp1914.D2OFFBYP_SRC.25
                                                       HIO/HIO/HIO/IOB_BTN/R_DI_0
    -------------------------------------------------  ---------------------------
    Total                                      2.445ns (2.281ns logic, 0.164ns route)
                                                       (93.3% logic, 6.7% route)

  Maximum Clock Path at Slow Process Corner: I_CLK100 to HIO/HIO/HIO/IOB_BTN/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X7Y60.CLK0    net (fanout=1029)     1.732   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.866ns (2.356ns logic, 4.510ns route)
                                                       (34.3% logic, 65.7% route)

--------------------------------------------------------------------------------
Offset (hold paths):    -3.978ns (data path - clock path + uncertainty)
  Source:               I_BTN<3> (PAD)
  Destination:          HIO/HIO/HIO/IOB_BTN/R_DI_3 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Data Path Delay:      2.506ns (Levels of Logic = 2)
  Clock Path Delay:     6.906ns (Levels of Logic = 4)
  Clock Uncertainty:    0.422ns

  Clock Uncertainty:          0.422ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Slow Process Corner: I_BTN<3> to HIO/HIO/HIO/IOB_BTN/R_DI_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    C4.I                 Tiopi                 0.902   I_BTN<3>
                                                       I_BTN<3>
                                                       I_BTN_3_IBUF
                                                       ProtoComp1910.IMUX.17
    ILOGIC_X1Y62.D       net (fanout=1)        0.225   I_BTN_3_IBUF
    ILOGIC_X1Y62.CLK0    Tiockd      (-Th)    -1.379   HIO/HIO/HIO/IOB_BTN/R_DI<3>
                                                       ProtoComp1914.D2OFFBYP_SRC.28
                                                       HIO/HIO/HIO/IOB_BTN/R_DI_3
    -------------------------------------------------  ---------------------------
    Total                                      2.506ns (2.281ns logic, 0.225ns route)
                                                       (91.0% logic, 9.0% route)

  Maximum Clock Path at Slow Process Corner: I_CLK100 to HIO/HIO/HIO/IOB_BTN/R_DI_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X1Y62.CLK0    net (fanout=1029)     1.772   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.906ns (2.356ns logic, 4.550ns route)
                                                       (34.1% logic, 65.9% route)

--------------------------------------------------------------------------------
Offset (hold paths):    -3.933ns (data path - clock path + uncertainty)
  Source:               I_BTN<4> (PAD)
  Destination:          HIO/HIO/HIO/IOB_BTN/R_DI_4 (FF)
  Destination Clock:    CLK rising at 0.000ns
  Data Path Delay:      2.511ns (Levels of Logic = 2)
  Clock Path Delay:     6.866ns (Levels of Logic = 4)
  Clock Uncertainty:    0.422ns

  Clock Uncertainty:          0.422ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Slow Process Corner: I_BTN<4> to HIO/HIO/HIO/IOB_BTN/R_DI_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 0.902   I_BTN<4>
                                                       I_BTN<4>
                                                       I_BTN_4_IBUF
                                                       ProtoComp1910.IMUX.18
    ILOGIC_X7Y61.D       net (fanout=1)        0.230   I_BTN_4_IBUF
    ILOGIC_X7Y61.CLK0    Tiockd      (-Th)    -1.379   HIO/HIO/HIO/IOB_BTN/R_DI<4>
                                                       ProtoComp1914.D2OFFBYP_SRC.29
                                                       HIO/HIO/HIO/IOB_BTN/R_DI_4
    -------------------------------------------------  ---------------------------
    Total                                      2.511ns (2.281ns logic, 0.230ns route)
                                                       (90.8% logic, 9.2% route)

  Maximum Clock Path at Slow Process Corner: I_CLK100 to HIO/HIO/HIO/IOB_BTN/R_DI_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    ILOGIC_X7Y61.CLK0    net (fanout=1029)     1.732   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.866ns (2.356ns logic, 4.510ns route)
                                                       (34.3% logic, 65.7% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = OUT 20 ns AFTER COMP "I_CLK100";
For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612).

 81 paths analyzed, 65 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
 Minimum allowable offset is  18.043ns.
--------------------------------------------------------------------------------
Slack (slowest paths):  1.957ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               SRAM_CTL/IOB_MEM_WE/IOB/R_DO_0 (FF)
  Destination:          O_MEM_WE_N (PAD)
  Source Clock:         CLK falling at 7.352ns
  Requirement:          20.000ns
  Data Path Delay:      3.371ns (Levels of Logic = 1)
  Clock Path Delay:     6.898ns (Levels of Logic = 4)
  Clock Uncertainty:    0.422ns

  Clock Uncertainty:          0.422ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Clock Path at Slow Process Corner: I_CLK100 to SRAM_CTL/IOB_MEM_WE/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    OLOGIC_X18Y21.CLK0   net (fanout=1029)     1.764   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.898ns (2.356ns logic, 4.542ns route)
                                                       (34.2% logic, 65.8% route)

  Maximum Data Path at Slow Process Corner: SRAM_CTL/IOB_MEM_WE/IOB/R_DO_0 to O_MEM_WE_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X18Y21.OQ     Tockq                 1.080   SRAM_CTL/IOB_MEM_WE/IOB/R_DO
                                                       SRAM_CTL/IOB_MEM_WE/IOB/R_DO_0
    M16.O                net (fanout=1)        0.309   SRAM_CTL/IOB_MEM_WE/IOB/R_DO
    M16.PAD              Tioop                 1.982   O_MEM_WE_N
                                                       O_MEM_WE_N_OBUF
                                                       O_MEM_WE_N
    -------------------------------------------------  ---------------------------
    Total                                      3.371ns (3.062ns logic, 0.309ns route)
                                                       (90.8% logic, 9.2% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  7.985ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               IOB_RS232/P1/IOB_TXD/IOB/R_DO_0 (FF)
  Destination:          O_FUSP_TXD (PAD)
  Source Clock:         CLK rising at 0.000ns
  Requirement:          20.000ns
  Data Path Delay:      4.702ns (Levels of Logic = 1)
  Clock Path Delay:     6.891ns (Levels of Logic = 4)
  Clock Uncertainty:    0.422ns

  Clock Uncertainty:          0.422ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Clock Path at Slow Process Corner: I_CLK100 to IOB_RS232/P1/IOB_TXD/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    OLOGIC_X0Y24.CLK0    net (fanout=1029)     1.757   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.891ns (2.356ns logic, 4.535ns route)
                                                       (34.2% logic, 65.8% route)

  Maximum Data Path at Slow Process Corner: IOB_RS232/P1/IOB_TXD/IOB/R_DO_0 to O_FUSP_TXD
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X0Y24.OQ      Tockq                 1.080   IOB_RS232/P1/IOB_TXD/IOB/R_DO
                                                       IOB_RS232/P1/IOB_TXD/IOB/R_DO_0
    L3.O                 net (fanout=1)        0.310   IOB_RS232/P1/IOB_TXD/IOB/R_DO
    L3.PAD               Tioop                 3.312   O_FUSP_TXD
                                                       O_FUSP_TXD_OBUF
                                                       O_FUSP_TXD
    -------------------------------------------------  ---------------------------
    Total                                      4.702ns (4.392ns logic, 0.310ns route)
                                                       (93.4% logic, 6.6% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  7.989ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               IOB_RS232/P1/IOB_RTS/IOB/R_DO_0 (FF)
  Destination:          O_FUSP_RTS_N (PAD)
  Source Clock:         CLK rising at 0.000ns
  Requirement:          20.000ns
  Data Path Delay:      4.702ns (Levels of Logic = 1)
  Clock Path Delay:     6.887ns (Levels of Logic = 4)
  Clock Uncertainty:    0.422ns

  Clock Uncertainty:          0.422ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Clock Path at Slow Process Corner: I_CLK100 to IOB_RS232/P1/IOB_RTS/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    OLOGIC_X0Y23.CLK0    net (fanout=1029)     1.753   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.887ns (2.356ns logic, 4.531ns route)
                                                       (34.2% logic, 65.8% route)

  Maximum Data Path at Slow Process Corner: IOB_RS232/P1/IOB_RTS/IOB/R_DO_0 to O_FUSP_RTS_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X0Y23.OQ      Tockq                 1.080   IOB_RS232/P1/IOB_RTS/IOB/R_DO
                                                       IOB_RS232/P1/IOB_RTS/IOB/R_DO_0
    K2.O                 net (fanout=1)        0.310   IOB_RS232/P1/IOB_RTS/IOB/R_DO
    K2.PAD               Tioop                 3.312   O_FUSP_RTS_N
                                                       O_FUSP_RTS_N_OBUF
                                                       O_FUSP_RTS_N
    -------------------------------------------------  ---------------------------
    Total                                      4.702ns (4.392ns logic, 0.310ns route)
                                                       (93.4% logic, 6.6% route)

--------------------------------------------------------------------------------

Fastest Paths: OFFSET = OUT 20 ns AFTER COMP "I_CLK100";
--------------------------------------------------------------------------------
Delay (fastest paths):  3.622ns (clock arrival + clock path + data path - uncertainty)
  Source:               SRAM_CTL/IOB_MEM_BE/R_DO_1 (FF)
  Destination:          O_MEM_BE_N<1> (PAD)
  Source Clock:         CLK rising at 0.000ns
  Data Path Delay:      1.225ns (Levels of Logic = 1)
  Clock Path Delay:     2.819ns (Levels of Logic = 4)
  Clock Uncertainty:    0.422ns

  Clock Uncertainty:          0.422ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Clock Path at Fast Process Corner: I_CLK100 to SRAM_CTL/IOB_MEM_BE/R_DO_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    OLOGIC_X18Y33.CLK0   net (fanout=1029)     0.687   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.819ns (1.274ns logic, 1.545ns route)
                                                       (45.2% logic, 54.8% route)

  Minimum Data Path at Fast Process Corner: SRAM_CTL/IOB_MEM_BE/R_DO_1 to O_MEM_BE_N<1>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X18Y33.OQ     Tockq                 0.336   SRAM_CTL/IOB_MEM_BE/R_DO<1>
                                                       SRAM_CTL/IOB_MEM_BE/R_DO_1
    K15.O                net (fanout=1)        0.190   SRAM_CTL/IOB_MEM_BE/R_DO<1>
    K15.PAD              Tioop                 0.699   O_MEM_BE_N<1>
                                                       O_MEM_BE_N_1_OBUF
                                                       O_MEM_BE_N<1>
    -------------------------------------------------  ---------------------------
    Total                                      1.225ns (1.035ns logic, 0.190ns route)
                                                       (84.5% logic, 15.5% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  3.622ns (clock arrival + clock path + data path - uncertainty)
  Source:               SRAM_CTL/IOB_MEM_BE/R_DO_0 (FF)
  Destination:          O_MEM_BE_N<0> (PAD)
  Source Clock:         CLK rising at 0.000ns
  Data Path Delay:      1.225ns (Levels of Logic = 1)
  Clock Path Delay:     2.819ns (Levels of Logic = 4)
  Clock Uncertainty:    0.422ns

  Clock Uncertainty:          0.422ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Clock Path at Fast Process Corner: I_CLK100 to SRAM_CTL/IOB_MEM_BE/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    OLOGIC_X18Y32.CLK0   net (fanout=1029)     0.687   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.819ns (1.274ns logic, 1.545ns route)
                                                       (45.2% logic, 54.8% route)

  Minimum Data Path at Fast Process Corner: SRAM_CTL/IOB_MEM_BE/R_DO_0 to O_MEM_BE_N<0>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X18Y32.OQ     Tockq                 0.336   SRAM_CTL/IOB_MEM_BE/R_DO<0>
                                                       SRAM_CTL/IOB_MEM_BE/R_DO_0
    K16.O                net (fanout=1)        0.190   SRAM_CTL/IOB_MEM_BE/R_DO<0>
    K16.PAD              Tioop                 0.699   O_MEM_BE_N<0>
                                                       O_MEM_BE_N_0_OBUF
                                                       O_MEM_BE_N<0>
    -------------------------------------------------  ---------------------------
    Total                                      1.225ns (1.035ns logic, 0.190ns route)
                                                       (84.5% logic, 15.5% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  3.611ns (clock arrival + clock path + data path - uncertainty)
  Source:               SRAM_CTL/IOB_MEM_OE/IOB/R_DO_0 (FF)
  Destination:          O_MEM_OE_N (PAD)
  Source Clock:         CLK rising at 0.000ns
  Data Path Delay:      1.225ns (Levels of Logic = 1)
  Clock Path Delay:     2.808ns (Levels of Logic = 4)
  Clock Uncertainty:    0.422ns

  Clock Uncertainty:          0.422ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Clock Path at Fast Process Corner: I_CLK100 to SRAM_CTL/IOB_MEM_OE/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 0.763   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.253   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.122   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        0.342   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.330   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.263   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.059   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    OLOGIC_X18Y22.CLK0   net (fanout=1029)     0.676   CLK
    -------------------------------------------------  ---------------------------
    Total                                      2.808ns (1.274ns logic, 1.534ns route)
                                                       (45.4% logic, 54.6% route)

  Minimum Data Path at Fast Process Corner: SRAM_CTL/IOB_MEM_OE/IOB/R_DO_0 to O_MEM_OE_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X18Y22.OQ     Tockq                 0.336   SRAM_CTL/IOB_MEM_OE/IOB/R_DO
                                                       SRAM_CTL/IOB_MEM_OE/IOB/R_DO_0
    L18.O                net (fanout=1)        0.190   SRAM_CTL/IOB_MEM_OE/IOB/R_DO
    L18.PAD              Tioop                 0.699   O_MEM_OE_N
                                                       O_MEM_OE_N_OBUF
                                                       O_MEM_OE_N
    -------------------------------------------------  ---------------------------
    Total                                      1.225ns (1.035ns logic, 0.190ns route)
                                                       (84.5% logic, 15.5% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = IN 2 ns VALID 33 ns BEFORE COMP "I_FX2_IFCLK";
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 11 paths analyzed, 11 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   0.982ns.
--------------------------------------------------------------------------------
Slack (setup path):     1.018ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               IO_FX2_DATA<4> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          2.000ns
  Data Path Delay:      4.724ns (Levels of Logic = 3)
  Clock Path Delay:     3.767ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: IO_FX2_DATA<4> to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    D1.I                 Tiopi                 1.557   IO_FX2_DATA<4>
                                                       IO_FX2_DATA<4>
                                                       IO_FX2_DATA_4_IOBUF/IBUF
                                                       ProtoComp1909.IMUX.20
    IODELAY_X0Y50.IDATAINnet (fanout=1)        0.168   N634
    IODELAY_X0Y50.DATAOUTTioddo_IDATAIN        2.460   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4_ML_IODELAY2
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4_ML_IODELAY2
    ILOGIC_X0Y50.DDLY    net (fanout=1)        0.007   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4_ML_IODELAY2_SIG_ML
    ILOGIC_X0Y50.CLK0    Tidockd               0.532   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI<4>
                                                       ProtoComp1921.D2OFFBYP_SRC.7
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4
    -------------------------------------------------  ---------------------------
    Total                                      4.724ns (4.549ns logic, 0.175ns route)
                                                       (96.3% logic, 3.7% route)

  Minimum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.344   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.855   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.197   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y50.CLK0    net (fanout=49)       1.371   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.767ns (1.541ns logic, 2.226ns route)
                                                       (40.9% logic, 59.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.018ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               IO_FX2_DATA<3> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          2.000ns
  Data Path Delay:      4.724ns (Levels of Logic = 3)
  Clock Path Delay:     3.767ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: IO_FX2_DATA<3> to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    D2.I                 Tiopi                 1.557   IO_FX2_DATA<3>
                                                       IO_FX2_DATA<3>
                                                       IO_FX2_DATA_3_IOBUF/IBUF
                                                       ProtoComp1909.IMUX.19
    IODELAY_X0Y51.IDATAINnet (fanout=1)        0.168   N635
    IODELAY_X0Y51.DATAOUTTioddo_IDATAIN        2.460   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3_ML_IODELAY2
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3_ML_IODELAY2
    ILOGIC_X0Y51.DDLY    net (fanout=1)        0.007   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3_ML_IODELAY2_SIG_ML
    ILOGIC_X0Y51.CLK0    Tidockd               0.532   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI<3>
                                                       ProtoComp1921.D2OFFBYP_SRC.6
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3
    -------------------------------------------------  ---------------------------
    Total                                      4.724ns (4.549ns logic, 0.175ns route)
                                                       (96.3% logic, 3.7% route)

  Minimum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.344   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.855   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.197   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y51.CLK0    net (fanout=49)       1.371   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.767ns (1.541ns logic, 2.226ns route)
                                                       (40.9% logic, 59.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     1.018ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               IO_FX2_DATA<5> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          2.000ns
  Data Path Delay:      4.724ns (Levels of Logic = 3)
  Clock Path Delay:     3.767ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: IO_FX2_DATA<5> to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H7.I                 Tiopi                 1.557   IO_FX2_DATA<5>
                                                       IO_FX2_DATA<5>
                                                       IO_FX2_DATA_5_IOBUF/IBUF
                                                       ProtoComp1909.IMUX.21
    IODELAY_X0Y53.IDATAINnet (fanout=1)        0.168   N633
    IODELAY_X0Y53.DATAOUTTioddo_IDATAIN        2.460   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5_ML_IODELAY2
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5_ML_IODELAY2
    ILOGIC_X0Y53.DDLY    net (fanout=1)        0.007   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5_ML_IODELAY2_SIG_ML
    ILOGIC_X0Y53.CLK0    Tidockd               0.532   RLINK/FX2CNTL/IOB_FX2_DATA/R_DI<5>
                                                       ProtoComp1921.D2OFFBYP_SRC.8
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5
    -------------------------------------------------  ---------------------------
    Total                                      4.724ns (4.549ns logic, 0.175ns route)
                                                       (96.3% logic, 3.7% route)

  Minimum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_DI_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.344   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.855   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.197   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y53.CLK0    net (fanout=49)       1.371   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.767ns (1.541ns logic, 2.226ns route)
                                                       (40.9% logic, 59.1% route)

--------------------------------------------------------------------------------

Hold Paths: OFFSET = IN 2 ns VALID 33 ns BEFORE COMP "I_FX2_IFCLK";
--------------------------------------------------------------------------------
Slack (hold path):      30.419ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               I_FX2_FLAG<1> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          31.000ns
  Data Path Delay:      3.926ns (Levels of Logic = 3)
  Clock Path Delay:     4.482ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path at Slow Process Corner: I_FX2_FLAG<1> to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    K4.I                 Tiopi                 1.344   I_FX2_FLAG<1>
                                                       I_FX2_FLAG<1>
                                                       I_FX2_FLAG_1_IBUF
                                                       ProtoComp1910.IMUX.11
    IODELAY_X0Y31.IDATAINnet (fanout=1)        0.168   I_FX2_FLAG_1_IBUF
    IODELAY_X0Y31.DATAOUTTioddo_IDATAIN        2.150   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1_ML_IODELAY2
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1_ML_IODELAY2
    ILOGIC_X0Y31.DDLY    net (fanout=1)        0.007   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1_ML_IODELAY2_SIG_ML
    ILOGIC_X0Y31.CLK0    Tiockdd     (-Th)    -0.257   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<1>
                                                       ProtoComp1921.D2OFFBYP_SRC.1
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1
    -------------------------------------------------  ---------------------------
    Total                                      3.926ns (3.751ns logic, 0.175ns route)
                                                       (95.5% logic, 4.5% route)

  Maximum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y31.CLK0    net (fanout=49)       1.710   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.482ns (1.766ns logic, 2.716ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      30.420ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               I_FX2_FLAG<2> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          31.000ns
  Data Path Delay:      3.926ns (Levels of Logic = 3)
  Clock Path Delay:     4.481ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path at Slow Process Corner: I_FX2_FLAG<2> to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    F5.I                 Tiopi                 1.344   I_FX2_FLAG<2>
                                                       I_FX2_FLAG<2>
                                                       I_FX2_FLAG_2_IBUF
                                                       ProtoComp1910.IMUX.12
    IODELAY_X0Y56.IDATAINnet (fanout=1)        0.168   I_FX2_FLAG_2_IBUF
    IODELAY_X0Y56.DATAOUTTioddo_IDATAIN        2.150   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2_ML_IODELAY2
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2_ML_IODELAY2
    ILOGIC_X0Y56.DDLY    net (fanout=1)        0.007   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2_ML_IODELAY2_SIG_ML
    ILOGIC_X0Y56.CLK0    Tiockdd     (-Th)    -0.257   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<2>
                                                       ProtoComp1921.D2OFFBYP_SRC.2
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2
    -------------------------------------------------  ---------------------------
    Total                                      3.926ns (3.751ns logic, 0.175ns route)
                                                       (95.5% logic, 4.5% route)

  Maximum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y56.CLK0    net (fanout=49)       1.709   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.481ns (1.766ns logic, 2.715ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      30.420ns (requirement - (clock path + clock arrival + uncertainty - data path))
  Source:               I_FX2_FLAG<0> (PAD)
  Destination:          RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0 (FF)
  Destination Clock:    I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          31.000ns
  Data Path Delay:      3.926ns (Levels of Logic = 3)
  Clock Path Delay:     4.481ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path at Slow Process Corner: I_FX2_FLAG<0> to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H1.I                 Tiopi                 1.344   I_FX2_FLAG<0>
                                                       I_FX2_FLAG<0>
                                                       I_FX2_FLAG_0_IBUF
                                                       ProtoComp1910.IMUX.10
    IODELAY_X0Y28.IDATAINnet (fanout=1)        0.168   I_FX2_FLAG_0_IBUF
    IODELAY_X0Y28.DATAOUTTioddo_IDATAIN        2.150   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0_ML_IODELAY2
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0_ML_IODELAY2
    ILOGIC_X0Y28.DDLY    net (fanout=1)        0.007   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0_ML_IODELAY2_SIG_ML
    ILOGIC_X0Y28.CLK0    Tiockdd     (-Th)    -0.257   RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI<0>
                                                       ProtoComp1921.D2OFFBYP_SRC
                                                       RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0
    -------------------------------------------------  ---------------------------
    Total                                      3.926ns (3.751ns logic, 0.175ns route)
                                                       (95.5% logic, 4.5% route)

  Maximum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_FLAG/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    ILOGIC_X0Y28.CLK0    net (fanout=49)       1.709   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.481ns (1.766ns logic, 2.715ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = OUT 10 ns VALID 33 ns AFTER COMP "I_FX2_IFCLK";
For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612).

 22 paths analyzed, 14 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
 Minimum allowable offset is   7.871ns.
--------------------------------------------------------------------------------
Slack (slowest paths):  2.129ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO_0 (FF)
  Destination:          O_FX2_SLWR_N (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      3.372ns (Levels of Logic = 1)
  Clock Path Delay:     4.474ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    OLOGIC_X0Y60.CLK0    net (fanout=49)       1.702   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.474ns (1.766ns logic, 2.708ns route)
                                                       (39.5% logic, 60.5% route)

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO_0 to O_FX2_SLWR_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X0Y60.OQ      Tockq                 1.080   RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO
                                                       RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO_0
    C1.O                 net (fanout=1)        0.310   RLINK/FX2CNTL/IOB_FX2_SLWR/IOB/R_DO
    C1.PAD               Tioop                 1.982   O_FX2_SLWR_N
                                                       O_FX2_SLWR_N_OBUF
                                                       O_FX2_SLWR_N
    -------------------------------------------------  ---------------------------
    Total                                      3.372ns (3.062ns logic, 0.310ns route)
                                                       (90.8% logic, 9.2% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  2.129ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0 (FF)
  Destination:          O_FX2_SLRD_N (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      3.372ns (Levels of Logic = 1)
  Clock Path Delay:     4.474ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    OLOGIC_X0Y61.CLK0    net (fanout=49)       1.702   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.474ns (1.766ns logic, 2.708ns route)
                                                       (39.5% logic, 60.5% route)

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0 to O_FX2_SLRD_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X0Y61.OQ      Tockq                 1.080   RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO
                                                       RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0
    C2.O                 net (fanout=1)        0.310   RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO
    C2.PAD               Tioop                 1.982   O_FX2_SLRD_N
                                                       O_FX2_SLRD_N_OBUF
                                                       O_FX2_SLRD_N
    -------------------------------------------------  ---------------------------
    Total                                      3.372ns (3.062ns logic, 0.310ns route)
                                                       (90.8% logic, 9.2% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  2.133ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               RLINK/FX2CNTL/IOB_FX2_SLOE/IOB/R_DO_0 (FF)
  Destination:          O_FX2_SLOE_N (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      3.372ns (Levels of Logic = 1)
  Clock Path Delay:     4.470ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Clock Path at Slow Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_SLOE/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 1.557   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        1.006   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.209   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    OLOGIC_X0Y45.CLK0    net (fanout=49)       1.698   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      4.470ns (1.766ns logic, 2.704ns route)
                                                       (39.5% logic, 60.5% route)

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/IOB_FX2_SLOE/IOB/R_DO_0 to O_FX2_SLOE_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X0Y45.OQ      Tockq                 1.080   RLINK/FX2CNTL/IOB_FX2_SLOE/IOB/R_DO
                                                       RLINK/FX2CNTL/IOB_FX2_SLOE/IOB/R_DO_0
    H6.O                 net (fanout=1)        0.310   RLINK/FX2CNTL/IOB_FX2_SLOE/IOB/R_DO
    H6.PAD               Tioop                 1.982   O_FX2_SLOE_N
                                                       O_FX2_SLOE_N_OBUF
                                                       O_FX2_SLOE_N
    -------------------------------------------------  ---------------------------
    Total                                      3.372ns (3.062ns logic, 0.310ns route)
                                                       (90.8% logic, 9.2% route)

--------------------------------------------------------------------------------

Fastest Paths: OFFSET = OUT 10 ns VALID 33 ns AFTER COMP "I_FX2_IFCLK";
--------------------------------------------------------------------------------
Delay (fastest paths):  2.894ns (clock arrival + clock path + data path - uncertainty)
  Source:               RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3 (FF)
  Destination:          IO_FX2_DATA<3> (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Data Path Delay:      1.226ns (Levels of Logic = 1)
  Clock Path Delay:     1.693ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Clock Path at Fast Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 0.763   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.272   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.059   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    OLOGIC_X0Y51.CLK0    net (fanout=49)       0.599   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      1.693ns (0.822ns logic, 0.871ns route)
                                                       (48.6% logic, 51.4% route)

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3 to IO_FX2_DATA<3>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X0Y51.OQ      Tockq                 0.336   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<3>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    D2.O                 net (fanout=1)        0.191   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<3>
    D2.PAD               Tioop                 0.699   IO_FX2_DATA<3>
                                                       IO_FX2_DATA_3_IOBUF/OBUFT
                                                       IO_FX2_DATA<3>
    -------------------------------------------------  ---------------------------
    Total                                      1.226ns (1.035ns logic, 0.191ns route)
                                                       (84.4% logic, 15.6% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  2.894ns (clock arrival + clock path + data path - uncertainty)
  Source:               RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5 (FF)
  Destination:          IO_FX2_DATA<5> (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Data Path Delay:      1.226ns (Levels of Logic = 1)
  Clock Path Delay:     1.693ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Clock Path at Fast Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 0.763   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.272   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.059   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    OLOGIC_X0Y53.CLK0    net (fanout=49)       0.599   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      1.693ns (0.822ns logic, 0.871ns route)
                                                       (48.6% logic, 51.4% route)

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5 to IO_FX2_DATA<5>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X0Y53.OQ      Tockq                 0.336   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<5>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    H7.O                 net (fanout=1)        0.191   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<5>
    H7.PAD               Tioop                 0.699   IO_FX2_DATA<5>
                                                       IO_FX2_DATA_5_IOBUF/OBUFT
                                                       IO_FX2_DATA<5>
    -------------------------------------------------  ---------------------------
    Total                                      1.226ns (1.035ns logic, 0.191ns route)
                                                       (84.4% logic, 15.6% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  2.894ns (clock arrival + clock path + data path - uncertainty)
  Source:               RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4 (FF)
  Destination:          IO_FX2_DATA<4> (PAD)
  Source Clock:         I_FX2_IFCLK_BUFGP rising at 0.000ns
  Data Path Delay:      1.226ns (Levels of Logic = 1)
  Clock Path Delay:     1.693ns (Levels of Logic = 2)
  Clock Uncertainty:    0.025ns

  Clock Uncertainty:          0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.050ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Clock Path at Fast Process Corner: I_FX2_IFCLK to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H2.I                 Tiopi                 0.763   I_FX2_IFCLK
                                                       I_FX2_IFCLK
                                                       I_FX2_IFCLK_BUFGP/IBUFG
                                                       ProtoComp1910.IMUX.8
    BUFGMUX_X2Y9.I0      net (fanout=1)        0.272   I_FX2_IFCLK_BUFGP/IBUFG
    BUFGMUX_X2Y9.O       Tgi0o                 0.059   I_FX2_IFCLK_BUFGP/BUFG
                                                       I_FX2_IFCLK_BUFGP/BUFG
    OLOGIC_X0Y50.CLK0    net (fanout=49)       0.599   I_FX2_IFCLK_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      1.693ns (0.822ns logic, 0.871ns route)
                                                       (48.6% logic, 51.4% route)

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4 to IO_FX2_DATA<4>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    OLOGIC_X0Y50.OQ      Tockq                 0.336   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<4>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    D1.O                 net (fanout=1)        0.191   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<4>
    D1.PAD               Tioop                 0.699   IO_FX2_DATA<4>
                                                       IO_FX2_DATA_4_IOBUF/OBUFT
                                                       IO_FX2_DATA<4>
    -------------------------------------------------  ---------------------------
    Total                                      1.226ns (1.035ns logic, 0.191ns route)
                                                       (84.4% logic, 15.6% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: Unconstrained path analysis 

 244 paths analyzed, 68 endpoints analyzed, 5 failing endpoints
 5 timing errors detected. (0 setup errors, 5 hold errors)
 Minimum period is   8.472ns.
--------------------------------------------------------------------------------
Delay (setup path):     8.472ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6 (FF)
  Data Path Delay:      5.567ns (Levels of Logic = 1)
  Clock Path Skew:      -2.473ns (3.758 - 6.231)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X22Y63.BMUX    Tshcko                1.131   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM1/DP
    SLICE_X15Y61.D2      net (fanout=1)        1.441   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<6>
    SLICE_X15Y61.DMUX    Tilo                  0.337   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB71
    OLOGIC_X0Y52.D1      net (fanout=1)        1.480   RLINK/FX2CNTL/TXFIFO_DO<6>
    OLOGIC_X0Y52.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<6>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    -------------------------------------------------  ---------------------------
    Total                                      5.567ns (2.646ns logic, 2.921ns route)
                                                       (47.5% logic, 52.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.377ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4 (FF)
  Data Path Delay:      5.472ns (Levels of Logic = 1)
  Clock Path Skew:      -2.473ns (3.758 - 6.231)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X22Y63.AMUX    Tshcko                1.081   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X15Y61.C1      net (fanout=1)        1.350   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X15Y61.CMUX    Tilo                  0.337   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB51
    OLOGIC_X0Y50.D1      net (fanout=1)        1.526   RLINK/FX2CNTL/TXFIFO_DO<4>
    OLOGIC_X0Y50.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<4>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    -------------------------------------------------  ---------------------------
    Total                                      5.472ns (2.596ns logic, 2.876ns route)
                                                       (47.4% logic, 52.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.159ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5 (FF)
  Data Path Delay:      5.254ns (Levels of Logic = 1)
  Clock Path Skew:      -2.473ns (3.758 - 6.231)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X22Y63.A       Tshcko                1.012   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM1/DP
    SLICE_X15Y61.C2      net (fanout=1)        1.152   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<5>
    SLICE_X15Y61.C       Tilo                  0.259   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB61
    OLOGIC_X0Y53.D1      net (fanout=1)        1.653   RLINK/FX2CNTL/TXFIFO_DO<5>
    OLOGIC_X0Y53.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<5>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    -------------------------------------------------  ---------------------------
    Total                                      5.254ns (2.449ns logic, 2.805ns route)
                                                       (46.6% logic, 53.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.121ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6 (FF)
  Data Path Delay:      5.221ns (Levels of Logic = 1)
  Clock Path Skew:      -2.468ns (3.758 - 6.226)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y61.BMUX    Tshcko                1.131   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X15Y61.D5      net (fanout=1)        1.095   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X15Y61.DMUX    Tilo                  0.337   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB71
    OLOGIC_X0Y52.D1      net (fanout=1)        1.480   RLINK/FX2CNTL/TXFIFO_DO<6>
    OLOGIC_X0Y52.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<6>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    -------------------------------------------------  ---------------------------
    Total                                      5.221ns (2.646ns logic, 2.575ns route)
                                                       (50.7% logic, 49.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     8.030ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7 (FF)
  Data Path Delay:      5.130ns (Levels of Logic = 1)
  Clock Path Skew:      -2.468ns (3.763 - 6.231)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X22Y63.B       Tshcko                1.106   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM1/DP
    SLICE_X15Y61.D1      net (fanout=1)        1.301   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
    SLICE_X15Y61.D       Tilo                  0.259   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB81
    OLOGIC_X0Y55.D1      net (fanout=1)        1.286   RLINK/FX2CNTL/TXFIFO_DO<7>
    OLOGIC_X0Y55.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<7>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    -------------------------------------------------  ---------------------------
    Total                                      5.130ns (2.543ns logic, 2.587ns route)
                                                       (49.6% logic, 50.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.816ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1 (FF)
  Data Path Delay:      4.922ns (Levels of Logic = 1)
  Clock Path Skew:      -2.462ns (3.760 - 6.222)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y59.A       Tshcko                1.012   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X12Y59.D1      net (fanout=1)        0.939   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X12Y59.D       Tilo                  0.235   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB21
    OLOGIC_X0Y49.D1      net (fanout=1)        1.558   RLINK/FX2CNTL/TXFIFO_DO<1>
    OLOGIC_X0Y49.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<1>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    -------------------------------------------------  ---------------------------
    Total                                      4.922ns (2.425ns logic, 2.497ns route)
                                                       (49.3% logic, 50.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.744ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0 (FF)
  Data Path Delay:      4.853ns (Levels of Logic = 1)
  Clock Path Skew:      -2.459ns (3.763 - 6.222)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y59.AMUX    Tshcko                1.081   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X12Y59.D2      net (fanout=1)        0.775   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X12Y59.DMUX    Tilo                  0.298   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB11
    OLOGIC_X0Y46.D1      net (fanout=1)        1.521   RLINK/FX2CNTL/TXFIFO_DO<0>
    OLOGIC_X0Y46.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<0>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    -------------------------------------------------  ---------------------------
    Total                                      4.853ns (2.557ns logic, 2.296ns route)
                                                       (52.7% logic, 47.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.649ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3 (FF)
  Data Path Delay:      4.756ns (Levels of Logic = 1)
  Clock Path Skew:      -2.461ns (3.758 - 6.219)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y58.B       Tshcko                1.106   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X15Y58.C2      net (fanout=1)        0.801   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X15Y58.C       Tilo                  0.259   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB41
    OLOGIC_X0Y51.D1      net (fanout=1)        1.412   RLINK/FX2CNTL/TXFIFO_DO<3>
    OLOGIC_X0Y51.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<3>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    -------------------------------------------------  ---------------------------
    Total                                      4.756ns (2.543ns logic, 2.213ns route)
                                                       (53.5% logic, 46.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.477ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0 (FF)
  Data Path Delay:      4.589ns (Levels of Logic = 1)
  Clock Path Skew:      -2.456ns (3.763 - 6.219)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y58.AMUX    Tshcko                1.081   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X12Y59.D5      net (fanout=1)        0.511   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X12Y59.DMUX    Tilo                  0.298   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB11
    OLOGIC_X0Y46.D1      net (fanout=1)        1.521   RLINK/FX2CNTL/TXFIFO_DO<0>
    OLOGIC_X0Y46.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<0>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    -------------------------------------------------  ---------------------------
    Total                                      4.589ns (2.557ns logic, 2.032ns route)
                                                       (55.7% logic, 44.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.441ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3 (FF)
  Data Path Delay:      4.545ns (Levels of Logic = 1)
  Clock Path Skew:      -2.464ns (3.758 - 6.222)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y59.B       Tshcko                1.106   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM1/DP
    SLICE_X15Y58.C5      net (fanout=1)        0.590   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
    SLICE_X15Y58.C       Tilo                  0.259   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB41
    OLOGIC_X0Y51.D1      net (fanout=1)        1.412   RLINK/FX2CNTL/TXFIFO_DO<3>
    OLOGIC_X0Y51.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<3>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    -------------------------------------------------  ---------------------------
    Total                                      4.545ns (2.543ns logic, 2.002ns route)
                                                       (56.0% logic, 44.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.423ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2 (FF)
  Data Path Delay:      4.529ns (Levels of Logic = 1)
  Clock Path Skew:      -2.462ns (3.760 - 6.222)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y59.BMUX    Tshcko                1.131   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X15Y58.C3      net (fanout=1)        0.597   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X15Y58.CMUX    Tilo                  0.337   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB31
    OLOGIC_X0Y48.D1      net (fanout=1)        1.286   RLINK/FX2CNTL/TXFIFO_DO<2>
    OLOGIC_X0Y48.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<2>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2
    -------------------------------------------------  ---------------------------
    Total                                      4.529ns (2.646ns logic, 1.883ns route)
                                                       (58.4% logic, 41.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.420ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1 (FF)
  Data Path Delay:      4.529ns (Levels of Logic = 1)
  Clock Path Skew:      -2.459ns (3.760 - 6.219)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y58.A       Tshcko                1.012   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X12Y59.D3      net (fanout=1)        0.546   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X12Y59.D       Tilo                  0.235   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB21
    OLOGIC_X0Y49.D1      net (fanout=1)        1.558   RLINK/FX2CNTL/TXFIFO_DO<1>
    OLOGIC_X0Y49.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<1>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    -------------------------------------------------  ---------------------------
    Total                                      4.529ns (2.425ns logic, 2.104ns route)
                                                       (53.5% logic, 46.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.367ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2 (FF)
  Data Path Delay:      4.476ns (Levels of Logic = 1)
  Clock Path Skew:      -2.459ns (3.760 - 6.219)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y58.BMUX    Tshcko                1.131   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X15Y58.C1      net (fanout=1)        0.544   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X15Y58.CMUX    Tilo                  0.337   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB31
    OLOGIC_X0Y48.D1      net (fanout=1)        1.286   RLINK/FX2CNTL/TXFIFO_DO<2>
    OLOGIC_X0Y48.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<2>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2
    -------------------------------------------------  ---------------------------
    Total                                      4.476ns (2.646ns logic, 1.830ns route)
                                                       (59.1% logic, 40.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.360ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5 (FF)
  Data Path Delay:      4.460ns (Levels of Logic = 1)
  Clock Path Skew:      -2.468ns (3.758 - 6.226)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y61.A       Tshcko                1.012   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X15Y61.C3      net (fanout=1)        0.358   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X15Y61.C       Tilo                  0.259   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB61
    OLOGIC_X0Y53.D1      net (fanout=1)        1.653   RLINK/FX2CNTL/TXFIFO_DO<5>
    OLOGIC_X0Y53.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<5>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    -------------------------------------------------  ---------------------------
    Total                                      4.460ns (2.449ns logic, 2.011ns route)
                                                       (54.9% logic, 45.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.247ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4 (FF)
  Data Path Delay:      4.347ns (Levels of Logic = 1)
  Clock Path Skew:      -2.468ns (3.758 - 6.226)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y61.AMUX    Tshcko                1.081   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X15Y61.C5      net (fanout=1)        0.225   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X15Y61.CMUX    Tilo                  0.337   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB51
    OLOGIC_X0Y50.D1      net (fanout=1)        1.526   RLINK/FX2CNTL/TXFIFO_DO<4>
    OLOGIC_X0Y50.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<4>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    -------------------------------------------------  ---------------------------
    Total                                      4.347ns (2.596ns logic, 1.751ns route)
                                                       (59.7% logic, 40.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     7.014ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7 (FF)
  Data Path Delay:      4.119ns (Levels of Logic = 1)
  Clock Path Skew:      -2.463ns (3.763 - 6.226)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y61.B       Tshcko                1.106   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM0/DP
    SLICE_X15Y61.D4      net (fanout=1)        0.290   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
    SLICE_X15Y61.D       Tilo                  0.259   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB81
    OLOGIC_X0Y55.D1      net (fanout=1)        1.286   RLINK/FX2CNTL/TXFIFO_DO<7>
    OLOGIC_X0Y55.CLK0    Todck                 1.178   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<7>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    -------------------------------------------------  ---------------------------
    Total                                      4.119ns (2.543ns logic, 1.576ns route)
                                                       (61.7% logic, 38.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.266ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/IBMON.I0/BRAM1/UMEM/AW_09_S32.GL[0].MEM (RAM)
  Data Path Delay:      6.266ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/IBMON.I0/BRAM1/UMEM/AW_09_S32.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y16.CLKA    net (fanout=1029)     1.132   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.266ns (2.356ns logic, 3.910ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.266ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          RLINK/RBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM (RAM)
  Data Path Delay:      6.266ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to RLINK/RBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y8.CLKA     net (fanout=1029)     1.132   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.266ns (2.356ns logic, 3.910ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.265ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM (RAM)
  Data Path Delay:      6.265ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/IBMON.I0/BRAM0/UMEM/AW_09_S32.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y14.CLKA    net (fanout=1029)     1.131   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.265ns (2.356ns logic, 3.909ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.265ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          RLINK/RBMON.I0/BRAM1/UMEM/AW_09_S32.GL[0].MEM (RAM)
  Data Path Delay:      6.265ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to RLINK/RBMON.I0/BRAM1/UMEM/AW_09_S32.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y6.CLKA     net (fanout=1029)     1.131   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.265ns (2.356ns logic, 3.909ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.265ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[1].MEM (RAM)
  Data Path Delay:      6.265ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[1].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y22.CLKB    net (fanout=1029)     1.131   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.265ns (2.356ns logic, 3.909ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.265ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[1].MEM (RAM)
  Data Path Delay:      6.265ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[1].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y22.CLKA    net (fanout=1029)     1.131   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.265ns (2.356ns logic, 3.909ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.264ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_DAT2/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.264ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_DAT2/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y8.CLKB     net (fanout=1029)     1.130   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.264ns (2.356ns logic, 3.908ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.264ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_DAT2/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.264ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_DAT2/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y8.CLKA     net (fanout=1029)     1.130   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.264ns (2.356ns logic, 3.908ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.263ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_DAT0/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.263ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_DAT0/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y6.CLKA     net (fanout=1029)     1.129   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.263ns (2.356ns logic, 3.907ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.263ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.263ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y14.CLKB    net (fanout=1029)     1.129   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.263ns (2.356ns logic, 3.907ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.263ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.263ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_TAG/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y14.CLKA    net (fanout=1029)     1.129   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.263ns (2.356ns logic, 3.907ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.263ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_DAT0/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.263ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_DAT0/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y6.CLKB     net (fanout=1029)     1.129   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.263ns (2.356ns logic, 3.907ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.257ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.257ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y10.CLKA    net (fanout=1029)     1.123   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.257ns (2.356ns logic, 3.901ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.257ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/W11A/SEQ_Mram__n3264 (RAM)
  Data Path Delay:      6.257ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/W11A/SEQ_Mram__n3264
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB8_X0Y5.CLKAWRCLK net (fanout=1029)     1.123   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.257ns (2.356ns logic, 3.901ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.257ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.257ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_DAT1/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y10.CLKB    net (fanout=1029)     1.123   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.257ns (2.356ns logic, 3.901ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.256ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[0].MEM (RAM)
  Data Path Delay:      6.256ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y20.CLKB    net (fanout=1029)     1.122   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.256ns (2.356ns logic, 3.900ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.256ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[0].MEM (RAM)
  Data Path Delay:      6.256ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to RLINK/CORE/RL/RTBUF/UMEM/AW_12_S4.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X1Y20.CLKA    net (fanout=1029)     1.122   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.256ns (2.356ns logic, 3.900ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.255ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.255ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y12.CLKA    net (fanout=1029)     1.121   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.255ns (2.356ns logic, 3.899ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.255ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM (RAM)
  Data Path Delay:      6.255ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/CACHE/CMEM_DAT3/UMEM/AW_11_S9.GL[0].MEM
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    RAMB16_X0Y12.CLKB    net (fanout=1029)     1.121   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.255ns (2.356ns logic, 3.899ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     6.248ns (data path)
  Source:               I_CLK100 (PAD)
  Destination:          SYS70/W11A/DPATH/MUNIT/Mmult_proc_omux.prod (DSP)
  Data Path Delay:      6.248ns (Levels of Logic = 4)

  Maximum Data Path at Slow Process Corner: I_CLK100 to SYS70/W11A/DPATH/MUNIT/Mmult_proc_omux.prod
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    V10.I                Tiopi                 1.557   I_CLK100
                                                       I_CLK100
                                                       I_CLK100_IBUFG
                                                       ProtoComp1910.IMUX.13
    BUFIO2_X1Y7.I        net (fanout=1)        0.676   I_CLK100_IBUFG
    BUFIO2_X1Y7.DIVCLK   Tbufcko_DIVCLK        0.190   SP6_BUFIO_INSERT_ML_BUFIO2_0
                                                       SP6_BUFIO_INSERT_ML_BUFIO2_0
    DCM_X0Y1.CLKIN       net (fanout=1)        1.202   GEN_CLKSYS/USEDCM.DCM_ML_NEW_DIVCLK
    DCM_X0Y1.CLKFX       Tdmcko_CLKFX          0.400   GEN_CLKSYS/USEDCM.DCM
                                                       GEN_CLKSYS/USEDCM.DCM
    BUFGMUX_X2Y3.I0      net (fanout=1)        0.900   GEN_CLKSYS/USEDCM.CLKOUT0
    BUFGMUX_X2Y3.O       Tgi0o                 0.209   GEN_CLKSYS/USEDCM.BUFG_CLKOUT
                                                       GEN_CLKSYS/USEDCM.BUFG_CLKOUT
    DSP48_X0Y4.CLK       net (fanout=1029)     1.114   CLK
    -------------------------------------------------  ---------------------------
    Total                                      6.248ns (2.356ns logic, 3.892ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.875ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      6.714ns (Levels of Logic = 5)
  Clock Path Skew:      1.271ns (5.153 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X18Y54.D2      net (fanout=1)        1.799   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X18Y54.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X19Y55.A3      net (fanout=1)        0.543   N10
    SLICE_X19Y55.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X23Y54.C5      net (fanout=4)        0.688   RLINK/RLB_DI<4>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.B4      net (fanout=6)        0.566   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      6.714ns (2.485ns logic, 4.229ns route)
                                                       (37.0% logic, 63.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.861ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Data Path Delay:      6.702ns (Levels of Logic = 5)
  Clock Path Skew:      1.273ns (5.155 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X18Y54.D2      net (fanout=1)        1.799   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X18Y54.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X19Y55.A3      net (fanout=1)        0.543   N10
    SLICE_X19Y55.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X23Y54.C5      net (fanout=4)        0.688   RLINK/RLB_DI<4>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.554   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      6.702ns (2.485ns logic, 4.217ns route)
                                                       (37.1% logic, 62.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.818ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Data Path Delay:      6.679ns (Levels of Logic = 5)
  Clock Path Skew:      1.293ns (5.155 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.BMUX    Tshcko                1.131   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X18Y53.D2      net (fanout=1)        1.425   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X18Y53.DMUX    Tilo                  0.326   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.271   N6
    SLICE_X18Y53.A       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X23Y54.C2      net (fanout=10)       1.269   RLINK/RLB_DI<2>
    SLICE_X23Y54.CMUX    Tilo                  0.337   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o_SW0
    SLICE_X18Y54.B3      net (fanout=1)        0.826   N42
    SLICE_X18Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.A5      net (fanout=1)        0.247   RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.CLK     Tas                   0.339   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      6.679ns (2.641ns logic, 4.038ns route)
                                                       (39.5% logic, 60.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.786ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Data Path Delay:      6.630ns (Levels of Logic = 5)
  Clock Path Skew:      1.276ns (5.158 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X18Y54.D2      net (fanout=1)        1.799   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X18Y54.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X19Y55.A3      net (fanout=1)        0.543   N10
    SLICE_X19Y55.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X23Y54.C5      net (fanout=4)        0.688   RLINK/RLB_DI<4>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.B4      net (fanout=6)        0.516   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.CLK     Tas                   0.339   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      6.630ns (2.451ns logic, 4.179ns route)
                                                       (37.0% logic, 63.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.757ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      6.596ns (Levels of Logic = 5)
  Clock Path Skew:      1.271ns (5.153 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X18Y54.D2      net (fanout=1)        1.799   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X18Y54.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X19Y55.A3      net (fanout=1)        0.543   N10
    SLICE_X19Y55.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X23Y54.C5      net (fanout=4)        0.688   RLINK/RLB_DI<4>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.D5      net (fanout=6)        0.448   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      6.596ns (2.485ns logic, 4.111ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.752ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Data Path Delay:      6.593ns (Levels of Logic = 5)
  Clock Path Skew:      1.273ns (5.155 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X18Y54.D2      net (fanout=1)        1.799   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X18Y54.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X19Y55.A3      net (fanout=1)        0.543   N10
    SLICE_X19Y55.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X23Y54.C5      net (fanout=4)        0.688   RLINK/RLB_DI<4>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.554   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.264   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      6.593ns (2.376ns logic, 4.217ns route)
                                                       (36.0% logic, 64.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.731ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      6.583ns (Levels of Logic = 5)
  Clock Path Skew:      1.284ns (5.166 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X18Y54.D2      net (fanout=1)        1.799   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X18Y54.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X19Y55.A3      net (fanout=1)        0.543   N10
    SLICE_X19Y55.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X23Y54.C5      net (fanout=4)        0.688   RLINK/RLB_DI<4>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.A6      net (fanout=6)        0.435   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      6.583ns (2.485ns logic, 4.098ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.722ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Data Path Delay:      6.563ns (Levels of Logic = 5)
  Clock Path Skew:      1.273ns (5.155 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X18Y54.D2      net (fanout=1)        1.799   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X18Y54.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X19Y55.A3      net (fanout=1)        0.543   N10
    SLICE_X19Y55.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X23Y54.C5      net (fanout=4)        0.688   RLINK/RLB_DI<4>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.D3      net (fanout=6)        0.415   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      6.563ns (2.485ns logic, 4.078ns route)
                                                       (37.9% logic, 62.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.712ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      6.580ns (Levels of Logic = 5)
  Clock Path Skew:      1.300ns (5.153 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X22Y54.B1      net (fanout=1)        1.632   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X22Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.502   N2
    SLICE_X19Y54.B       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.762   RLINK/RLB_DI<0>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.B4      net (fanout=6)        0.566   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      6.580ns (2.485ns logic, 4.095ns route)
                                                       (37.8% logic, 62.2% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.698ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Data Path Delay:      6.568ns (Levels of Logic = 5)
  Clock Path Skew:      1.302ns (5.155 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X22Y54.B1      net (fanout=1)        1.632   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X22Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.502   N2
    SLICE_X19Y54.B       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.762   RLINK/RLB_DI<0>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.554   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      6.568ns (2.485ns logic, 4.083ns route)
                                                       (37.8% logic, 62.2% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.634ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      6.473ns (Levels of Logic = 5)
  Clock Path Skew:      1.271ns (5.153 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X18Y54.D5      net (fanout=1)        1.558   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X18Y54.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X19Y55.A3      net (fanout=1)        0.543   N10
    SLICE_X19Y55.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X23Y54.C5      net (fanout=4)        0.688   RLINK/RLB_DI<4>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.B4      net (fanout=6)        0.566   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      6.473ns (2.485ns logic, 3.988ns route)
                                                       (38.4% logic, 61.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.623ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Data Path Delay:      6.493ns (Levels of Logic = 5)
  Clock Path Skew:      1.302ns (5.155 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X22Y54.B1      net (fanout=1)        1.632   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X22Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.502   N2
    SLICE_X19Y54.B       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.762   RLINK/RLB_DI<0>
    SLICE_X23Y54.CMUX    Tilo                  0.337   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o_SW0
    SLICE_X18Y54.B3      net (fanout=1)        0.826   N42
    SLICE_X18Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.A5      net (fanout=1)        0.247   RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.CLK     Tas                   0.339   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      6.493ns (2.524ns logic, 3.969ns route)
                                                       (38.9% logic, 61.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.623ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Data Path Delay:      6.496ns (Levels of Logic = 5)
  Clock Path Skew:      1.305ns (5.158 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X22Y54.B1      net (fanout=1)        1.632   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X22Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.502   N2
    SLICE_X19Y54.B       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.762   RLINK/RLB_DI<0>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.B4      net (fanout=6)        0.516   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.CLK     Tas                   0.339   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      6.496ns (2.451ns logic, 4.045ns route)
                                                       (37.7% logic, 62.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.620ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Data Path Delay:      6.461ns (Levels of Logic = 5)
  Clock Path Skew:      1.273ns (5.155 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X18Y54.D5      net (fanout=1)        1.558   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X18Y54.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X19Y55.A3      net (fanout=1)        0.543   N10
    SLICE_X19Y55.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X23Y54.C5      net (fanout=4)        0.688   RLINK/RLB_DI<4>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.554   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      6.461ns (2.485ns logic, 3.976ns route)
                                                       (38.5% logic, 61.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.594ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      6.462ns (Levels of Logic = 5)
  Clock Path Skew:      1.300ns (5.153 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X22Y54.B1      net (fanout=1)        1.632   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X22Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.502   N2
    SLICE_X19Y54.B       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.762   RLINK/RLB_DI<0>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.D5      net (fanout=6)        0.448   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      6.462ns (2.485ns logic, 3.977ns route)
                                                       (38.5% logic, 61.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.589ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Data Path Delay:      6.459ns (Levels of Logic = 5)
  Clock Path Skew:      1.302ns (5.155 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X22Y54.B1      net (fanout=1)        1.632   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X22Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.502   N2
    SLICE_X19Y54.B       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.762   RLINK/RLB_DI<0>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.554   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.264   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      6.459ns (2.376ns logic, 4.083ns route)
                                                       (36.8% logic, 63.2% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.568ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      6.449ns (Levels of Logic = 5)
  Clock Path Skew:      1.313ns (5.166 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X22Y54.B1      net (fanout=1)        1.632   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X22Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.502   N2
    SLICE_X19Y54.B       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.762   RLINK/RLB_DI<0>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.A6      net (fanout=6)        0.435   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      6.449ns (2.485ns logic, 3.964ns route)
                                                       (38.5% logic, 61.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.559ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Data Path Delay:      6.429ns (Levels of Logic = 5)
  Clock Path Skew:      1.302ns (5.155 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X22Y54.B1      net (fanout=1)        1.632   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X22Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.502   N2
    SLICE_X19Y54.B       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.762   RLINK/RLB_DI<0>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.D3      net (fanout=6)        0.415   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      6.429ns (2.485ns logic, 3.944ns route)
                                                       (38.7% logic, 61.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.545ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Data Path Delay:      6.389ns (Levels of Logic = 5)
  Clock Path Skew:      1.276ns (5.158 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X18Y54.D5      net (fanout=1)        1.558   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X18Y54.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X19Y55.A3      net (fanout=1)        0.543   N10
    SLICE_X19Y55.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X23Y54.C5      net (fanout=4)        0.688   RLINK/RLB_DI<4>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.B4      net (fanout=6)        0.516   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.CLK     Tas                   0.339   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      6.389ns (2.451ns logic, 3.938ns route)
                                                       (38.4% logic, 61.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.516ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      6.355ns (Levels of Logic = 5)
  Clock Path Skew:      1.271ns (5.153 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X18Y54.D5      net (fanout=1)        1.558   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X18Y54.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X19Y55.A3      net (fanout=1)        0.543   N10
    SLICE_X19Y55.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X23Y54.C5      net (fanout=4)        0.688   RLINK/RLB_DI<4>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.D5      net (fanout=6)        0.448   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      6.355ns (2.485ns logic, 3.870ns route)
                                                       (39.1% logic, 60.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.511ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Data Path Delay:      6.352ns (Levels of Logic = 5)
  Clock Path Skew:      1.273ns (5.155 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X18Y54.D5      net (fanout=1)        1.558   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X18Y54.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X19Y55.A3      net (fanout=1)        0.543   N10
    SLICE_X19Y55.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X23Y54.C5      net (fanout=4)        0.688   RLINK/RLB_DI<4>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.554   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.264   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      6.352ns (2.376ns logic, 3.976ns route)
                                                       (37.4% logic, 62.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.490ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      6.342ns (Levels of Logic = 5)
  Clock Path Skew:      1.284ns (5.166 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X18Y54.D5      net (fanout=1)        1.558   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X18Y54.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X19Y55.A3      net (fanout=1)        0.543   N10
    SLICE_X19Y55.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X23Y54.C5      net (fanout=4)        0.688   RLINK/RLB_DI<4>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.A6      net (fanout=6)        0.435   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      6.342ns (2.485ns logic, 3.857ns route)
                                                       (39.2% logic, 60.8% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.481ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Data Path Delay:      6.322ns (Levels of Logic = 5)
  Clock Path Skew:      1.273ns (5.155 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.AMUX     Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X18Y54.D5      net (fanout=1)        1.558   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X18Y54.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X19Y55.A3      net (fanout=1)        0.543   N10
    SLICE_X19Y55.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X23Y54.C5      net (fanout=4)        0.688   RLINK/RLB_DI<4>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.D3      net (fanout=6)        0.415   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      6.322ns (2.485ns logic, 3.837ns route)
                                                       (39.3% logic, 60.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.401ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Data Path Delay:      6.271ns (Levels of Logic = 5)
  Clock Path Skew:      1.302ns (5.155 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.BMUX    Tshcko                1.131   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X18Y53.D4      net (fanout=1)        1.017   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X18Y53.DMUX    Tilo                  0.326   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.271   N6
    SLICE_X18Y53.A       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X23Y54.C2      net (fanout=10)       1.269   RLINK/RLB_DI<2>
    SLICE_X23Y54.CMUX    Tilo                  0.337   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o_SW0
    SLICE_X18Y54.B3      net (fanout=1)        0.826   N42
    SLICE_X18Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.A5      net (fanout=1)        0.247   RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.CLK     Tas                   0.339   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      6.271ns (2.641ns logic, 3.630ns route)
                                                       (42.1% logic, 57.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.259ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      6.118ns (Levels of Logic = 5)
  Clock Path Skew:      1.291ns (5.153 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        1.202   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.143   N4
    SLICE_X18Y53.C       Tilo                  0.255   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        1.162   RLINK/RLB_DI<1>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.B4      net (fanout=6)        0.566   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      6.118ns (2.412ns logic, 3.706ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.245ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Data Path Delay:      6.106ns (Levels of Logic = 5)
  Clock Path Skew:      1.293ns (5.155 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        1.202   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.143   N4
    SLICE_X18Y53.C       Tilo                  0.255   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        1.162   RLINK/RLB_DI<1>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.554   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      6.106ns (2.412ns logic, 3.694ns route)
                                                       (39.5% logic, 60.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.189ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      6.048ns (Levels of Logic = 5)
  Clock Path Skew:      1.291ns (5.153 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.B       Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X22Y54.B3      net (fanout=1)        1.525   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X22Y54.BMUX    Tilo                  0.326   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X22Y54.A3      net (fanout=1)        0.382   N8
    SLICE_X22Y54.A       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X23Y54.C3      net (fanout=3)        0.365   RLINK/RLB_DI<3>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.B4      net (fanout=6)        0.566   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      6.048ns (2.577ns logic, 3.471ns route)
                                                       (42.6% logic, 57.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.175ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Data Path Delay:      6.036ns (Levels of Logic = 5)
  Clock Path Skew:      1.293ns (5.155 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.B       Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X22Y54.B3      net (fanout=1)        1.525   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X22Y54.BMUX    Tilo                  0.326   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X22Y54.A3      net (fanout=1)        0.382   N8
    SLICE_X22Y54.A       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X23Y54.C3      net (fanout=3)        0.365   RLINK/RLB_DI<3>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.554   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      6.036ns (2.577ns logic, 3.459ns route)
                                                       (42.7% logic, 57.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.170ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Data Path Delay:      6.034ns (Levels of Logic = 5)
  Clock Path Skew:      1.296ns (5.158 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        1.202   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.143   N4
    SLICE_X18Y53.C       Tilo                  0.255   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        1.162   RLINK/RLB_DI<1>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.B4      net (fanout=6)        0.516   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.CLK     Tas                   0.339   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      6.034ns (2.378ns logic, 3.656ns route)
                                                       (39.4% logic, 60.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.170ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Data Path Delay:      6.031ns (Levels of Logic = 5)
  Clock Path Skew:      1.293ns (5.155 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        1.202   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.143   N4
    SLICE_X18Y53.C       Tilo                  0.255   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        1.162   RLINK/RLB_DI<1>
    SLICE_X23Y54.CMUX    Tilo                  0.337   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o_SW0
    SLICE_X18Y54.B3      net (fanout=1)        0.826   N42
    SLICE_X18Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.A5      net (fanout=1)        0.247   RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.CLK     Tas                   0.339   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      6.031ns (2.451ns logic, 3.580ns route)
                                                       (40.6% logic, 59.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.141ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      6.000ns (Levels of Logic = 5)
  Clock Path Skew:      1.291ns (5.153 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        1.202   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.143   N4
    SLICE_X18Y53.C       Tilo                  0.255   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        1.162   RLINK/RLB_DI<1>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.D5      net (fanout=6)        0.448   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      6.000ns (2.412ns logic, 3.588ns route)
                                                       (40.2% logic, 59.8% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.137ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      6.005ns (Levels of Logic = 5)
  Clock Path Skew:      1.300ns (5.153 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        1.089   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.143   N4
    SLICE_X18Y53.C       Tilo                  0.255   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        1.162   RLINK/RLB_DI<1>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.B4      net (fanout=6)        0.566   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      6.005ns (2.412ns logic, 3.593ns route)
                                                       (40.2% logic, 59.8% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.136ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Data Path Delay:      5.997ns (Levels of Logic = 5)
  Clock Path Skew:      1.293ns (5.155 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        1.202   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.143   N4
    SLICE_X18Y53.C       Tilo                  0.255   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        1.162   RLINK/RLB_DI<1>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.554   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.264   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      5.997ns (2.303ns logic, 3.694ns route)
                                                       (38.4% logic, 61.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.135ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Data Path Delay:      5.976ns (Levels of Logic = 4)
  Clock Path Skew:      1.273ns (5.155 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP
    SLICE_X20Y55.C1      net (fanout=1)        1.999   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
    SLICE_X20Y55.CMUX    Tilo                  0.298   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X20Y55.A2      net (fanout=1)        0.725   N16
    SLICE_X20Y55.A       Tilo                  0.235   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X18Y54.B2      net (fanout=5)        0.773   RLINK/RLB_DI<7>
    SLICE_X18Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.A5      net (fanout=1)        0.247   RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.CLK     Tas                   0.339   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      5.976ns (2.232ns logic, 3.744ns route)
                                                       (37.3% logic, 62.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.123ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Data Path Delay:      5.993ns (Levels of Logic = 5)
  Clock Path Skew:      1.302ns (5.155 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        1.089   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.143   N4
    SLICE_X18Y53.C       Tilo                  0.255   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        1.162   RLINK/RLB_DI<1>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.554   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      5.993ns (2.412ns logic, 3.581ns route)
                                                       (40.2% logic, 59.8% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.117ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      5.976ns (Levels of Logic = 5)
  Clock Path Skew:      1.291ns (5.153 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X22Y54.B4      net (fanout=1)        1.028   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X22Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.502   N2
    SLICE_X19Y54.B       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.762   RLINK/RLB_DI<0>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.B4      net (fanout=6)        0.566   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      5.976ns (2.485ns logic, 3.491ns route)
                                                       (41.6% logic, 58.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.115ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      5.987ns (Levels of Logic = 5)
  Clock Path Skew:      1.304ns (5.166 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        1.202   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.143   N4
    SLICE_X18Y53.C       Tilo                  0.255   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        1.162   RLINK/RLB_DI<1>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.A6      net (fanout=6)        0.435   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      5.987ns (2.412ns logic, 3.575ns route)
                                                       (40.3% logic, 59.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.115ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Data Path Delay:      5.954ns (Levels of Logic = 4)
  Clock Path Skew:      1.271ns (5.153 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP
    SLICE_X20Y55.C1      net (fanout=1)        1.999   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
    SLICE_X20Y55.CMUX    Tilo                  0.298   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X20Y55.A2      net (fanout=1)        0.725   N16
    SLICE_X20Y55.A       Tilo                  0.235   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X19Y54.A6      net (fanout=5)        0.393   RLINK/RLB_DI<7>
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.B4      net (fanout=6)        0.566   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      5.954ns (2.271ns logic, 3.683ns route)
                                                       (38.1% logic, 61.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.106ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Data Path Delay:      5.967ns (Levels of Logic = 5)
  Clock Path Skew:      1.293ns (5.155 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        1.202   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.143   N4
    SLICE_X18Y53.C       Tilo                  0.255   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        1.162   RLINK/RLB_DI<1>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.D3      net (fanout=6)        0.415   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      5.967ns (2.412ns logic, 3.555ns route)
                                                       (40.4% logic, 59.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.103ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Data Path Delay:      5.964ns (Levels of Logic = 5)
  Clock Path Skew:      1.293ns (5.155 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X22Y54.B4      net (fanout=1)        1.028   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X22Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.502   N2
    SLICE_X19Y54.B       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.762   RLINK/RLB_DI<0>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.554   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      5.964ns (2.485ns logic, 3.479ns route)
                                                       (41.7% logic, 58.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.101ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Data Path Delay:      5.942ns (Levels of Logic = 4)
  Clock Path Skew:      1.273ns (5.155 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP
    SLICE_X20Y55.C1      net (fanout=1)        1.999   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
    SLICE_X20Y55.CMUX    Tilo                  0.298   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X20Y55.A2      net (fanout=1)        0.725   N16
    SLICE_X20Y55.A       Tilo                  0.235   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X19Y54.A6      net (fanout=5)        0.393   RLINK/RLB_DI<7>
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.554   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      5.942ns (2.271ns logic, 3.671ns route)
                                                       (38.2% logic, 61.8% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.100ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Data Path Delay:      5.964ns (Levels of Logic = 5)
  Clock Path Skew:      1.296ns (5.158 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.B       Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X22Y54.B3      net (fanout=1)        1.525   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X22Y54.BMUX    Tilo                  0.326   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X22Y54.A3      net (fanout=1)        0.382   N8
    SLICE_X22Y54.A       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X23Y54.C3      net (fanout=3)        0.365   RLINK/RLB_DI<3>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.B4      net (fanout=6)        0.516   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.CLK     Tas                   0.339   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      5.964ns (2.543ns logic, 3.421ns route)
                                                       (42.6% logic, 57.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.100ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Data Path Delay:      5.961ns (Levels of Logic = 5)
  Clock Path Skew:      1.293ns (5.155 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.B       Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X22Y54.B3      net (fanout=1)        1.525   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X22Y54.BMUX    Tilo                  0.326   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X22Y54.A3      net (fanout=1)        0.382   N8
    SLICE_X22Y54.A       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X23Y54.C3      net (fanout=3)        0.365   RLINK/RLB_DI<3>
    SLICE_X23Y54.CMUX    Tilo                  0.337   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o_SW0
    SLICE_X18Y54.B3      net (fanout=1)        0.826   N42
    SLICE_X18Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.A5      net (fanout=1)        0.247   RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.CLK     Tas                   0.339   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      5.961ns (2.616ns logic, 3.345ns route)
                                                       (43.9% logic, 56.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.071ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      5.930ns (Levels of Logic = 5)
  Clock Path Skew:      1.291ns (5.153 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.B       Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X22Y54.B3      net (fanout=1)        1.525   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X22Y54.BMUX    Tilo                  0.326   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X22Y54.A3      net (fanout=1)        0.382   N8
    SLICE_X22Y54.A       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X23Y54.C3      net (fanout=3)        0.365   RLINK/RLB_DI<3>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.D5      net (fanout=6)        0.448   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      5.930ns (2.577ns logic, 3.353ns route)
                                                       (43.5% logic, 56.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.066ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Data Path Delay:      5.927ns (Levels of Logic = 5)
  Clock Path Skew:      1.293ns (5.155 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.B       Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X22Y54.B3      net (fanout=1)        1.525   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X22Y54.BMUX    Tilo                  0.326   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X22Y54.A3      net (fanout=1)        0.382   N8
    SLICE_X22Y54.A       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X23Y54.C3      net (fanout=3)        0.365   RLINK/RLB_DI<3>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.554   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.264   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      5.927ns (2.468ns logic, 3.459ns route)
                                                       (41.6% logic, 58.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.048ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Data Path Delay:      5.918ns (Levels of Logic = 5)
  Clock Path Skew:      1.302ns (5.155 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        1.089   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.143   N4
    SLICE_X18Y53.C       Tilo                  0.255   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        1.162   RLINK/RLB_DI<1>
    SLICE_X23Y54.CMUX    Tilo                  0.337   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o_SW0
    SLICE_X18Y54.B3      net (fanout=1)        0.826   N42
    SLICE_X18Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.A5      net (fanout=1)        0.247   RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.CLK     Tas                   0.339   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      5.918ns (2.451ns logic, 3.467ns route)
                                                       (41.4% logic, 58.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.048ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Data Path Delay:      5.921ns (Levels of Logic = 5)
  Clock Path Skew:      1.305ns (5.158 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        1.089   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.143   N4
    SLICE_X18Y53.C       Tilo                  0.255   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        1.162   RLINK/RLB_DI<1>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.B4      net (fanout=6)        0.516   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.CLK     Tas                   0.339   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      5.921ns (2.378ns logic, 3.543ns route)
                                                       (40.2% logic, 59.8% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.045ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      5.917ns (Levels of Logic = 5)
  Clock Path Skew:      1.304ns (5.166 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.B       Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X22Y54.B3      net (fanout=1)        1.525   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X22Y54.BMUX    Tilo                  0.326   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X22Y54.A3      net (fanout=1)        0.382   N8
    SLICE_X22Y54.A       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X23Y54.C3      net (fanout=3)        0.365   RLINK/RLB_DI<3>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.A6      net (fanout=6)        0.435   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      5.917ns (2.577ns logic, 3.340ns route)
                                                       (43.6% logic, 56.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.036ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Data Path Delay:      5.897ns (Levels of Logic = 5)
  Clock Path Skew:      1.293ns (5.155 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.B       Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X22Y54.B3      net (fanout=1)        1.525   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X22Y54.BMUX    Tilo                  0.326   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X22Y54.A3      net (fanout=1)        0.382   N8
    SLICE_X22Y54.A       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X23Y54.C3      net (fanout=3)        0.365   RLINK/RLB_DI<3>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.D3      net (fanout=6)        0.415   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      5.897ns (2.577ns logic, 3.320ns route)
                                                       (43.7% logic, 56.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.028ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Data Path Delay:      5.892ns (Levels of Logic = 5)
  Clock Path Skew:      1.296ns (5.158 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X22Y54.B4      net (fanout=1)        1.028   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X22Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.502   N2
    SLICE_X19Y54.B       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.762   RLINK/RLB_DI<0>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.B4      net (fanout=6)        0.516   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.CLK     Tas                   0.339   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      5.892ns (2.451ns logic, 3.441ns route)
                                                       (41.6% logic, 58.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.028ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Data Path Delay:      5.889ns (Levels of Logic = 5)
  Clock Path Skew:      1.293ns (5.155 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X22Y54.B4      net (fanout=1)        1.028   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X22Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.502   N2
    SLICE_X19Y54.B       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.762   RLINK/RLB_DI<0>
    SLICE_X23Y54.CMUX    Tilo                  0.337   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o_SW0
    SLICE_X18Y54.B3      net (fanout=1)        0.826   N42
    SLICE_X18Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.A5      net (fanout=1)        0.247   RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.CLK     Tas                   0.339   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      5.889ns (2.524ns logic, 3.365ns route)
                                                       (42.9% logic, 57.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.026ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Data Path Delay:      5.870ns (Levels of Logic = 4)
  Clock Path Skew:      1.276ns (5.158 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP
    SLICE_X20Y55.C1      net (fanout=1)        1.999   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
    SLICE_X20Y55.CMUX    Tilo                  0.298   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X20Y55.A2      net (fanout=1)        0.725   N16
    SLICE_X20Y55.A       Tilo                  0.235   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X19Y54.A6      net (fanout=5)        0.393   RLINK/RLB_DI<7>
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.B4      net (fanout=6)        0.516   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.CLK     Tas                   0.339   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      5.870ns (2.237ns logic, 3.633ns route)
                                                       (38.1% logic, 61.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.019ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      5.887ns (Levels of Logic = 5)
  Clock Path Skew:      1.300ns (5.153 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        1.089   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.143   N4
    SLICE_X18Y53.C       Tilo                  0.255   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        1.162   RLINK/RLB_DI<1>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.D5      net (fanout=6)        0.448   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      5.887ns (2.412ns logic, 3.475ns route)
                                                       (41.0% logic, 59.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     5.014ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Data Path Delay:      5.884ns (Levels of Logic = 5)
  Clock Path Skew:      1.302ns (5.155 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        1.089   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.143   N4
    SLICE_X18Y53.C       Tilo                  0.255   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        1.162   RLINK/RLB_DI<1>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.554   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.264   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      5.884ns (2.303ns logic, 3.581ns route)
                                                       (39.1% logic, 60.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.999ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      5.858ns (Levels of Logic = 5)
  Clock Path Skew:      1.291ns (5.153 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X22Y54.B4      net (fanout=1)        1.028   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X22Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.502   N2
    SLICE_X19Y54.B       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.762   RLINK/RLB_DI<0>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.D5      net (fanout=6)        0.448   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      5.858ns (2.485ns logic, 3.373ns route)
                                                       (42.4% logic, 57.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.997ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Data Path Delay:      5.836ns (Levels of Logic = 4)
  Clock Path Skew:      1.271ns (5.153 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP
    SLICE_X20Y55.C1      net (fanout=1)        1.999   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
    SLICE_X20Y55.CMUX    Tilo                  0.298   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X20Y55.A2      net (fanout=1)        0.725   N16
    SLICE_X20Y55.A       Tilo                  0.235   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X19Y54.A6      net (fanout=5)        0.393   RLINK/RLB_DI<7>
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.D5      net (fanout=6)        0.448   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      5.836ns (2.271ns logic, 3.565ns route)
                                                       (38.9% logic, 61.1% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.994ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Data Path Delay:      5.855ns (Levels of Logic = 5)
  Clock Path Skew:      1.293ns (5.155 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X22Y54.B4      net (fanout=1)        1.028   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X22Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.502   N2
    SLICE_X19Y54.B       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.762   RLINK/RLB_DI<0>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.554   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.264   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      5.855ns (2.376ns logic, 3.479ns route)
                                                       (40.6% logic, 59.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.993ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      5.874ns (Levels of Logic = 5)
  Clock Path Skew:      1.313ns (5.166 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        1.089   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.143   N4
    SLICE_X18Y53.C       Tilo                  0.255   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        1.162   RLINK/RLB_DI<1>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.A6      net (fanout=6)        0.435   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      5.874ns (2.412ns logic, 3.462ns route)
                                                       (41.1% logic, 58.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.992ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Data Path Delay:      5.833ns (Levels of Logic = 4)
  Clock Path Skew:      1.273ns (5.155 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP
    SLICE_X20Y55.C1      net (fanout=1)        1.999   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
    SLICE_X20Y55.CMUX    Tilo                  0.298   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X20Y55.A2      net (fanout=1)        0.725   N16
    SLICE_X20Y55.A       Tilo                  0.235   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X19Y54.A6      net (fanout=5)        0.393   RLINK/RLB_DI<7>
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.554   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.264   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      5.833ns (2.162ns logic, 3.671ns route)
                                                       (37.1% logic, 62.9% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.984ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Data Path Delay:      5.854ns (Levels of Logic = 5)
  Clock Path Skew:      1.302ns (5.155 - 3.853)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                1.012   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        1.089   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.143   N4
    SLICE_X18Y53.C       Tilo                  0.255   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        1.162   RLINK/RLB_DI<1>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.D3      net (fanout=6)        0.415   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      5.854ns (2.412ns logic, 3.442ns route)
                                                       (41.2% logic, 58.8% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.973ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      5.845ns (Levels of Logic = 5)
  Clock Path Skew:      1.304ns (5.166 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X22Y54.B4      net (fanout=1)        1.028   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X22Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.502   N2
    SLICE_X19Y54.B       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.762   RLINK/RLB_DI<0>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.A6      net (fanout=6)        0.435   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      5.845ns (2.485ns logic, 3.360ns route)
                                                       (42.5% logic, 57.5% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.971ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Data Path Delay:      5.823ns (Levels of Logic = 4)
  Clock Path Skew:      1.284ns (5.166 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP
    SLICE_X20Y55.C1      net (fanout=1)        1.999   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
    SLICE_X20Y55.CMUX    Tilo                  0.298   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X20Y55.A2      net (fanout=1)        0.725   N16
    SLICE_X20Y55.A       Tilo                  0.235   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X19Y54.A6      net (fanout=5)        0.393   RLINK/RLB_DI<7>
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.A6      net (fanout=6)        0.435   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      5.823ns (2.271ns logic, 3.552ns route)
                                                       (39.0% logic, 61.0% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.964ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Data Path Delay:      5.825ns (Levels of Logic = 5)
  Clock Path Skew:      1.293ns (5.155 - 3.862)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.AMUX    Tshcko                1.081   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X22Y54.B4      net (fanout=1)        1.028   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X22Y54.B       Tilo                  0.254   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.502   N2
    SLICE_X19Y54.B       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.762   RLINK/RLB_DI<0>
    SLICE_X23Y54.C       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X19Y54.A3      net (fanout=2)        0.633   N40
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.D3      net (fanout=6)        0.415   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      5.825ns (2.485ns logic, 3.340ns route)
                                                       (42.7% logic, 57.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.962ns (data path - clock path skew + uncertainty)
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Data Path Delay:      5.803ns (Levels of Logic = 4)
  Clock Path Skew:      1.273ns (5.155 - 3.882)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Maximum Data Path at Slow Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.B        Tshcko                1.106   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM0/DP
    SLICE_X20Y55.C1      net (fanout=1)        1.999   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
    SLICE_X20Y55.CMUX    Tilo                  0.298   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X20Y55.A2      net (fanout=1)        0.725   N16
    SLICE_X20Y55.A       Tilo                  0.235   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X19Y54.A6      net (fanout=5)        0.393   RLINK/RLB_DI<7>
    SLICE_X19Y54.A       Tilo                  0.259   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.D3      net (fanout=6)        0.415   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tas                   0.373   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      5.803ns (2.271ns logic, 3.532ns route)
                                                       (39.1% logic, 60.9% route)

--------------------------------------------------------------------------------

Hold Paths: Unconstrained path analysis

--------------------------------------------------------------------------------
Slack (hold path):      1.872ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.806ns (Levels of Logic = 1)
  Clock Path Skew:      -0.498ns (2.049 - 2.547)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y61.B       Tshcko                0.449   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM0/DP
    SLICE_X15Y61.D4      net (fanout=1)        0.099   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
    SLICE_X15Y61.D       Tilo                  0.156   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB81
    OLOGIC_X0Y55.D1      net (fanout=1)        0.692   RLINK/FX2CNTL/TXFIFO_DO<7>
    OLOGIC_X0Y55.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<7>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    -------------------------------------------------  ---------------------------
    Total                                      1.806ns (1.015ns logic, 0.791ns route)
                                                       (56.2% logic, 43.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.103ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.032ns (Levels of Logic = 1)
  Clock Path Skew:      -0.503ns (2.044 - 2.547)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y61.A       Tshcko                0.441   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X15Y61.C3      net (fanout=1)        0.138   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X15Y61.C       Tilo                  0.156   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB61
    OLOGIC_X0Y53.D1      net (fanout=1)        0.887   RLINK/FX2CNTL/TXFIFO_DO<5>
    OLOGIC_X0Y53.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<5>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    -------------------------------------------------  ---------------------------
    Total                                      2.032ns (1.007ns logic, 1.025ns route)
                                                       (49.6% logic, 50.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.064ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.993ns (Levels of Logic = 1)
  Clock Path Skew:      -0.503ns (2.044 - 2.547)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y61.AMUX    Tshcko                0.490   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X15Y61.C5      net (fanout=1)        0.055   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X15Y61.CMUX    Tilo                  0.203   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB51
    OLOGIC_X0Y50.D1      net (fanout=1)        0.835   RLINK/FX2CNTL/TXFIFO_DO<4>
    OLOGIC_X0Y50.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<4>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    -------------------------------------------------  ---------------------------
    Total                                      1.993ns (1.103ns logic, 0.890ns route)
                                                       (55.3% logic, 44.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.149ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.087ns (Levels of Logic = 1)
  Clock Path Skew:      -0.494ns (2.046 - 2.540)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y58.A       Tshcko                0.441   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X12Y59.D3      net (fanout=1)        0.240   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X12Y59.D       Tilo                  0.142   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB21
    OLOGIC_X0Y49.D1      net (fanout=1)        0.854   RLINK/FX2CNTL/TXFIFO_DO<1>
    OLOGIC_X0Y49.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<1>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    -------------------------------------------------  ---------------------------
    Total                                      2.087ns (0.993ns logic, 1.094ns route)
                                                       (47.6% logic, 52.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.173ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.730ns (Levels of Logic = 3)
  Clock Path Skew:      1.471ns (2.969 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X18Y53.D4      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X18Y53.B6      net (fanout=10)       0.033   RLINK/RLB_DI<2>
    SLICE_X18Y53.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      1.730ns (1.039ns logic, 0.691ns route)
                                                       (60.1% logic, 39.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.113ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.051ns (Levels of Logic = 1)
  Clock Path Skew:      -0.494ns (2.046 - 2.540)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y58.BMUX    Tshcko                0.495   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X15Y58.C1      net (fanout=1)        0.247   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X15Y58.CMUX    Tilo                  0.203   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB31
    OLOGIC_X0Y48.D1      net (fanout=1)        0.696   RLINK/FX2CNTL/TXFIFO_DO<2>
    OLOGIC_X0Y48.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<2>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2
    -------------------------------------------------  ---------------------------
    Total                                      2.051ns (1.108ns logic, 0.943ns route)
                                                       (54.0% logic, 46.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.175ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.116ns (Levels of Logic = 1)
  Clock Path Skew:      -0.491ns (2.049 - 2.540)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y58.AMUX    Tshcko                0.490   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X12Y59.D5      net (fanout=1)        0.201   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X12Y59.DMUX    Tilo                  0.183   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB11
    OLOGIC_X0Y46.D1      net (fanout=1)        0.832   RLINK/FX2CNTL/TXFIFO_DO<0>
    OLOGIC_X0Y46.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<0>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    -------------------------------------------------  ---------------------------
    Total                                      2.116ns (1.083ns logic, 1.033ns route)
                                                       (51.2% logic, 48.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.131ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.066ns (Levels of Logic = 1)
  Clock Path Skew:      -0.497ns (2.046 - 2.543)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y59.BMUX    Tshcko                0.495   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X15Y58.C3      net (fanout=1)        0.262   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X15Y58.CMUX    Tilo                  0.203   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB31
    OLOGIC_X0Y48.D1      net (fanout=1)        0.696   RLINK/FX2CNTL/TXFIFO_DO<2>
    OLOGIC_X0Y48.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<2>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_2
    -------------------------------------------------  ---------------------------
    Total                                      2.066ns (1.108ns logic, 0.958ns route)
                                                       (53.6% logic, 46.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.040ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.863ns (Levels of Logic = 3)
  Clock Path Skew:      1.471ns (2.969 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        0.646   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X18Y53.B5      net (fanout=8)        0.256   RLINK/RLB_DI<1>
    SLICE_X18Y53.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      1.863ns (0.950ns logic, 0.913ns route)
                                                       (51.0% logic, 49.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.012ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.879ns (Levels of Logic = 3)
  Clock Path Skew:      1.459ns (2.966 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.AMUX    Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X22Y54.B4      net (fanout=1)        0.546   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X22Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.203   N2
    SLICE_X19Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X19Y54.C4      net (fanout=6)        0.113   RLINK/RLB_DI<0>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      1.879ns (1.017ns logic, 0.862ns route)
                                                       (54.1% logic, 45.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.072ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.819ns (Levels of Logic = 3)
  Clock Path Skew:      1.459ns (2.966 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.AMUX    Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X22Y54.B4      net (fanout=1)        0.546   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X22Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.203   N2
    SLICE_X19Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X19Y54.C4      net (fanout=6)        0.113   RLINK/RLB_DI<0>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.155   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      1.819ns (0.957ns logic, 0.862ns route)
                                                       (52.6% logic, 47.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.011ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.909ns (Levels of Logic = 3)
  Clock Path Skew:      1.466ns (2.964 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        0.646   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X19Y55.B5      net (fanout=8)        0.284   RLINK/RLB_DI<1>
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      1.909ns (0.968ns logic, 0.941ns route)
                                                       (50.7% logic, 49.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.173ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.106ns (Levels of Logic = 1)
  Clock Path Skew:      -0.499ns (2.044 - 2.543)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y59.B       Tshcko                0.449   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM1/DP
    SLICE_X15Y58.C5      net (fanout=1)        0.272   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
    SLICE_X15Y58.C       Tilo                  0.156   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB41
    OLOGIC_X0Y51.D1      net (fanout=1)        0.819   RLINK/FX2CNTL/TXFIFO_DO<3>
    OLOGIC_X0Y51.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<3>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    -------------------------------------------------  ---------------------------
    Total                                      2.106ns (1.015ns logic, 1.091ns route)
                                                       (48.2% logic, 51.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.014ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.908ns (Levels of Logic = 3)
  Clock Path Skew:      1.462ns (2.969 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        0.691   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X18Y53.B5      net (fanout=8)        0.256   RLINK/RLB_DI<1>
    SLICE_X18Y53.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      1.908ns (0.950ns logic, 0.958ns route)
                                                       (49.8% logic, 50.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.065ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.954ns (Levels of Logic = 3)
  Clock Path Skew:      1.457ns (2.964 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        0.691   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X19Y55.B5      net (fanout=8)        0.284   RLINK/RLB_DI<1>
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      1.954ns (0.968ns logic, 0.986ns route)
                                                       (49.5% logic, 50.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      -0.008ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.892ns (Levels of Logic = 3)
  Clock Path Skew:      1.468ns (2.966 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X18Y53.D4      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X19Y54.D5      net (fanout=10)       0.177   RLINK/RLB_DI<2>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      1.892ns (1.057ns logic, 0.835ns route)
                                                       (55.9% logic, 44.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.240ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.176ns (Levels of Logic = 1)
  Clock Path Skew:      -0.496ns (2.044 - 2.540)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y58.B       Tshcko                0.449   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X15Y58.C2      net (fanout=1)        0.342   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X15Y58.C       Tilo                  0.156   RLINK/FX2CNTL/TXFIFO_DO<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB41
    OLOGIC_X0Y51.D1      net (fanout=1)        0.819   RLINK/FX2CNTL/TXFIFO_DO<3>
    OLOGIC_X0Y51.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<3>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_3
    -------------------------------------------------  ---------------------------
    Total                                      2.176ns (1.015ns logic, 1.161ns route)
                                                       (46.6% logic, 53.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.090ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.990ns (Levels of Logic = 3)
  Clock Path Skew:      1.468ns (2.966 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        0.646   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X19Y54.D2      net (fanout=8)        0.365   RLINK/RLB_DI<1>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      1.990ns (0.968ns logic, 1.022ns route)
                                                       (48.6% logic, 51.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.337ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.272ns (Levels of Logic = 1)
  Clock Path Skew:      -0.497ns (2.046 - 2.543)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y59.A       Tshcko                0.441   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X12Y59.D1      net (fanout=1)        0.425   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X12Y59.D       Tilo                  0.142   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB21
    OLOGIC_X0Y49.D1      net (fanout=1)        0.854   RLINK/FX2CNTL/TXFIFO_DO<1>
    OLOGIC_X0Y49.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<1>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_1
    -------------------------------------------------  ---------------------------
    Total                                      2.272ns (0.993ns logic, 1.279ns route)
                                                       (43.7% logic, 56.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.340ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.278ns (Levels of Logic = 1)
  Clock Path Skew:      -0.494ns (2.049 - 2.543)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y59.AMUX    Tshcko                0.490   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X12Y59.D2      net (fanout=1)        0.363   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X12Y59.DMUX    Tilo                  0.183   RLINK/FX2CNTL/TXFIFO/GCR/GRAY_5.CNT/R_DATA<4>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB11
    OLOGIC_X0Y46.D1      net (fanout=1)        0.832   RLINK/FX2CNTL/TXFIFO_DO<0>
    OLOGIC_X0Y46.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<0>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_0
    -------------------------------------------------  ---------------------------
    Total                                      2.278ns (1.083ns logic, 1.195ns route)
                                                       (47.5% logic, 52.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.144ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.035ns (Levels of Logic = 3)
  Clock Path Skew:      1.459ns (2.966 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        0.691   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X19Y54.D2      net (fanout=8)        0.365   RLINK/RLB_DI<1>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      2.035ns (0.968ns logic, 1.067ns route)
                                                       (47.6% logic, 52.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.125ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.036ns (Levels of Logic = 3)
  Clock Path Skew:      1.479ns (2.977 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        0.646   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.A3      net (fanout=8)        0.411   RLINK/RLB_DI<1>
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      2.036ns (0.968ns logic, 1.068ns route)
                                                       (47.5% logic, 52.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.048ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.942ns (Levels of Logic = 3)
  Clock Path Skew:      1.462ns (2.969 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X18Y53.D2      net (fanout=1)        0.797   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X18Y53.B6      net (fanout=10)       0.033   RLINK/RLB_DI<2>
    SLICE_X18Y53.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      1.942ns (1.039ns logic, 0.903ns route)
                                                       (53.5% logic, 46.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.143ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.037ns (Levels of Logic = 3)
  Clock Path Skew:      1.462ns (2.969 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.AMUX    Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X22Y54.B4      net (fanout=1)        0.546   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X22Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.203   N2
    SLICE_X19Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X18Y53.B3      net (fanout=6)        0.289   RLINK/RLB_DI<0>
    SLICE_X18Y53.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      2.037ns (0.999ns logic, 1.038ns route)
                                                       (49.0% logic, 51.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.179ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.081ns (Levels of Logic = 3)
  Clock Path Skew:      1.470ns (2.977 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        0.691   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.A3      net (fanout=8)        0.411   RLINK/RLB_DI<1>
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      2.081ns (0.968ns logic, 1.113ns route)
                                                       (46.5% logic, 53.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.191ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.091ns (Levels of Logic = 3)
  Clock Path Skew:      1.468ns (2.966 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        0.646   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X19Y54.C3      net (fanout=8)        0.466   RLINK/RLB_DI<1>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      2.091ns (0.968ns logic, 1.123ns route)
                                                       (46.3% logic, 53.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.131ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.031ns (Levels of Logic = 3)
  Clock Path Skew:      1.468ns (2.966 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        0.646   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X19Y54.C3      net (fanout=8)        0.466   RLINK/RLB_DI<1>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.155   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      2.031ns (0.908ns logic, 1.123ns route)
                                                       (44.7% logic, 55.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.196ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.094ns (Levels of Logic = 3)
  Clock Path Skew:      1.466ns (2.964 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        0.646   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X19Y55.D2      net (fanout=8)        0.469   RLINK/RLB_DI<1>
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      2.094ns (0.968ns logic, 1.126ns route)
                                                       (46.2% logic, 53.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.136ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.034ns (Levels of Logic = 3)
  Clock Path Skew:      1.466ns (2.964 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X18Y53.D4      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X19Y55.D3      net (fanout=10)       0.319   RLINK/RLB_DI<2>
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      2.034ns (1.057ns logic, 0.977ns route)
                                                       (52.0% logic, 48.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.185ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.076ns (Levels of Logic = 3)
  Clock Path Skew:      1.459ns (2.966 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        0.691   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X19Y54.C3      net (fanout=8)        0.466   RLINK/RLB_DI<1>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.155   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      2.076ns (0.908ns logic, 1.168ns route)
                                                       (43.7% logic, 56.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.245ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.136ns (Levels of Logic = 3)
  Clock Path Skew:      1.459ns (2.966 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        0.691   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X19Y54.C3      net (fanout=8)        0.466   RLINK/RLB_DI<1>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      2.136ns (0.968ns logic, 1.168ns route)
                                                       (45.3% logic, 54.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.250ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.139ns (Levels of Logic = 3)
  Clock Path Skew:      1.457ns (2.964 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        0.691   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X19Y55.D2      net (fanout=8)        0.469   RLINK/RLB_DI<1>
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      2.139ns (0.968ns logic, 1.171ns route)
                                                       (45.3% logic, 54.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.136ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.047ns (Levels of Logic = 4)
  Clock Path Skew:      1.479ns (2.977 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        0.646   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X22Y54.D6      net (fanout=8)        0.273   RLINK/RLB_DI<1>
    SLICE_X22Y54.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/_n0059_SW0
    SLICE_X22Y54.C6      net (fanout=1)        0.011   N44
    SLICE_X22Y54.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.047ns (1.106ns logic, 0.941ns route)
                                                       (54.0% logic, 46.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.282ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.173ns (Levels of Logic = 3)
  Clock Path Skew:      1.459ns (2.966 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.AMUX    Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X22Y54.B4      net (fanout=1)        0.546   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X22Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.203   N2
    SLICE_X19Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X19Y54.D1      net (fanout=6)        0.407   RLINK/RLB_DI<0>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      2.173ns (1.017ns logic, 1.156ns route)
                                                       (46.8% logic, 53.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.190ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.092ns (Levels of Logic = 4)
  Clock Path Skew:      1.470ns (2.977 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        0.691   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X22Y54.D6      net (fanout=8)        0.273   RLINK/RLB_DI<1>
    SLICE_X22Y54.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/_n0059_SW0
    SLICE_X22Y54.C6      net (fanout=1)        0.011   N44
    SLICE_X22Y54.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.092ns (1.106ns logic, 0.986ns route)
                                                       (52.9% logic, 47.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.213ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.104ns (Levels of Logic = 3)
  Clock Path Skew:      1.459ns (2.966 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X18Y53.D2      net (fanout=1)        0.797   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X19Y54.D5      net (fanout=10)       0.177   RLINK/RLB_DI<2>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      2.104ns (1.057ns logic, 1.047ns route)
                                                       (50.2% logic, 49.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.205ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.105ns (Levels of Logic = 3)
  Clock Path Skew:      1.468ns (2.966 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X18Y53.D4      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X19Y54.C1      net (fanout=10)       0.390   RLINK/RLB_DI<2>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      2.105ns (1.057ns logic, 1.048ns route)
                                                       (50.2% logic, 49.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.145ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.045ns (Levels of Logic = 3)
  Clock Path Skew:      1.468ns (2.966 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X18Y53.D4      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X19Y54.C1      net (fanout=10)       0.390   RLINK/RLB_DI<2>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.155   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      2.045ns (0.997ns logic, 1.048ns route)
                                                       (48.8% logic, 51.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.312ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.181ns (Levels of Logic = 3)
  Clock Path Skew:      1.437ns (2.964 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.AMUX     Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X18Y54.D5      net (fanout=1)        0.892   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X18Y54.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X19Y55.A3      net (fanout=1)        0.247   N10
    SLICE_X19Y55.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X19Y55.B6      net (fanout=4)        0.025   RLINK/RLB_DI<4>
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      2.181ns (1.017ns logic, 1.164ns route)
                                                       (46.6% logic, 53.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.221ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.119ns (Levels of Logic = 3)
  Clock Path Skew:      1.466ns (2.964 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X18Y53.D4      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X19Y55.B1      net (fanout=10)       0.404   RLINK/RLB_DI<2>
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      2.119ns (1.057ns logic, 1.062ns route)
                                                       (49.9% logic, 50.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.496ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.425ns (Levels of Logic = 1)
  Clock Path Skew:      -0.503ns (2.044 - 2.547)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y61.BMUX    Tshcko                0.495   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X15Y61.D5      net (fanout=1)        0.513   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X15Y61.DMUX    Tilo                  0.203   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB71
    OLOGIC_X0Y52.D1      net (fanout=1)        0.804   RLINK/FX2CNTL/TXFIFO_DO<6>
    OLOGIC_X0Y52.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<6>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    -------------------------------------------------  ---------------------------
    Total                                      2.425ns (1.108ns logic, 1.317ns route)
                                                       (45.7% logic, 54.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.234ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.134ns (Levels of Logic = 3)
  Clock Path Skew:      1.468ns (2.966 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.B       Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP
    SLICE_X22Y54.B5      net (fanout=1)        0.580   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
    SLICE_X22Y54.BMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X22Y54.A3      net (fanout=1)        0.153   N8
    SLICE_X22Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X19Y54.D4      net (fanout=3)        0.390   RLINK/RLB_DI<3>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      2.134ns (1.011ns logic, 1.123ns route)
                                                       (47.4% logic, 52.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.270ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.170ns (Levels of Logic = 3)
  Clock Path Skew:      1.468ns (2.966 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.AMUX    Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X22Y54.B1      net (fanout=1)        0.897   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X22Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.203   N2
    SLICE_X19Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X19Y54.C4      net (fanout=6)        0.113   RLINK/RLB_DI<0>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.155   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      2.170ns (0.957ns logic, 1.213ns route)
                                                       (44.1% logic, 55.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.330ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.230ns (Levels of Logic = 3)
  Clock Path Skew:      1.468ns (2.966 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.AMUX    Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X22Y54.B1      net (fanout=1)        0.897   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X22Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.203   N2
    SLICE_X19Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X19Y54.C4      net (fanout=6)        0.113   RLINK/RLB_DI<0>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      2.230ns (1.017ns logic, 1.213ns route)
                                                       (45.6% logic, 54.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.140ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.051ns (Levels of Logic = 4)
  Clock Path Skew:      1.479ns (2.977 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.B       Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP
    SLICE_X22Y54.B5      net (fanout=1)        0.580   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
    SLICE_X22Y54.BMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X22Y54.A3      net (fanout=1)        0.153   N8
    SLICE_X22Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X22Y54.D3      net (fanout=3)        0.158   RLINK/RLB_DI<3>
    SLICE_X22Y54.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/_n0059_SW0
    SLICE_X22Y54.C6      net (fanout=1)        0.011   N44
    SLICE_X22Y54.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.051ns (1.149ns logic, 0.902ns route)
                                                       (56.0% logic, 44.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.615ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.539ns (Levels of Logic = 1)
  Clock Path Skew:      -0.508ns (2.044 - 2.552)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X22Y63.A       Tshcko                0.441   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[5].MEM1/DP
    SLICE_X15Y61.C2      net (fanout=1)        0.645   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<5>
    SLICE_X15Y61.C       Tilo                  0.156   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB61
    OLOGIC_X0Y53.D1      net (fanout=1)        0.887   RLINK/FX2CNTL/TXFIFO_DO<5>
    OLOGIC_X0Y53.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<5>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_5
    -------------------------------------------------  ---------------------------
    Total                                      2.539ns (1.007ns logic, 1.532ns route)
                                                       (39.7% logic, 60.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.550ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.479ns (Levels of Logic = 1)
  Clock Path Skew:      -0.503ns (2.049 - 2.552)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X22Y63.B       Tshcko                0.449   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[7].MEM1/DP
    SLICE_X15Y61.D1      net (fanout=1)        0.772   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
    SLICE_X15Y61.D       Tilo                  0.156   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB81
    OLOGIC_X0Y55.D1      net (fanout=1)        0.692   RLINK/FX2CNTL/TXFIFO_DO<7>
    OLOGIC_X0Y55.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<7>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_7
    -------------------------------------------------  ---------------------------
    Total                                      2.479ns (1.015ns logic, 1.464ns route)
                                                       (40.9% logic, 59.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.419ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.288ns (Levels of Logic = 3)
  Clock Path Skew:      1.437ns (2.964 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.AMUX     Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[4].MEM0/DP
    SLICE_X18Y54.D2      net (fanout=1)        0.999   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<4>
    SLICE_X18Y54.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI5_SW0
    SLICE_X19Y55.A3      net (fanout=1)        0.247   N10
    SLICE_X19Y55.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/RLBMUX/Mmux_RLB_DI5
    SLICE_X19Y55.B6      net (fanout=4)        0.025   RLINK/RLB_DI<4>
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      2.288ns (1.017ns logic, 1.271ns route)
                                                       (44.4% logic, 55.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.334ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.245ns (Levels of Logic = 3)
  Clock Path Skew:      1.479ns (2.977 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X18Y53.D4      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X23Y54.B2      net (fanout=10)       0.530   RLINK/RLB_DI<2>
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.245ns (1.057ns logic, 1.188ns route)
                                                       (47.1% logic, 52.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.357ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.246ns (Levels of Logic = 3)
  Clock Path Skew:      1.457ns (2.964 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X18Y53.D2      net (fanout=1)        0.797   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X19Y55.D3      net (fanout=10)       0.319   RLINK/RLB_DI<2>
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      2.246ns (1.057ns logic, 1.189ns route)
                                                       (47.1% logic, 52.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.238ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.149ns (Levels of Logic = 4)
  Clock Path Skew:      1.479ns (2.977 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.B       Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM1/DP
    SLICE_X22Y54.B5      net (fanout=1)        0.580   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
    SLICE_X22Y54.BMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X22Y54.A3      net (fanout=1)        0.153   N8
    SLICE_X22Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X23Y54.C3      net (fanout=3)        0.145   RLINK/RLB_DI<3>
    SLICE_X23Y54.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X23Y54.B4      net (fanout=2)        0.104   N40
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.149ns (1.167ns logic, 0.982ns route)
                                                       (54.3% logic, 45.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.445ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.327ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.977 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X18Y54.D4      net (fanout=1)        0.827   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X18Y54.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X18Y54.C4      net (fanout=2)        0.149   N12
    SLICE_X18Y54.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X23Y54.B5      net (fanout=4)        0.348   RLINK/RLB_DI<5>
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.327ns (1.003ns logic, 1.324ns route)
                                                       (43.1% logic, 56.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.362ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.264ns (Levels of Logic = 4)
  Clock Path Skew:      1.470ns (2.977 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.AMUX    Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X22Y54.B4      net (fanout=1)        0.546   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X22Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.203   N2
    SLICE_X19Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X22Y54.D4      net (fanout=6)        0.349   RLINK/RLB_DI<0>
    SLICE_X22Y54.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/_n0059_SW0
    SLICE_X22Y54.C6      net (fanout=1)        0.011   N44
    SLICE_X22Y54.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.264ns (1.155ns logic, 1.109ns route)
                                                       (51.0% logic, 49.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.577ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.446ns (Levels of Logic = 2)
  Clock Path Skew:      1.437ns (2.964 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X18Y54.D4      net (fanout=1)        0.827   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X18Y54.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X19Y55.C6      net (fanout=2)        0.772   N12
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata61
                                                       RLINK/CORE/B2CD/R_REGS_data_5
    -------------------------------------------------  ---------------------------
    Total                                      2.446ns (0.847ns logic, 1.599ns route)
                                                       (34.6% logic, 65.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.397ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.268ns (Levels of Logic = 4)
  Clock Path Skew:      1.439ns (2.966 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X18Y54.D4      net (fanout=1)        0.827   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X18Y54.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X18Y54.C4      net (fanout=2)        0.149   N12
    SLICE_X18Y54.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X18Y54.B6      net (fanout=4)        0.088   RLINK/RLB_DI<5>
    SLICE_X18Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.A5      net (fanout=1)        0.063   RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      2.268ns (1.141ns logic, 1.127ns route)
                                                       (50.3% logic, 49.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.485ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.354ns (Levels of Logic = 3)
  Clock Path Skew:      1.437ns (2.964 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X20Y55.C2      net (fanout=1)        0.880   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X20Y55.C       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X20Y55.B4      net (fanout=1)        0.114   N14
    SLICE_X20Y55.B       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X19Y55.D1      net (fanout=5)        0.366   RLINK/RLB_DI<6>
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      2.354ns (0.994ns logic, 1.360ns route)
                                                       (42.2% logic, 57.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.366ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.257ns (Levels of Logic = 3)
  Clock Path Skew:      1.459ns (2.966 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X18Y53.D2      net (fanout=1)        0.797   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X19Y54.C1      net (fanout=10)       0.390   RLINK/RLB_DI<2>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.155   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      2.257ns (0.997ns logic, 1.260ns route)
                                                       (44.2% logic, 55.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.426ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.317ns (Levels of Logic = 3)
  Clock Path Skew:      1.459ns (2.966 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X18Y53.D2      net (fanout=1)        0.797   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X19Y54.C1      net (fanout=10)       0.390   RLINK/RLB_DI<2>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      2.317ns (1.057ns logic, 1.260ns route)
                                                       (45.6% logic, 54.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.479ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.361ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.977 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X20Y55.C2      net (fanout=1)        0.880   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X20Y55.C       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X20Y55.B4      net (fanout=1)        0.114   N14
    SLICE_X20Y55.B       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X23Y54.B3      net (fanout=5)        0.373   RLINK/RLB_DI<6>
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.361ns (0.994ns logic, 1.367ns route)
                                                       (42.1% logic, 57.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.442ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.331ns (Levels of Logic = 3)
  Clock Path Skew:      1.457ns (2.964 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X18Y53.D2      net (fanout=1)        0.797   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X19Y55.B1      net (fanout=10)       0.404   RLINK/RLB_DI<2>
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      2.331ns (1.057ns logic, 1.274ns route)
                                                       (45.3% logic, 54.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.485ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.388ns (Levels of Logic = 3)
  Clock Path Skew:      1.471ns (2.969 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.AMUX    Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X22Y54.B1      net (fanout=1)        0.897   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X22Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.203   N2
    SLICE_X19Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X18Y53.B3      net (fanout=6)        0.289   RLINK/RLB_DI<0>
    SLICE_X18Y53.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      2.388ns (0.999ns logic, 1.389ns route)
                                                       (41.8% logic, 58.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.755ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.679ns (Levels of Logic = 1)
  Clock Path Skew:      -0.508ns (2.044 - 2.552)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X22Y63.AMUX    Tshcko                0.490   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[4].MEM1/DP
    SLICE_X15Y61.C1      net (fanout=1)        0.741   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<4>
    SLICE_X15Y61.CMUX    Tilo                  0.203   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB51
    OLOGIC_X0Y50.D1      net (fanout=1)        0.835   RLINK/FX2CNTL/TXFIFO_DO<4>
    OLOGIC_X0Y50.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<4>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_4
    -------------------------------------------------  ---------------------------
    Total                                      2.679ns (1.103ns logic, 1.576ns route)
                                                       (41.2% logic, 58.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.465ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.376ns (Levels of Logic = 3)
  Clock Path Skew:      1.479ns (2.977 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X18Y53.D4      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X23Y54.A2      net (fanout=10)       0.661   RLINK/RLB_DI<2>
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      2.376ns (1.057ns logic, 1.319ns route)
                                                       (44.5% logic, 55.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.459ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.361ns (Levels of Logic = 4)
  Clock Path Skew:      1.470ns (2.977 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.AMUX    Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X22Y54.B4      net (fanout=1)        0.546   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X22Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.203   N2
    SLICE_X19Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X23Y54.C4      net (fanout=6)        0.335   RLINK/RLB_DI<0>
    SLICE_X23Y54.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X23Y54.B4      net (fanout=2)        0.104   N40
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.361ns (1.173ns logic, 1.188ns route)
                                                       (49.7% logic, 50.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.519ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.401ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.977 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.B        Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP
    SLICE_X20Y55.C5      net (fanout=1)        0.880   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
    SLICE_X20Y55.CMUX    Tilo                  0.183   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X20Y55.A2      net (fanout=1)        0.372   N16
    SLICE_X20Y55.A       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X23Y54.B6      net (fanout=5)        0.160   RLINK/RLB_DI<7>
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.401ns (0.989ns logic, 1.412ns route)
                                                       (41.2% logic, 58.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.583ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.465ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.977 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP
    SLICE_X18Y54.D3      net (fanout=1)        0.965   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<5>
    SLICE_X18Y54.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X18Y54.C4      net (fanout=2)        0.149   N12
    SLICE_X18Y54.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X23Y54.B5      net (fanout=4)        0.348   RLINK/RLB_DI<5>
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.465ns (1.003ns logic, 1.462ns route)
                                                       (40.7% logic, 59.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.547ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.429ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.977 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X20Y55.C2      net (fanout=1)        0.880   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X20Y55.C       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X20Y55.B4      net (fanout=1)        0.114   N14
    SLICE_X20Y55.B       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X22Y54.C2      net (fanout=5)        0.459   RLINK/RLB_DI<6>
    SLICE_X22Y54.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.429ns (0.976ns logic, 1.453ns route)
                                                       (40.2% logic, 59.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.523ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.414ns (Levels of Logic = 3)
  Clock Path Skew:      1.459ns (2.966 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.B       Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X22Y54.B3      net (fanout=1)        0.860   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X22Y54.BMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X22Y54.A3      net (fanout=1)        0.153   N8
    SLICE_X22Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X19Y54.D4      net (fanout=3)        0.390   RLINK/RLB_DI<3>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      2.414ns (1.011ns logic, 1.403ns route)
                                                       (41.9% logic, 58.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.609ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.478ns (Levels of Logic = 3)
  Clock Path Skew:      1.437ns (2.964 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP
    SLICE_X20Y55.C3      net (fanout=1)        1.004   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<6>
    SLICE_X20Y55.C       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X20Y55.B4      net (fanout=1)        0.114   N14
    SLICE_X20Y55.B       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X19Y55.D1      net (fanout=5)        0.366   RLINK/RLB_DI<6>
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      2.478ns (0.994ns logic, 1.484ns route)
                                                       (40.1% logic, 59.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.715ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.584ns (Levels of Logic = 2)
  Clock Path Skew:      1.437ns (2.964 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP
    SLICE_X18Y54.D3      net (fanout=1)        0.965   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<5>
    SLICE_X18Y54.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X19Y55.C6      net (fanout=2)        0.772   N12
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata61
                                                       RLINK/CORE/B2CD/R_REGS_data_5
    -------------------------------------------------  ---------------------------
    Total                                      2.584ns (0.847ns logic, 1.737ns route)
                                                       (32.8% logic, 67.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.603ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.485ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.977 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP
    SLICE_X20Y55.C3      net (fanout=1)        1.004   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<6>
    SLICE_X20Y55.C       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X20Y55.B4      net (fanout=1)        0.114   N14
    SLICE_X20Y55.B       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X23Y54.B3      net (fanout=5)        0.373   RLINK/RLB_DI<6>
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.485ns (0.994ns logic, 1.491ns route)
                                                       (40.0% logic, 60.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.535ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.406ns (Levels of Logic = 4)
  Clock Path Skew:      1.439ns (2.966 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM1/DP
    SLICE_X18Y54.D3      net (fanout=1)        0.965   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<5>
    SLICE_X18Y54.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X18Y54.C4      net (fanout=2)        0.149   N12
    SLICE_X18Y54.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X18Y54.B6      net (fanout=4)        0.088   RLINK/RLB_DI<5>
    SLICE_X18Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.A5      net (fanout=1)        0.063   RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      2.406ns (1.141ns logic, 1.265ns route)
                                                       (47.4% logic, 52.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.518ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.389ns (Levels of Logic = 4)
  Clock Path Skew:      1.439ns (2.966 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X20Y55.C2      net (fanout=1)        0.880   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X20Y55.C       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X20Y55.B4      net (fanout=1)        0.114   N14
    SLICE_X20Y55.B       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X18Y54.B5      net (fanout=5)        0.200   RLINK/RLB_DI<6>
    SLICE_X18Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.A5      net (fanout=1)        0.063   RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      2.389ns (1.132ns logic, 1.257ns route)
                                                       (47.4% logic, 52.6% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.552ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.421ns (Levels of Logic = 4)
  Clock Path Skew:      1.437ns (2.964 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X18Y54.D4      net (fanout=1)        0.827   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X18Y54.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X18Y54.C4      net (fanout=2)        0.149   N12
    SLICE_X18Y54.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X19Y54.A4      net (fanout=4)        0.108   RLINK/RLB_DI<5>
    SLICE_X19Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.D5      net (fanout=6)        0.178   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      2.421ns (1.159ns logic, 1.262ns route)
                                                       (47.9% logic, 52.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.539ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.421ns (Levels of Logic = 4)
  Clock Path Skew:      1.450ns (2.977 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X18Y54.D4      net (fanout=1)        0.827   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X18Y54.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X18Y54.C4      net (fanout=2)        0.149   N12
    SLICE_X18Y54.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X19Y54.A4      net (fanout=4)        0.108   RLINK/RLB_DI<5>
    SLICE_X19Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.A6      net (fanout=6)        0.178   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      2.421ns (1.159ns logic, 1.262ns route)
                                                       (47.9% logic, 52.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.624ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.524ns (Levels of Logic = 3)
  Clock Path Skew:      1.468ns (2.966 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.AMUX    Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM1/DP
    SLICE_X22Y54.B1      net (fanout=1)        0.897   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<0>
    SLICE_X22Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.203   N2
    SLICE_X19Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X19Y54.D1      net (fanout=6)        0.407   RLINK/RLB_DI<0>
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      2.524ns (1.017ns logic, 1.507ns route)
                                                       (40.3% logic, 59.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.429ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.331ns (Levels of Logic = 4)
  Clock Path Skew:      1.470ns (2.977 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.B       Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X22Y54.B3      net (fanout=1)        0.860   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X22Y54.BMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X22Y54.A3      net (fanout=1)        0.153   N8
    SLICE_X22Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X22Y54.D3      net (fanout=3)        0.158   RLINK/RLB_DI<3>
    SLICE_X22Y54.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/_n0059_SW0
    SLICE_X22Y54.C6      net (fanout=1)        0.011   N44
    SLICE_X22Y54.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.331ns (1.149ns logic, 1.182ns route)
                                                       (49.3% logic, 50.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.555ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.457ns (Levels of Logic = 3)
  Clock Path Skew:      1.470ns (2.977 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM0/DP
    SLICE_X18Y53.D2      net (fanout=1)        0.797   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X23Y54.B2      net (fanout=10)       0.530   RLINK/RLB_DI<2>
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.457ns (1.057ns logic, 1.400ns route)
                                                       (43.0% logic, 57.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.562ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.433ns (Levels of Logic = 4)
  Clock Path Skew:      1.439ns (2.966 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X18Y54.D4      net (fanout=1)        0.827   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X18Y54.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X18Y54.C4      net (fanout=2)        0.149   N12
    SLICE_X18Y54.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X19Y54.A4      net (fanout=4)        0.108   RLINK/RLB_DI<5>
    SLICE_X19Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.D3      net (fanout=6)        0.190   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      2.433ns (1.159ns logic, 1.274ns route)
                                                       (47.6% logic, 52.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      2.829ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM1/DP (RAM)
  Destination:          RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.753ns (Levels of Logic = 1)
  Clock Path Skew:      -0.508ns (2.044 - 2.552)
  Source Clock:         CLK rising
  Destination Clock:    I_FX2_IFCLK_BUFGP rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM1/DP to RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X22Y63.BMUX    Tshcko                0.495   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/AW_5.GL[6].MEM1/DP
    SLICE_X15Y61.D2      net (fanout=1)        0.841   RLINK/FX2CNTL/TXFIFO/RAM/AW_5.DOB1<6>
    SLICE_X15Y61.DMUX    Tilo                  0.203   RLINK/FX2CNTL/TXFIFO/R_REGW_raddr_c<3>
                                                       RLINK/FX2CNTL/TXFIFO/RAM/Mmux_DOB71
    OLOGIC_X0Y52.D1      net (fanout=1)        0.804   RLINK/FX2CNTL/TXFIFO_DO<6>
    OLOGIC_X0Y52.CLK0    Tockd       (-Th)    -0.410   RLINK/FX2CNTL/IOB_FX2_DATA/R_DO<6>
                                                       RLINK/FX2CNTL/IOB_FX2_DATA/R_DO_6
    -------------------------------------------------  ---------------------------
    Total                                      2.753ns (1.108ns logic, 1.645ns route)
                                                       (40.2% logic, 59.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.570ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.481ns (Levels of Logic = 4)
  Clock Path Skew:      1.479ns (2.977 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM1/DP
    SLICE_X18Y53.D3      net (fanout=1)        0.646   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        0.596   RLINK/RLB_DI<1>
    SLICE_X23Y54.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X23Y54.B4      net (fanout=2)        0.104   N40
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.481ns (1.124ns logic, 1.357ns route)
                                                       (45.3% logic, 54.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.578ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.452ns (Levels of Logic = 4)
  Clock Path Skew:      1.442ns (2.969 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X18Y54.D4      net (fanout=1)        0.827   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X18Y54.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X18Y54.C4      net (fanout=2)        0.149   N12
    SLICE_X18Y54.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X19Y54.A4      net (fanout=4)        0.108   RLINK/RLB_DI<5>
    SLICE_X19Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.B4      net (fanout=6)        0.227   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      2.452ns (1.141ns logic, 1.311ns route)
                                                       (46.5% logic, 53.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.601ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.470ns (Levels of Logic = 4)
  Clock Path Skew:      1.437ns (2.964 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X18Y54.D4      net (fanout=1)        0.827   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X18Y54.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X18Y54.C4      net (fanout=2)        0.149   N12
    SLICE_X18Y54.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X19Y54.A4      net (fanout=4)        0.108   RLINK/RLB_DI<5>
    SLICE_X19Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.B4      net (fanout=6)        0.227   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      2.470ns (1.159ns logic, 1.311ns route)
                                                       (46.9% logic, 53.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.490ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.401ns (Levels of Logic = 4)
  Clock Path Skew:      1.479ns (2.977 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X18Y53.D4      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X22Y54.D2      net (fanout=10)       0.537   RLINK/RLB_DI<2>
    SLICE_X22Y54.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/_n0059_SW0
    SLICE_X22Y54.C6      net (fanout=1)        0.011   N44
    SLICE_X22Y54.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.401ns (1.195ns logic, 1.206ns route)
                                                       (49.8% logic, 50.2% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.534ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.432ns (Levels of Logic = 4)
  Clock Path Skew:      1.466ns (2.964 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X18Y53.D4      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X19Y54.A2      net (fanout=10)       0.383   RLINK/RLB_DI<2>
    SLICE_X19Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.D5      net (fanout=6)        0.178   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      2.432ns (1.213ns logic, 1.219ns route)
                                                       (49.9% logic, 50.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.521ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.432ns (Levels of Logic = 4)
  Clock Path Skew:      1.479ns (2.977 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X18Y53.D4      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X19Y54.A2      net (fanout=10)       0.383   RLINK/RLB_DI<2>
    SLICE_X19Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.A6      net (fanout=6)        0.178   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      2.432ns (1.213ns logic, 1.219ns route)
                                                       (49.9% logic, 50.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.624ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.526ns (Levels of Logic = 4)
  Clock Path Skew:      1.470ns (2.977 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.A       Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[1].MEM0/DP
    SLICE_X18Y53.D5      net (fanout=1)        0.691   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<1>
    SLICE_X18Y53.D       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2_SW0
    SLICE_X18Y53.C6      net (fanout=1)        0.011   N4
    SLICE_X18Y53.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI2
    SLICE_X23Y54.C1      net (fanout=8)        0.596   RLINK/RLB_DI<1>
    SLICE_X23Y54.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X23Y54.B4      net (fanout=2)        0.104   N40
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.526ns (1.124ns logic, 1.402ns route)
                                                       (44.5% logic, 55.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.707ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.596ns (Levels of Logic = 3)
  Clock Path Skew:      1.457ns (2.964 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.AMUX    Tshcko                0.490   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[0].MEM0/DP
    SLICE_X22Y54.B4      net (fanout=1)        0.546   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<0>
    SLICE_X22Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI1_SW0
    SLICE_X19Y54.B5      net (fanout=1)        0.203   N2
    SLICE_X19Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/RLBMUX/Mmux_RLB_DI1
    SLICE_X19Y55.B2      net (fanout=6)        0.830   RLINK/RLB_DI<0>
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      2.596ns (1.017ns logic, 1.579ns route)
                                                       (39.2% logic, 60.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.544ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.444ns (Levels of Logic = 4)
  Clock Path Skew:      1.468ns (2.966 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X18Y53.D4      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X19Y54.A2      net (fanout=10)       0.383   RLINK/RLB_DI<2>
    SLICE_X19Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.D3      net (fanout=6)        0.190   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata41
                                                       RLINK/CORE/B2CD/R_REGS_data_3
    -------------------------------------------------  ---------------------------
    Total                                      2.444ns (1.213ns logic, 1.231ns route)
                                                       (49.6% logic, 50.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.671ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.553ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.977 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP
    SLICE_X20Y55.C3      net (fanout=1)        1.004   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<6>
    SLICE_X20Y55.C       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X20Y55.B4      net (fanout=1)        0.114   N14
    SLICE_X20Y55.B       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X22Y54.C2      net (fanout=5)        0.459   RLINK/RLB_DI<6>
    SLICE_X22Y54.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.553ns (0.976ns logic, 1.577ns route)
                                                       (38.2% logic, 61.8% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.527ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_8 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.429ns (Levels of Logic = 4)
  Clock Path Skew:      1.470ns (2.977 - 1.507)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_8
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y54.B       Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[3].MEM0/DP
    SLICE_X22Y54.B3      net (fanout=1)        0.860   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<3>
    SLICE_X22Y54.BMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4_SW0
    SLICE_X22Y54.A3      net (fanout=1)        0.153   N8
    SLICE_X22Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/RLBMUX/Mmux_RLB_DI4
    SLICE_X23Y54.C3      net (fanout=3)        0.145   RLINK/RLB_DI<3>
    SLICE_X23Y54.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o_SW0
    SLICE_X23Y54.B4      net (fanout=2)        0.104   N40
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata91
                                                       RLINK/CORE/B2CD/R_REGS_data_8
    -------------------------------------------------  ---------------------------
    Total                                      2.429ns (1.167ns logic, 1.262ns route)
                                                       (48.0% logic, 52.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.585ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.456ns (Levels of Logic = 4)
  Clock Path Skew:      1.439ns (2.966 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X18Y54.D4      net (fanout=1)        0.827   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X18Y54.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X18Y54.C4      net (fanout=2)        0.149   N12
    SLICE_X18Y54.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X19Y54.A4      net (fanout=4)        0.108   RLINK/RLB_DI<5>
    SLICE_X19Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.273   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.155   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata31
                                                       RLINK/CORE/B2CD/R_REGS_data_2
    -------------------------------------------------  ---------------------------
    Total                                      2.456ns (1.099ns logic, 1.357ns route)
                                                       (44.7% logic, 55.3% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.645ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.516ns (Levels of Logic = 4)
  Clock Path Skew:      1.439ns (2.966 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.A        Tshcko                0.441   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[5].MEM0/DP
    SLICE_X18Y54.D4      net (fanout=1)        0.827   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<5>
    SLICE_X18Y54.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6_SW0
    SLICE_X18Y54.C4      net (fanout=2)        0.149   N12
    SLICE_X18Y54.C       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/RLBMUX/Mmux_RLB_DI6
    SLICE_X19Y54.A4      net (fanout=4)        0.108   RLINK/RLB_DI<5>
    SLICE_X19Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.C2      net (fanout=6)        0.273   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata21
                                                       RLINK/CORE/B2CD/R_REGS_data_1
    -------------------------------------------------  ---------------------------
    Total                                      2.516ns (1.159ns logic, 1.357ns route)
                                                       (46.1% logic, 53.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.652ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_edpend (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.534ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.977 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP to RLINK/CORE/B2CD/R_REGS_edpend
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.B        Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP
    SLICE_X20Y55.C5      net (fanout=1)        0.880   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
    SLICE_X20Y55.CMUX    Tilo                  0.183   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X20Y55.A2      net (fanout=1)        0.372   N16
    SLICE_X20Y55.A       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X22Y54.C3      net (fanout=5)        0.311   RLINK/RLB_DI<7>
    SLICE_X22Y54.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_edpend
                                                       RLINK/CORE/B2CD/R_REGS_edpend_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_edpend
    -------------------------------------------------  ---------------------------
    Total                                      2.534ns (0.971ns logic, 1.563ns route)
                                                       (38.3% logic, 61.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.678ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.560ns (Levels of Logic = 3)
  Clock Path Skew:      1.450ns (2.977 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.B        Tshcko                0.449   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[7].MEM1/DP
    SLICE_X20Y55.C5      net (fanout=1)        0.880   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
    SLICE_X20Y55.CMUX    Tilo                  0.183   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8_SW0
    SLICE_X20Y55.A2      net (fanout=1)        0.372   N16
    SLICE_X20Y55.A       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI8
    SLICE_X23Y54.A4      net (fanout=5)        0.319   RLINK/RLB_DI<7>
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      2.560ns (0.989ns logic, 1.571ns route)
                                                       (38.6% logic, 61.4% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.583ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.481ns (Levels of Logic = 4)
  Clock Path Skew:      1.466ns (2.964 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X18Y53.D4      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X19Y54.A2      net (fanout=10)       0.383   RLINK/RLB_DI<2>
    SLICE_X19Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.B4      net (fanout=6)        0.227   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata51
                                                       RLINK/CORE/B2CD/R_REGS_data_4
    -------------------------------------------------  ---------------------------
    Total                                      2.481ns (1.213ns logic, 1.268ns route)
                                                       (48.9% logic, 51.1% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.560ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.463ns (Levels of Logic = 4)
  Clock Path Skew:      1.471ns (2.969 - 1.498)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP to RLINK/CORE/B2CD/R_REGS_data_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X14Y54.BMUX    Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<3>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[2].MEM1/DP
    SLICE_X18Y53.D4      net (fanout=1)        0.585   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<2>
    SLICE_X18Y53.DMUX    Tilo                  0.191   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3_SW0
    SLICE_X18Y53.A5      net (fanout=1)        0.073   N6
    SLICE_X18Y53.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/RLBMUX/Mmux_RLB_DI3
    SLICE_X19Y54.A2      net (fanout=10)       0.383   RLINK/RLB_DI<2>
    SLICE_X19Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.B4      net (fanout=6)        0.227   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X18Y53.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_data<0>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata11
                                                       RLINK/CORE/B2CD/R_REGS_data_0
    -------------------------------------------------  ---------------------------
    Total                                      2.463ns (1.195ns logic, 1.268ns route)
                                                       (48.5% logic, 51.5% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.642ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_dataval (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.513ns (Levels of Logic = 4)
  Clock Path Skew:      1.439ns (2.966 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP to RLINK/CORE/B2CD/R_REGS_dataval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y54.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM1/DP
    SLICE_X20Y55.C3      net (fanout=1)        1.004   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB1<6>
    SLICE_X20Y55.C       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X20Y55.B4      net (fanout=1)        0.114   N14
    SLICE_X20Y55.B       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X18Y54.B5      net (fanout=5)        0.200   RLINK/RLB_DI<6>
    SLICE_X18Y54.B       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.A5      net (fanout=1)        0.063   RLINK/CORE/B2CD/PWR_60_o_INV_189_o
    SLICE_X18Y54.CLK     Tah         (-Th)    -0.197   RLINK/CORE/B2CD/R_REGS_dataval
                                                       RLINK/CORE/B2CD/R_REGS_dataval_glue_set
                                                       RLINK/CORE/B2CD/R_REGS_dataval
    -------------------------------------------------  ---------------------------
    Total                                      2.513ns (1.132ns logic, 1.381ns route)
                                                       (45.0% logic, 55.0% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.654ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.536ns (Levels of Logic = 4)
  Clock Path Skew:      1.450ns (2.977 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X20Y55.C2      net (fanout=1)        0.880   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X20Y55.C       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X20Y55.B4      net (fanout=1)        0.114   N14
    SLICE_X20Y55.B       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X19Y54.A5      net (fanout=5)        0.214   RLINK/RLB_DI<6>
    SLICE_X19Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.A6      net (fanout=6)        0.178   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X23Y54.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<8>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata81
                                                       RLINK/CORE/B2CD/R_REGS_data_7
    -------------------------------------------------  ---------------------------
    Total                                      2.536ns (1.150ns logic, 1.386ns route)
                                                       (45.3% logic, 54.7% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.667ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP (RAM)
  Destination:          RLINK/CORE/B2CD/R_REGS_data_6 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.536ns (Levels of Logic = 4)
  Clock Path Skew:      1.437ns (2.964 - 1.527)
  Source Clock:         I_FX2_IFCLK_BUFGP rising
  Destination Clock:    CLK rising
  Clock Uncertainty:    0.432ns

  Clock Uncertainty:          0.432ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.494ns
    Phase Error (PE):           0.150ns

  Minimum Data Path at Fast Process Corner: RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP to RLINK/CORE/B2CD/R_REGS_data_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X6Y57.BMUX     Tshcko                0.495   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<7>
                                                       RLINK/FX2CNTL/RXFIFO/RAM/AW_5.GL[6].MEM0/DP
    SLICE_X20Y55.C2      net (fanout=1)        0.880   RLINK/FX2CNTL/RXFIFO/RAM/AW_5.DOB0<6>
    SLICE_X20Y55.C       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7_SW0
    SLICE_X20Y55.B4      net (fanout=1)        0.114   N14
    SLICE_X20Y55.B       Tilo                  0.142   N14
                                                       RLINK/RLBMUX/Mmux_RLB_DI7
    SLICE_X19Y54.A5      net (fanout=5)        0.214   RLINK/RLB_DI<6>
    SLICE_X19Y54.A       Tilo                  0.156   RLINK/CORE/B2CD/R_REGS_data<3>
                                                       RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.D5      net (fanout=6)        0.178   RLINK/CORE/B2CD/GND_59_o_DI[2]_AND_24_o
    SLICE_X19Y55.CLK     Tah         (-Th)    -0.215   RLINK/CORE/B2CD/R_REGS_data<6>
                                                       RLINK/CORE/B2CD/Mmux_proc_next.idata71
                                                       RLINK/CORE/B2CD/R_REGS_data_6
    -------------------------------------------------  ---------------------------
    Total                                      2.536ns (1.150ns logic, 1.386ns route)
                                                       (45.3% logic, 54.7% route)

--------------------------------------------------------------------------------


Derived Constraint Report
Derived Constraints for TS_I_CLK100
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_I_CLK100                    |     10.000ns|      5.340ns|      9.841ns|            0|            0|            0|     12817577|
| TS_GEN_CLKSYS_USEDCM_CLKOUT0  |     14.706ns|     14.472ns|          N/A|            0|            0|     12817577|            0|
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+

1 constraint not met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock I_CLK100
---------------+------------+------------+------------+------------+------------------+--------+
               |Max Setup to|  Process   |Max Hold to |  Process   |                  | Clock  |
Source         | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s) | Phase  |
---------------+------------+------------+------------+------------+------------------+--------+
IO_MEM_DATA<0> |   -0.572(R)|      FAST  |    4.319(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<1> |   -0.625(R)|      FAST  |    4.372(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<2> |   -0.656(R)|      FAST  |    4.438(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<3> |   -0.620(R)|      FAST  |    4.367(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<4> |   -0.651(R)|      FAST  |    4.433(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<5> |   -0.568(R)|      FAST  |    4.315(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<6> |   -0.599(R)|      FAST  |    4.381(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<7> |   -0.560(R)|      FAST  |    4.307(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<8> |   -0.569(R)|      FAST  |    4.316(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<9> |   -0.600(R)|      FAST  |    4.382(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<10>|   -0.592(R)|      FAST  |    4.374(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<11>|   -0.621(R)|      FAST  |    4.368(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<12>|   -0.652(R)|      FAST  |    4.434(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<13>|   -0.580(R)|      FAST  |    4.327(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<14>|   -0.522(R)|      FAST  |    4.269(R)|      SLOW  |CLK               |   0.000|
IO_MEM_DATA<15>|   -0.553(R)|      FAST  |    4.335(R)|      SLOW  |CLK               |   0.000|
I_BTN<0>       |   -1.139(R)|      FAST  |    4.843(R)|      SLOW  |CLK               |   0.000|
I_BTN<1>       |   -1.041(R)|      FAST  |    4.710(R)|      SLOW  |CLK               |   0.000|
I_BTN<2>       |   -1.072(R)|      FAST  |    4.776(R)|      SLOW  |CLK               |   0.000|
I_BTN<3>       |   -1.118(R)|      FAST  |    4.822(R)|      SLOW  |CLK               |   0.000|
I_BTN<4>       |   -1.108(R)|      FAST  |    4.777(R)|      SLOW  |CLK               |   0.000|
I_FUSP_CTS_N   |   -0.592(R)|      FAST  |    4.374(R)|      SLOW  |CLK               |   0.000|
I_FUSP_RXD     |   -0.566(R)|      FAST  |    4.218(R)|      SLOW  |CLK               |   0.000|
I_RXD          |   -0.635(R)|      FAST  |    4.287(R)|      SLOW  |CLK               |   0.000|
I_SWI<0>       |   -0.550(R)|      FAST  |    4.332(R)|      SLOW  |CLK               |   0.000|
I_SWI<1>       |   -0.583(R)|      FAST  |    4.330(R)|      SLOW  |CLK               |   0.000|
I_SWI<2>       |   -0.614(R)|      FAST  |    4.396(R)|      SLOW  |CLK               |   0.000|
I_SWI<3>       |   -0.527(R)|      FAST  |    4.274(R)|      SLOW  |CLK               |   0.000|
I_SWI<4>       |   -0.558(R)|      FAST  |    4.340(R)|      SLOW  |CLK               |   0.000|
I_SWI<5>       |   -0.587(R)|      FAST  |    4.334(R)|      SLOW  |CLK               |   0.000|
I_SWI<6>       |   -0.618(R)|      FAST  |    4.400(R)|      SLOW  |CLK               |   0.000|
I_SWI<7>       |   -0.591(R)|      FAST  |    4.373(R)|      SLOW  |CLK               |   0.000|
---------------+------------+------------+------------+------------+------------------+--------+

Setup/Hold to clock I_FX2_IFCLK
--------------+------------+------------+------------+------------+------------------+--------+
              |Max Setup to|  Process   |Max Hold to |  Process   |                  | Clock  |
Source        | clk (edge) |   Corner   | clk (edge) |   Corner   |Internal Clock(s) | Phase  |
--------------+------------+------------+------------+------------+------------------+--------+
IO_FX2_DATA<0>|    0.977(R)|      SLOW  |    0.575(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<1>|    0.979(R)|      SLOW  |    0.573(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<2>|    0.979(R)|      SLOW  |    0.573(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<3>|    0.982(R)|      SLOW  |    0.570(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<4>|    0.982(R)|      SLOW  |    0.570(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<5>|    0.982(R)|      SLOW  |    0.570(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<6>|    0.982(R)|      SLOW  |    0.570(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<7>|    0.977(R)|      SLOW  |    0.575(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
I_FX2_FLAG<0> |    0.972(R)|      SLOW  |    0.580(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
I_FX2_FLAG<1> |    0.971(R)|      SLOW  |    0.581(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
I_FX2_FLAG<2> |    0.972(R)|      SLOW  |    0.580(R)|      SLOW  |I_FX2_IFCLK_BUFGP |   0.000|
--------------+------------+------------+------------+------------+------------------+--------+

Clock I_CLK100 to Pad
---------------+-----------------+------------+-----------------+------------+------------------+--------+
               |Max (slowest) clk|  Process   |Min (fastest) clk|  Process   |                  | Clock  |
Destination    |  (edge) to PAD  |   Corner   |  (edge) to PAD  |   Corner   |Internal Clock(s) | Phase  |
---------------+-----------------+------------+-----------------+------------+------------------+--------+
IO_MEM_DATA<0> |        11.703(R)|      SLOW  |         4.468(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<1> |        11.746(R)|      SLOW  |         4.511(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<2> |        11.746(R)|      SLOW  |         4.511(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<3> |        11.741(R)|      SLOW  |         4.506(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<4> |        11.741(R)|      SLOW  |         4.506(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<5> |        11.699(R)|      SLOW  |         4.464(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<6> |        11.699(R)|      SLOW  |         4.464(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<7> |        11.690(R)|      SLOW  |         4.455(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<8> |        11.699(R)|      SLOW  |         4.464(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<9> |        11.699(R)|      SLOW  |         4.464(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<10>|        11.692(R)|      SLOW  |         4.457(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<11>|        11.742(R)|      SLOW  |         4.507(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<12>|        11.742(R)|      SLOW  |         4.507(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<13>|        11.700(R)|      SLOW  |         4.465(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<14>|        11.653(R)|      SLOW  |         4.418(R)|      FAST  |CLK               |   0.000|
IO_MEM_DATA<15>|        11.653(R)|      SLOW  |         4.418(R)|      FAST  |CLK               |   0.000|
O_ANO_N<0>     |        11.431(R)|      SLOW  |         4.315(R)|      FAST  |CLK               |   0.000|
O_ANO_N<1>     |        11.431(R)|      SLOW  |         4.315(R)|      FAST  |CLK               |   0.000|
O_ANO_N<2>     |        11.436(R)|      SLOW  |         4.320(R)|      FAST  |CLK               |   0.000|
O_ANO_N<3>     |        11.436(R)|      SLOW  |         4.320(R)|      FAST  |CLK               |   0.000|
O_FUSP_RTS_N   |        12.011(R)|      SLOW  |         4.861(R)|      FAST  |CLK               |   0.000|
O_FUSP_TXD     |        12.015(R)|      SLOW  |         4.865(R)|      FAST  |CLK               |   0.000|
O_LED<0>       |        11.563(R)|      SLOW  |         4.447(R)|      FAST  |CLK               |   0.000|
O_LED<1>       |        11.563(R)|      SLOW  |         4.447(R)|      FAST  |CLK               |   0.000|
O_LED<2>       |        11.563(R)|      SLOW  |         4.447(R)|      FAST  |CLK               |   0.000|
O_LED<3>       |        11.563(R)|      SLOW  |         4.447(R)|      FAST  |CLK               |   0.000|
O_LED<4>       |        11.489(R)|      SLOW  |         4.373(R)|      FAST  |CLK               |   0.000|
O_LED<5>       |        11.489(R)|      SLOW  |         4.373(R)|      FAST  |CLK               |   0.000|
O_LED<6>       |        11.540(R)|      SLOW  |         4.424(R)|      FAST  |CLK               |   0.000|
O_LED<7>       |        11.540(R)|      SLOW  |         4.424(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<0>  |        11.358(R)|      SLOW  |         4.246(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<1>  |        11.358(R)|      SLOW  |         4.246(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<2>  |        11.365(R)|      SLOW  |         4.253(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<3>  |        11.365(R)|      SLOW  |         4.253(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<4>  |        11.358(R)|      SLOW  |         4.246(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<5>  |        11.358(R)|      SLOW  |         4.246(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<6>  |        11.356(R)|      SLOW  |         4.244(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<7>  |        11.356(R)|      SLOW  |         4.244(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<8>  |        11.353(R)|      SLOW  |         4.241(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<9>  |        11.353(R)|      SLOW  |         4.241(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<10> |        11.361(R)|      SLOW  |         4.249(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<11> |        11.361(R)|      SLOW  |         4.249(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<12> |        11.358(R)|      SLOW  |         4.246(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<13> |        11.358(R)|      SLOW  |         4.246(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<14> |        11.355(R)|      SLOW  |         4.243(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<15> |        11.355(R)|      SLOW  |         4.243(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<16> |        11.353(R)|      SLOW  |         4.241(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<17> |        11.353(R)|      SLOW  |         4.241(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<18> |        11.353(R)|      SLOW  |         4.241(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<19> |        11.353(R)|      SLOW  |         4.241(R)|      FAST  |CLK               |   0.000|
O_MEM_ADDR<20> |        11.357(R)|      SLOW  |         4.245(R)|      FAST  |CLK               |   0.000|
O_MEM_BE_N<0>  |        10.695(R)|      SLOW  |         3.622(R)|      FAST  |CLK               |   0.000|
O_MEM_BE_N<1>  |        10.695(R)|      SLOW  |         3.622(R)|      FAST  |CLK               |   0.000|
O_MEM_CE_N     |        10.697(R)|      SLOW  |         3.624(R)|      FAST  |CLK               |   0.000|
O_MEM_OE_N     |        10.684(R)|      SLOW  |         3.611(R)|      FAST  |CLK               |   0.000|
O_MEM_WE_N     |        18.043(F)|      SLOW  |        10.970(F)|      FAST  |CLK               |   7.352|
O_SEG_N<0>     |        11.424(R)|      SLOW  |         4.308(R)|      FAST  |CLK               |   0.000|
O_SEG_N<1>     |        11.424(R)|      SLOW  |         4.308(R)|      FAST  |CLK               |   0.000|
O_SEG_N<2>     |        11.429(R)|      SLOW  |         4.313(R)|      FAST  |CLK               |   0.000|
O_SEG_N<3>     |        11.429(R)|      SLOW  |         4.313(R)|      FAST  |CLK               |   0.000|
O_SEG_N<4>     |        11.431(R)|      SLOW  |         4.315(R)|      FAST  |CLK               |   0.000|
O_SEG_N<5>     |        11.431(R)|      SLOW  |         4.315(R)|      FAST  |CLK               |   0.000|
O_SEG_N<6>     |        11.433(R)|      SLOW  |         4.317(R)|      FAST  |CLK               |   0.000|
O_SEG_N<7>     |        11.433(R)|      SLOW  |         4.317(R)|      FAST  |CLK               |   0.000|
O_TXD          |        11.436(R)|      SLOW  |         4.320(R)|      FAST  |CLK               |   0.000|
---------------+-----------------+------------+-----------------+------------+------------------+--------+

Clock I_FX2_IFCLK to Pad
--------------+-----------------+------------+-----------------+------------+------------------+--------+
              |Max (slowest) clk|  Process   |Min (fastest) clk|  Process   |                  | Clock  |
Destination   |  (edge) to PAD  |   Corner   |  (edge) to PAD  |   Corner   |Internal Clock(s) | Phase  |
--------------+-----------------+------------+-----------------+------------+------------------+--------+
IO_FX2_DATA<0>|         7.864(R)|      SLOW  |         2.791(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<1>|         7.861(R)|      SLOW  |         2.788(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<2>|         7.861(R)|      SLOW  |         2.788(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<3>|         7.859(R)|      SLOW  |         2.786(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<4>|         7.859(R)|      SLOW  |         2.786(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<5>|         7.859(R)|      SLOW  |         2.786(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<6>|         7.859(R)|      SLOW  |         2.786(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
IO_FX2_DATA<7>|         7.864(R)|      SLOW  |         2.791(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_FIFO<0> |         7.867(R)|      SLOW  |         2.902(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_FIFO<1> |         7.864(R)|      SLOW  |         2.899(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_PKTEND_N|         7.864(R)|      SLOW  |         2.899(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_SLOE_N  |         7.867(R)|      SLOW  |         2.902(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_SLRD_N  |         7.871(R)|      SLOW  |         2.906(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
O_FX2_SLWR_N  |         7.871(R)|      SLOW  |         2.906(R)|      FAST  |I_FX2_IFCLK_BUFGP |   0.000|
--------------+-----------------+------------+-----------------+------------+------------------+--------+

Clock to Setup on destination clock I_CLK100
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
I_CLK100       |   14.472|         |    4.187|         |
I_FX2_IFCLK    |    5.875|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock I_FX2_IFCLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
I_CLK100       |    8.472|         |         |         |
I_FX2_IFCLK    |    9.510|         |         |         |
---------------+---------+---------+---------+---------+

OFFSET = IN 2 ns VALID 33 ns BEFORE COMP "I_FX2_IFCLK";
Worst Case Data Window 1.563; Ideal Clock Offset To Actual Clock 14.701; 
------------------+------------+------------+------------+------------+---------+---------+-------------+
                  |            |  Process   |            |  Process   |  Setup  |  Hold   |Source Offset|
Source            |   Setup    |   Corner   |    Hold    |   Corner   |  Slack  |  Slack  |  To Center  |
------------------+------------+------------+------------+------------+---------+---------+-------------+
IO_FX2_DATA<0>    |    0.977(R)|      SLOW  |    0.575(R)|      SLOW  |    1.023|   30.425|      -14.701|
IO_FX2_DATA<1>    |    0.979(R)|      SLOW  |    0.573(R)|      SLOW  |    1.021|   30.427|      -14.703|
IO_FX2_DATA<2>    |    0.979(R)|      SLOW  |    0.573(R)|      SLOW  |    1.021|   30.427|      -14.703|
IO_FX2_DATA<3>    |    0.982(R)|      SLOW  |    0.570(R)|      SLOW  |    1.018|   30.430|      -14.706|
IO_FX2_DATA<4>    |    0.982(R)|      SLOW  |    0.570(R)|      SLOW  |    1.018|   30.430|      -14.706|
IO_FX2_DATA<5>    |    0.982(R)|      SLOW  |    0.570(R)|      SLOW  |    1.018|   30.430|      -14.706|
IO_FX2_DATA<6>    |    0.982(R)|      SLOW  |    0.570(R)|      SLOW  |    1.018|   30.430|      -14.706|
IO_FX2_DATA<7>    |    0.977(R)|      SLOW  |    0.575(R)|      SLOW  |    1.023|   30.425|      -14.701|
I_FX2_FLAG<0>     |    0.972(R)|      SLOW  |    0.580(R)|      SLOW  |    1.028|   30.420|      -14.696|
I_FX2_FLAG<1>     |    0.971(R)|      SLOW  |    0.581(R)|      SLOW  |    1.029|   30.419|      -14.695|
I_FX2_FLAG<2>     |    0.972(R)|      SLOW  |    0.580(R)|      SLOW  |    1.028|   30.420|      -14.696|
------------------+------------+------------+------------+------------+---------+---------+-------------+
Worst Case Summary|       0.982|         -  |       0.581|         -  |    1.018|   30.419|             |
------------------+------------+------------+------------+------------+---------+---------+-------------+

OFFSET = OUT 20 ns AFTER COMP "I_CLK100";
Bus Skew: 7.359 ns; 
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
                                               |Max (slowest)|  Process   |Min (fastest)|  Process   |              |
PAD                                            | Delay (ns)  |   Corner   | Delay (ns)  |   Corner   |Edge Skew (ns)|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
IO_MEM_DATA<0>                                 |       11.703|      SLOW  |        4.468|      FAST  |         1.019|
IO_MEM_DATA<1>                                 |       11.746|      SLOW  |        4.511|      FAST  |         1.062|
IO_MEM_DATA<2>                                 |       11.746|      SLOW  |        4.511|      FAST  |         1.062|
IO_MEM_DATA<3>                                 |       11.741|      SLOW  |        4.506|      FAST  |         1.057|
IO_MEM_DATA<4>                                 |       11.741|      SLOW  |        4.506|      FAST  |         1.057|
IO_MEM_DATA<5>                                 |       11.699|      SLOW  |        4.464|      FAST  |         1.015|
IO_MEM_DATA<6>                                 |       11.699|      SLOW  |        4.464|      FAST  |         1.015|
IO_MEM_DATA<7>                                 |       11.690|      SLOW  |        4.455|      FAST  |         1.006|
IO_MEM_DATA<8>                                 |       11.699|      SLOW  |        4.464|      FAST  |         1.015|
IO_MEM_DATA<9>                                 |       11.699|      SLOW  |        4.464|      FAST  |         1.015|
IO_MEM_DATA<10>                                |       11.692|      SLOW  |        4.457|      FAST  |         1.008|
IO_MEM_DATA<11>                                |       11.742|      SLOW  |        4.507|      FAST  |         1.058|
IO_MEM_DATA<12>                                |       11.742|      SLOW  |        4.507|      FAST  |         1.058|
IO_MEM_DATA<13>                                |       11.700|      SLOW  |        4.465|      FAST  |         1.016|
IO_MEM_DATA<14>                                |       11.653|      SLOW  |        4.418|      FAST  |         0.969|
IO_MEM_DATA<15>                                |       11.653|      SLOW  |        4.418|      FAST  |         0.969|
O_ANO_N<0>                                     |       11.431|      SLOW  |        4.315|      FAST  |         0.747|
O_ANO_N<1>                                     |       11.431|      SLOW  |        4.315|      FAST  |         0.747|
O_ANO_N<2>                                     |       11.436|      SLOW  |        4.320|      FAST  |         0.752|
O_ANO_N<3>                                     |       11.436|      SLOW  |        4.320|      FAST  |         0.752|
O_FUSP_RTS_N                                   |       12.011|      SLOW  |        4.861|      FAST  |         1.327|
O_FUSP_TXD                                     |       12.015|      SLOW  |        4.865|      FAST  |         1.331|
O_LED<0>                                       |       11.563|      SLOW  |        4.447|      FAST  |         0.879|
O_LED<1>                                       |       11.563|      SLOW  |        4.447|      FAST  |         0.879|
O_LED<2>                                       |       11.563|      SLOW  |        4.447|      FAST  |         0.879|
O_LED<3>                                       |       11.563|      SLOW  |        4.447|      FAST  |         0.879|
O_LED<4>                                       |       11.489|      SLOW  |        4.373|      FAST  |         0.805|
O_LED<5>                                       |       11.489|      SLOW  |        4.373|      FAST  |         0.805|
O_LED<6>                                       |       11.540|      SLOW  |        4.424|      FAST  |         0.856|
O_LED<7>                                       |       11.540|      SLOW  |        4.424|      FAST  |         0.856|
O_MEM_ADDR<0>                                  |       11.358|      SLOW  |        4.246|      FAST  |         0.674|
O_MEM_ADDR<1>                                  |       11.358|      SLOW  |        4.246|      FAST  |         0.674|
O_MEM_ADDR<2>                                  |       11.365|      SLOW  |        4.253|      FAST  |         0.681|
O_MEM_ADDR<3>                                  |       11.365|      SLOW  |        4.253|      FAST  |         0.681|
O_MEM_ADDR<4>                                  |       11.358|      SLOW  |        4.246|      FAST  |         0.674|
O_MEM_ADDR<5>                                  |       11.358|      SLOW  |        4.246|      FAST  |         0.674|
O_MEM_ADDR<6>                                  |       11.356|      SLOW  |        4.244|      FAST  |         0.672|
O_MEM_ADDR<7>                                  |       11.356|      SLOW  |        4.244|      FAST  |         0.672|
O_MEM_ADDR<8>                                  |       11.353|      SLOW  |        4.241|      FAST  |         0.669|
O_MEM_ADDR<9>                                  |       11.353|      SLOW  |        4.241|      FAST  |         0.669|
O_MEM_ADDR<10>                                 |       11.361|      SLOW  |        4.249|      FAST  |         0.677|
O_MEM_ADDR<11>                                 |       11.361|      SLOW  |        4.249|      FAST  |         0.677|
O_MEM_ADDR<12>                                 |       11.358|      SLOW  |        4.246|      FAST  |         0.674|
O_MEM_ADDR<13>                                 |       11.358|      SLOW  |        4.246|      FAST  |         0.674|
O_MEM_ADDR<14>                                 |       11.355|      SLOW  |        4.243|      FAST  |         0.671|
O_MEM_ADDR<15>                                 |       11.355|      SLOW  |        4.243|      FAST  |         0.671|
O_MEM_ADDR<16>                                 |       11.353|      SLOW  |        4.241|      FAST  |         0.669|
O_MEM_ADDR<17>                                 |       11.353|      SLOW  |        4.241|      FAST  |         0.669|
O_MEM_ADDR<18>                                 |       11.353|      SLOW  |        4.241|      FAST  |         0.669|
O_MEM_ADDR<19>                                 |       11.353|      SLOW  |        4.241|      FAST  |         0.669|
O_MEM_ADDR<20>                                 |       11.357|      SLOW  |        4.245|      FAST  |         0.673|
O_MEM_BE_N<0>                                  |       10.695|      SLOW  |        3.622|      FAST  |         0.011|
O_MEM_BE_N<1>                                  |       10.695|      SLOW  |        3.622|      FAST  |         0.011|
O_MEM_CE_N                                     |       10.697|      SLOW  |        3.624|      FAST  |         0.013|
O_MEM_OE_N                                     |       10.684|      SLOW  |        3.611|      FAST  |         0.000|
O_MEM_WE_N                                     |       18.043|      SLOW  |       10.970|      FAST  |         7.359|
O_SEG_N<0>                                     |       11.424|      SLOW  |        4.308|      FAST  |         0.740|
O_SEG_N<1>                                     |       11.424|      SLOW  |        4.308|      FAST  |         0.740|
O_SEG_N<2>                                     |       11.429|      SLOW  |        4.313|      FAST  |         0.745|
O_SEG_N<3>                                     |       11.429|      SLOW  |        4.313|      FAST  |         0.745|
O_SEG_N<4>                                     |       11.431|      SLOW  |        4.315|      FAST  |         0.747|
O_SEG_N<5>                                     |       11.431|      SLOW  |        4.315|      FAST  |         0.747|
O_SEG_N<6>                                     |       11.433|      SLOW  |        4.317|      FAST  |         0.749|
O_SEG_N<7>                                     |       11.433|      SLOW  |        4.317|      FAST  |         0.749|
O_TXD                                          |       11.436|      SLOW  |        4.320|      FAST  |         0.752|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+

OFFSET = OUT 10 ns VALID 33 ns AFTER COMP "I_FX2_IFCLK";
Bus Skew: 0.012 ns; 
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
                                               |Max (slowest)|  Process   |Min (fastest)|  Process   |              |
PAD                                            | Delay (ns)  |   Corner   | Delay (ns)  |   Corner   |Edge Skew (ns)|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+
IO_FX2_DATA<0>                                 |        7.864|      SLOW  |        2.791|      FAST  |         0.005|
IO_FX2_DATA<1>                                 |        7.861|      SLOW  |        2.788|      FAST  |         0.002|
IO_FX2_DATA<2>                                 |        7.861|      SLOW  |        2.788|      FAST  |         0.002|
IO_FX2_DATA<3>                                 |        7.859|      SLOW  |        2.786|      FAST  |         0.000|
IO_FX2_DATA<4>                                 |        7.859|      SLOW  |        2.786|      FAST  |         0.000|
IO_FX2_DATA<5>                                 |        7.859|      SLOW  |        2.786|      FAST  |         0.000|
IO_FX2_DATA<6>                                 |        7.859|      SLOW  |        2.786|      FAST  |         0.000|
IO_FX2_DATA<7>                                 |        7.864|      SLOW  |        2.791|      FAST  |         0.005|
O_FX2_FIFO<0>                                  |        7.867|      SLOW  |        2.902|      FAST  |         0.008|
O_FX2_FIFO<1>                                  |        7.864|      SLOW  |        2.899|      FAST  |         0.005|
O_FX2_PKTEND_N                                 |        7.864|      SLOW  |        2.899|      FAST  |         0.005|
O_FX2_SLOE_N                                   |        7.867|      SLOW  |        2.902|      FAST  |         0.008|
O_FX2_SLRD_N                                   |        7.871|      SLOW  |        2.906|      FAST  |         0.012|
O_FX2_SLWR_N                                   |        7.871|      SLOW  |        2.906|      FAST  |         0.012|
-----------------------------------------------+-------------+------------+-------------+------------+--------------+


Timing summary:
---------------

Timing errors: 5  Score: 305  (Setup/Max: 0, Hold: 305)

Constraints cover 12822073 paths, 0 nets, and 27301 connections

Design statistics:
   Minimum period:  14.472ns{1}   (Maximum frequency:  69.099MHz)
   Maximum path delay from/to any node:   6.912ns
   Minimum input required time before clock:   0.982ns
   Minimum output required time after clock:  18.043ns


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Thu May 14 16:45:57 2015 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 492 MB



