# 1 "sys_w11a_n3.ucf_cpp"
# 1 "<command-line>"
# 1 "/usr/include/stdc-predef.h" 1 3 4
# 1 "<command-line>" 2
# 1 "sys_w11a_n3.ucf_cpp"
## $Id: sys_w11a_n3.ucf_cpp 540 2013-10-13 18:42:50Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-10-13 540 1.1 add pad->clk and fx2 cdc constraints
## 2013-04-21 509 1.1 add fx2 support
## 2011-11-20 430 1.0 Initial version
##

NET "I_CLK100" TNM_NET = "I_CLK100";
TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK100";
OFFSET = OUT 20 ns AFTER "I_CLK100";

## constrain pad->net clock delay
NET CLK TNM = TNM_CLK;
TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns;
NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK;
TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns;

## FX2 controller specific constraints
## constrain cdc path in fifos and reset
TIMESPEC TS_CDC_FIFO =
   FROM FFS(*FIFO/GC?/GRAY_*.CNT/R_DATA*)
   TO FFS(*FIFO/R_REG?_?addr_c*)
   5 ns DATAPATHONLY;

## std board
##
# 1 "/home/walter/tmp/octest/trunk/rtl/bplib/nexys3/nexys3_pins.ucf" 1
## $Id: nexys3_pins.ucf 432 2011-11-25 20:16:28Z mueller $
##
## Pin locks for Nexys 3 core functionality
## - USB UART
## - human I/O (switches, buttons, leds, display)
## - cram
##
## Revision History:
## Date Rev Version Comment
## 2011-11-23 432 1.0.2 add PPCM controls
## 2011-10-10 413 1.0.1 new BTN sequence: clockwise(U-R-D-L) - middle
## 2011-07-04 388 1.0 Initial version
##
## Note: default is DRIVE=12 | SLEW=SLOW
##
## Assume that VCCB0 is jumpered for 2.5 V (for VHDCI LVDS usage)
##
## clocks -- in bank 2 -------------------------------------------------------
NET "I_CLK100" LOC = "v10" | IOSTANDARD=LVCMOS33;
##
## USB UART Interface -- in bank 1--------------------------------------------
## I_RXD -> signal MCU_RX -> TXD pin of FT232R
## O_TXD -> signal MCU_TX -> RXD pin of FT232R
## I_CTS_N ?? signal RTS -> RTS pin of FT232R (only on J14)
## O_RTS_N ?? signal CTS -> CTS pin of FT232R (only on J14)
NET "I_RXD" LOC = "n17" | IOSTANDARD=LVCMOS33;
NET "O_TXD" LOC = "n18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=SLOW;
##
## switches -- in bank 2 -----------------------------------------------------
NET "I_SWI<0>" LOC = "t10" | IOSTANDARD=LVCMOS33;
NET "I_SWI<1>" LOC = "t9" | IOSTANDARD=LVCMOS33;
NET "I_SWI<2>" LOC = "v9" | IOSTANDARD=LVCMOS33;
NET "I_SWI<3>" LOC = "m8" | IOSTANDARD=LVCMOS33;
NET "I_SWI<4>" LOC = "n8" | IOSTANDARD=LVCMOS33;
NET "I_SWI<5>" LOC = "u8" | IOSTANDARD=LVCMOS33;
NET "I_SWI<6>" LOC = "v8" | IOSTANDARD=LVCMOS33;
NET "I_SWI<7>" LOC = "t5" | IOSTANDARD=LVCMOS33;
##
## buttons -- in bank 0-------------------------------------------------------
## sequence: clockwise(U-R-D-L) - middle
NET "I_BTN<0>" LOC = "a8" | IOSTANDARD=LVCMOS25; # BTNU
NET "I_BTN<1>" LOC = "d9" | IOSTANDARD=LVCMOS25; # BTNR
NET "I_BTN<2>" LOC = "c9" | IOSTANDARD=LVCMOS25; # BTND
NET "I_BTN<3>" LOC = "c4" | IOSTANDARD=LVCMOS25; # BTNL
NET "I_BTN<4>" LOC = "b8" | IOSTANDARD=LVCMOS25; # BTNS
##
## LEDs -- in bank 2 ---------------------------------------------------------
NET "O_LED<0>" LOC = "u16" | IOSTANDARD=LVCMOS33;
NET "O_LED<1>" LOC = "v16" | IOSTANDARD=LVCMOS33;
NET "O_LED<2>" LOC = "u15" | IOSTANDARD=LVCMOS33;
NET "O_LED<3>" LOC = "v15" | IOSTANDARD=LVCMOS33;
NET "O_LED<4>" LOC = "m11" | IOSTANDARD=LVCMOS33;
NET "O_LED<5>" LOC = "n11" | IOSTANDARD=LVCMOS33;
NET "O_LED<6>" LOC = "r11" | IOSTANDARD=LVCMOS33;
NET "O_LED<7>" LOC = "t11" | IOSTANDARD=LVCMOS33;
NET "O_LED<*>" DRIVE=12 | SLEW=SLOW;
##
## 7 segment display -- in bank 1 --------------------------------------------
NET "O_ANO_N<0>" LOC = "n16" | IOSTANDARD=LVCMOS33;
NET "O_ANO_N<1>" LOC = "n15" | IOSTANDARD=LVCMOS33;
NET "O_ANO_N<2>" LOC = "p18" | IOSTANDARD=LVCMOS33;
NET "O_ANO_N<3>" LOC = "p17" | IOSTANDARD=LVCMOS33;
NET "O_ANO_N<*>" DRIVE=12 | SLEW=SLOW;
##
NET "O_SEG_N<0>" LOC = "t17" | IOSTANDARD=LVCMOS33; # CA
NET "O_SEG_N<1>" LOC = "t18" | IOSTANDARD=LVCMOS33; # CB
NET "O_SEG_N<2>" LOC = "u17" | IOSTANDARD=LVCMOS33; # CC
NET "O_SEG_N<3>" LOC = "u18" | IOSTANDARD=LVCMOS33; # CD
NET "O_SEG_N<4>" LOC = "m14" | IOSTANDARD=LVCMOS33; # CE
NET "O_SEG_N<5>" LOC = "n14" | IOSTANDARD=LVCMOS33; # CF
NET "O_SEG_N<6>" LOC = "l14" | IOSTANDARD=LVCMOS33; # CG
NET "O_SEG_N<7>" LOC = "m13" | IOSTANDARD=LVCMOS33; # DP
NET "O_SEG_N<*>" DRIVE=12 | SLEW=SLOW;
##
## CRAM -- in bank 2 (data) and 1 (addr) -------------------------------------
NET "O_MEM_CE_N" LOC = "l15" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_WE_N" LOC = "m16" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_OE_N" LOC = "l18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_MEM_BE_N<0>" LOC = "k16" | IOSTANDARD=LVCMOS33;
NET "O_MEM_BE_N<1>" LOC = "k15" | IOSTANDARD=LVCMOS33;
NET "O_MEM_BE_N<*>" DRIVE=12 | SLEW=FAST;
##
NET "O_MEM_ADV_N" LOC = "h18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_CLK" LOC = "r10" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_MEM_CRE" LOC = "m18" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "I_MEM_WAIT" LOC = "v4" | IOSTANDARD=LVCMOS33 | PULLDOWN;
##
NET "O_MEM_ADDR<0>" LOC = "k18" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<1>" LOC = "k17" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<2>" LOC = "j18" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<3>" LOC = "j16" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<4>" LOC = "g18" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<5>" LOC = "g16" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<6>" LOC = "h16" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<7>" LOC = "h15" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<8>" LOC = "h14" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<9>" LOC = "h13" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<10>" LOC = "f18" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<11>" LOC = "f17" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<12>" LOC = "k13" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<13>" LOC = "k12" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<14>" LOC = "e18" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<15>" LOC = "e16" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<16>" LOC = "g13" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<17>" LOC = "h12" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<18>" LOC = "d18" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<19>" LOC = "d17" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<20>" LOC = "g14" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<21>" LOC = "f14" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<22>" LOC = "c18" | IOSTANDARD=LVCMOS33;
NET "O_MEM_ADDR<*>" DRIVE=6 | SLEW=FAST;
##
NET "IO_MEM_DATA<0>" LOC = "r13" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<1>" LOC = "t14" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<2>" LOC = "v14" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<3>" LOC = "u5" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<4>" LOC = "v5" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<5>" LOC = "r3" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<6>" LOC = "t3" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<7>" LOC = "r5" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<8>" LOC = "n5" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<9>" LOC = "p6" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<10>" LOC = "p12" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<11>" LOC = "u13" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<12>" LOC = "v13" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<13>" LOC = "u10" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<14>" LOC = "r8" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<15>" LOC = "t8" | IOSTANDARD=LVCMOS33;
NET "IO_MEM_DATA<*>" DRIVE=6 | SLEW=SLOW | KEEPER;
##
## PPCM -- parallel PCM memory -----------------------------------------------
NET "O_PPCM_CE_N" LOC = "l17" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW;
NET "O_PPCM_RST_N" LOC = "t4" | IOSTANDARD=LVCMOS33 | DRIVE=6 | SLEW=SLOW;
##
# 31 "sys_w11a_n3.ucf_cpp" 2
##
## Pmod B0 - RS232
##
# 1 "/home/walter/tmp/octest/trunk/rtl/bplib/nexys3/nexys3_pins_pmb0_rs232.ucf" 1
## $Id: nexys3_pins_pmb0_rs232.ucf 534 2013-09-22 21:37:24Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2011-11-20 430 1.0 Initial version
##
## Pmod connector B top / usage RS232 for FTDI USB serport -------------------
##
NET "O_FUSP_RTS_N" LOC = "k2" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
NET "I_FUSP_CTS_N" LOC = "k1" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "I_FUSP_RXD" LOC = "l4" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "O_FUSP_TXD" LOC = "l3" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
##
# 35 "sys_w11a_n3.ucf_cpp" 2
##
## Cypress FX2
##
# 1 "/home/walter/tmp/octest/trunk/rtl/bplib/nexys3/nexys3_pins_fx2.ucf" 1
## $Id: nexys3_pins_fx2.ucf 455 2012-01-24 09:11:25Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2012-01-23 455 1.2 fix SLOE_N (h4->h6)
## 2012-01-01 448 1.1 use 12/FAST instead of 6/SLOW for _DATA<*>
## 2011-11-27 433 1.0 Initial version
##
## Cypress EZ-USB FX2 Interface -- in Bank 3 ---------------------------------
##
##
NET "I_FX2_IFCLK" LOC = "h2" | IOSTANDARD=LVCMOS33;
##
NET "IO_FX2_DATA<0>" LOC = "e1" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<1>" LOC = "f4" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<2>" LOC = "f3" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<3>" LOC = "d2" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<4>" LOC = "d1" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<5>" LOC = "h7" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<6>" LOC = "g6" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<7>" LOC = "e4" | IOSTANDARD=LVCMOS33;
NET "IO_FX2_DATA<*>" DRIVE=12 | SLEW=FAST | KEEPER;
##
NET "O_FX2_SLWR_N" LOC = "c1" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_FX2_SLRD_N" LOC = "c2" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_FX2_SLOE_N" LOC = "h6" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_FX2_PKTEND_N" LOC = "d3" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
NET "O_FX2_FIFO<0>" LOC = "h5" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
NET "O_FX2_FIFO<1>" LOC = "e3" | IOSTANDARD=LVCMOS33 | DRIVE=12 | SLEW=FAST;
##
## assume that PA.7 is used as FLAGD (and not as SLCS#)
NET "I_FX2_FLAG<0>" LOC = "h1" | IOSTANDARD=LVCMOS33; ## flag a (program)
NET "I_FX2_FLAG<1>" LOC = "k4" | IOSTANDARD=LVCMOS33; ## flag b (full)
NET "I_FX2_FLAG<2>" LOC = "f5" | IOSTANDARD=LVCMOS33; ## flag c (empty)
NET "I_FX2_FLAG<3>" LOC = "f6" | IOSTANDARD=LVCMOS33; ## flag d (slcs)
##
# 39 "sys_w11a_n3.ucf_cpp" 2
# 1 "/home/walter/tmp/octest/trunk/rtl/bplib/nexys3/nexys3_time_fx2_ic.ucf" 1
## $Id: nexys3_time_fx2_ic.ucf 537 2013-10-06 09:06:23Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-10-05 537 1.1 add VALID for hold time check
## 2012-01-01 448 1.0 Initial version
##
## timing rules for a 30 MHz internal clock design:
## Period: 30 MHz
## clk->out: longest setup time in FX2 is t_SRD (clk->SLRD) of 18.7 ns
## clk->out < 33.3-18.7 = 14.6 ns
## --> use 10 ns
##

NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK";
TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %;
OFFSET = IN 2 ns VALID 33 ns BEFORE "I_FX2_IFCLK";
OFFSET = OUT 10 ns VALID 33 ns AFTER "I_FX2_IFCLK";
# 39 "sys_w11a_n3.ucf_cpp" 2
