--------------------------------------------------------------------------------
Release 14.7 Trace  (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

/mnt/data/opt/Xilinx/ISE/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -v 3
-fastpaths -u 25 -intstyle xflow -xml sys_tst_rlink_n2.twx -tsi
sys_tst_rlink_n2.tsi sys_tst_rlink_n2.ncd sys_tst_rlink_n2.pcf

Design file:              sys_tst_rlink_n2.ncd
Physical constraint file: sys_tst_rlink_n2.pcf
Device,package,speed:     xc3s1200e,fg320,-4 (PRODUCTION 1.27 2013-10-13)
Report level:             verbose report
                          unconstrained path report, limited to 25 items

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

WARNING:Timing:3391 - Timing constraint OFFSET = IN 10 ns BEFORE COMP 
   "I_CLK50"; does not specify a data valid duration and will not be hold 
   checked. To enable hold checking on this offset constraint please specify a 
   data valid duration using the VALID <duration> option.
INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more 
   information, see the TSI report.  Please consult the Xilinx Command Line 
   Tools User Guide for information on generating a TSI report.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter 
   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock 
   Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 
   'Phase Error' calculations, these terms will be zero in the Clock 
   Uncertainty calculation.  Please make appropriate modification to 
   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase 
   Error.

================================================================================
Timing constraint: TS_I_CLK50 = PERIOD TIMEGRP "I_CLK50" 20 ns HIGH 50%;
For more information, see Period Analysis in the Timing Closure User Guide (UG612).

 34868 paths analyzed, 3682 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is  14.429ns.
--------------------------------------------------------------------------------
Slack (setup path):     5.571ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RBDTST/TEST/R_REGS.cntbusy_6 (FF)
  Destination:          RBDTST/MON/R_REGS.rbdata_7 (FF)
  Requirement:          20.000ns
  Data Path Delay:      14.386ns (Levels of Logic = 7)
  Clock Path Skew:      -0.043ns (0.154 - 0.197)
  Source Clock:         I_CLK50_BUFGP rising at 0.000ns
  Destination Clock:    I_CLK50_BUFGP rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RBDTST/TEST/R_REGS.cntbusy_6 to RBDTST/MON/R_REGS.rbdata_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X46Y99.YQ      Tcko                  0.652   RBDTST/TEST/R_REGS.cntbusy_7
                                                       RBDTST/TEST/R_REGS.cntbusy_6
    SLICE_X46Y98.F4      net (fanout=2)        0.738   RBDTST/TEST/R_REGS.cntbusy_6
    SLICE_X46Y98.X       Tilo                  0.759   RBDTST/TEST/isbusy_and000037
                                                       RBDTST/TEST/isbusy_and000037
    SLICE_X46Y96.F2      net (fanout=1)        0.361   RBDTST/TEST/isbusy_and000037
    SLICE_X46Y96.X       Tilo                  0.759   RBDTST/TEST/isbusy_and0000
                                                       RBDTST/TEST/isbusy_and000039
    SLICE_X76Y70.G4      net (fanout=18)       2.771   RBDTST/TEST/isbusy_and0000
    SLICE_X76Y70.Y       Tilo                  0.759   RBDTST/MON/R_REGS.rbbusy
                                                       RBDTST/TEST/irb_busy_mux0001
    SLICE_X74Y73.F4      net (fanout=5)        0.420   RBDTST/RB_SRES_TEST_busy
    SLICE_X74Y73.X       Tilo                  0.759   RBDTST/TEST/N28
                                                       RBDTST/TEST/irb_dout_1_mux000221
    SLICE_X67Y57.F2      net (fanout=5)        2.108   RBDTST/TEST/N28
    SLICE_X67Y57.X       Tilo                  0.704   RB_SRES_OR1/RB_SRES_OR_dout<7>149
                                                       RB_SRES_OR1/RB_SRES_OR_dout<7>149
    SLICE_X77Y49.G4      net (fanout=1)        0.884   RB_SRES_OR1/RB_SRES_OR_dout<7>149
    SLICE_X77Y49.Y       Tilo                  0.704   RLINK/CORE/RL/R_REGS.dol_7
                                                       RB_SRES_OR1/RB_SRES_OR_dout<7>321
    SLICE_X77Y68.F1      net (fanout=2)        1.171   RB_SRES_dout<7>
    SLICE_X77Y68.CLK     Tfck                  0.837   RBDTST/MON/R_REGS.rbdata_7
                                                       RBDTST/MON/R_REGS_rbdata_mux0001<7>1
                                                       RBDTST/MON/R_REGS.rbdata_7
    -------------------------------------------------  ---------------------------
    Total                                     14.386ns (5.933ns logic, 8.453ns route)
                                                       (41.2% logic, 58.8% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.606ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RBDTST/TEST/R_REGS.cntbusy_7 (FF)
  Destination:          RBDTST/MON/R_REGS.rbdata_7 (FF)
  Requirement:          20.000ns
  Data Path Delay:      14.351ns (Levels of Logic = 7)
  Clock Path Skew:      -0.043ns (0.154 - 0.197)
  Source Clock:         I_CLK50_BUFGP rising at 0.000ns
  Destination Clock:    I_CLK50_BUFGP rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RBDTST/TEST/R_REGS.cntbusy_7 to RBDTST/MON/R_REGS.rbdata_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X46Y99.XQ      Tcko                  0.592   RBDTST/TEST/R_REGS.cntbusy_7
                                                       RBDTST/TEST/R_REGS.cntbusy_7
    SLICE_X46Y98.F2      net (fanout=2)        0.763   RBDTST/TEST/R_REGS.cntbusy_7
    SLICE_X46Y98.X       Tilo                  0.759   RBDTST/TEST/isbusy_and000037
                                                       RBDTST/TEST/isbusy_and000037
    SLICE_X46Y96.F2      net (fanout=1)        0.361   RBDTST/TEST/isbusy_and000037
    SLICE_X46Y96.X       Tilo                  0.759   RBDTST/TEST/isbusy_and0000
                                                       RBDTST/TEST/isbusy_and000039
    SLICE_X76Y70.G4      net (fanout=18)       2.771   RBDTST/TEST/isbusy_and0000
    SLICE_X76Y70.Y       Tilo                  0.759   RBDTST/MON/R_REGS.rbbusy
                                                       RBDTST/TEST/irb_busy_mux0001
    SLICE_X74Y73.F4      net (fanout=5)        0.420   RBDTST/RB_SRES_TEST_busy
    SLICE_X74Y73.X       Tilo                  0.759   RBDTST/TEST/N28
                                                       RBDTST/TEST/irb_dout_1_mux000221
    SLICE_X67Y57.F2      net (fanout=5)        2.108   RBDTST/TEST/N28
    SLICE_X67Y57.X       Tilo                  0.704   RB_SRES_OR1/RB_SRES_OR_dout<7>149
                                                       RB_SRES_OR1/RB_SRES_OR_dout<7>149
    SLICE_X77Y49.G4      net (fanout=1)        0.884   RB_SRES_OR1/RB_SRES_OR_dout<7>149
    SLICE_X77Y49.Y       Tilo                  0.704   RLINK/CORE/RL/R_REGS.dol_7
                                                       RB_SRES_OR1/RB_SRES_OR_dout<7>321
    SLICE_X77Y68.F1      net (fanout=2)        1.171   RB_SRES_dout<7>
    SLICE_X77Y68.CLK     Tfck                  0.837   RBDTST/MON/R_REGS.rbdata_7
                                                       RBDTST/MON/R_REGS_rbdata_mux0001<7>1
                                                       RBDTST/MON/R_REGS.rbdata_7
    -------------------------------------------------  ---------------------------
    Total                                     14.351ns (5.873ns logic, 8.478ns route)
                                                       (40.9% logic, 59.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     5.730ns (requirement - (data path - clock path skew + uncertainty))
  Source:               RBDTST/TEST/R_REGS.cntbusy_6 (FF)
  Destination:          RBDTST/MON/R_REGS.rbdata_3 (FF)
  Requirement:          20.000ns
  Data Path Delay:      14.230ns (Levels of Logic = 7)
  Clock Path Skew:      -0.040ns (0.157 - 0.197)
  Source Clock:         I_CLK50_BUFGP rising at 0.000ns
  Destination Clock:    I_CLK50_BUFGP rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Maximum Data Path: RBDTST/TEST/R_REGS.cntbusy_6 to RBDTST/MON/R_REGS.rbdata_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X46Y99.YQ      Tcko                  0.652   RBDTST/TEST/R_REGS.cntbusy_7
                                                       RBDTST/TEST/R_REGS.cntbusy_6
    SLICE_X46Y98.F4      net (fanout=2)        0.738   RBDTST/TEST/R_REGS.cntbusy_6
    SLICE_X46Y98.X       Tilo                  0.759   RBDTST/TEST/isbusy_and000037
                                                       RBDTST/TEST/isbusy_and000037
    SLICE_X46Y96.F2      net (fanout=1)        0.361   RBDTST/TEST/isbusy_and000037
    SLICE_X46Y96.X       Tilo                  0.759   RBDTST/TEST/isbusy_and0000
                                                       RBDTST/TEST/isbusy_and000039
    SLICE_X76Y70.G4      net (fanout=18)       2.771   RBDTST/TEST/isbusy_and0000
    SLICE_X76Y70.Y       Tilo                  0.759   RBDTST/MON/R_REGS.rbbusy
                                                       RBDTST/TEST/irb_busy_mux0001
    SLICE_X74Y73.F4      net (fanout=5)        0.420   RBDTST/RB_SRES_TEST_busy
    SLICE_X74Y73.X       Tilo                  0.759   RBDTST/TEST/N28
                                                       RBDTST/TEST/irb_dout_1_mux000221
    SLICE_X67Y56.F4      net (fanout=5)        1.737   RBDTST/TEST/N28
    SLICE_X67Y56.X       Tilo                  0.704   RB_SRES_OR1/RB_SRES_OR_dout<3>172
                                                       RB_SRES_OR1/RB_SRES_OR_dout<3>172
    SLICE_X67Y52.G2      net (fanout=1)        0.326   RB_SRES_OR1/RB_SRES_OR_dout<3>172
    SLICE_X67Y52.Y       Tilo                  0.704   RLINK/CORE/RL/R_REGS.dol_3
                                                       RB_SRES_OR1/RB_SRES_OR_dout<3>343
    SLICE_X78Y72.F1      net (fanout=2)        1.889   RB_SRES_dout<3>
    SLICE_X78Y72.CLK     Tfck                  0.892   RBDTST/MON/R_REGS.rbdata_3
                                                       RBDTST/MON/R_REGS_rbdata_mux0001<3>1
                                                       RBDTST/MON/R_REGS.rbdata_3
    -------------------------------------------------  ---------------------------
    Total                                     14.230ns (5.988ns logic, 8.242ns route)
                                                       (42.1% logic, 57.9% route)

--------------------------------------------------------------------------------

Hold Paths: TS_I_CLK50 = PERIOD TIMEGRP "I_CLK50" 20 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack (hold path):      0.765ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/SERPORT/XONRX/R_REGS.rxdata_4 (FF)
  Destination:          RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[4].MEM1.SLICEM_G (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.761ns (Levels of Logic = 1)
  Clock Path Skew:      -0.004ns (0.005 - 0.009)
  Source Clock:         I_CLK50_BUFGP rising at 20.000ns
  Destination Clock:    I_CLK50_BUFGP rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/SERPORT/XONRX/R_REGS.rxdata_4 to RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[4].MEM1.SLICEM_G
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X33Y38.YQ      Tcko                  0.470   RLINK/SERPORT/XONRX/R_REGS.rxdata_5
                                                       RLINK/SERPORT/XONRX/R_REGS.rxdata_4
    SLICE_X32Y41.BY      net (fanout=2)        0.418   RLINK/SERPORT/XONRX/R_REGS.rxdata_4
    SLICE_X32Y41.CLK     Tdh         (-Th)     0.127   RLINK/SERPORT/RXFIFO/FIFO/RAM/DOB1<4>
                                                       RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[4].MEM1.SLICEM_G
    -------------------------------------------------  ---------------------------
    Total                                      0.761ns (0.343ns logic, 0.418ns route)
                                                       (45.1% logic, 54.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.765ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/SERPORT/XONRX/R_REGS.rxdata_4 (FF)
  Destination:          RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[4].MEM0.SLICEM_G (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.761ns (Levels of Logic = 1)
  Clock Path Skew:      -0.004ns (0.005 - 0.009)
  Source Clock:         I_CLK50_BUFGP rising at 20.000ns
  Destination Clock:    I_CLK50_BUFGP rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/SERPORT/XONRX/R_REGS.rxdata_4 to RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[4].MEM0.SLICEM_G
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X33Y38.YQ      Tcko                  0.470   RLINK/SERPORT/XONRX/R_REGS.rxdata_5
                                                       RLINK/SERPORT/XONRX/R_REGS.rxdata_4
    SLICE_X32Y40.BY      net (fanout=2)        0.418   RLINK/SERPORT/XONRX/R_REGS.rxdata_4
    SLICE_X32Y40.CLK     Tdh         (-Th)     0.127   RLINK/SERPORT/RXFIFO/FIFO/RAM/DOB0<4>
                                                       RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[4].MEM0.SLICEM_G
    -------------------------------------------------  ---------------------------
    Total                                      0.761ns (0.343ns logic, 0.418ns route)
                                                       (45.1% logic, 54.9% route)

--------------------------------------------------------------------------------
Slack (hold path):      0.768ns (requirement - (clock path skew + uncertainty - data path))
  Source:               RLINK/SERPORT/XONRX/R_REGS.rxdata_3 (FF)
  Destination:          RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[3].MEM0.SLICEM_G (RAM)
  Requirement:          0.000ns
  Data Path Delay:      0.764ns (Levels of Logic = 1)
  Clock Path Skew:      -0.004ns (0.005 - 0.009)
  Source Clock:         I_CLK50_BUFGP rising at 20.000ns
  Destination Clock:    I_CLK50_BUFGP rising at 20.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path: RLINK/SERPORT/XONRX/R_REGS.rxdata_3 to RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[3].MEM0.SLICEM_G
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X35Y38.XQ      Tcko                  0.473   RLINK/SERPORT/XONRX/R_REGS.rxdata_3
                                                       RLINK/SERPORT/XONRX/R_REGS.rxdata_3
    SLICE_X34Y40.BY      net (fanout=2)        0.418   RLINK/SERPORT/XONRX/R_REGS.rxdata_3
    SLICE_X34Y40.CLK     Tdh         (-Th)     0.127   RLINK/SERPORT/RXFIFO/FIFO/RAM/DOB0<3>
                                                       RLINK/SERPORT/RXFIFO/FIFO/RAM/AW_5.GL[3].MEM0.SLICEM_G
    -------------------------------------------------  ---------------------------
    Total                                      0.764ns (0.346ns logic, 0.418ns route)
                                                       (45.3% logic, 54.7% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_I_CLK50 = PERIOD TIMEGRP "I_CLK50" 20 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 16.808ns (period - (min low pulse limit / (low pulse / period)))
  Period: 20.000ns
  Low pulse: 10.000ns
  Low pulse limit: 1.596ns (Trpw)
  Physical resource: O_ANO_N<0>/SR
  Logical resource: HIO/HIO/IOB_ANO_N/R_DO_0/SR
  Location pin: F17.SR
  Clock network: HIO/HIO/DRV/R_REGS.dcnt_0
--------------------------------------------------------------------------------
Slack: 16.808ns (period - (min high pulse limit / (high pulse / period)))
  Period: 20.000ns
  High pulse: 10.000ns
  High pulse limit: 1.596ns (Trpw)
  Physical resource: O_ANO_N<0>/SR
  Logical resource: HIO/HIO/IOB_ANO_N/R_DO_0/SR
  Location pin: F17.SR
  Clock network: HIO/HIO/DRV/R_REGS.dcnt_0
--------------------------------------------------------------------------------
Slack: 16.808ns (period - (min low pulse limit / (low pulse / period)))
  Period: 20.000ns
  Low pulse: 10.000ns
  Low pulse limit: 1.596ns (Trpw)
  Physical resource: O_ANO_N<1>/SR
  Logical resource: HIO/HIO/IOB_ANO_N/R_DO_1/SR
  Location pin: H17.SR
  Clock network: HIO/HIO/DRV/R_REGS.dcnt_1
--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = IN 10 ns BEFORE COMP "I_CLK50";
For more information, see Offset In Analysis in the Timing Closure User Guide (UG612).

 15 paths analyzed, 15 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum allowable offset is   3.327ns.
--------------------------------------------------------------------------------
Slack (setup path):     6.673ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               I_RXD (PAD)
  Destination:          IOB_RS232/P0/IOB_RXD/IOB/R_DI_0 (FF)
  Destination Clock:    I_CLK50_BUFGP rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      6.222ns (Levels of Logic = 0)
  Clock Path Delay:     2.895ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: I_RXD to IOB_RS232/P0/IOB_RXD/IOB/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    U6.ICLK1             Tiopickd              6.222   I_RXD
                                                       I_RXD
                                                       I_RXD_IBUF
                                                       I_RXD.IFD_DELAY
                                                       IOB_RS232/P0/IOB_RXD/IOB/R_DI_0
    -------------------------------------------------  ---------------------------
    Total                                      6.222ns (6.222ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: I_CLK50 to IOB_RS232/P0/IOB_RXD/IOB/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    U6.ICLK1             net (fanout=594)      0.227   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.895ns (2.632ns logic, 0.263ns route)
                                                       (90.9% logic, 9.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     6.694ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               I_SWI<5> (PAD)
  Destination:          HIO/HIO/HIO/IOB_SWI/R_DI_5 (FF)
  Destination Clock:    I_CLK50_BUFGP rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      6.222ns (Levels of Logic = 0)
  Clock Path Delay:     2.916ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: I_SWI<5> to HIO/HIO/HIO/IOB_SWI/R_DI_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    L13.ICLK1            Tiopickd              6.222   I_SWI<5>
                                                       I_SWI<5>
                                                       I_SWI_5_IBUF
                                                       I_SWI<5>.IFD_DELAY
                                                       HIO/HIO/HIO/IOB_SWI/R_DI_5
    -------------------------------------------------  ---------------------------
    Total                                      6.222ns (6.222ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: I_CLK50 to HIO/HIO/HIO/IOB_SWI/R_DI_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    L13.ICLK1            net (fanout=594)      0.248   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.916ns (2.632ns logic, 0.284ns route)
                                                       (90.3% logic, 9.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     6.694ns (requirement - (data path - clock path - clock arrival + uncertainty))
  Source:               I_SWI<0> (PAD)
  Destination:          HIO/HIO/HIO/IOB_SWI/R_DI_0 (FF)
  Destination Clock:    I_CLK50_BUFGP rising at 0.000ns
  Requirement:          10.000ns
  Data Path Delay:      6.222ns (Levels of Logic = 0)
  Clock Path Delay:     2.916ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Data Path: I_SWI<0> to HIO/HIO/HIO/IOB_SWI/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    G18.ICLK1            Tiopickd              6.222   I_SWI<0>
                                                       I_SWI<0>
                                                       I_SWI_0_IBUF
                                                       I_SWI<0>.IFD_DELAY
                                                       HIO/HIO/HIO/IOB_SWI/R_DI_0
    -------------------------------------------------  ---------------------------
    Total                                      6.222ns (6.222ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Minimum Clock Path: I_CLK50 to HIO/HIO/HIO/IOB_SWI/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    G18.ICLK1            net (fanout=594)      0.248   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.916ns (2.632ns logic, 0.284ns route)
                                                       (90.3% logic, 9.7% route)

--------------------------------------------------------------------------------

Hold Paths: OFFSET = IN 10 ns BEFORE COMP "I_CLK50";
--------------------------------------------------------------------------------
Offset (hold paths):    0.097ns (data path - clock path + uncertainty)
  Source:               I_SWI<6> (PAD)
  Destination:          HIO/HIO/HIO/IOB_SWI/R_DI_6 (FF)
  Destination Clock:    I_CLK50_BUFGP rising at 0.000ns
  Data Path Delay:      3.705ns (Levels of Logic = 0)
  Clock Path Delay:     3.608ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Minimum Data Path: I_SWI<6> to HIO/HIO/HIO/IOB_SWI/R_DI_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    N17.ICLK1            Tioickpd    (-Th)    -3.705   I_SWI<6>
                                                       I_SWI<6>
                                                       I_SWI_6_IBUF
                                                       I_SWI<6>.IFD_DELAY
                                                       HIO/HIO/HIO/IOB_SWI/R_DI_6
    -------------------------------------------------  ---------------------------
    Total                                      3.705ns (3.705ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Maximum Clock Path: I_CLK50 to HIO/HIO/HIO/IOB_SWI/R_DI_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    N17.ICLK1            net (fanout=594)      0.379   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.608ns (3.183ns logic, 0.425ns route)
                                                       (88.2% logic, 11.8% route)

--------------------------------------------------------------------------------
Offset (hold paths):    0.101ns (data path - clock path + uncertainty)
  Source:               I_BTN<0> (PAD)
  Destination:          HIO/HIO/HIO/IOB_BTN/R_DI_0 (FF)
  Destination Clock:    I_CLK50_BUFGP rising at 0.000ns
  Data Path Delay:      3.705ns (Levels of Logic = 0)
  Clock Path Delay:     3.604ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Minimum Data Path: I_BTN<0> to HIO/HIO/HIO/IOB_BTN/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B18.ICLK1            Tioickpd    (-Th)    -3.705   I_BTN<0>
                                                       I_BTN<0>
                                                       I_BTN_0_IBUF
                                                       I_BTN<0>.IFD_DELAY
                                                       HIO/HIO/HIO/IOB_BTN/R_DI_0
    -------------------------------------------------  ---------------------------
    Total                                      3.705ns (3.705ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Maximum Clock Path: I_CLK50 to HIO/HIO/HIO/IOB_BTN/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    B18.ICLK1            net (fanout=594)      0.375   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.604ns (3.183ns logic, 0.421ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Offset (hold paths):    0.104ns (data path - clock path + uncertainty)
  Source:               I_FUSP_CTS_N (PAD)
  Destination:          IOB_RS232/P1/IOB_CTS/IOB/R_DI_0 (FF)
  Destination Clock:    I_CLK50_BUFGP rising at 0.000ns
  Data Path Delay:      3.705ns (Levels of Logic = 0)
  Clock Path Delay:     3.601ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Minimum Data Path: I_FUSP_CTS_N to IOB_RS232/P1/IOB_CTS/IOB/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    R18.ICLK1            Tioickpd    (-Th)    -3.705   I_FUSP_CTS_N
                                                       I_FUSP_CTS_N
                                                       I_FUSP_CTS_N_IBUF
                                                       I_FUSP_CTS_N.IFD_DELAY
                                                       IOB_RS232/P1/IOB_CTS/IOB/R_DI_0
    -------------------------------------------------  ---------------------------
    Total                                      3.705ns (3.705ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

  Maximum Clock Path: I_CLK50 to IOB_RS232/P1/IOB_CTS/IOB/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    R18.ICLK1            net (fanout=594)      0.372   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.601ns (3.183ns logic, 0.418ns route)
                                                       (88.4% logic, 11.6% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: OFFSET = OUT 20 ns AFTER COMP "I_CLK50";
For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612).

 23 paths analyzed, 23 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
 Minimum allowable offset is   7.992ns.
--------------------------------------------------------------------------------
Slack (slowest paths):  12.008ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               IOB_RS232/P1/IOB_TXD/IOB/R_DO_0 (FF)
  Destination:          O_FUSP_TXD (PAD)
  Source Clock:         I_CLK50_BUFGP rising at 0.000ns
  Requirement:          20.000ns
  Data Path Delay:      4.388ns (Levels of Logic = 0)
  Clock Path Delay:     3.604ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: I_CLK50 to IOB_RS232/P1/IOB_TXD/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    T17.OTCLK1           net (fanout=594)      0.375   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.604ns (3.183ns logic, 0.421ns route)
                                                       (88.3% logic, 11.7% route)

  Maximum Data Path: IOB_RS232/P1/IOB_TXD/IOB/R_DO_0 to O_FUSP_TXD
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    T17.PAD              Tiockp                4.388   O_FUSP_TXD
                                                       IOB_RS232/P1/IOB_TXD/IOB/R_DO_0
                                                       O_FUSP_TXD_OBUF
                                                       O_FUSP_TXD
    -------------------------------------------------  ---------------------------
    Total                                      4.388ns (4.388ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  12.077ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               IOB_RS232/P1/IOB_RTS/IOB/R_DO_0 (FF)
  Destination:          O_FUSP_RTS_N (PAD)
  Source Clock:         I_CLK50_BUFGP rising at 0.000ns
  Requirement:          20.000ns
  Data Path Delay:      4.388ns (Levels of Logic = 0)
  Clock Path Delay:     3.535ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: I_CLK50 to IOB_RS232/P1/IOB_RTS/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    M13.OTCLK1           net (fanout=594)      0.306   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.535ns (3.183ns logic, 0.352ns route)
                                                       (90.0% logic, 10.0% route)

  Maximum Data Path: IOB_RS232/P1/IOB_RTS/IOB/R_DO_0 to O_FUSP_RTS_N
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    M13.PAD              Tiockp                4.388   O_FUSP_RTS_N
                                                       IOB_RS232/P1/IOB_RTS/IOB/R_DO_0
                                                       O_FUSP_RTS_N_OBUF
                                                       O_FUSP_RTS_N
    -------------------------------------------------  ---------------------------
    Total                                      4.388ns (4.388ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------
Slack (slowest paths):  13.482ns (requirement - (clock arrival + clock path + data path + uncertainty))
  Source:               HIO/HIO/IOB_ANO_N/R_DO_3 (FF)
  Destination:          O_ANO_N<3> (PAD)
  Source Clock:         I_CLK50_BUFGP rising at 0.000ns
  Requirement:          20.000ns
  Data Path Delay:      2.912ns (Levels of Logic = 0)
  Clock Path Delay:     3.606ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Maximum Clock Path: I_CLK50 to HIO/HIO/IOB_ANO_N/R_DO_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    F15.OTCLK1           net (fanout=594)      0.377   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.606ns (3.183ns logic, 0.423ns route)
                                                       (88.3% logic, 11.7% route)

  Maximum Data Path: HIO/HIO/IOB_ANO_N/R_DO_3 to O_ANO_N<3>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    F15.PAD              Tiockp                2.912   O_ANO_N<3>
                                                       HIO/HIO/IOB_ANO_N/R_DO_3
                                                       O_ANO_N_3_OBUF
                                                       O_ANO_N<3>
    -------------------------------------------------  ---------------------------
    Total                                      2.912ns (2.912ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------

Fastest Paths: OFFSET = OUT 20 ns AFTER COMP "I_CLK50";
--------------------------------------------------------------------------------
Delay (fastest paths):  5.330ns (clock arrival + clock path + data path - uncertainty)
  Source:               HIO/HIO/IOB_ANO_N/R_DO_1 (FF)
  Destination:          O_ANO_N<1> (PAD)
  Source Clock:         I_CLK50_BUFGP rising at 0.000ns
  Data Path Delay:      2.412ns (Levels of Logic = 0)
  Clock Path Delay:     2.918ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Minimum Clock Path: I_CLK50 to HIO/HIO/IOB_ANO_N/R_DO_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    H17.OTCLK1           net (fanout=594)      0.250   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.918ns (2.632ns logic, 0.286ns route)
                                                       (90.2% logic, 9.8% route)

  Minimum Data Path: HIO/HIO/IOB_ANO_N/R_DO_1 to O_ANO_N<1>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H17.PAD              Tiockp                2.412   O_ANO_N<1>
                                                       HIO/HIO/IOB_ANO_N/R_DO_1
                                                       O_ANO_N_1_OBUF
                                                       O_ANO_N<1>
    -------------------------------------------------  ---------------------------
    Total                                      2.412ns (2.412ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  5.328ns (clock arrival + clock path + data path - uncertainty)
  Source:               HIO/HIO/IOB_SEG_N/R_DO_6 (FF)
  Destination:          O_SEG_N<6> (PAD)
  Source Clock:         I_CLK50_BUFGP rising at 0.000ns
  Data Path Delay:      2.412ns (Levels of Logic = 0)
  Clock Path Delay:     2.916ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Minimum Clock Path: I_CLK50 to HIO/HIO/IOB_SEG_N/R_DO_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    H14.OTCLK1           net (fanout=594)      0.248   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.916ns (2.632ns logic, 0.284ns route)
                                                       (90.3% logic, 9.7% route)

  Minimum Data Path: HIO/HIO/IOB_SEG_N/R_DO_6 to O_SEG_N<6>
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    H14.PAD              Tiockp                2.412   O_SEG_N<6>
                                                       HIO/HIO/IOB_SEG_N/R_DO_6
                                                       O_SEG_N_6_OBUF
                                                       O_SEG_N<6>
    -------------------------------------------------  ---------------------------
    Total                                      2.412ns (2.412ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------
Delay (fastest paths):  5.313ns (clock arrival + clock path + data path - uncertainty)
  Source:               IOB_RS232/P0/IOB_TXD/IOB/R_DO_0 (FF)
  Destination:          O_TXD (PAD)
  Source Clock:         I_CLK50_BUFGP rising at 0.000ns
  Data Path Delay:      2.412ns (Levels of Logic = 0)
  Clock Path Delay:     2.901ns (Levels of Logic = 2)
  Clock Uncertainty:    0.000ns

  Minimum Clock Path: I_CLK50 to IOB_RS232/P0/IOB_TXD/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    P9.OTCLK1            net (fanout=594)      0.233   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.901ns (2.632ns logic, 0.269ns route)
                                                       (90.7% logic, 9.3% route)

  Minimum Data Path: IOB_RS232/P0/IOB_TXD/IOB/R_DO_0 to O_TXD
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    P9.PAD               Tiockp                2.412   O_TXD
                                                       IOB_RS232/P0/IOB_TXD/IOB/R_DO_0
                                                       O_TXD_OBUF
                                                       O_TXD
    -------------------------------------------------  ---------------------------
    Total                                      2.412ns (2.412ns logic, 0.000ns route)
                                                       (100.0% logic, 0.0% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: Unconstrained path analysis 

 941 paths analyzed, 941 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   3.608ns.
--------------------------------------------------------------------------------
Delay (setup path):     3.608ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/HIO/IOB_SWI/R_DI_6 (FF)
  Data Path Delay:      3.608ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/HIO/IOB_SWI/R_DI_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    N17.ICLK1            net (fanout=594)      0.379   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.608ns (3.183ns logic, 0.425ns route)
                                                       (88.2% logic, 11.8% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.606ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/DRV/R_REGS.cdiv_6 (FF)
  Data Path Delay:      3.606ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/DRV/R_REGS.cdiv_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X90Y94.CLK     net (fanout=594)      0.377   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.606ns (3.183ns logic, 0.423ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.606ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/IOB_ANO_N/R_DO_3 (FF)
  Data Path Delay:      3.606ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/IOB_ANO_N/R_DO_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    F15.OTCLK1           net (fanout=594)      0.377   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.606ns (3.183ns logic, 0.423ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.605ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/DRV/R_REGS.cdiv_3 (FF)
  Data Path Delay:      3.605ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/DRV/R_REGS.cdiv_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X91Y97.CLK     net (fanout=594)      0.376   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.605ns (3.183ns logic, 0.422ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.605ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/DRV/R_REGS.cdiv_4 (FF)
  Data Path Delay:      3.605ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/DRV/R_REGS.cdiv_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X91Y96.CLK     net (fanout=594)      0.376   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.605ns (3.183ns logic, 0.422ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.605ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/DRV/R_REGS.cdiv_2 (FF)
  Data Path Delay:      3.605ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/DRV/R_REGS.cdiv_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X91Y97.CLK     net (fanout=594)      0.376   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.605ns (3.183ns logic, 0.422ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.605ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/DRV/R_REGS.dcnt_0 (FF)
  Data Path Delay:      3.605ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/DRV/R_REGS.dcnt_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X90Y96.CLK     net (fanout=594)      0.376   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.605ns (3.183ns logic, 0.422ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.605ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/DRV/R_REGS.cdiv_5 (FF)
  Data Path Delay:      3.605ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/DRV/R_REGS.cdiv_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X90Y97.CLK     net (fanout=594)      0.376   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.605ns (3.183ns logic, 0.422ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.605ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/DRV/R_REGS.dcnt_1 (FF)
  Data Path Delay:      3.605ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/DRV/R_REGS.dcnt_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X90Y96.CLK     net (fanout=594)      0.376   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.605ns (3.183ns logic, 0.422ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.604ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/HIO/IOB_BTN/R_DI_0 (FF)
  Data Path Delay:      3.604ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/HIO/IOB_BTN/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    B18.ICLK1            net (fanout=594)      0.375   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.604ns (3.183ns logic, 0.421ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.604ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          IOB_RS232/P1/IOB_TXD/IOB/R_DO_0 (FF)
  Data Path Delay:      3.604ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to IOB_RS232/P1/IOB_TXD/IOB/R_DO_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    T17.OTCLK1           net (fanout=594)      0.375   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.604ns (3.183ns logic, 0.421ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.604ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/HIO/IOB_LED/R_DO_6 (FF)
  Data Path Delay:      3.604ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/HIO/IOB_LED/R_DO_6
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    E4.OTCLK1            net (fanout=594)      0.375   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.604ns (3.183ns logic, 0.421ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.603ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RBDTST/MON/R_REGS.hilim_3 (FF)
  Data Path Delay:      3.603ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to RBDTST/MON/R_REGS.hilim_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X89Y92.CLK     net (fanout=594)      0.374   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.603ns (3.183ns logic, 0.420ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.603ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RBDTST/MON/R_REGS.lolim_3 (FF)
  Data Path Delay:      3.603ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to RBDTST/MON/R_REGS.lolim_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X89Y93.CLK     net (fanout=594)      0.374   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.603ns (3.183ns logic, 0.420ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.603ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RBDTST/MON/R_REGS.hilim_2 (FF)
  Data Path Delay:      3.603ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to RBDTST/MON/R_REGS.hilim_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X89Y92.CLK     net (fanout=594)      0.374   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.603ns (3.183ns logic, 0.420ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.603ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RBDTST/MON/R_REGS.lolim_2 (FF)
  Data Path Delay:      3.603ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to RBDTST/MON/R_REGS.lolim_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X89Y93.CLK     net (fanout=594)      0.374   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.603ns (3.183ns logic, 0.420ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.603ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/DRV/R_REGS.cdiv_0 (FF)
  Data Path Delay:      3.603ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/DRV/R_REGS.cdiv_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X91Y98.CLK     net (fanout=594)      0.374   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.603ns (3.183ns logic, 0.420ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.603ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/DRV/R_REGS.cdiv_1 (FF)
  Data Path Delay:      3.603ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/DRV/R_REGS.cdiv_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X90Y99.CLK     net (fanout=594)      0.374   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.603ns (3.183ns logic, 0.420ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.603ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/IOB_ANO_N/R_DO_2 (FF)
  Data Path Delay:      3.603ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/IOB_ANO_N/R_DO_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    C18.OTCLK1           net (fanout=594)      0.374   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.603ns (3.183ns logic, 0.420ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.603ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/IOB_SEG_N/R_DO_7 (FF)
  Data Path Delay:      3.603ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/IOB_SEG_N/R_DO_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    C17.OTCLK1           net (fanout=594)      0.374   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.603ns (3.183ns logic, 0.420ns route)
                                                       (88.3% logic, 11.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.602ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/HIO/IOB_LED/R_DO_7 (FF)
  Data Path Delay:      3.602ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/HIO/IOB_LED/R_DO_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    P4.OTCLK1            net (fanout=594)      0.373   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.602ns (3.183ns logic, 0.419ns route)
                                                       (88.4% logic, 11.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.601ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          IOB_RS232/P1/IOB_CTS/IOB/R_DI_0 (FF)
  Data Path Delay:      3.601ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to IOB_RS232/P1/IOB_CTS/IOB/R_DI_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    R18.ICLK1            net (fanout=594)      0.372   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.601ns (3.183ns logic, 0.418ns route)
                                                       (88.4% logic, 11.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.599ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/HIO/IOB_LED/R_DO_5 (FF)
  Data Path Delay:      3.599ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/HIO/IOB_LED/R_DO_5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    P16.OTCLK1           net (fanout=594)      0.370   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.599ns (3.183ns logic, 0.416ns route)
                                                       (88.4% logic, 11.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.599ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/IOB_SEG_N/R_DO_3 (FF)
  Data Path Delay:      3.599ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/IOB_SEG_N/R_DO_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    D16.OTCLK1           net (fanout=594)      0.370   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.599ns (3.183ns logic, 0.416ns route)
                                                       (88.4% logic, 11.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.599ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          HIO/HIO/IOB_SEG_N/R_DO_2 (FF)
  Data Path Delay:      3.599ns (Levels of Logic = 2)

  Maximum Data Path: I_CLK50 to HIO/HIO/IOB_SEG_N/R_DO_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.726   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.046   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.457   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    D17.OTCLK1           net (fanout=594)      0.370   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      3.599ns (3.183ns logic, 0.416ns route)
                                                       (88.4% logic, 11.6% route)

--------------------------------------------------------------------------------

Hold Paths: Unconstrained path analysis

--------------------------------------------------------------------------------
Delay (hold path):      2.812ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/CORE/RL/R_REGS.ccmd_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.812ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/CORE/RL/R_REGS.ccmd_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X62Y44.CLK     net (fanout=594)      0.144   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.812ns (2.632ns logic, 0.180ns route)
                                                       (93.6% logic, 6.4% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.812ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/CORE/RL/R_REGS.ccmd_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.812ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/CORE/RL/R_REGS.ccmd_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X62Y44.CLK     net (fanout=594)      0.144   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.812ns (2.632ns logic, 0.180ns route)
                                                       (93.6% logic, 6.4% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.812ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/SERPORT/R_RXOK (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.812ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/SERPORT/R_RXOK
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X29Y42.CLK     net (fanout=594)      0.144   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.812ns (2.632ns logic, 0.180ns route)
                                                       (93.6% logic, 6.4% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.812ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/SERPORT/RXFIFO/FIFO/R_REGS.empty (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.812ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/SERPORT/RXFIFO/FIFO/R_REGS.empty
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X28Y42.CLK     net (fanout=594)      0.144   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.812ns (2.632ns logic, 0.180ns route)
                                                       (93.6% logic, 6.4% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.814ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/SERPORT/UART/AB/R_REGS.seen1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.814ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/SERPORT/UART/AB/R_REGS.seen1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X29Y41.CLK     net (fanout=594)      0.146   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.814ns (2.632ns logic, 0.182ns route)
                                                       (93.5% logic, 6.5% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.814ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RBDTST/TEST/FIFO/RAM/AW_4.GL[0].MEM.SLICEM_G (RAM)
  Requirement:          0.000ns
  Data Path Delay:      2.814ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RBDTST/TEST/FIFO/RAM/AW_4.GL[0].MEM.SLICEM_G
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X62Y73.CLK     net (fanout=594)      0.146   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.814ns (2.632ns logic, 0.182ns route)
                                                       (93.5% logic, 6.5% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.814ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RBDTST/TEST/FIFO/RAM/AW_4.GL[0].MEM.SLICEM_F (RAM)
  Requirement:          0.000ns
  Data Path Delay:      2.814ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RBDTST/TEST/FIFO/RAM/AW_4.GL[0].MEM.SLICEM_F
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X62Y73.CLK     net (fanout=594)      0.146   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.814ns (2.632ns logic, 0.182ns route)
                                                       (93.5% logic, 6.5% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.814ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RBDTST/TEST/FIFO/RAM/AW_4.GL[0].MEM.WE (RAM)
  Requirement:          0.000ns
  Data Path Delay:      2.814ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RBDTST/TEST/FIFO/RAM/AW_4.GL[0].MEM.WE
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X62Y73.CLK     net (fanout=594)      0.146   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.814ns (2.632ns logic, 0.182ns route)
                                                       (93.5% logic, 6.5% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.814ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/SERPORT/UART/AB/R_REGS.state_FSM_FFd2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.814ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/SERPORT/UART/AB/R_REGS.state_FSM_FFd2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X28Y41.CLK     net (fanout=594)      0.146   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.814ns (2.632ns logic, 0.182ns route)
                                                       (93.5% logic, 6.5% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.814ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/CORE/RL/R_REGS.rberr (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.814ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/CORE/RL/R_REGS.rberr
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X63Y46.CLK     net (fanout=594)      0.146   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.814ns (2.632ns logic, 0.182ns route)
                                                       (93.5% logic, 6.5% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.815ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/CORE/RL/ICRC/R_CRC_7 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.815ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/CORE/RL/ICRC/R_CRC_7
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X27Y44.CLK     net (fanout=594)      0.147   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.815ns (2.632ns logic, 0.183ns route)
                                                       (93.5% logic, 6.5% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.815ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/CORE/RL/ICRC/R_CRC_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.815ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/CORE/RL/ICRC/R_CRC_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X27Y45.CLK     net (fanout=594)      0.147   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.815ns (2.632ns logic, 0.183ns route)
                                                       (93.5% logic, 6.5% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.815ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/CORE/RL/ICRC/R_CRC_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.815ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/CORE/RL/ICRC/R_CRC_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X26Y45.CLK     net (fanout=594)      0.147   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.815ns (2.632ns logic, 0.183ns route)
                                                       (93.5% logic, 6.5% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.817ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/CORE/RL/R_REGS.andone (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.817ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/CORE/RL/R_REGS.andone
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X63Y49.CLK     net (fanout=594)      0.149   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.817ns (2.632ns logic, 0.185ns route)
                                                       (93.4% logic, 6.6% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.817ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/SERPORT/UART/AB/R_REGS.mcnt_0 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.817ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/SERPORT/UART/AB/R_REGS.mcnt_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X29Y49.CLK     net (fanout=594)      0.149   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.817ns (2.632ns logic, 0.185ns route)
                                                       (93.4% logic, 6.6% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.817ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RBDTST/TEST/R_REGS.ncyc_2 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.817ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RBDTST/TEST/R_REGS.ncyc_2
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X61Y74.CLK     net (fanout=594)      0.149   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.817ns (2.632ns logic, 0.185ns route)
                                                       (93.4% logic, 6.6% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.817ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RBDTST/TEST/R_REGS.ncyc_3 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.817ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RBDTST/TEST/R_REGS.ncyc_3
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X61Y74.CLK     net (fanout=594)      0.149   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.817ns (2.632ns logic, 0.185ns route)
                                                       (93.4% logic, 6.6% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.817ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/SERPORT/RXFIFO/FIFO/R_REGS.full (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.817ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/SERPORT/RXFIFO/FIFO/R_REGS.full
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X30Y42.CLK     net (fanout=594)      0.149   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.817ns (2.632ns logic, 0.185ns route)
                                                       (93.4% logic, 6.6% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.817ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/CORE/RL/R_REGS.state_FSM_FFd4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.817ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/CORE/RL/R_REGS.state_FSM_FFd4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X61Y42.CLK     net (fanout=594)      0.149   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.817ns (2.632ns logic, 0.185ns route)
                                                       (93.4% logic, 6.6% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.817ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/CORE/CD2B/R_REGS.data_4 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.817ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/CORE/CD2B/R_REGS.data_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X62Y48.CLK     net (fanout=594)      0.149   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.817ns (2.632ns logic, 0.185ns route)
                                                       (93.4% logic, 6.6% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.817ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/SERPORT/UART/AB/R_REGS.mcnt_1 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.817ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/SERPORT/UART/AB/R_REGS.mcnt_1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X29Y49.CLK     net (fanout=594)      0.149   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.817ns (2.632ns logic, 0.185ns route)
                                                       (93.4% logic, 6.6% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.818ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RBDTST/TIM1/R_REGS.rbsel (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.818ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RBDTST/TIM1/R_REGS.rbsel
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X63Y71.CLK     net (fanout=594)      0.150   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.818ns (2.632ns logic, 0.186ns route)
                                                       (93.4% logic, 6.6% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.818ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/CORE/RL/R_REGS.rbnak (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.818ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/CORE/RL/R_REGS.rbnak
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X64Y47.CLK     net (fanout=594)      0.150   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.818ns (2.632ns logic, 0.186ns route)
                                                       (93.4% logic, 6.6% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.818ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/CORE/RL/R_REGS.rbaval (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.818ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/CORE/RL/R_REGS.rbaval
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X65Y46.CLK     net (fanout=594)      0.150   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.818ns (2.632ns logic, 0.186ns route)
                                                       (93.4% logic, 6.6% route)

--------------------------------------------------------------------------------
Delay (hold path):      2.818ns (data path)
  Source:               I_CLK50 (PAD)
  Destination:          RLINK/CORE/RL/R_REGS.state_FSM_FFd5 (FF)
  Requirement:          0.000ns
  Data Path Delay:      2.818ns (Levels of Logic = 2)

  Minimum Data Path: I_CLK50 to RLINK/CORE/RL/R_REGS.state_FSM_FFd5
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    B8.I                 Tiopi                 1.466   I_CLK50
                                                       I_CLK50
                                                       I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.I0     net (fanout=1)        0.036   I_CLK50_BUFGP/IBUFG
    BUFGMUX_X2Y11.O      Tgi0o                 1.166   I_CLK50_BUFGP/BUFG
                                                       I_CLK50_BUFGP/BUFG.GCLKMUX
                                                       I_CLK50_BUFGP/BUFG
    SLICE_X64Y46.CLK     net (fanout=594)      0.150   I_CLK50_BUFGP
    -------------------------------------------------  ---------------------------
    Total                                      2.818ns (2.632ns logic, 0.186ns route)
                                                       (93.4% logic, 6.6% route)

--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock I_CLK50
------------+------------+------------+------------------+--------+
            |Max Setup to|Max Hold to |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
I_BTN<0>    |    3.235(R)|   -0.101(R)|I_CLK50_BUFGP     |   0.000|
I_BTN<1>    |    3.244(R)|   -0.112(R)|I_CLK50_BUFGP     |   0.000|
I_BTN<2>    |    3.294(R)|   -0.170(R)|I_CLK50_BUFGP     |   0.000|
I_BTN<3>    |    3.299(R)|   -0.176(R)|I_CLK50_BUFGP     |   0.000|
I_FUSP_CTS_N|    3.238(R)|   -0.104(R)|I_CLK50_BUFGP     |   0.000|
I_FUSP_RXD  |    3.243(R)|   -0.110(R)|I_CLK50_BUFGP     |   0.000|
I_RXD       |    3.327(R)|   -0.209(R)|I_CLK50_BUFGP     |   0.000|
I_SWI<0>    |    3.306(R)|   -0.185(R)|I_CLK50_BUFGP     |   0.000|
I_SWI<1>    |    3.297(R)|   -0.173(R)|I_CLK50_BUFGP     |   0.000|
I_SWI<2>    |    3.294(R)|   -0.170(R)|I_CLK50_BUFGP     |   0.000|
I_SWI<3>    |    3.299(R)|   -0.176(R)|I_CLK50_BUFGP     |   0.000|
I_SWI<4>    |    3.297(R)|   -0.174(R)|I_CLK50_BUFGP     |   0.000|
I_SWI<5>    |    3.306(R)|   -0.185(R)|I_CLK50_BUFGP     |   0.000|
I_SWI<6>    |    3.232(R)|   -0.097(R)|I_CLK50_BUFGP     |   0.000|
I_SWI<7>    |    3.240(R)|   -0.107(R)|I_CLK50_BUFGP     |   0.000|
------------+------------+------------+------------------+--------+

Clock I_CLK50 to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
O_ANO_N<0>  |    6.444(R)|I_CLK50_BUFGP     |   0.000|
O_ANO_N<1>  |    6.435(R)|I_CLK50_BUFGP     |   0.000|
O_ANO_N<2>  |    6.515(R)|I_CLK50_BUFGP     |   0.000|
O_ANO_N<3>  |    6.518(R)|I_CLK50_BUFGP     |   0.000|
O_FUSP_RTS_N|    7.923(R)|I_CLK50_BUFGP     |   0.000|
O_FUSP_TXD  |    7.992(R)|I_CLK50_BUFGP     |   0.000|
O_LED<0>    |    6.445(R)|I_CLK50_BUFGP     |   0.000|
O_LED<1>    |    6.445(R)|I_CLK50_BUFGP     |   0.000|
O_LED<2>    |    6.447(R)|I_CLK50_BUFGP     |   0.000|
O_LED<3>    |    6.447(R)|I_CLK50_BUFGP     |   0.000|
O_LED<4>    |    6.505(R)|I_CLK50_BUFGP     |   0.000|
O_LED<5>    |    6.511(R)|I_CLK50_BUFGP     |   0.000|
O_LED<6>    |    6.516(R)|I_CLK50_BUFGP     |   0.000|
O_LED<7>    |    6.514(R)|I_CLK50_BUFGP     |   0.000|
O_SEG_N<0>  |    6.438(R)|I_CLK50_BUFGP     |   0.000|
O_SEG_N<1>  |    6.444(R)|I_CLK50_BUFGP     |   0.000|
O_SEG_N<2>  |    6.511(R)|I_CLK50_BUFGP     |   0.000|
O_SEG_N<3>  |    6.511(R)|I_CLK50_BUFGP     |   0.000|
O_SEG_N<4>  |    6.447(R)|I_CLK50_BUFGP     |   0.000|
O_SEG_N<5>  |    6.447(R)|I_CLK50_BUFGP     |   0.000|
O_SEG_N<6>  |    6.432(R)|I_CLK50_BUFGP     |   0.000|
O_SEG_N<7>  |    6.515(R)|I_CLK50_BUFGP     |   0.000|
O_TXD       |    6.415(R)|I_CLK50_BUFGP     |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock I_CLK50
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
I_CLK50        |   14.429|         |         |         |
---------------+---------+---------+---------+---------+

OFFSET = OUT 20 ns AFTER COMP "I_CLK50";
Bus Skew: 1.577 ns; 
-----------------------------------------------+-------------+--------------+
PAD                                            | Delay (ns)  |Edge Skew (ns)|
-----------------------------------------------+-------------+--------------+
O_ANO_N<0>                                     |        6.444|         0.029|
O_ANO_N<1>                                     |        6.435|         0.020|
O_ANO_N<2>                                     |        6.515|         0.100|
O_ANO_N<3>                                     |        6.518|         0.103|
O_FUSP_RTS_N                                   |        7.923|         1.508|
O_FUSP_TXD                                     |        7.992|         1.577|
O_LED<0>                                       |        6.445|         0.030|
O_LED<1>                                       |        6.445|         0.030|
O_LED<2>                                       |        6.447|         0.032|
O_LED<3>                                       |        6.447|         0.032|
O_LED<4>                                       |        6.505|         0.090|
O_LED<5>                                       |        6.511|         0.096|
O_LED<6>                                       |        6.516|         0.101|
O_LED<7>                                       |        6.514|         0.099|
O_SEG_N<0>                                     |        6.438|         0.023|
O_SEG_N<1>                                     |        6.444|         0.029|
O_SEG_N<2>                                     |        6.511|         0.096|
O_SEG_N<3>                                     |        6.511|         0.096|
O_SEG_N<4>                                     |        6.447|         0.032|
O_SEG_N<5>                                     |        6.447|         0.032|
O_SEG_N<6>                                     |        6.432|         0.017|
O_SEG_N<7>                                     |        6.515|         0.100|
O_TXD                                          |        6.415|         0.000|
-----------------------------------------------+-------------+--------------+


Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

Constraints cover 35847 paths, 0 nets, and 7497 connections

Design statistics:
   Minimum period:  14.429ns{1}   (Maximum frequency:  69.305MHz)
   Maximum combinational path delay:   3.608ns
   Minimum input required time before clock:   3.327ns
   Minimum output required time after clock:   7.992ns


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Tue Aug  5 18:58:37 2014 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 395 MB



