Release 14.7 par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.

athome::  Tue Aug 05 18:57:43 2014

par -w -ol high -xe n -intstyle xflow sys_tst_rlink_n2_map.ncd
sys_tst_rlink_n2.ncd sys_tst_rlink_n2.pcf 


Constraints file: sys_tst_rlink_n2.pcf.
Loading device for application Rf_Device from file '3s1200e.nph' in environment
/mnt/data/opt/Xilinx/ISE/14.7/ISE_DS/ISE/.
   "sys_tst_rlink_n2" is an NCD, version 3.2, device xc3s1200e, package fg320, speed -4
WARNING:ConstraintSystem - The Offset constraint <OFFSET = IN 10 ns BEFORE COMP "I_CLK50";> [sys_tst_rlink_n2.pcf(720)],
   is specified without a duration.  This will result in a lack of hold time checks in timing reports.  If hold time
   checks are desired a duration value should be specified following the 'VALID' keyword.


Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)


Device speed data version:  "PRODUCTION 1.27 2013-10-13".


Design Summary Report:

 Number of External IOBs                          88 out of 250    35%

   Number of External Input IOBs                 17

      Number of External Input IBUFs             17
        Number of LOCed External Input IBUFs     17 out of 17    100%


   Number of External Output IOBs                71

      Number of External Output IOBs             71
        Number of LOCed External Output IOBs     71 out of 71    100%


   Number of External Bidir IOBs                  0


   Number of BUFGMUXs                        1 out of 24      4%
   Number of RAMB16s                         4 out of 28     14%
   Number of Slices                       1057 out of 8672   12%
      Number of SLICEMs                     48 out of 4336    1%



Overall effort level (-ol):   High 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    High 
Extra effort level (-xe):     Normal 

Starting initial Timing Analysis.  REAL time: 5 secs 
Finished initial Timing Analysis.  REAL time: 5 secs 

WARNING:Par:288 - The signal I_MEM_WAIT_IBUF has no load.  PAR will not attempt to route this signal.

Starting Placer
Total REAL time at the beginning of Placer: 5 secs 
Total CPU  time at the beginning of Placer: 2 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:cd29530b) REAL time: 7 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:cd29530b) REAL time: 7 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:cd29530b) REAL time: 7 secs 

Phase 4.2  Initial Clock and IO Placement

Phase 4.2  Initial Clock and IO Placement (Checksum:9bce4f5b) REAL time: 7 secs 

Phase 5.30  Global Clock Region Assignment
Phase 5.30  Global Clock Region Assignment (Checksum:9bce4f5b) REAL time: 7 secs 

Phase 6.36  Local Placement Optimization
Phase 6.36  Local Placement Optimization (Checksum:9bce4f5b) REAL time: 7 secs 

Phase 7.8  Global Placement
........................................................................................................
...............
Phase 7.8  Global Placement (Checksum:f680c697) REAL time: 13 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:f680c697) REAL time: 13 secs 

Phase 9.18  Placement Optimization
Phase 9.18  Placement Optimization (Checksum:91958bb8) REAL time: 17 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:91958bb8) REAL time: 17 secs 

Total REAL time to Placer completion: 17 secs 
Total CPU  time to Placer completion: 8 secs 
Writing design to file sys_tst_rlink_n2.ncd



Starting Router


Phase  1  : 7591 unrouted;      REAL time: 32 secs 

Phase  2  : 6957 unrouted;      REAL time: 33 secs 

Phase  3  : 1743 unrouted;      REAL time: 34 secs 

Phase  4  : 1743 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 36 secs 

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 38 secs 

Updating file: sys_tst_rlink_n2.ncd with current fully routed design.

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 40 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 40 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 41 secs 

Total REAL time to Router completion: 41 secs 
Total CPU time to Router completion: 20 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|       I_CLK50_BUFGP | BUFGMUX_X2Y11| No   |  594 |  0.210     |  0.379      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_I_CLK50 = PERIOD TIMEGRP "I_CLK50" 20  | SETUP       |     5.571ns|    14.429ns|       0|           0
  ns HIGH 50%                               | HOLD        |     0.765ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  OFFSET = IN 10 ns BEFORE COMP "I_CLK50"   | SETUP       |     6.673ns|     3.327ns|       0|           0
----------------------------------------------------------------------------------------------------------
  OFFSET = OUT 20 ns AFTER COMP "I_CLK50"   | MAXDELAY    |    12.008ns|     7.992ns|       0|           0
----------------------------------------------------------------------------------------------------------


All constraints were met.


Generating Pad Report.

All signals are completely routed.

WARNING:Par:283 - There are 1 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.

Total REAL time to PAR completion: 43 secs 
Total CPU time to PAR completion: 21 secs 

Peak Memory Usage:  606 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 4
Number of info messages: 0

Writing design to file sys_tst_rlink_n2.ncd



PAR done!
