Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> 

Reading constraint file sys_tst_rlink_n2.xcf.
XCF parsing done.
Reading design: /home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/sys_tst_rlink_n2.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
	9.1) Device utilization summary
	9.2) Partition Resource Summary
	9.3) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/sys_tst_rlink_n2.prj"
Input Format                       : VHDL
Synthesis Constraint File          : sys_tst_rlink_n2.xcf

---- Target Parameters
Output File Name                   : "sys_tst_rlink_n2"
Output Format                      : ngc
Target Device                      : xc3s1200e-fg320-4

---- Source Options
Shift Register Extraction          : NO

---- General Options
Optimization Goal                  : SPEED
Optimization Effort                : 2

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/slvtypes.vhd" in Library work.
Package <slvtypes> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/memlib.vhd" in Library work.
Package <memlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/ram_1swar_1ar_gen_unisim.vhd" in Library work.
Entity <ram_1swar_1ar_gen> compiled.
Entity <ram_1swar_1ar_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serportlib.vhd" in Library work.
Package <serportlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_uart_rx.vhd" in Library work.
Entity <serport_uart_rx> compiled.
Entity <serport_uart_rx> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_uart_tx.vhd" in Library work.
Entity <serport_uart_tx> compiled.
Entity <serport_uart_tx> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/comlib/comlib.vhd" in Library work.
Package <comlib> compiled.
Package body <comlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rblib.vhd" in Library work.
Package <rblib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/xlib.vhd" in Library work.
Package <xlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd" in Library work.
Entity <ram_2swsr_xfirst_gen_unisim> compiled.
Entity <ram_2swsr_xfirst_gen_unisim> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd" in Library work.
Entity <ram_1swsr_xfirst_gen_unisim> compiled.
Entity <ram_1swsr_xfirst_gen_unisim> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/fifo_1c_dram_raw.vhd" in Library work.
Entity <fifo_1c_dram_raw> compiled.
Entity <fifo_1c_dram_raw> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_uart_autobaud.vhd" in Library work.
Entity <serport_uart_autobaud> compiled.
Entity <serport_uart_autobaud> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_uart_rxtx.vhd" in Library work.
Entity <serport_uart_rxtx> compiled.
Entity <serport_uart_rxtx> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rlink/rlinklib.vhd" in Library work.
Package <rlinklib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/comlib/crc8.vhd" in Library work.
Entity <crc8> compiled.
Entity <crc8> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/genlib/genlib.vhd" in Library work.
Package <genlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/bpgenlib.vhd" in Library work.
Package <bpgenlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/iob_reg_i_gen.vhd" in Library work.
Entity <iob_reg_i_gen> compiled.
Entity <iob_reg_i_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd" in Library work.
Entity <iob_reg_o_gen> compiled.
Entity <iob_reg_o_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/genlib/debounce_gen.vhd" in Library work.
Entity <debounce_gen> compiled.
Entity <debounce_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/ram_2swsr_wfirst_gen_unisim.vhd" in Library work.
Entity <ram_2swsr_wfirst_gen> compiled.
Entity <ram_2swsr_wfirst_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd" in Library work.
Entity <ram_1swsr_wfirst_gen> compiled.
Entity <ram_1swsr_wfirst_gen> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_uart_rxtx_ab.vhd" in Library work.
Entity <serport_uart_rxtx_ab> compiled.
Entity <serport_uart_rxtx_ab> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_xonrx.vhd" in Library work.
Entity <serport_xonrx> compiled.
Entity <serport_xonrx> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_xontx.vhd" in Library work.
Entity <serport_xontx> compiled.
Entity <serport_xontx> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/fifo_1c_dram.vhd" in Library work.
Entity <fifo_1c_dram> compiled.
Entity <fifo_1c_dram> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rlink/rlink_core.vhd" in Library work.
Entity <rlink_core> compiled.
Entity <rlink_core> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/comlib/byte2cdata.vhd" in Library work.
Entity <byte2cdata> compiled.
Entity <byte2cdata> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/comlib/cdata2byte.vhd" in Library work.
Entity <cdata2byte> compiled.
Entity <cdata2byte> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/bp_swibtnled.vhd" in Library work.
Entity <bp_swibtnled> compiled.
Entity <bp_swibtnled> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/sn_4x7segctl.vhd" in Library work.
Entity <sn_4x7segctl> compiled.
Entity <sn_4x7segctl> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/iob_reg_i.vhd" in Library work.
Entity <iob_reg_i> compiled.
Entity <iob_reg_i> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/iob_reg_o.vhd" in Library work.
Entity <iob_reg_o> compiled.
Entity <iob_reg_o> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rbdlib.vhd" in Library work.
Package <rbdlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rbd_tester.vhd" in Library work.
Entity <rbd_tester> compiled.
Entity <rbd_tester> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rbd_bram.vhd" in Library work.
Entity <rbd_bram> compiled.
Entity <rbd_bram> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rbd_rbmon.vhd" in Library work.
Entity <rbd_rbmon> compiled.
Entity <rbd_rbmon> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rbd_eyemon.vhd" in Library work.
Entity <rbd_eyemon> compiled.
Entity <rbd_eyemon> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rbd_timer.vhd" in Library work.
Entity <rbd_timer> compiled.
Entity <rbd_timer> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rb_sres_or_3.vhd" in Library work.
Entity <rb_sres_or_3> compiled.
Entity <rb_sres_or_3> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rb_sres_or_4.vhd" in Library work.
Entity <rb_sres_or_4> compiled.
Entity <rb_sres_or_4> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rlink/rlink_core8.vhd" in Library work.
Entity <rlink_core8> compiled.
Entity <rlink_core8> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_1clock.vhd" in Library work.
Entity <serport_1clock> compiled.
Entity <serport_1clock> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/sn_humanio.vhd" in Library work.
Entity <sn_humanio> compiled.
Entity <sn_humanio> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/bp_rs232_2line_iob.vhd" in Library work.
Entity <bp_rs232_2line_iob> compiled.
Entity <bp_rs232_2line_iob> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/bp_rs232_4line_iob.vhd" in Library work.
Entity <bp_rs232_4line_iob> compiled.
Entity <bp_rs232_4line_iob> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/bpgenrbuslib.vhd" in Library work.
Package <bpgenrbuslib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/nxcramlib/nxcramlib.vhd" in Library work.
Package <nxcramlib> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../sys_conf.vhd" in Library work.
Package <sys_conf> compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/dcm_sfs_unisim_s3e.vhd" in Library work.
Entity <dcm_sfs> compiled.
Entity <dcm_sfs> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/genlib/clkdivce.vhd" in Library work.
Entity <clkdivce> compiled.
Entity <clkdivce> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/bp_rs232_2l4l_iob.vhd" in Library work.
Entity <bp_rs232_2l4l_iob> compiled.
Entity <bp_rs232_2l4l_iob> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/sn_humanio_rbus.vhd" in Library work.
Entity <sn_humanio_rbus> compiled.
Entity <sn_humanio_rbus> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rlink/rlink_sp1c.vhd" in Library work.
Entity <rlink_sp1c> compiled.
Entity <rlink_sp1c> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../rbd_tst_rlink.vhd" in Library work.
Entity <rbd_tst_rlink> compiled.
Entity <rbd_tst_rlink> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rb_sres_or_2.vhd" in Library work.
Entity <rb_sres_or_2> compiled.
Entity <rb_sres_or_2> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/nxcramlib/nx_cram_dummy.vhd" in Library work.
Entity <nx_cram_dummy> compiled.
Entity <nx_cram_dummy> (Architecture <syn>) compiled.
Compiling vhdl file "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../sys_tst_rlink_n2.vhd" in Library work.
Entity <sys_tst_rlink_n2> compiled.
Entity <sys_tst_rlink_n2> (Architecture <syn>) compiled.

Reading constraint file sys_tst_rlink_n2.xcf.
XCF parsing done.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <sys_tst_rlink_n2> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <dcm_sfs> in library <work> (architecture <syn>) with generics.
	CLKFX_DIVIDE = 1
	CLKFX_MULTIPLY = 1
	CLKIN_PERIOD = 20.000000

Analyzing hierarchy for entity <clkdivce> in library <work> (architecture <syn>) with generics.
	CDUWIDTH = 7
	MSECDIV = 1000
	USECDIV = 50

Analyzing hierarchy for entity <bp_rs232_2l4l_iob> in library <work> (architecture <syn>) with generics.
	RELAY = false

Analyzing hierarchy for entity <sn_humanio_rbus> in library <work> (architecture <syn>) with generics.
	BWIDTH = 4
	DEBOUNCE = true
	RB_ADDR = "11000000"

Analyzing hierarchy for entity <rlink_sp1c> in library <work> (architecture <syn>) with generics.
	ATOWIDTH = 6
	CDINIT = 433
	CDWIDTH = 15
	CPREF = "1000"
	ENAPIN_RBMON = 14
	ENAPIN_RLMON = 15
	IFAWIDTH = 5
	ITOWIDTH = 6
	OFAWIDTH = 5

Analyzing hierarchy for entity <rbd_tst_rlink> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <rb_sres_or_2> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <nx_cram_dummy> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <bp_rs232_2line_iob> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <bp_rs232_4line_iob> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <sn_humanio> in library <work> (architecture <syn>) with generics.
	BWIDTH = 4
	DEBOUNCE = true

Analyzing hierarchy for entity <rlink_core8> in library <work> (architecture <syn>) with generics.
	ATOWIDTH = 6
	CPREF = "1000"
	ENAPIN_RBMON = 14
	ENAPIN_RLMON = 15
	ITOWIDTH = 6

Analyzing hierarchy for entity <serport_1clock> in library <work> (architecture <syn>) with generics.
	CDINIT = 433
	CDWIDTH = 15
	RXFAWIDTH = 5
	TXFAWIDTH = 5

Analyzing hierarchy for entity <rbd_tester> in library <work> (architecture <syn>) with generics.
	RB_ADDR = "11110000"

Analyzing hierarchy for entity <rbd_bram> in library <work> (architecture <syn>) with generics.
	RB_ADDR = "11110100"

Analyzing hierarchy for entity <rbd_rbmon> in library <work> (architecture <syn>) with generics.
	AWIDTH = 9
	RB_ADDR = "11111100"

Analyzing hierarchy for entity <rbd_eyemon> in library <work> (architecture <syn>) with generics.
	RB_ADDR = "11111000"
	RDIV = "00000000"

Analyzing hierarchy for entity <rbd_timer> in library <work> (architecture <syn>) with generics.
	RB_ADDR = "11100000"

Analyzing hierarchy for entity <rbd_timer> in library <work> (architecture <syn>) with generics.
	RB_ADDR = "11100001"

Analyzing hierarchy for entity <rb_sres_or_3> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <rb_sres_or_4> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <iob_reg_i> in library <work> (architecture <syn>) with generics.
	INIT = '1'

Analyzing hierarchy for entity <iob_reg_o> in library <work> (architecture <syn>) with generics.
	INIT = '1'

Analyzing hierarchy for entity <iob_reg_i> in library <work> (architecture <syn>) with generics.
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_o> in library <work> (architecture <syn>) with generics.
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 4
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 8
	INIT = '0'

Analyzing hierarchy for entity <bp_swibtnled> in library <work> (architecture <syn>) with generics.
	BWIDTH = 4
	DEBOUNCE = true
	LWIDTH = 8
	SWIDTH = 8

Analyzing hierarchy for entity <sn_4x7segctl> in library <work> (architecture <syn>) with generics.
	CDWIDTH = 7

Analyzing hierarchy for entity <rlink_core> in library <work> (architecture <syn>) with generics.
	ATOWIDTH = 6
	ITOWIDTH = 6

Analyzing hierarchy for entity <byte2cdata> in library <work> (architecture <syn>) with generics.
	CPREF = "1000"
	NCOMM = 4

Analyzing hierarchy for entity <cdata2byte> in library <work> (architecture <syn>) with generics.
	CPREF = "1000"
	NCOMM = 4

Analyzing hierarchy for entity <serport_uart_rxtx_ab> in library <work> (architecture <syn>) with generics.
	CDINIT = 433
	CDWIDTH = 15

Analyzing hierarchy for entity <serport_xonrx> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <serport_xontx> in library <work> (architecture <syn>).

Analyzing hierarchy for entity <fifo_1c_dram> in library <work> (architecture <syn>) with generics.
	AWIDTH = 5
	DWIDTH = 8

Analyzing hierarchy for entity <fifo_1c_dram_raw> in library <work> (architecture <syn>) with generics.
	AWIDTH = 4
	DWIDTH = 16

Analyzing hierarchy for entity <ram_1swsr_wfirst_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 10
	DWIDTH = 16

Analyzing hierarchy for entity <ram_1swsr_wfirst_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 9
	DWIDTH = 32

Analyzing hierarchy for entity <ram_2swsr_wfirst_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 9
	DWIDTH = 32

Analyzing hierarchy for entity <iob_reg_i_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 1
	INIT = '1'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 1
	INIT = '1'

Analyzing hierarchy for entity <iob_reg_i_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 1
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 1
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_i_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 8
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_i_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 4
	INIT = '0'

Analyzing hierarchy for entity <iob_reg_o_gen> in library <work> (architecture <syn>) with generics.
	DWIDTH = 8
	INIT = '0'

Analyzing hierarchy for entity <debounce_gen> in library <work> (architecture <syn>) with generics.
	CEDIV = 3
	CWIDTH = 2
	DWIDTH = 8

Analyzing hierarchy for entity <debounce_gen> in library <work> (architecture <syn>) with generics.
	CEDIV = 3
	CWIDTH = 2
	DWIDTH = 4

Analyzing hierarchy for entity <crc8> in library <work> (architecture <syn>) with generics.
	INIT = "00000000"

Analyzing hierarchy for entity <serport_uart_autobaud> in library <work> (architecture <syn>) with generics.
	CDINIT = 433
	CDWIDTH = 15

Analyzing hierarchy for entity <serport_uart_rxtx> in library <work> (architecture <syn>) with generics.
	CDWIDTH = 15

Analyzing hierarchy for entity <fifo_1c_dram_raw> in library <work> (architecture <syn>) with generics.
	AWIDTH = 5
	DWIDTH = 8

Analyzing hierarchy for entity <ram_1swar_1ar_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 4
	DWIDTH = 16

Analyzing hierarchy for entity <ram_1swsr_xfirst_gen_unisim> in library <work> (architecture <syn>) with generics.
	AWIDTH = 10
	DWIDTH = 16
	WRITE_MODE = "WRITE_FIRST"

Analyzing hierarchy for entity <ram_1swsr_xfirst_gen_unisim> in library <work> (architecture <syn>) with generics.
	AWIDTH = 9
	DWIDTH = 32
	WRITE_MODE = "WRITE_FIRST"

Analyzing hierarchy for entity <ram_2swsr_xfirst_gen_unisim> in library <work> (architecture <syn>) with generics.
	AWIDTH = 9
	DWIDTH = 32
	WRITE_MODE = "WRITE_FIRST"

Analyzing hierarchy for entity <serport_uart_rx> in library <work> (architecture <syn>) with generics.
	CDWIDTH = 15

Analyzing hierarchy for entity <serport_uart_tx> in library <work> (architecture <syn>) with generics.
	CDWIDTH = 15

Analyzing hierarchy for entity <ram_1swar_1ar_gen> in library <work> (architecture <syn>) with generics.
	AWIDTH = 5
	DWIDTH = 8


=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sys_tst_rlink_n2> in library <work> (Architecture <syn>).
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../sys_tst_rlink_n2.vhd" line 156: Unconnected output port 'LOCKED' of component 'dcm_sfs'.
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../sys_tst_rlink_n2.vhd" line 217: Unconnected output port 'RL_MONI' of component 'rlink_sp1c'.
Entity <sys_tst_rlink_n2> analyzed. Unit <sys_tst_rlink_n2> generated.

Analyzing generic Entity <dcm_sfs> in library <work> (Architecture <syn>).
	CLKFX_DIVIDE = 1
	CLKFX_MULTIPLY = 1
	CLKIN_PERIOD = 20.000000
Entity <dcm_sfs> analyzed. Unit <dcm_sfs> generated.

Analyzing generic Entity <clkdivce> in library <work> (Architecture <syn>).
	CDUWIDTH = 7
	MSECDIV = 1000
	USECDIV = 50
Entity <clkdivce> analyzed. Unit <clkdivce> generated.

Analyzing generic Entity <bp_rs232_2l4l_iob> in library <work> (Architecture <syn>).
	RELAY = false
Entity <bp_rs232_2l4l_iob> analyzed. Unit <bp_rs232_2l4l_iob> generated.

Analyzing Entity <bp_rs232_2line_iob> in library <work> (Architecture <syn>).
Entity <bp_rs232_2line_iob> analyzed. Unit <bp_rs232_2line_iob> generated.

Analyzing generic Entity <iob_reg_i.1> in library <work> (Architecture <syn>).
	INIT = '1'
Entity <iob_reg_i.1> analyzed. Unit <iob_reg_i.1> generated.

Analyzing generic Entity <iob_reg_i_gen.1> in library <work> (Architecture <syn>).
	DWIDTH = 1
	INIT = '1'
    Set user-defined property "IOB =  true" for signal <R_DI>.
Entity <iob_reg_i_gen.1> analyzed. Unit <iob_reg_i_gen.1> generated.

Analyzing generic Entity <iob_reg_o.1> in library <work> (Architecture <syn>).
	INIT = '1'
Entity <iob_reg_o.1> analyzed. Unit <iob_reg_o.1> generated.

Analyzing generic Entity <iob_reg_o_gen.3> in library <work> (Architecture <syn>).
	DWIDTH = 1
	INIT = '1'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.3> analyzed. Unit <iob_reg_o_gen.3> generated.

Analyzing Entity <bp_rs232_4line_iob> in library <work> (Architecture <syn>).
Entity <bp_rs232_4line_iob> analyzed. Unit <bp_rs232_4line_iob> generated.

Analyzing generic Entity <iob_reg_i.2> in library <work> (Architecture <syn>).
	INIT = '0'
Entity <iob_reg_i.2> analyzed. Unit <iob_reg_i.2> generated.

Analyzing generic Entity <iob_reg_i_gen.2> in library <work> (Architecture <syn>).
	DWIDTH = 1
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DI>.
Entity <iob_reg_i_gen.2> analyzed. Unit <iob_reg_i_gen.2> generated.

Analyzing generic Entity <iob_reg_o.2> in library <work> (Architecture <syn>).
	INIT = '0'
Entity <iob_reg_o.2> analyzed. Unit <iob_reg_o.2> generated.

Analyzing generic Entity <iob_reg_o_gen.4> in library <work> (Architecture <syn>).
	DWIDTH = 1
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.4> analyzed. Unit <iob_reg_o_gen.4> generated.

Analyzing generic Entity <sn_humanio_rbus> in library <work> (Architecture <syn>).
	BWIDTH = 4
	DEBOUNCE = true
	RB_ADDR = "11000000"
Entity <sn_humanio_rbus> analyzed. Unit <sn_humanio_rbus> generated.

Analyzing generic Entity <sn_humanio> in library <work> (Architecture <syn>).
	BWIDTH = 4
	DEBOUNCE = true
Entity <sn_humanio> analyzed. Unit <sn_humanio> generated.

Analyzing generic Entity <iob_reg_o_gen.1> in library <work> (Architecture <syn>).
	DWIDTH = 4
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.1> analyzed. Unit <iob_reg_o_gen.1> generated.

Analyzing generic Entity <iob_reg_o_gen.2> in library <work> (Architecture <syn>).
	DWIDTH = 8
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DO>.
Entity <iob_reg_o_gen.2> analyzed. Unit <iob_reg_o_gen.2> generated.

Analyzing generic Entity <bp_swibtnled> in library <work> (Architecture <syn>).
	BWIDTH = 4
	DEBOUNCE = true
	LWIDTH = 8
	SWIDTH = 8
Entity <bp_swibtnled> analyzed. Unit <bp_swibtnled> generated.

Analyzing generic Entity <iob_reg_i_gen.3> in library <work> (Architecture <syn>).
	DWIDTH = 8
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DI>.
Entity <iob_reg_i_gen.3> analyzed. Unit <iob_reg_i_gen.3> generated.

Analyzing generic Entity <iob_reg_i_gen.4> in library <work> (Architecture <syn>).
	DWIDTH = 4
	INIT = '0'
    Set user-defined property "IOB =  true" for signal <R_DI>.
Entity <iob_reg_i_gen.4> analyzed. Unit <iob_reg_i_gen.4> generated.

Analyzing generic Entity <debounce_gen.1> in library <work> (Architecture <syn>).
	CEDIV = 3
	CWIDTH = 2
	DWIDTH = 8
Entity <debounce_gen.1> analyzed. Unit <debounce_gen.1> generated.

Analyzing generic Entity <debounce_gen.2> in library <work> (Architecture <syn>).
	CEDIV = 3
	CWIDTH = 2
	DWIDTH = 4
Entity <debounce_gen.2> analyzed. Unit <debounce_gen.2> generated.

Analyzing generic Entity <sn_4x7segctl> in library <work> (Architecture <syn>).
	CDWIDTH = 7
INFO:Xst:1561 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/sn_4x7segctl.vhd" line 129: Mux is complete : default of case is discarded
Entity <sn_4x7segctl> analyzed. Unit <sn_4x7segctl> generated.

Analyzing generic Entity <rlink_sp1c> in library <work> (Architecture <syn>).
	ATOWIDTH = 6
	CDINIT = 433
	CDWIDTH = 15
	CPREF = "1000"
	ENAPIN_RBMON = 14
	ENAPIN_RLMON = 15
	IFAWIDTH = 5
	ITOWIDTH = 6
	OFAWIDTH = 5
Entity <rlink_sp1c> analyzed. Unit <rlink_sp1c> generated.

Analyzing generic Entity <rlink_core8> in library <work> (Architecture <syn>).
	ATOWIDTH = 6
	CPREF = "1000"
	ENAPIN_RBMON = 14
	ENAPIN_RLMON = 15
	ITOWIDTH = 6
Entity <rlink_core8> analyzed. Unit <rlink_core8> generated.

Analyzing generic Entity <rlink_core> in library <work> (Architecture <syn>).
	ATOWIDTH = 6
	ITOWIDTH = 6
Entity <rlink_core> analyzed. Unit <rlink_core> generated.

Analyzing generic Entity <crc8> in library <work> (Architecture <syn>).
	INIT = "00000000"
Entity <crc8> analyzed. Unit <crc8> generated.

Analyzing generic Entity <byte2cdata> in library <work> (Architecture <syn>).
	CPREF = "1000"
	NCOMM = 4
Entity <byte2cdata> analyzed. Unit <byte2cdata> generated.

Analyzing generic Entity <cdata2byte> in library <work> (Architecture <syn>).
	CPREF = "1000"
	NCOMM = 4
Entity <cdata2byte> analyzed. Unit <cdata2byte> generated.

Analyzing generic Entity <serport_1clock> in library <work> (Architecture <syn>).
	CDINIT = 433
	CDWIDTH = 15
	RXFAWIDTH = 5
	TXFAWIDTH = 5
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_1clock.vhd" line 183: Unconnected output port 'SIZE' of component 'fifo_1c_dram'.
Entity <serport_1clock> analyzed. Unit <serport_1clock> generated.

Analyzing generic Entity <serport_uart_rxtx_ab> in library <work> (Architecture <syn>).
	CDINIT = 433
	CDWIDTH = 15
Entity <serport_uart_rxtx_ab> analyzed. Unit <serport_uart_rxtx_ab> generated.

Analyzing generic Entity <serport_uart_autobaud> in library <work> (Architecture <syn>).
	CDINIT = 433
	CDWIDTH = 15
Entity <serport_uart_autobaud> analyzed. Unit <serport_uart_autobaud> generated.

Analyzing generic Entity <serport_uart_rxtx> in library <work> (Architecture <syn>).
	CDWIDTH = 15
Entity <serport_uart_rxtx> analyzed. Unit <serport_uart_rxtx> generated.

Analyzing generic Entity <serport_uart_rx> in library <work> (Architecture <syn>).
	CDWIDTH = 15
Entity <serport_uart_rx> analyzed. Unit <serport_uart_rx> generated.

Analyzing generic Entity <serport_uart_tx> in library <work> (Architecture <syn>).
	CDWIDTH = 15
Entity <serport_uart_tx> analyzed. Unit <serport_uart_tx> generated.

Analyzing Entity <serport_xonrx> in library <work> (Architecture <syn>).
Entity <serport_xonrx> analyzed. Unit <serport_xonrx> generated.

Analyzing Entity <serport_xontx> in library <work> (Architecture <syn>).
Entity <serport_xontx> analyzed. Unit <serport_xontx> generated.

Analyzing generic Entity <fifo_1c_dram> in library <work> (Architecture <syn>).
	AWIDTH = 5
	DWIDTH = 8
Entity <fifo_1c_dram> analyzed. Unit <fifo_1c_dram> generated.

Analyzing generic Entity <fifo_1c_dram_raw.2> in library <work> (Architecture <syn>).
	AWIDTH = 5
	DWIDTH = 8
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/fifo_1c_dram_raw.vhd" line 79: Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'.
Entity <fifo_1c_dram_raw.2> analyzed. Unit <fifo_1c_dram_raw.2> generated.

Analyzing generic Entity <ram_1swar_1ar_gen.2> in library <work> (Architecture <syn>).
	AWIDTH = 5
	DWIDTH = 8
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[7].MEM0> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[7].MEM1> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[6].MEM0> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[6].MEM1> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[5].MEM0> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[5].MEM1> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[4].MEM0> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[4].MEM1> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[3].MEM0> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[3].MEM1> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[2].MEM0> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[2].MEM1> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[1].MEM0> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[1].MEM1> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[0].MEM0> in unit <ram_1swar_1ar_gen.2>.
    Set user-defined property "INIT =  0000" for instance <AW_5.GL[0].MEM1> in unit <ram_1swar_1ar_gen.2>.
Entity <ram_1swar_1ar_gen.2> analyzed. Unit <ram_1swar_1ar_gen.2> generated.

Analyzing Entity <rbd_tst_rlink> in library <work> (Architecture <syn>).
Entity <rbd_tst_rlink> analyzed. Unit <rbd_tst_rlink> generated.

Analyzing generic Entity <rbd_tester> in library <work> (Architecture <syn>).
	RB_ADDR = "11110000"
Entity <rbd_tester> analyzed. Unit <rbd_tester> generated.

Analyzing generic Entity <fifo_1c_dram_raw.1> in library <work> (Architecture <syn>).
	AWIDTH = 4
	DWIDTH = 16
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/fifo_1c_dram_raw.vhd" line 79: Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'.
Entity <fifo_1c_dram_raw.1> analyzed. Unit <fifo_1c_dram_raw.1> generated.

Analyzing generic Entity <ram_1swar_1ar_gen.1> in library <work> (Architecture <syn>).
	AWIDTH = 4
	DWIDTH = 16
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[15].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[14].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[13].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[12].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[11].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[10].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[9].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[8].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[7].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[6].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[5].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[4].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[3].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[2].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[1].MEM> in unit <ram_1swar_1ar_gen.1>.
    Set user-defined property "INIT =  0000" for instance <AW_4.GL[0].MEM> in unit <ram_1swar_1ar_gen.1>.
Entity <ram_1swar_1ar_gen.1> analyzed. Unit <ram_1swar_1ar_gen.1> generated.

Analyzing generic Entity <rbd_bram> in library <work> (Architecture <syn>).
	RB_ADDR = "11110100"
Entity <rbd_bram> analyzed. Unit <rbd_bram> generated.

Analyzing generic Entity <ram_1swsr_wfirst_gen.1> in library <work> (Architecture <syn>).
	AWIDTH = 10
	DWIDTH = 16
Entity <ram_1swsr_wfirst_gen.1> analyzed. Unit <ram_1swsr_wfirst_gen.1> generated.

Analyzing generic Entity <ram_1swsr_xfirst_gen_unisim.1> in library <work> (Architecture <syn>).
	AWIDTH = 10
	DWIDTH = 16
	WRITE_MODE = "WRITE_FIRST"
    Set user-defined property "INIT =  00000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "SRVAL =  00000" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
    Set user-defined property "WRITE_MODE =  WRITE_FIRST" for instance <AW_10_S18.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.1>.
Entity <ram_1swsr_xfirst_gen_unisim.1> analyzed. Unit <ram_1swsr_xfirst_gen_unisim.1> generated.

Analyzing generic Entity <rbd_rbmon> in library <work> (Architecture <syn>).
	AWIDTH = 9
	RB_ADDR = "11111100"
Entity <rbd_rbmon> analyzed. Unit <rbd_rbmon> generated.

Analyzing generic Entity <ram_1swsr_wfirst_gen.2> in library <work> (Architecture <syn>).
	AWIDTH = 9
	DWIDTH = 32
Entity <ram_1swsr_wfirst_gen.2> analyzed. Unit <ram_1swsr_wfirst_gen.2> generated.

Analyzing generic Entity <ram_1swsr_xfirst_gen_unisim.2> in library <work> (Architecture <syn>).
	AWIDTH = 9
	DWIDTH = 32
	WRITE_MODE = "WRITE_FIRST"
    Set user-defined property "INIT =  000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "SRVAL =  000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
    Set user-defined property "WRITE_MODE =  WRITE_FIRST" for instance <AW_09_S32.GL[0].MEM> in unit <ram_1swsr_xfirst_gen_unisim.2>.
Entity <ram_1swsr_xfirst_gen_unisim.2> analyzed. Unit <ram_1swsr_xfirst_gen_unisim.2> generated.

Analyzing generic Entity <rbd_eyemon> in library <work> (Architecture <syn>).
	RB_ADDR = "11111000"
	RDIV = "00000000"
WARNING:Xst:753 - "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rbd_eyemon.vhd" line 143: Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen'.
Entity <rbd_eyemon> analyzed. Unit <rbd_eyemon> generated.

Analyzing generic Entity <ram_2swsr_wfirst_gen> in library <work> (Architecture <syn>).
	AWIDTH = 9
	DWIDTH = 32
Entity <ram_2swsr_wfirst_gen> analyzed. Unit <ram_2swsr_wfirst_gen> generated.

Analyzing generic Entity <ram_2swsr_xfirst_gen_unisim> in library <work> (Architecture <syn>).
	AWIDTH = 9
	DWIDTH = 32
	WRITE_MODE = "WRITE_FIRST"
    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_A =  000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "INIT_B =  000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "SRVAL_A =  000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "SRVAL_B =  000000000" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <AW_09_S32.GL[0].MEM> in unit <ram_2swsr_xfirst_gen_unisim>.
Entity <ram_2swsr_xfirst_gen_unisim> analyzed. Unit <ram_2swsr_xfirst_gen_unisim> generated.

Analyzing generic Entity <rbd_timer.1> in library <work> (Architecture <syn>).
	RB_ADDR = "11100000"
Entity <rbd_timer.1> analyzed. Unit <rbd_timer.1> generated.

Analyzing generic Entity <rbd_timer.2> in library <work> (Architecture <syn>).
	RB_ADDR = "11100001"
Entity <rbd_timer.2> analyzed. Unit <rbd_timer.2> generated.

Analyzing Entity <rb_sres_or_3> in library <work> (Architecture <syn>).
Entity <rb_sres_or_3> analyzed. Unit <rb_sres_or_3> generated.

Analyzing Entity <rb_sres_or_4> in library <work> (Architecture <syn>).
Entity <rb_sres_or_4> analyzed. Unit <rb_sres_or_4> generated.

Analyzing Entity <rb_sres_or_2> in library <work> (Architecture <syn>).
Entity <rb_sres_or_2> analyzed. Unit <rb_sres_or_2> generated.

Analyzing Entity <nx_cram_dummy> in library <work> (Architecture <syn>).
Entity <nx_cram_dummy> analyzed. Unit <nx_cram_dummy> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <dcm_sfs>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/dcm_sfs_unisim_s3e.vhd".
Unit <dcm_sfs> synthesized.


Synthesizing Unit <clkdivce>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/genlib/clkdivce.vhd".
    Found 7-bit subtractor for signal <N_REGS.ucnt$addsub0000> created at line 96.
    Found 10-bit down counter for signal <R_REGS.mcnt>.
    Found 1-bit register for signal <R_REGS.msec>.
    Found 7-bit register for signal <R_REGS.ucnt>.
    Found 1-bit register for signal <R_REGS.usec>.
    Summary:
	inferred   1 Counter(s).
	inferred   9 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <clkdivce> synthesized.


Synthesizing Unit <rb_sres_or_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rb_sres_or_2.vhd".
Unit <rb_sres_or_2> synthesized.


Synthesizing Unit <nx_cram_dummy>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/nxcramlib/nx_cram_dummy.vhd".
WARNING:Xst:647 - Input <I_MEM_WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <nx_cram_dummy> synthesized.


Synthesizing Unit <iob_reg_i_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/iob_reg_i_gen.vhd".
    Found 1-bit register for signal <R_DI<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <iob_reg_i_gen_1> synthesized.


Synthesizing Unit <iob_reg_o_gen_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 1-bit register for signal <R_DO<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <iob_reg_o_gen_3> synthesized.


Synthesizing Unit <iob_reg_i_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/iob_reg_i_gen.vhd".
    Found 1-bit register for signal <R_DI<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <iob_reg_i_gen_2> synthesized.


Synthesizing Unit <iob_reg_o_gen_4>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 1-bit register for signal <R_DO<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <iob_reg_o_gen_4> synthesized.


Synthesizing Unit <iob_reg_o_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 4-bit register for signal <R_DO>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <iob_reg_o_gen_1> synthesized.


Synthesizing Unit <iob_reg_o_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/iob_reg_o_gen.vhd".
    Found 8-bit register for signal <R_DO>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <iob_reg_o_gen_2> synthesized.


Synthesizing Unit <sn_4x7segctl>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/sn_4x7segctl.vhd".
    Found 16x7-bit ROM for signal <SEG_N$rom0000> created at line 152.
    Found 4-bit 4-to-1 multiplexer for signal <$n0001> created at line 125.
    Found 1-bit 4-to-1 multiplexer for signal <cdp$mux0000> created at line 125.
    Found 7-bit down counter for signal <R_REGS.cdiv>.
    Found 2-bit up counter for signal <R_REGS.dcnt>.
    Summary:
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred   5 Multiplexer(s).
Unit <sn_4x7segctl> synthesized.


Synthesizing Unit <iob_reg_i_gen_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/iob_reg_i_gen.vhd".
    Found 8-bit register for signal <R_DI>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <iob_reg_i_gen_3> synthesized.


Synthesizing Unit <iob_reg_i_gen_4>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/iob_reg_i_gen.vhd".
    Found 4-bit register for signal <R_DI>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <iob_reg_i_gen_4> synthesized.


Synthesizing Unit <debounce_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/genlib/debounce_gen.vhd".
    Found 1-bit xor2 for signal <n.dchange_0$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_1$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_2$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_3$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_4$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_5$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_6$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_7$xor0000> created at line 104.
    Found 2-bit down counter for signal <R_REGS.cecnt>.
    Found 8-bit register for signal <R_REGS.dchange>.
    Found 8-bit register for signal <R_REGS.dout>.
    Found 8-bit register for signal <R_REGS.dref>.
    Summary:
	inferred   1 Counter(s).
	inferred  24 D-type flip-flop(s).
Unit <debounce_gen_1> synthesized.


Synthesizing Unit <debounce_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/genlib/debounce_gen.vhd".
    Found 1-bit xor2 for signal <n.dchange_0$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_1$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_2$xor0000> created at line 104.
    Found 1-bit xor2 for signal <n.dchange_3$xor0000> created at line 104.
    Found 2-bit down counter for signal <R_REGS.cecnt>.
    Found 4-bit register for signal <R_REGS.dchange>.
    Found 4-bit register for signal <R_REGS.dout>.
    Found 4-bit register for signal <R_REGS.dref>.
    Summary:
	inferred   1 Counter(s).
	inferred  12 D-type flip-flop(s).
Unit <debounce_gen_2> synthesized.


Synthesizing Unit <byte2cdata>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/comlib/byte2cdata.vhd".
    Found finite state machine <FSM_0> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 8                                              |
    | Inputs             | 4                                              |
    | Outputs            | 4                                              |
    | Clock              | CLK                       (rising_edge)        |
    | Power Up State     | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 9-bit register for signal <R_REGS.data>.
    Found 31-bit comparator lessequal for signal <R_REGS.data$cmp_le0000> created at line 118.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   9 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <byte2cdata> synthesized.


Synthesizing Unit <cdata2byte>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/comlib/cdata2byte.vhd".
    Found finite state machine <FSM_1> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 14                                             |
    | Inputs             | 6                                              |
    | Outputs            | 5                                              |
    | Clock              | CLK                       (rising_edge)        |
    | Power Up State     | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 8-bit register for signal <R_REGS.data>.
    Found 31-bit comparator lessequal for signal <R_REGS.state$cmp_le0000> created at line 123.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   8 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <cdata2byte> synthesized.


Synthesizing Unit <crc8>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/comlib/crc8.vhd".
    Found 1-bit xor5 for signal <n_3$xor0000> created at line 131.
    Found 1-bit xor5 for signal <n_4$xor0000> created at line 132.
    Found 8-bit register for signal <R_CRC>.
    Found 1-bit xor3 for signal <R_CRC$xor0000> created at line 135.
    Found 1-bit xor3 for signal <R_CRC$xor0001> created at line 134.
    Found 1-bit xor4 for signal <R_CRC$xor0002> created at line 133.
    Found 1-bit xor4 for signal <R_CRC$xor0003> created at line 130.
    Found 1-bit xor4 for signal <R_CRC$xor0004> created at line 129.
    Found 1-bit xor2 for signal <R_CRC$xor0005> created at line 128.
    Found 1-bit xor2 for signal <R_CRC$xor0006> created at line 135.
    Found 1-bit xor2 for signal <R_CRC$xor0007> created at line 135.
    Found 1-bit xor2 for signal <R_CRC$xor0008> created at line 135.
    Found 1-bit xor2 for signal <R_CRC$xor0009> created at line 134.
    Found 1-bit xor2 for signal <R_CRC$xor0010> created at line 134.
    Found 1-bit xor2 for signal <R_CRC$xor0011> created at line 133.
    Found 1-bit xor2 for signal <R_CRC$xor0013> created at line 130.
    Found 1-bit xor2 for signal <R_CRC$xor0014> created at line 130.
    Found 1-bit xor2 for signal <R_CRC$xor0016> created at line 128.
    Found 1-bit xor2 for signal <R_CRC$xor0017> created at line 128.
    Found 1-bit xor2 for signal <R_CRC$xor0018> created at line 134.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   7 Xor(s).
Unit <crc8> synthesized.


Synthesizing Unit <serport_xonrx>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_xonrx.vhd".
    Found 1-bit register for signal <R_REGS.escseen>.
    Found 8-bit register for signal <R_REGS.rxdata>.
    Found 1-bit register for signal <R_REGS.rxovr>.
    Found 1-bit register for signal <R_REGS.rxval>.
    Found 1-bit register for signal <R_REGS.txok>.
    Summary:
	inferred  12 D-type flip-flop(s).
Unit <serport_xonrx> synthesized.


Synthesizing Unit <serport_xontx>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_xontx.vhd".
    Found 1-bit register for signal <R_REGS.enaxon_1>.
    Found 1-bit register for signal <R_REGS.escpend>.
    Found 8-bit register for signal <R_REGS.ibuf>.
    Found 1-bit register for signal <R_REGS.ival>.
    Found 8-bit register for signal <R_REGS.obuf>.
    Found 1-bit xor2 for signal <R_REGS.obuf$xor0000> created at line 108.
    Found 1-bit register for signal <R_REGS.oval>.
    Found 1-bit register for signal <R_REGS.rxok>.
    Summary:
	inferred  21 D-type flip-flop(s).
Unit <serport_xontx> synthesized.


Synthesizing Unit <serport_uart_autobaud>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_uart_autobaud.vhd".
    Found finite state machine <FSM_2> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 4                                              |
    | Clock              | CLK                       (rising_edge)        |
    | Power Up State     | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 18-bit register for signal <R_REGS.ccnt>.
    Found 18-bit adder for signal <R_REGS.ccnt$addsub0000> created at line 160.
    Found 7-bit up counter for signal <R_REGS.mcnt>.
    Found 1-bit register for signal <R_REGS.seen1>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  19 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <serport_uart_autobaud> synthesized.


Synthesizing Unit <serport_uart_rx>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_uart_rx.vhd".
    Found finite state machine <FSM_3> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 23                                             |
    | Inputs             | 4                                              |
    | Outputs            | 8                                              |
    | Clock              | CLK                       (rising_edge)        |
    | Reset              | RESET                     (positive)           |
    | Reset type         | synchronous                                    |
    | Reset State        | 000                                            |
    | Power Up State     | 000                                            |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 16-bit comparator greater for signal <dbit$cmp_gt0000> created at line 150.
    Found 16-bit adder for signal <n.dcnt$add0000> created at line 287.
    Found 15-bit subtractor for signal <N_REGS.ccnt$addsub0000> created at line 279.
    Found 4-bit up counter for signal <R_REGS.bcnt>.
    Found 15-bit register for signal <R_REGS.ccnt>.
    Found 16-bit register for signal <R_REGS.dcnt>.
    Found 8-bit register for signal <R_REGS.sreg>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  39 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <serport_uart_rx> synthesized.


Synthesizing Unit <serport_uart_tx>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_uart_tx.vhd".
    Found 15-bit subtractor for signal <N_REGS.ccnt$addsub0000> created at line 123.
    Found 4-bit up counter for signal <R_REGS.bcnt>.
    Found 1-bit register for signal <R_REGS.busy>.
    Found 15-bit register for signal <R_REGS.ccnt>.
    Found 9-bit register for signal <R_REGS.sreg>.
    Summary:
	inferred   1 Counter(s).
	inferred  25 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <serport_uart_tx> synthesized.


Synthesizing Unit <rbd_timer_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rbd_timer.vhd".
WARNING:Xst:647 - Input <RB_MREQ.init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_REGS.rbsel>.
    Found 16-bit register for signal <R_REGS.timer>.
    Found 16-bit subtractor for signal <R_REGS.timer$addsub0000> created at line 136.
    Found 1-bit register for signal <R_REGS.timer_act>.
    Found 1-bit register for signal <R_REGS.timer_end>.
    Summary:
	inferred  19 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <rbd_timer_1> synthesized.


Synthesizing Unit <rbd_timer_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rbd_timer.vhd".
WARNING:Xst:647 - Input <RB_MREQ.init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <R_REGS.rbsel>.
    Found 16-bit register for signal <R_REGS.timer>.
    Found 16-bit subtractor for signal <R_REGS.timer$addsub0000> created at line 136.
    Found 1-bit register for signal <R_REGS.timer_act>.
    Found 1-bit register for signal <R_REGS.timer_end>.
    Summary:
	inferred  19 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <rbd_timer_2> synthesized.


Synthesizing Unit <rb_sres_or_3>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rb_sres_or_3.vhd".
Unit <rb_sres_or_3> synthesized.


Synthesizing Unit <rb_sres_or_4>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rb_sres_or_4.vhd".
Unit <rb_sres_or_4> synthesized.


Synthesizing Unit <iob_reg_i_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/iob_reg_i.vhd".
Unit <iob_reg_i_1> synthesized.


Synthesizing Unit <iob_reg_o_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/iob_reg_o.vhd".
Unit <iob_reg_o_1> synthesized.


Synthesizing Unit <iob_reg_i_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/iob_reg_i.vhd".
Unit <iob_reg_i_2> synthesized.


Synthesizing Unit <iob_reg_o_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/xlib/iob_reg_o.vhd".
Unit <iob_reg_o_2> synthesized.


Synthesizing Unit <bp_swibtnled>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/bp_swibtnled.vhd".
Unit <bp_swibtnled> synthesized.


Synthesizing Unit <rlink_core>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rlink/rlink_core.vhd".
    Found finite state machine <FSM_4> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 26                                             |
    | Transitions        | 118                                            |
    | Inputs             | 31                                             |
    | Outputs            | 34                                             |
    | Clock              | CLK                       (rising_edge)        |
    | Power Up State     | 00000                                          |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 6-bit subtractor for signal <N_REGS.atocnt$addsub0000> created at line 856.
    Found 8-bit register for signal <R_REGS.addr>.
    Found 1-bit register for signal <R_REGS.andone>.
    Found 1-bit register for signal <R_REGS.anena>.
    Found 6-bit register for signal <R_REGS.atocnt>.
    Found 16-bit register for signal <R_REGS.attn>.
    Found 8-bit register for signal <R_REGS.ccmd>.
    Found 1-bit register for signal <R_REGS.cerr>.
    Found 8-bit register for signal <R_REGS.cnt>.
    Found 8-bit subtractor for signal <R_REGS.cnt$addsub0000> created at line 777.
    Found 1-bit register for signal <R_REGS.derr>.
    Found 8-bit register for signal <R_REGS.dih>.
    Found 8-bit register for signal <R_REGS.dil>.
    Found 8-bit register for signal <R_REGS.doh>.
    Found 8-bit register for signal <R_REGS.dol>.
    Found 6-bit down counter for signal <R_REGS.itocnt>.
    Found 1-bit register for signal <R_REGS.itoena>.
    Found 6-bit register for signal <R_REGS.itoval>.
    Found 1-bit register for signal <R_REGS.monattn>.
    Found 1-bit register for signal <R_REGS.moneop>.
    Found 1-bit register for signal <R_REGS.monlamp>.
    Found 1-bit register for signal <R_REGS.nakcerr>.
    Found 1-bit register for signal <R_REGS.nakderr>.
    Found 1-bit register for signal <R_REGS.nakeop>.
    Found 1-bit register for signal <R_REGS.rbaval>.
    Found 1-bit register for signal <R_REGS.rberr>.
    Found 1-bit register for signal <R_REGS.rbinit>.
    Found 1-bit register for signal <R_REGS.rbnak>.
    Found 1-bit register for signal <R_REGS.rbre>.
    Found 1-bit register for signal <R_REGS.rbwe>.
    Found 8-bit register for signal <R_REGS.rcmd>.
    Found 3-bit register for signal <R_REGS.stat>.
    Found 8-bit comparator not equal for signal <R_REGS.state$cmp_ne0000> created at line 627.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred 112 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   1 Comparator(s).
Unit <rlink_core> synthesized.


Synthesizing Unit <serport_uart_rxtx>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_uart_rxtx.vhd".
Unit <serport_uart_rxtx> synthesized.


Synthesizing Unit <ram_1swar_1ar_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/ram_1swar_1ar_gen_unisim.vhd".
Unit <ram_1swar_1ar_gen_2> synthesized.


Synthesizing Unit <ram_1swar_1ar_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/ram_1swar_1ar_gen_unisim.vhd".
Unit <ram_1swar_1ar_gen_1> synthesized.


Synthesizing Unit <ram_1swsr_xfirst_gen_unisim_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd".
WARNING:Xst:646 - Signal <L_DO<17:16>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <ram_1swsr_xfirst_gen_unisim_1> synthesized.


Synthesizing Unit <ram_1swsr_xfirst_gen_unisim_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/ram_1swsr_xfirst_gen_unisim.vhd".
Unit <ram_1swsr_xfirst_gen_unisim_2> synthesized.


Synthesizing Unit <ram_2swsr_xfirst_gen_unisim>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/ram_2swsr_xfirst_gen_unisim.vhd".
Unit <ram_2swsr_xfirst_gen_unisim> synthesized.


Synthesizing Unit <bp_rs232_2line_iob>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/bp_rs232_2line_iob.vhd".
Unit <bp_rs232_2line_iob> synthesized.


Synthesizing Unit <bp_rs232_4line_iob>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/bp_rs232_4line_iob.vhd".
Unit <bp_rs232_4line_iob> synthesized.


Synthesizing Unit <sn_humanio>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/sn_humanio.vhd".
Unit <sn_humanio> synthesized.


Synthesizing Unit <rlink_core8>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rlink/rlink_core8.vhd".
Unit <rlink_core8> synthesized.


Synthesizing Unit <serport_uart_rxtx_ab>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_uart_rxtx_ab.vhd".
Unit <serport_uart_rxtx_ab> synthesized.


Synthesizing Unit <fifo_1c_dram_raw_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/fifo_1c_dram_raw.vhd".
    Found 1-bit register for signal <R_REGS.empty>.
    Found 1-bit register for signal <R_REGS.full>.
    Found 5-bit up counter for signal <R_REGS.raddr>.
    Found 5-bit up counter for signal <R_REGS.waddr>.
    Found 5-bit subtractor for signal <SIZE$sub0000> created at line 120.
    Summary:
	inferred   2 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <fifo_1c_dram_raw_2> synthesized.


Synthesizing Unit <fifo_1c_dram_raw_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/fifo_1c_dram_raw.vhd".
    Found 1-bit register for signal <R_REGS.empty>.
    Found 1-bit register for signal <R_REGS.full>.
    Found 4-bit up counter for signal <R_REGS.raddr>.
    Found 4-bit up counter for signal <R_REGS.waddr>.
    Found 4-bit subtractor for signal <SIZE$sub0000> created at line 120.
    Summary:
	inferred   2 Counter(s).
	inferred   2 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <fifo_1c_dram_raw_1> synthesized.


Synthesizing Unit <ram_1swsr_wfirst_gen_1>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd".
Unit <ram_1swsr_wfirst_gen_1> synthesized.


Synthesizing Unit <ram_1swsr_wfirst_gen_2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vhd".
Unit <ram_1swsr_wfirst_gen_2> synthesized.


Synthesizing Unit <ram_2swsr_wfirst_gen>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/ram_2swsr_wfirst_gen_unisim.vhd".
Unit <ram_2swsr_wfirst_gen> synthesized.


Synthesizing Unit <bp_rs232_2l4l_iob>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/bp_rs232_2l4l_iob.vhd".
    Found 1-bit register for signal <R_CTS_N>.
    Found 1-bit register for signal <R_RTS1_N>.
    Found 1-bit register for signal <R_RXD>.
    Found 1-bit register for signal <R_TXD0>.
    Found 1-bit register for signal <R_TXD1>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <bp_rs232_2l4l_iob> synthesized.


Synthesizing Unit <sn_humanio_rbus>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../bplib/bpgen/sn_humanio_rbus.vhd".
WARNING:Xst:647 - Input <RB_MREQ.init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 4-bit register for signal <R_REGS.btn>.
    Found 4-bit register for signal <R_REGS.btneff>.
    Found 16-bit register for signal <R_REGS.dateff>.
    Found 1-bit register for signal <R_REGS.dp_en>.
    Found 4-bit register for signal <R_REGS.dpeff>.
    Found 16-bit register for signal <R_REGS.dsp_dat>.
    Found 4-bit register for signal <R_REGS.dsp_dp>.
    Found 1-bit register for signal <R_REGS.dsp_en>.
    Found 8-bit register for signal <R_REGS.led>.
    Found 1-bit register for signal <R_REGS.led_en>.
    Found 8-bit register for signal <R_REGS.ledeff>.
    Found 8-bit register for signal <R_REGS.ledin>.
    Found 1-bit register for signal <R_REGS.rbsel>.
    Found 8-bit register for signal <R_REGS.swi>.
    Found 1-bit register for signal <R_REGS.swi_en>.
    Found 8-bit register for signal <R_REGS.swieff>.
    Summary:
	inferred  93 D-type flip-flop(s).
Unit <sn_humanio_rbus> synthesized.


Synthesizing Unit <fifo_1c_dram>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/memlib/fifo_1c_dram.vhd".
Unit <fifo_1c_dram> synthesized.


Synthesizing Unit <rbd_tester>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rbd_tester.vhd".
WARNING:Xst:646 - Signal <FIFO_SIZE> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <R_REGS.act_1>.
    Found 10-bit register for signal <R_REGS.cntbusy>.
    Found 10-bit subtractor for signal <R_REGS.cntbusy$addsub0000> created at line 212.
    Found 10-bit register for signal <R_REGS.cntcyc>.
    Found 10-bit adder for signal <R_REGS.cntcyc$addsub0000> created at line 215.
    Found 16-bit register for signal <R_REGS.data>.
    Found 10-bit register for signal <R_REGS.nbusy>.
    Found 10-bit register for signal <R_REGS.ncyc>.
    Found 1-bit register for signal <R_REGS.nofifo>.
    Found 1-bit register for signal <R_REGS.rbsel>.
    Found 3-bit register for signal <R_REGS.stat>.
    Summary:
	inferred  62 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <rbd_tester> synthesized.


Synthesizing Unit <rbd_bram>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rbd_bram.vhd".
WARNING:Xst:647 - Input <RB_MREQ.init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 10-bit up counter for signal <R_REGS.addr>.
    Found 6-bit register for signal <R_REGS.cntbusy>.
    Found 6-bit subtractor for signal <R_REGS.cntbusy$addsub0000> created at line 169.
    Found 6-bit register for signal <R_REGS.nbusy>.
    Found 1-bit register for signal <R_REGS.rbsel>.
    Summary:
	inferred   1 Counter(s).
	inferred  13 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <rbd_bram> synthesized.


Synthesizing Unit <rbd_rbmon>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rbd_rbmon.vhd".
    Found 1-bit register for signal <R_REGS.go>.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS.go$mux0001> created at line 255.
    Found 8-bit register for signal <R_REGS.hilim>.
    Found 9-bit register for signal <R_REGS.laddr>.
    Found 9-bit adder for signal <R_REGS.laddr$addsub0000> created at line 378.
    Found 8-bit register for signal <R_REGS.lolim>.
    Found 1-bit register for signal <R_REGS.rback>.
    Found 8-bit register for signal <R_REGS.rbaddr>.
    Found 1-bit register for signal <R_REGS.rbbusy>.
    Found 16-bit register for signal <R_REGS.rbdata>.
    Found 1-bit register for signal <R_REGS.rberr>.
    Found 1-bit register for signal <R_REGS.rbinit>.
    Found 1-bit register for signal <R_REGS.rbnak>.
    Found 12-bit up counter for signal <R_REGS.rbnbusy>.
    Found 20-bit up counter for signal <R_REGS.rbndly>.
    Found 1-bit register for signal <R_REGS.rbsel>.
    Found 1-bit register for signal <R_REGS.rbtake_1>.
    Found 1-bit register for signal <R_REGS.rbtout>.
    Found 1-bit register for signal <R_REGS.rbwe>.
    Found 2-bit register for signal <R_REGS.waddr>.
    Found 2-bit adder for signal <R_REGS.waddr$addsub0000> created at line 286.
    Found 2-bit 4-to-1 multiplexer for signal <R_REGS.waddr$mux0001> created at line 255.
    Found 1-bit register for signal <R_REGS.wrap>.
    Found 8-bit comparator greatequal for signal <rbtake$cmp_ge0000> created at line 326.
    Found 8-bit comparator lessequal for signal <rbtake$cmp_le0000> created at line 326.
    Summary:
	inferred   2 Counter(s).
	inferred  62 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   2 Comparator(s).
	inferred   3 Multiplexer(s).
Unit <rbd_rbmon> synthesized.


Synthesizing Unit <rbd_eyemon>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rbus/rbd_eyemon.vhd".
WARNING:Xst:647 - Input <RB_MREQ.init> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <RB_MREQ.din<15:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found finite state machine <FSM_5> for signal <R_REGS.state>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 9                                              |
    | Inputs             | 5                                              |
    | Outputs            | 3                                              |
    | Clock              | CLK                       (rising_edge)        |
    | Power Up State     | 00                                             |
    | Encoding           | automatic                                      |
    | Implementation     | automatic                                      |
    -----------------------------------------------------------------------
    Found 32-bit adder for signal <BRAM_DIB$addsub0000> created at line 345.
    Found 1-bit 4-to-1 multiplexer for signal <n.clr$mux0002> created at line 216.
    Found 1-bit register for signal <R_REGS.clr>.
    Found 1-bit register for signal <R_REGS.ena01>.
    Found 1-bit register for signal <R_REGS.ena10>.
    Found 1-bit register for signal <R_REGS.go>.
    Found 9-bit up counter for signal <R_REGS.laddr>.
    Found 9-bit register for signal <R_REGS.laddr_1>.
    Found 1-bit register for signal <R_REGS.memclr>.
    Found 1-bit register for signal <R_REGS.memwe>.
    Found 1-bit register for signal <R_REGS.rbsel>.
    Found 8-bit register for signal <R_REGS.rdiv>.
    Found 8-bit register for signal <R_REGS.rdivcnt>.
    Found 8-bit subtractor for signal <R_REGS.rdivcnt$addsub0000> created at line 317.
    Found 1-bit register for signal <R_REGS.rxsd_1>.
    Found 1-bit register for signal <R_REGS.waddr>.
    Found 1-bit 4-to-1 multiplexer for signal <R_REGS.waddr$mux0001> created at line 216.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 Counter(s).
	inferred  34 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   2 Multiplexer(s).
Unit <rbd_eyemon> synthesized.


Synthesizing Unit <rbd_tst_rlink>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../rbd_tst_rlink.vhd".
WARNING:Xst:646 - Signal <RB_LAM_TEST<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <rbd_tst_rlink> synthesized.


Synthesizing Unit <serport_1clock>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/serport/serport_1clock.vhd".
WARNING:Xst:646 - Signal <RXFIFO_SIZE<2:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
    Found 1-bit register for signal <R_RXOK>.
    Found 3-bit comparator greatequal for signal <R_RXOK$cmp_ge0000> created at line 212.
    Found 3-bit comparator lessequal for signal <R_RXOK$cmp_le0000> created at line 213.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   2 Comparator(s).
Unit <serport_1clock> synthesized.


Synthesizing Unit <rlink_sp1c>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../../../../vlib/rlink/rlink_sp1c.vhd".
WARNING:Xst:647 - Input <CE_USEC> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <rlink_sp1c> synthesized.


Synthesizing Unit <sys_tst_rlink_n2>.
    Related source file is "/home/walter/tmp/octest/trunk/rtl/sys_gen/tst_rlink/nexys2/ise/../sys_tst_rlink_n2.vhd".
WARNING:Xst:646 - Signal <SWI<7:2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <STAT<7:2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SER_MONI.rxovr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SER_MONI.rxerr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SER_MONI.abdone> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <BTN> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
Unit <sys_tst_rlink_n2> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 16x7-bit ROM                                          : 1
# Adders/Subtractors                                   : 19
 10-bit adder                                          : 1
 10-bit subtractor                                     : 1
 15-bit subtractor                                     : 2
 16-bit adder                                          : 1
 16-bit subtractor                                     : 2
 18-bit adder                                          : 1
 2-bit adder                                           : 1
 32-bit adder                                          : 1
 4-bit subtractor                                      : 1
 5-bit subtractor                                      : 2
 6-bit subtractor                                      : 2
 7-bit subtractor                                      : 1
 8-bit subtractor                                      : 2
 9-bit adder                                           : 1
# Counters                                             : 19
 10-bit down counter                                   : 1
 10-bit up counter                                     : 1
 12-bit up counter                                     : 1
 2-bit down counter                                    : 2
 2-bit up counter                                      : 1
 20-bit up counter                                     : 1
 4-bit up counter                                      : 4
 5-bit up counter                                      : 4
 6-bit down counter                                    : 1
 7-bit down counter                                    : 1
 7-bit up counter                                      : 1
 9-bit up counter                                      : 1
# Registers                                            : 150
 1-bit register                                        : 83
 10-bit register                                       : 4
 15-bit register                                       : 2
 16-bit register                                       : 8
 18-bit register                                       : 1
 2-bit register                                        : 1
 3-bit register                                        : 2
 4-bit register                                        : 9
 6-bit register                                        : 4
 7-bit register                                        : 1
 8-bit register                                        : 31
 9-bit register                                        : 4
# Comparators                                          : 8
 16-bit comparator greater                             : 1
 3-bit comparator greatequal                           : 1
 3-bit comparator lessequal                            : 1
 31-bit comparator lessequal                           : 2
 8-bit comparator greatequal                           : 1
 8-bit comparator lessequal                            : 1
 8-bit comparator not equal                            : 1
# Multiplexers                                         : 6
 1-bit 4-to-1 multiplexer                              : 4
 2-bit 4-to-1 multiplexer                              : 1
 4-bit 4-to-1 multiplexer                              : 1
# Xors                                                 : 51
 1-bit xor2                                            : 37
 1-bit xor3                                            : 4
 1-bit xor4                                            : 6
 1-bit xor5                                            : 4

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_5> for best encoding.
Optimizing FSM <RBDTST/EMON/R_REGS.state/FSM> on signal <R_REGS.state[1:2]> with user encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 10
-------------------
Analyzing FSM <FSM_4> for best encoding.
Optimizing FSM <RLINK/CORE/RL/R_REGS.state/FSM> on signal <R_REGS.state[1:26]> with one-hot encoding.
-------------------------------------
 State | Encoding
-------------------------------------
 00000 | 00000000000000000000000001
 00001 | 00000000000000000000000010
 00010 | 00000000000000000000000100
 00011 | 00000000000000000000001000
 00100 | 00000000000000000000100000
 00101 | 00000000000000000001000000
 00110 | 00000000000000000000010000
 00111 | 00000000000000000010000000
 01000 | 00000000000000001000000000
 01001 | 00000000000000100000000000
 01010 | 00000000000000010000000000
 01011 | 00000000000000000100000000
 01100 | 00000000000010000000000000
 01101 | 00000000001000000000000000
 01110 | 00000000000100000000000000
 01111 | 00000010000000000000000000
 10000 | 00000100000000000000000000
 10001 | 00001000000000000000000000
 10010 | 00000000000001000000000000
 10011 | 00100000000000000000000000
 10100 | 00010000000000000000000000
 10101 | 01000000000000000000000000
 10110 | 00000000100000000000000000
 10111 | 00000000010000000000000000
 11000 | 00000001000000000000000000
 11001 | 10000000000000000000000000
-------------------------------------
Analyzing FSM <FSM_3> for best encoding.
Optimizing FSM <RLINK/SERPORT/UART/RXTX/RX/R_REGS.state/FSM> on signal <R_REGS.state[1:7]> with one-hot encoding.
-------------------
 State | Encoding
-------------------
 000   | 0000001
 001   | 0000100
 010   | 0000010
 011   | 0010000
 100   | 0001000
 101   | 1000000
 110   | 0100000
-------------------
Analyzing FSM <FSM_2> for best encoding.
Optimizing FSM <RLINK/SERPORT/UART/AB/R_REGS.state/FSM> on signal <R_REGS.state[1:2]> with gray encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 11
 11    | 10
-------------------
Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <RLINK/CORE/CD2B/R_REGS.state/FSM> on signal <R_REGS.state[1:3]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 001   | 011
 010   | 001
 011   | 010
 100   | 100
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <RLINK/CORE/B2CD/R_REGS.state/FSM> on signal <R_REGS.state[1:2]> with user encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 10
-------------------

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 6
# ROMs                                                 : 1
 16x7-bit ROM                                          : 1
# Adders/Subtractors                                   : 19
 10-bit adder                                          : 1
 10-bit subtractor                                     : 1
 15-bit subtractor                                     : 2
 16-bit adder                                          : 1
 16-bit subtractor                                     : 2
 18-bit adder                                          : 1
 2-bit adder                                           : 1
 32-bit adder                                          : 1
 4-bit subtractor                                      : 1
 5-bit subtractor                                      : 2
 6-bit subtractor                                      : 2
 7-bit subtractor                                      : 1
 8-bit subtractor                                      : 2
 9-bit adder                                           : 1
# Counters                                             : 19
 10-bit down counter                                   : 1
 10-bit up counter                                     : 1
 12-bit up counter                                     : 1
 2-bit down counter                                    : 2
 2-bit up counter                                      : 1
 20-bit up counter                                     : 1
 4-bit up counter                                      : 4
 5-bit up counter                                      : 4
 6-bit down counter                                    : 1
 7-bit down counter                                    : 1
 7-bit up counter                                      : 1
 9-bit up counter                                      : 1
# Registers                                            : 658
 Flip-Flops                                            : 658
# Comparators                                          : 8
 16-bit comparator greater                             : 1
 3-bit comparator greatequal                           : 1
 3-bit comparator lessequal                            : 1
 31-bit comparator lessequal                           : 2
 8-bit comparator greatequal                           : 1
 8-bit comparator lessequal                            : 1
 8-bit comparator not equal                            : 1
# Multiplexers                                         : 6
 1-bit 4-to-1 multiplexer                              : 4
 2-bit 4-to-1 multiplexer                              : 1
 4-bit 4-to-1 multiplexer                              : 1
# Xors                                                 : 51
 1-bit xor2                                            : 37
 1-bit xor3                                            : 4
 1-bit xor4                                            : 6
 1-bit xor5                                            : 4

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
INFO:Xst:2261 - The FF/Latch <R_REGS.ledin_2> in Unit <sn_humanio_rbus> is equivalent to the following 4 FFs/Latches, which will be removed : <R_REGS.ledin_3> <R_REGS.ledin_4> <R_REGS.ledin_5> <R_REGS.ledin_6> 
WARNING:Xst:1293 - FF/Latch <R_REGS.ledin_2> has a constant value of 0 in block <sn_humanio_rbus>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent to the following FF/Latch, which will be removed : <R_REGS.state_FSM_FFd7> 

Optimizing unit <sys_tst_rlink_n2> ...

Optimizing unit <clkdivce> ...
WARNING:Xst:1293 - FF/Latch <R_REGS.ucnt_6> has a constant value of 0 in block <clkdivce>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <R_REGS.ucnt_6> has a constant value of 0 in block <clkdivce>. This FF/Latch will be trimmed during the optimization process.

Optimizing unit <iob_reg_o_gen_2> ...

Optimizing unit <sn_4x7segctl> ...

Optimizing unit <iob_reg_i_gen_3> ...

Optimizing unit <debounce_gen_1> ...

Optimizing unit <debounce_gen_2> ...

Optimizing unit <byte2cdata> ...

Optimizing unit <cdata2byte> ...

Optimizing unit <crc8> ...

Optimizing unit <serport_xonrx> ...

Optimizing unit <serport_xontx> ...

Optimizing unit <serport_uart_autobaud> ...

Optimizing unit <serport_uart_rx> ...

Optimizing unit <serport_uart_tx> ...

Optimizing unit <ram_1swar_1ar_gen_2> ...

Optimizing unit <ram_1swar_1ar_gen_1> ...

Optimizing unit <rlink_core> ...

Optimizing unit <fifo_1c_dram_raw_2> ...

Optimizing unit <fifo_1c_dram_raw_1> ...

Optimizing unit <rbd_tester> ...

Optimizing unit <rbd_bram> ...

Optimizing unit <rbd_rbmon> ...

Optimizing unit <rbd_eyemon> ...

Optimizing unit <bp_rs232_2l4l_iob> ...

Optimizing unit <sn_humanio_rbus> ...

Optimizing unit <rbd_tst_rlink> ...

Optimizing unit <serport_1clock> ...
WARNING:Xst:2677 - Node <RLINK/CORE/RL/R_REGS.monattn> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <RLINK/CORE/RL/R_REGS.monlamp> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <RLINK/CORE/RL/R_REGS.moneop> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swieff_7> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swieff_6> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swieff_5> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swieff_4> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swieff_3> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swieff_2> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swi_7> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swi_6> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swi_5> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swi_4> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swi_3> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.swi_2> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.btn_3> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.btn_2> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.btn_1> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.btn_0> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.btneff_3> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.btneff_2> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.btneff_1> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <HIO/R_REGS.btneff_0> of sequential type is unconnected in block <sys_tst_rlink_n2>.
WARNING:Xst:2677 - Node <RLINK/SERPORT/XONRX/R_REGS.rxovr> of sequential type is unconnected in block <sys_tst_rlink_n2>.

Mapping all equations...
Annotating constraints using XCF file 'sys_tst_rlink_n2.xcf'
XCF parsing done.
Building and optimizing final netlist ...

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 792
 Flip-Flops                                            : 792

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
Top Level Output File Name         : sys_tst_rlink_n2
Output Format                      : ngc
Optimization Goal                  : SPEED
Keep Hierarchy                     : no

Design Statistics
# IOs                              : 88

Cell Usage :
# BELS                             : 2271
#      GND                         : 1
#      INV                         : 97
#      LUT1                        : 117
#      LUT2                        : 191
#      LUT2_D                      : 13
#      LUT2_L                      : 9
#      LUT3                        : 344
#      LUT3_D                      : 31
#      LUT3_L                      : 23
#      LUT4                        : 744
#      LUT4_D                      : 47
#      LUT4_L                      : 107
#      MUXCY                       : 246
#      MUXF5                       : 72
#      VCC                         : 1
#      XORCY                       : 228
# FlipFlops/Latches                : 792
#      FD                          : 253
#      FDE                         : 320
#      FDR                         : 15
#      FDRE                        : 99
#      FDRS                        : 2
#      FDRSE                       : 32
#      FDS                         : 63
#      FDSE                        : 8
# RAMS                             : 52
#      RAM16X1D                    : 48
#      RAMB16_S18                  : 1
#      RAMB16_S36                  : 2
#      RAMB16_S36_S36              : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 86
#      IBUF                        : 15
#      OBUF                        : 71
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s1200efg320-4 

 Number of Slices:                      952  out of   8672    10%  
 Number of Slice Flip Flops:            754  out of  17344     4%  
 Number of 4 input LUTs:               1819  out of  17344    10%  
    Number used as logic:              1723
    Number used as RAMs:                 96
 Number of IOs:                          88
 Number of bonded IOBs:                  87  out of    250    34%  
    IOB Flip Flops:                      38
 Number of BRAMs:                         4  out of     28    14%  
 Number of GCLKs:                         1  out of     24     4%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
I_CLK50                            | BUFGP                  | 844   |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 10.083ns (Maximum Frequency: 99.177MHz)
   Minimum input arrival time before clock: 1.946ns
   Maximum output required time after clock: 4.283ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'I_CLK50'
  Clock period: 10.083ns (frequency: 99.177MHz)
  Total number of paths / destination ports: 34780 / 2109
-------------------------------------------------------------------------
Delay:               10.083ns (Levels of Logic = 7)
  Source:            RBDTST/TEST/R_REGS.cntbusy_6 (FF)
  Destination:       RBDTST/MON/R_REGS.rbdata_3 (FF)
  Source Clock:      I_CLK50 rising
  Destination Clock: I_CLK50 rising

  Data Path: RBDTST/TEST/R_REGS.cntbusy_6 to RBDTST/MON/R_REGS.rbdata_3
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              2   0.591   0.622  RBDTST/TEST/R_REGS.cntbusy_6 (RBDTST/TEST/R_REGS.cntbusy_6)
     LUT4:I0->O            1   0.704   0.424  RBDTST/TEST/isbusy_and000037 (RBDTST/TEST/isbusy_and000037)
     LUT4:I3->O           18   0.704   1.072  RBDTST/TEST/isbusy_and000039 (RBDTST/TEST/isbusy_and0000)
     LUT4_D:I3->O          4   0.704   0.622  RBDTST/TEST/irb_busy_mux0001 (RBDTST/RB_SRES_TEST_busy)
     LUT4:I2->O            5   0.704   0.668  RBDTST/TEST/irb_dout_1_mux000221 (RBDTST/TEST/N28)
     LUT3:I2->O            1   0.704   0.424  RB_SRES_OR1/RB_SRES_OR_dout<5>117 (RB_SRES_OR1/RB_SRES_OR_dout<5>117)
     LUT4_D:I3->O          1   0.704   0.424  RB_SRES_OR1/RB_SRES_OR_dout<5>289 (RB_SRES_dout<5>)
     LUT4:I3->O            1   0.704   0.000  RBDTST/MON/R_REGS_rbdata_mux0001<5>1 (RBDTST/MON/R_REGS_rbdata_mux0001<5>)
     FDE:D                     0.308          RBDTST/MON/R_REGS.rbdata_5
    ----------------------------------------
    Total                     10.083ns (5.827ns logic, 4.256ns route)
                                       (57.8% logic, 42.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'I_CLK50'
  Total number of paths / destination ports: 15 / 15
-------------------------------------------------------------------------
Offset:              1.946ns (Levels of Logic = 1)
  Source:            I_FUSP_RXD (PAD)
  Destination:       IOB_RS232/P1/IOB_RXD/IOB/R_DI_0 (FF)
  Destination Clock: I_CLK50 rising

  Data Path: I_FUSP_RXD to IOB_RS232/P1/IOB_RXD/IOB/R_DI_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.218   0.420  I_FUSP_RXD_IBUF (I_FUSP_RXD_IBUF)
     FDE:D                     0.308          IOB_RS232/P1/IOB_RXD/IOB/R_DI_0
    ----------------------------------------
    Total                      1.946ns (1.526ns logic, 0.420ns route)
                                       (78.4% logic, 21.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'I_CLK50'
  Total number of paths / destination ports: 23 / 23
-------------------------------------------------------------------------
Offset:              4.283ns (Levels of Logic = 1)
  Source:            IOB_RS232/P1/IOB_TXD/IOB/R_DO_0 (FF)
  Destination:       O_FUSP_TXD (PAD)
  Source Clock:      I_CLK50 rising

  Data Path: IOB_RS232/P1/IOB_TXD/IOB/R_DO_0 to O_FUSP_TXD
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   0.591   0.420  IOB_RS232/P1/IOB_TXD/IOB/R_DO_0 (IOB_RS232/P1/IOB_TXD/IOB/R_DO_0)
     OBUF:I->O                 3.272          O_FUSP_TXD_OBUF (O_FUSP_TXD)
    ----------------------------------------
    Total                      4.283ns (3.863ns logic, 0.420ns route)
                                       (90.2% logic, 9.8% route)

=========================================================================


Total REAL time to Xst completion: 53.00 secs
Total CPU time to Xst completion: 23.98 secs
 
--> 


Total memory usage is 591764 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   51 (   0 filtered)
Number of infos    :    3 (   0 filtered)

